TW201633520A - Imaging device and method of manufacturing the same - Google Patents
Imaging device and method of manufacturing the same Download PDFInfo
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- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 17
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 17
- 229910052721 tungsten Inorganic materials 0.000 description 17
- 239000010937 tungsten Substances 0.000 description 17
- 230000000052 comparative effect Effects 0.000 description 15
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- 229910000449 hafnium oxide Inorganic materials 0.000 description 12
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 12
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- 229910052715 tantalum Inorganic materials 0.000 description 3
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- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
本發明係有關於一種攝影裝置及其製造方法，例如可適合利用於包含有光電二極體及電極墊之攝影裝置。The present invention relates to a photographing apparatus and a method of manufacturing the same, and can be suitably used, for example, in an image pickup apparatus including a photodiode and an electrode pad.
例如包含有CMOS(Complementary Metal Oxide Semiconductor:互補金氧半導體)影像感測器之攝影裝置適用於數位相機等。攝影裝置為了將入射之光轉換成電荷而形成有光電二極體。在光電二極體中所產生之電荷以傳送電晶體傳送至浮置擴散區域。所傳送之電荷以放大用電晶體轉換成電信號後作為圖像信號而輸出。For example, a photographing device including a CMOS (Complementary Metal Oxide Semiconductor) image sensor is suitable for a digital camera or the like. The photographing device forms a photodiode in order to convert incident light into electric charge. The charge generated in the photodiode is transferred to the floating diffusion region by the transfer transistor. The transferred charge is converted into an electrical signal by the amplification transistor and then output as an image signal.
以往，使光入射至光電二極體之方法已知有使光從半導體基板之表面入射的方法。此種CMOS影像感測器稱為表面照射型CMOS影像感測器。而表面照射型影像感測器隨著攝影裝置之細微化，有入射之光被形成於光電二極體上之多層配線所遮蔽而使入射至光電二極體之光減弱的問題。Conventionally, a method of causing light to enter a photodiode is known to cause light to enter from the surface of a semiconductor substrate. Such a CMOS image sensor is called a surface illumination type CMOS image sensor. On the other hand, the surface-illuminated image sensor has a problem that the incident light is blocked by the multilayer wiring formed on the photodiode and the light incident on the photodiode is weakened.
是故，為了解決此問題，在例如專利文獻1(日本專利公開公報2011-14674號公報)及專利文獻2(日本專利公開公報2005-150463號)中，提出了使光從形成有配線之側的表面之反側的半導體基板背面入射之背面照射型CMOS影像感測器。即，提出了使光從藉研磨變薄之半導體基板的背面入射後將光引導至形成於半導體基板之表面側的光電二極體之方法。In order to solve this problem, it is proposed to make light from the side where wiring is formed, for example, in Patent Document 1 (Japanese Patent Laid-Open Publication No. 2011-14674) and Patent Document 2 (Japanese Patent Laid-Open Publication No. 2005-150463). A back side illumination type CMOS image sensor incident on the back side of the semiconductor substrate on the opposite side of the surface. That is, a method of guiding light to a photodiode formed on the surface side of the semiconductor substrate after incident on the back surface of the semiconductor substrate thinned by polishing is proposed.
此種包含有背面照射型COMS感測器之攝影裝置因使光從半導體基板之背面入射的關係，用以與外部進行電性連接之電極墊係形成於半導體基板之背面，並於該電極墊連結金屬線。形成於半導體基板之背面的電極墊與形成於半導體基板之表面側的配線以貫穿半導體基板之導體電性連接。習知之背面照射型攝影裝置便如上述構成。In the photographic apparatus including the back-illuminated COMS sensor, an electrode pad for electrically connecting to the outside is formed on the back surface of the semiconductor substrate by the light incident from the back surface of the semiconductor substrate, and the electrode pad is formed on the electrode pad. Connect the wire. The electrode pads formed on the back surface of the semiconductor substrate and the wiring formed on the surface side of the semiconductor substrate are electrically connected to the conductors penetrating the semiconductor substrate. The conventional back side illumination type photographing apparatus is constructed as described above.
包含有背面照射型CMOS感測器之攝影裝置於進行晶圓測試等電氣試驗之際，需使探針接觸電極墊。且最後，於電極墊連結金屬線。因此，對位於配置有電極墊之區域且包含貫穿半導體基板之導體的構造要求機械強度。A photographing device including a back-illuminated CMOS sensor is required to bring the probe into contact with the electrode pad during an electrical test such as wafer testing. And finally, the metal wire is connected to the electrode pad. Therefore, mechanical strength is required for a structure located in a region where the electrode pad is disposed and including a conductor penetrating through the semiconductor substrate.
然而，習知之攝影裝置由於該種貫穿半導體基板之導體形成有由形成於具有預定開口徑之接觸孔內的金屬材料構成之貫穿通路，故更加要求機械強度。However, the conventional imaging apparatus further requires mechanical strength because the conductor penetrating the semiconductor substrate is formed with a through-passage formed of a metal material formed in a contact hole having a predetermined opening diameter.
其他之課題及新特徵從本說明書的記述及附加圖式應可清楚明白。Other issues and new features should be clearly understood from the description of the specification and the additional drawings.
一實施形態之攝影裝置包含有受光感測部、支撐基板、複數之配線層、使光入射之區域、電極墊、及導電性貫穿部。受光感測部形成於具有對向之第1主表面及第2主表面的半導體層之第1主表面側。支撐基板中間隔著層間絕緣層來形成於半導體層的第1主表面側。複數之配線層形成於層間絕緣層之層間。使光入射之區域形成於半導體層之第2主表面側。電極墊形成於半導體層之第2主表面側。導電性貫穿部具有壁狀之壁型導電性貫穿部，該壁型導電性貫穿部以貫穿半導體層而接觸電極墊之態樣形成，並將電極墊與複數之配線層中的一配線層電性連接。A photographing apparatus according to an embodiment includes a light receiving portion, a supporting substrate, a plurality of wiring layers, a region where light is incident, an electrode pad, and a conductive penetrating portion. The light receiving portion is formed on the first main surface side of the semiconductor layer having the first main surface and the second main surface facing each other. The support substrate is formed on the first main surface side of the semiconductor layer with an interlayer insulating layer interposed therebetween. A plurality of wiring layers are formed between the layers of the interlayer insulating layer. A region where light is incident is formed on the second main surface side of the semiconductor layer. The electrode pad is formed on the second main surface side of the semiconductor layer. The conductive penetrating portion has a wall-shaped wall-shaped conductive penetrating portion formed to penetrate the semiconductor layer and contact the electrode pad, and electrically connect the electrode pad and one of the plurality of wiring layers Sexual connection.
另一實施形態之攝影裝置之製造方法包含有下列製程。(1)於支撐於第1支撐基板之半導體層的第1主表面形成受光感測部。(2)形成具有貫穿半導體層之溝狀的溝型貫穿孔之貫穿孔，該溝型貫穿孔係從半導體層之該第1主表面側貫穿至與第1主表面對向的第2主表面。(3)形成導電性貫穿部，該導電性貫穿部具有將導電性膜以與半導體層電性絕緣之態樣形成於貫穿孔且與溝型貫穿孔對應之壁狀的壁型導電性貫穿部。(4)於半導體層之第1主表面側形成具有電性連接於導電性貫穿部之配線層的複數之配線層及層間絕緣膜。(5)將第2支撐基板貼附於層間絕緣膜。(6)去除第1支撐基板。(7)於半導體層之第2主表面側形成以接觸導電性貫穿部之態樣電性連接之電極墊。A method of manufacturing a photographing apparatus according to another embodiment includes the following processes. (1) A light receiving portion is formed on the first main surface of the semiconductor layer supported on the first supporting substrate. (2) forming a through hole having a groove-shaped through hole penetrating through the semiconductor layer, the groove type through hole penetrating from the first main surface side of the semiconductor layer to the second main surface facing the first main surface . (3) forming a conductive penetrating portion having a wall-shaped conductive penetration portion which is formed in the through hole and electrically connected to the through hole and has a wall shape corresponding to the groove through hole in a state in which the conductive film is electrically insulated from the semiconductor layer . (4) A plurality of wiring layers and interlayer insulating films having a wiring layer electrically connected to the conductive penetrating portion are formed on the first main surface side of the semiconductor layer. (5) The second support substrate is attached to the interlayer insulating film. (6) The first support substrate is removed. (7) An electrode pad electrically connected to the conductive penetration portion is formed on the second main surface side of the semiconductor layer.
根據一實施形態之攝影裝置，可使配置有電極墊之區域的機械強度提高。According to the photographing apparatus of the embodiment, the mechanical strength of the region in which the electrode pads are disposed can be improved.
又，根據另一實施形態之攝影裝置之製造方法，可製造配置有電極墊之區域的機械強度提高之攝影裝置。 此發明之上述及其他目的、特徵、觀點及優點從可與附加圖式相關理解之有關此發明的下述詳細說明應可清楚明白。Further, according to the method of manufacturing an image pickup apparatus according to another embodiment, it is possible to manufacture an image pickup apparatus having improved mechanical strength in a region in which an electrode pad is disposed. The above and other objects, features, aspects and advantages of the present invention will become apparent from
第1實施形態 在此，就以壁型導電性貫穿部將電極墊與配線電性連接之攝影裝置作說明。[First Embodiment] Here, an imaging device in which an electrode pad and a wiring are electrically connected by a wall-shaped conductive penetrating portion will be described.
如圖1所示，在攝影裝置IS中，於形成有具有光電二極體之受光感測部的晶片形成區域TFR周圍配置有將受光感測部等與外部電性連接之電極墊PAD。如後述，電極墊PAD以形成於貫穿矽層之溝型貫穿孔的壁型導電性貫穿部TB1與預定配線(圖中皆未顯示)電性連接。又，電極墊PAD具有校準標記之功能。As shown in FIG. 1, in the imaging device IS, an electrode pad PAD that electrically connects a light-receiving portion or the like to the outside is disposed around a wafer formation region TFR in which a light-receiving portion having a photodiode is formed. As will be described later, the electrode pad PAD is electrically connected to a predetermined wiring (not shown) by the wall-shaped conductive penetrating portion TB1 formed in the groove-shaped through hole penetrating the layer. Further, the electrode pad PAD has a function of a calibration mark.
密封環SLR配置成包圍該電極墊PAD。此外，在切割前之晶圓狀態下，切割線SRL位在相鄰的密封環SLR與密封環SLR之間。The seal ring SLR is configured to surround the electrode pad PAD. Further, in the wafer state before cutting, the cutting line SRL is positioned between the adjacent seal ring SLR and the seal ring SLR.
接著，就電極墊PAD與晶片形成區域TFR(光電二極體)之構造詳細說明。如圖2所示，以分離區域STI於矽層SOI之其中一主表面規定了晶片形成區域TFR。於晶片形成區域TFR形成有包含光電二極體PD、浮置擴散區域FD、具有閘極TGE之傳送電晶體TT等的受光感測部。Next, the structure of the electrode pad PAD and the wafer formation region TFR (photodiode) will be described in detail. As shown in FIG. 2, the wafer formation region TFR is defined by one of the main surfaces of the 矽 layer SOI in the separation region STI. A light-receiving portion including a photodiode PD, a floating diffusion region FD, a transfer transistor TT having a gate TGE, and the like is formed in the wafer formation region TFR.
支撐基板SUB2形成為中間隔著第1層間絕緣膜IL1、第2層間絕緣膜IL2及層間絕緣膜IL3而覆蓋於該閘極TGE等。層間絕緣膜IL3由複數之層形成，並於其層間形成有第1配線M1、第2配線M2及第3配線M3。晶片形成區域TFR形成有將第1配線M1與浮置擴散區域FD電性連接之導電性插塞PG。The support substrate SUB2 is formed so as to cover the gate TGE and the like with the first interlayer insulating film IL1, the second interlayer insulating film IL2, and the interlayer insulating film IL3 interposed therebetween. The interlayer insulating film IL3 is formed of a plurality of layers, and the first wiring M1, the second wiring M2, and the third wiring M3 are formed between the layers. The wafer formation region TFR is formed with a conductive plug PG that electrically connects the first wiring M1 and the floating diffusion region FD.
於矽層SOI的另一主表面側之與光電二極體PD對向的區域形成有反射防止膜ARC、遮光膜SF、濾色片CF及微透鏡ML。反射防止膜ARC以氧化矽膜SOF1、氮化矽膜SNF、及氧化矽膜SOF2形成。遮光膜SF以例如鋁膜形成。反射防止膜ARC與濾色片CF之間存在氧化矽膜SOF3。此外，於晶片形成區域TFR形成有將在光電二極體PD中所產生之電荷處理作為圖像信號之電路部(圖中未顯示)等。An anti-reflection film ARC, a light-shielding film SF, a color filter CF, and a microlens ML are formed in a region facing the photodiode PD on the other main surface side of the SO layer SOI. The anti-reflection film ARC is formed of a hafnium oxide film SOF1, a tantalum nitride film SNF, and a hafnium oxide film SOF2. The light shielding film SF is formed of, for example, an aluminum film. A ruthenium oxide film SOF3 is present between the anti-reflection film ARC and the color filter CF. Further, in the wafer formation region TFR, a circuit portion (not shown) that processes charge generated in the photodiode PD as an image signal is formed.
於晶片形成區域TFR之周圍的區域形成有貫穿矽層SOI及第1層間絕緣膜IL1之溝型貫穿孔TH3，壁型導電性貫穿部TB1中間隔著第2層間絕緣膜IL2而形成於該溝型貫穿孔TH3。壁型導電性貫穿部TB1藉該第2層間絕緣膜IL2與矽層SOI電性絕緣。A groove-type through hole TH3 penetrating through the 矽 layer SOI and the first interlayer insulating film IL1 is formed in a region around the wafer formation region TFR, and the wall-shaped conductive penetrating portion TB1 is formed in the groove with the second interlayer insulating film IL2 interposed therebetween. Type through hole TH3. The wall-shaped conductive through portion TB1 is electrically insulated from the tantalum layer SOI by the second interlayer insulating film IL2.
又，壁型導電性貫穿部TB1形成為從該矽層SOI之表面突出至電極墊PAD側。因壁型導電性貫穿部TB1從矽層SOI之表面突出，而可提高作為校準標記ALM(參照圖3)之功能。Further, the wall-shaped conductive penetration portion TB1 is formed to protrude from the surface of the 矽 layer SOI to the electrode pad PAD side. Since the wall-shaped conductive penetration portion TB1 protrudes from the surface of the bismuth layer SOI, the function as the alignment mark ALM (see FIG. 3) can be improved.
在此，壁型導電性貫穿部TB1係指藉以預定導電膜填埋入以預定寬度朝一方向延伸之溝型貫穿孔TH3而形成且形狀為對應溝之壁狀的導電性貫穿部。如圖1及圖3所示，在此攝影裝置IS中，形成複數之壁型導電性貫穿部TB1，複數之壁型導電性貫穿部TB1分別朝一方向延伸，且在與該一方向交叉之另一方向相互隔開間隔配置。Here, the wall-shaped conductive penetration portion TB1 is a conductive penetration portion formed by filling a groove-shaped through hole TH3 extending in a predetermined direction in a predetermined width by a predetermined conductive film and having a shape corresponding to a wall shape of the groove. As shown in FIG. 1 and FIG. 3, in the image forming apparatus IS, a plurality of wall-shaped conductive penetrating portions TB1 are formed, and a plurality of wall-shaped conductive penetrating portions TB1 extend in one direction and intersect with the one direction. One direction is spaced apart from each other.
配置於晶片形成區域TFR周圍之電極墊PAD以該壁型導電性貫穿部TB1與預定之第1配線M1電性連接。又，該預定之第1配線M1藉由第1通路V1與第2配線M2電性連接，再者，該第2配線M2藉由第2通路V2與第3配線M3電性連接。第1實施形態之包含有背面照射型CMOS感測器的攝影裝置IS便如上述構成。The electrode pad PAD disposed around the wafer formation region TFR is electrically connected to the predetermined first wiring M1 by the wall-shaped conductive penetration portion TB1. Further, the predetermined first wiring M1 is electrically connected to the second wiring M2 via the first via V1, and the second wiring M2 is electrically connected to the third wiring M3 via the second via V2. The imaging device IS including the back side illumination type CMOS sensor according to the first embodiment has the above configuration.
接著，就上述包含有背面照射型CMOS感測器之攝影裝置IS之製造方法的一例作說明。Next, an example of a manufacturing method of the above-described image forming apparatus IS including a back side illumination type CMOS sensor will be described.
首先，準備SOI基板SBS。在SOI基板SBS中，矽層SOI中間隔著埋入用氧化膜BOX而形成於支撐基板SUB1上(參照圖4)。接著，如圖4所示，藉於矽層SOI之表面形成分離區域STI，而規定晶片形成區域TFR。並於晶片形成區域TFR之周圍規定形成電極墊之區域。First, an SOI substrate SBS is prepared. In the SOI substrate SBS, the germanium layer SOI is formed on the support substrate SUB1 with the buried oxide film BOX interposed therebetween (see FIG. 4). Next, as shown in FIG. 4, the wafer formation region TFR is defined by forming the separation region STI on the surface of the germanium layer SOI. A region where the electrode pads are formed is defined around the wafer formation region TFR.
接著，藉對晶片形成區域TFR進行一般之成膜、加工及離子注入處理等，而形成傳送電晶體TT之閘極TGE、光電二極體PD及浮置擴散區域FD等。然後，如圖5所示，以例如CVD(Chemical Vapor Deposition:化學氣相沈積)法，將氧化矽膜等第1層間絕緣層IL1形成為覆蓋閘極TGE等。Next, a general film formation, processing, ion implantation treatment, or the like is performed on the wafer formation region TFR to form a gate TGE, a photodiode PD, a floating diffusion region FD, and the like of the transmission transistor TT. Then, as shown in FIG. 5, the first interlayer insulating layer IL1 such as a hafnium oxide film is formed to cover the gate TGE or the like by, for example, a CVD (Chemical Vapor Deposition) method.
接著，藉進行預定之光刻處理，而形成光阻圖形PR1。之後，將該光阻圖形PR1作為蝕刻遮罩，對第1層間絕緣膜IL1進行蝕刻處理，藉此，形成貫穿第1層間絕緣膜IL1而使矽層SOI露出之溝型貫穿孔TH1。之後，去除光阻圖形PR1。Next, a photoresist pattern PR1 is formed by performing a predetermined photolithography process. After that, the photoresist pattern PR1 is used as an etching mask, and the first interlayer insulating film IL1 is etched to form a trench-type through hole TH1 that penetrates the first interlayer insulating film IL1 and exposes the germanium layer SOI. Thereafter, the photoresist pattern PR1 is removed.
然後，如圖6所示，將所露出之第1層間絕緣膜IL1作為蝕刻遮罩，對矽層SOI進行蝕刻處理，藉此，形成貫穿矽層SOI而使埋入用氧化膜BOX露出之溝型貫穿孔TH2。Then, as shown in FIG. 6, the exposed first interlayer insulating film IL1 is used as an etching mask, and the germanium layer SOI is etched to form a trench that penetrates the germanium layer SOI and exposes the buried oxide film BOX. Type through hole TH2.
之後，如圖7所示，以例如CVD法形成氧化矽膜等第2層間絕緣膜IL2。此時，以第2層間絕緣膜IL2埋入溝型貫穿孔TH2。此外，圖7雖顯示溝型貫穿孔TH2內形成有空隙之狀態，但並非顯示特意形成空隙。接著，藉對第2層間絕緣膜IL2進行CMP(Chemical Mechanical Polishing:化學機械研磨)處理(CMP處理A)，而將第2層間絕緣膜IL2之表面平坦化。Thereafter, as shown in FIG. 7, a second interlayer insulating film IL2 such as a hafnium oxide film is formed by, for example, a CVD method. At this time, the trench through-hole TH2 is buried in the second interlayer insulating film IL2. In addition, although FIG. 7 shows a state in which a void is formed in the groove-shaped through-hole TH2, it does not show that a void is intentionally formed. Then, CMP (Chemical Mechanical Polishing) treatment (CMP treatment A) is performed on the second interlayer insulating film IL2 to planarize the surface of the second interlayer insulating film IL2.
然後，藉進行預定之光刻處理，而形成光阻圖形PR2。接著，將光阻圖形PR2作為蝕刻遮罩，對第2層間絕緣膜IL2及第1層間絕緣膜IL1進行蝕刻處理，藉此，形成使浮置擴散區域FD露出之接觸孔CH。之後，去除光阻圖形PR2。Then, by performing a predetermined photolithography process, a photoresist pattern PR2 is formed. Then, the photoresist pattern PR2 is used as an etching mask, and the second interlayer insulating film IL2 and the first interlayer insulating film IL1 are etched to form a contact hole CH through which the floating diffusion region FD is exposed. Thereafter, the photoresist pattern PR2 is removed.
接著，如圖8所示，藉進行預定之光刻處理，而形成光阻圖形PR3。然後，將光阻圖形PR3作為蝕刻遮罩，對第2層間絕緣膜IL2進行蝕刻處理，藉此，形成溝型貫穿孔TH3。此時，藉過蝕刻，將埋入用氧化膜BOX去除例如數十nm左右。Next, as shown in FIG. 8, a photoresist pattern PR3 is formed by performing a predetermined photolithography process. Then, the photoresist pattern PR3 is used as an etching mask, and the second interlayer insulating film IL2 is etched to form the trench through holes TH3. At this time, the etching oxide film BOX is removed by etching for, for example, about several tens of nanometers.
又，為不使矽層SOI露出至溝型貫穿孔TH3之側壁，而將溝型貫穿孔TH3之尺寸及蝕刻條件預先設定為於溝型貫穿孔TH3與矽層SOI之間保留第1層間絕緣膜IL1(及第2層間絕緣膜IL2)數十nm左右。溝型貫穿溝TH3之尺寸相對於電極墊PAD之尺寸(約100μm´100μm左右)而言，溝型貫穿溝TH3之寬度為例如10μm左右，長度為數十μm左右(50~70μm左右)。之後，去除光阻圖形PR3。Further, in order to prevent the germanium layer SOI from being exposed to the sidewall of the trench through hole TH3, the size and etching condition of the trench through hole TH3 are previously set to maintain the first interlayer insulating between the trench through hole TH3 and the germanium layer SOI. The film IL1 (and the second interlayer insulating film IL2) is about several tens of nanometers. The size of the groove-type through-groove TH3 is about 10 μm (about 100 μm ́100 μm) with respect to the size of the electrode pad PAD, and the width of the groove-type through-groove TH3 is, for example, about 10 μm, and the length is about several tens of μm (about 50 to 70 μm). Thereafter, the photoresist pattern PR3 is removed.
然後，將例如鎢膜等導電膜(圖中未顯示)形成為埋入溝型貫穿孔TH3及接觸孔CH。接著，藉進行CMP處理(CMP處理B)，而保留分別位於溝型貫穿孔TH3及接觸孔CH之導電膜的部分，且去除位於第2層間絕緣膜IL2之上面上的導電膜之部分。藉此，如圖9所示，於溝型貫穿孔TH3形成對應溝形狀之壁狀的壁型導電性貫穿部TB1。又，於接觸孔CH形成導電性插塞PG。Then, a conductive film (not shown) such as a tungsten film is formed to be buried in the trench through-hole TH3 and the contact hole CH. Next, by performing the CMP process (CMP process B), portions of the conductive films respectively located in the trench through holes TH3 and the contact holes CH are left, and portions of the conductive film on the upper surface of the second interlayer insulating film IL2 are removed. As a result, as shown in FIG. 9, the wall-shaped conductive penetration portion TB1 corresponding to the groove shape is formed in the groove-shaped through hole TH3. Further, a conductive plug PG is formed in the contact hole CH.
接著，藉反覆進行一般之成膜及加工，而形成具有第1配線M1、第1通路V1、第2配線M2、第2通路V2、第3配線M3之多層配線構造。第1配線M1、第2配線M2及第3配線M3之材料可使用鋁或銅。第1通路V1及第2通路V2之材料可使用鎢、鈦、氮化鈦、或銅。當材料使用銅時，可以金屬鑲嵌法，形成配線或通路。Then, the general film formation and processing are repeated to form a multilayer wiring structure including the first wiring M1, the first via V1, the second wiring M2, the second via V2, and the third wiring M3. Aluminum or copper can be used as the material of the first wiring M1, the second wiring M2, and the third wiring M3. As the material of the first passage V1 and the second passage V2, tungsten, titanium, titanium nitride, or copper can be used. When the material uses copper, it can be metal damascene to form wiring or vias.
此外，將第1配線M1、第2配線M2及第3配線M3等電性絕緣之層間絕緣膜IL3由複數之層形成，為了圖式之簡略化，在圖10中顯示單層之層間絕緣膜。該層間絕緣膜IL3之表面藉進行CMP處理等而平坦化。In addition, the interlayer insulating film IL3 which is electrically insulated, such as the first wiring M1, the second wiring M2, and the third wiring M3, is formed of a plurality of layers, and a single layer of interlayer insulating film is shown in FIG. 10 for simplification of the drawing. . The surface of the interlayer insulating film IL3 is planarized by CMP treatment or the like.
然後，準備新的支撐基板，於該支撐基板之表面形成氧化膜。接著，如圖11所示，將該支撐基板SUB2貼附於層間絕緣膜IL3之表面。此外，圖11中未顯示支撐基板SUB2之氧化膜。之後，藉進行CMP處理、乾蝕刻處理或濕蝕刻處理，而如圖12所示，去除支撐基板SUB1。Then, a new support substrate is prepared, and an oxide film is formed on the surface of the support substrate. Next, as shown in FIG. 11, the support substrate SUB2 is attached to the surface of the interlayer insulating film IL3. Further, the oxide film of the support substrate SUB2 is not shown in FIG. Thereafter, by performing a CMP process, a dry etching process, or a wet etching process, as shown in FIG. 12, the support substrate SUB1 is removed.
接著，如圖13所示，藉進行乾蝕刻處理或濕蝕刻處理，而去除埋入用氧化膜BOX。藉此，壁型導電性貫穿部TB1從矽層SOI之表面(背面)突出的部分露出。然後，如圖14所示，以例如CVD法將氧化矽膜SOF1形成為覆蓋矽層SOI之表面。Next, as shown in FIG. 13, the buried oxide film BOX is removed by performing a dry etching process or a wet etching process. Thereby, the wall-shaped conductive penetration portion TB1 is exposed from a portion protruding from the surface (back surface) of the bismuth layer SOI. Then, as shown in FIG. 14, the yttrium oxide film SOF1 is formed to cover the surface of the ruthenium layer SOI by, for example, a CVD method.
之後，如圖15所示，以例如CVD法將氮化矽膜SNF及氧化矽膜SOF2依序形成為覆蓋氧化矽膜SOF1。氧化矽膜SOF1、氮化矽膜SNF及氧化矽膜SOF2形成作反射防止膜ARC。接著，將作為遮光膜之鋁膜AF形成為覆蓋氧化矽膜SOF2。Thereafter, as shown in FIG. 15, the tantalum nitride film SNF and the hafnium oxide film SOF2 are sequentially formed to cover the hafnium oxide film SOF1 by, for example, a CVD method. The ruthenium oxide film SOF1, the tantalum nitride film SNF, and the ruthenium oxide film SOF2 are formed as a reflection preventing film ARC. Next, an aluminum film AF as a light shielding film is formed to cover the ruthenium oxide film SOF2.
然後，藉將突出之壁型導電性貫穿部TB1作為校準標記來進行預定之光刻處理，而形成光阻圖形PR4。之後，將該光阻圖形PR4作為蝕刻遮罩，對該鋁膜AF進行蝕刻處理，藉此，形成遮光膜SF(參照圖16)。之後，去除光阻圖形PR4。接著，以例如CVD法將氧化矽膜SOF3(參照圖16) 形成為覆蓋遮光膜SF等。Then, a predetermined photolithography process is performed by using the protruding wall-type conductivity penetrating portion TB1 as a calibration mark to form a photoresist pattern PR4. Thereafter, the photoresist pattern PR4 is used as an etching mask, and the aluminum film AF is etched to form a light shielding film SF (see FIG. 16). Thereafter, the photoresist pattern PR4 is removed. Next, the hafnium oxide film SOF3 (see FIG. 16) is formed to cover the light shielding film SF or the like by, for example, a CVD method.
接著，藉將突出之壁型導電性貫穿部TB1作為校準標記來進行預定之光刻處理，而形成光阻圖形PR5(參照圖16)。然後，如圖16所示，將光阻圖形PR5作為蝕刻遮罩，對氧化矽膜SOF3及反射防止膜ARC等進行蝕刻處理，藉此，形成使壁型導電性貫穿部TB1露出之開口部SOH。之後，去除光阻圖形PR5。Next, a predetermined photolithography process is performed by using the protruding wall-type conductivity penetrating portion TB1 as a calibration mark to form a photoresist pattern PR5 (see FIG. 16). Then, as shown in FIG. 16, the photoresist pattern PR5 is used as an etching mask, and the ruthenium oxide film SOF3 and the anti-reflection film ARC are etched to form an opening portion SOH in which the wall-shaped conductive through portion TB1 is exposed. . Thereafter, the photoresist pattern PR5 is removed.
然後，將作為電極墊之導電膜(圖中未顯示)形成 為埋入開口部SOH。之後，將突出之壁型導電性貫穿部TB1作為校準標記，來形成覆蓋導電膜位於開口部SOH之部分且使導電膜位於其他區域之部分露出的光阻圖形(圖中未顯示)。Then, a conductive film (not shown) as an electrode pad is formed to be buried in the opening portion SOH. Thereafter, the protruding wall-shaped conductive through portion TB1 is used as a alignment mark to form a photoresist pattern (not shown) that covers a portion of the conductive film located at the opening portion SOH and exposes the conductive film to a portion of the other region.
接著，將該光阻圖形作為蝕刻遮罩，對導電膜進行乾蝕刻處理，藉此，保留導電膜位於開口部SOH之部份，且去除導電膜位於其他區域之部分。之後，去除光阻圖形。藉此，如圖17所示，於開口部SOH形成電極墊PAD。電極墊PAD接觸壁型導電性貫穿部TB1，並藉由該壁型導電性貫穿部TB1，與第1配線M1等電性連接。Next, the photoresist pattern is used as an etch mask, and the conductive film is subjected to dry etching treatment, whereby the portion of the conductive film located at the opening portion SOH is left, and the portion where the conductive film is located at other regions is removed. After that, the photoresist pattern is removed. Thereby, as shown in FIG. 17, the electrode pad PAD is formed in the opening portion SOH. The electrode pad PAD contacts the wall-shaped conductive penetration portion TB1, and is electrically connected to the first wiring M1 or the like by the wall-shaped conductive penetration portion TB1.
接著，形成作為濾色片之預定樹脂膜(圖中未顯示)。然後，藉將突出之壁型導電性貫穿部TB1作為校準標記來進行預定之光刻處理，而形成光阻圖形(圖中未顯示)。接著，將該光阻圖形作為蝕刻遮罩，對樹脂膜進行蝕刻處理，藉此，形成濾色片CF(參照圖18)。之後，去除光阻圖形。Next, a predetermined resin film (not shown) as a color filter is formed. Then, a predetermined photolithography process is performed by using the protruding wall-type conductivity penetrating portion TB1 as a calibration mark to form a photoresist pattern (not shown). Next, this photoresist pattern is used as an etching mask, and the resin film is etched to form a color filter CF (see FIG. 18). After that, the photoresist pattern is removed.
接著，形成作為微透鏡之預定樹脂膜(圖中未顯示)。然後，藉將突出之壁型導電性貫穿部TB1作為校準標記來進行預定之光刻處理，而形成光阻圖形(圖中未顯示)。接著，將該光阻圖形作為蝕刻遮罩，對樹脂膜進行蝕刻處理，藉此，形成微透鏡ML(參照圖18)。之後，去除光阻圖形。藉此，如圖18所示，包含有背面照射型CMOS感測器之攝影裝置的主要部分便完成。Next, a predetermined resin film (not shown) as a microlens is formed. Then, a predetermined photolithography process is performed by using the protruding wall-type conductivity penetrating portion TB1 as a calibration mark to form a photoresist pattern (not shown). Next, this photoresist pattern is used as an etching mask, and the resin film is etched to form a microlens ML (see FIG. 18). After that, the photoresist pattern is removed. Thereby, as shown in FIG. 18, the main part of the photographing apparatus including the back side illumination type CMOS sensor is completed.
在上述攝影裝置IS中，電極墊PAD藉由壁型導電性貫穿部TB1與第1配線M1等電性連接。藉此，可使配置有電極墊PAD之區域的機械強度提高。關於此點，與比較例之攝影裝置對照說明。In the above-described imaging device IS, the electrode pad PAD is electrically connected to the first wiring M1 or the like by the wall-shaped conductive penetration portion TB1. Thereby, the mechanical strength of the region in which the electrode pad PAD is disposed can be improved. In this regard, the description will be made in comparison with the photographing apparatus of the comparative example.
首先，就比較例之攝影裝置之製造方法作說明。如圖19所示，準備矽基板CSUB，對該矽基板CSUB之其中一表面進行離子注入等，藉此，形成光電二極體等受光部CLR。接著，如圖20所示，將氧化矽膜CSO1形成為覆蓋矽基板CSUB之其中一表面。First, a description will be given of a method of manufacturing a photographing apparatus of a comparative example. As shown in FIG. 19, the ruthenium substrate CSUB is prepared, and one surface of the ruthenium substrate CSUB is ion-implanted or the like to form a light-receiving portion CLR such as a photodiode. Next, as shown in FIG. 20, a hafnium oxide film CSO1 is formed to cover one surface of the tantalum substrate CSUB.
之後，藉進行預定之光刻處理與蝕刻處理，而形成接觸孔CCH1。然後，如圖21所示，將TEOS(Tetra Ethyl Ortho Silicate:矽酸四乙酯)膜CTE1形成為覆蓋包含接觸孔CCH1之內壁面的氧化矽膜CSO1之表面。接著，藉進行CMP處理(CMP處理CA)，保留TEOS膜CTE1位於接觸孔CCH1內之部分，且去除TEOS膜CTE1位於氧化矽膜CSO1之上面上的部分。Thereafter, a predetermined photolithography process and etching process are performed to form a contact hole CCH1. Then, as shown in FIG. 21, a TEOS (Tetra Ethyl Ortho Silicate) film CTE1 is formed to cover the surface of the ruthenium oxide film CSO1 including the inner wall surface of the contact hole CCH1. Next, by performing a CMP process (CMP process CA), a portion of the TEOS film CTE1 located in the contact hole CCH1 is left, and a portion of the TEOS film CTE1 on the upper surface of the ruthenium oxide film CSO1 is removed.
然後，如圖22所示，將鎢膜CWF1形成為埋入接觸孔CCH1並且覆蓋氧化膜CSO1之表面。之後，藉進行CMP處理(CMP處理CB)，而保留鎢膜CWF1位於接觸孔CCH1內之部分，且去除鎢膜CWF1位於氧化矽膜CSO1之上面上的部分。藉此，如圖23所示，形成貫穿通路CV。Then, as shown in FIG. 22, the tungsten film CWF1 is formed to be buried in the contact hole CCH1 and to cover the surface of the oxide film CSO1. Thereafter, by performing a CMP process (CMP process CB), a portion of the tungsten film CWF1 located in the contact hole CCH1 is left, and a portion of the tungsten film CWF1 on the upper surface of the tantalum oxide film CSO1 is removed. Thereby, as shown in FIG. 23, the through passage CV is formed.
接著，藉進行預定之光刻處理及蝕刻處理，而如圖24所示，於形成有受光部CLR之區域形成接觸孔CCH2。然後，將鎢膜CWF2形成為埋入接觸孔CCH2並且覆蓋氧化矽膜CSO1之表面。Next, by performing a predetermined photolithography process and etching process, as shown in FIG. 24, a contact hole CCH2 is formed in a region where the light receiving portion CLR is formed. Then, the tungsten film CWF2 is formed to be buried in the contact hole CCH2 and covers the surface of the yttrium oxide film CSO1.
接著，藉進行CMP處理(CMP處理CC)，而保留鎢膜CWF2位於接觸孔CCH2內之部分，且去除鎢膜CWF2位於氧化矽膜CSO1之上面上的部分。藉此，如圖25所示，形成插塞CPG。Next, by performing a CMP process (CMP process CC), a portion of the tungsten film CWF2 located in the contact hole CCH2 is left, and a portion of the tungsten film CWF2 on the upper surface of the ruthenium oxide film CSO1 is removed. Thereby, as shown in FIG. 25, the plug CPG is formed.
然後，如圖26所示，於TEOS膜CTE2中形成具有配線CM及配線電極CIC之多層配線構造。接著，將作為接著層之氧化矽膜CSO2形成為覆蓋TEOS膜CTE2之表面。之後，如圖27所示，準備形成有氧化矽膜CSO3作為接著層之支撐基板CSS，將該支撐基板CSS之氧化矽膜CSO3貼附於氧化矽膜CSO2。Then, as shown in FIG. 26, a multilayer wiring structure having the wiring CM and the wiring electrode CIC is formed in the TEOS film CTE2. Next, a ruthenium oxide film CSO2 as an adhesion layer is formed to cover the surface of the TEOS film CTE2. Thereafter, as shown in FIG. 27, a support substrate CSS in which a ruthenium oxide film CSO3 is formed as an adhesive layer is prepared, and the ruthenium oxide film CSO3 of the support substrate CSS is attached to the ruthenium oxide film CSO2.
接著，如圖28所示，藉進行CMP處理，使矽基板CSUB變薄而使貫穿通路CV露出。將所露出之貫穿通路CV利用作為之後的光刻處理之校準標記。之後，在使貫穿通路CV露出之態樣下，形成氧化矽膜CSO4。然後，形成鎢膜，進行預定之光刻處理及蝕刻處理，藉此，如圖29所示，形成接觸墊CCP。Next, as shown in FIG. 28, by performing CMP processing, the tantalum substrate CSUB is thinned and the through via CV is exposed. The exposed through-passage CV is utilized as a calibration mark for subsequent photolithography processing. Thereafter, the ruthenium oxide film CSO4 is formed in a state where the through via CV is exposed. Then, a tungsten film is formed, and a predetermined photolithography process and etching process are performed, whereby a contact pad CCP is formed as shown in FIG.
之後，如圖30所示，依序形成反射防止膜CARC、濾色片CCF及微透鏡CML，藉此，攝影裝置CIS之主要部分便完成。Thereafter, as shown in FIG. 30, the anti-reflection film CARC, the color filter CCF, and the microlens CML are sequentially formed, whereby the main portion of the photographing device CIS is completed.
在上述比較例之攝影裝置CIS中，接觸墊CCP藉由貫穿通路CV與配線電極CIC電性連接。該貫穿通路CV以埋入具有直徑約1.0μm左右之開口徑的接觸孔CCH1內之鎢膜CWF1形成。因而，圓柱狀導電膜(鎢膜CWF1)隔開間隔位於配置有接觸墊CCP之區域。In the photographing apparatus CIS of the above comparative example, the contact pad CCP is electrically connected to the wiring electrode CIC through the through via CV. The through-passage CV is formed by embedding a tungsten film CWF1 in a contact hole CCH1 having an opening diameter of about 1.0 μm in diameter. Thus, the cylindrical conductive film (tungsten film CWF1) is spaced apart in the region where the contact pads CCP are disposed.
因此，當使探針接觸接觸墊CCP來進行電氣測試時，或於接觸墊CCP連結金屬線時，配置有接觸墊CCP之區域的機械強度不足，而推想例如裂縫進入氧化矽膜CSO1。當產生裂縫時，也推想裂縫經過隔開間隔配置之一圓柱狀導電膜與另一圓柱狀導電膜之間而擴大。Therefore, when the probe is brought into contact with the contact pad CCP for electrical testing, or when the contact pad CCP is bonded to the metal wire, the mechanical strength of the region where the contact pad CCP is disposed is insufficient, and it is assumed that, for example, the crack enters the ruthenium oxide film CSO1. When a crack is generated, it is also conceivable that the crack is enlarged between the cylindrical conductive film and the other cylindrical conductive film which are disposed at intervals.
相對於比較例之攝影裝置CIS，在第1實施形態之攝影裝置IS中，於配置有電極墊PAD之區域形成溝型貫穿孔TH3，藉將導電膜埋入該溝型貫穿孔，而形成對應溝之形狀的壁狀之複數的壁型導電貫穿孔TB1。In the image forming apparatus IS of the first embodiment, the groove type through hole TH3 is formed in the region where the electrode pad PAD is disposed, and the conductive film is buried in the groove type through hole to form a corresponding portion. A plurality of wall-shaped conductive through holes TB1 having a wall shape of a groove.
藉此，比起隔開間隔形成有複數之圓柱狀導電膜的比較例之攝影裝置CIS，可使配置有電極墊PAD之區域的機械強度提高。結果，使探針接觸電極墊PAD來進行電氣測試時，或於電極墊PAD連結金屬線時，可抑制於第1層間絕緣膜IL1或第2層間絕緣膜IL2產生裂縫。又，若產生裂縫，亦可以複數之壁型導電性貫穿部TB1，確實地阻止裂縫擴大。Thereby, the mechanical strength of the region in which the electrode pad PAD is disposed can be improved as compared with the imaging device CIS of the comparative example in which a plurality of cylindrical conductive films are formed at intervals. As a result, when the probe is brought into contact with the electrode pad PAD for electrical testing, or when the electrode pad PAD is connected to the metal wire, cracking of the first interlayer insulating film IL1 or the second interlayer insulating film IL2 can be suppressed. Further, if a crack is generated, the plurality of wall-shaped conductive penetration portions TB1 can be surely prevented from expanding.
又，比起比較例之攝影裝置CIS之製造方法，第1實施形態之攝影裝置IS之製造方法可刪減形成壁型導電性貫穿部TB1等(貫穿通路CV等)之際的CMP處理次數。關於此，為易比較兩者，而將進行CMP處理之製程及其周邊之主要製程顯示為流程圖來說明。Moreover, compared with the manufacturing method of the imaging apparatus CIS of the comparative example, the manufacturing method of the imaging apparatus IS of the first embodiment can reduce the number of CMP processes when the wall-shaped conductive penetration portion TB1 or the like (through the passage CV or the like) is formed. In this regard, in order to compare the two, the process of performing the CMP process and the main processes around it are shown as a flowchart.
比較例之攝影裝置之製造方法如圖31所示，首先，於矽基板CSUB形成受光部CLR(步驟CK1、圖19)。其次，於矽基板CSUB等形成接觸孔CCH1(步驟CK2、圖20)。接著，於接觸孔CCH1形成絕緣膜(TEOS膜CTE1)(步驟CK3、圖21)。然後，對絕緣膜進行CMP處理(CMP處理CA)(步驟CK4、圖22)。As shown in FIG. 31, the manufacturing method of the image forming apparatus of the comparative example first forms the light receiving unit CLR on the ruthenium substrate CSUB (step CK1, FIG. 19). Next, a contact hole CCH1 is formed on the germanium substrate CSUB or the like (step CK2, FIG. 20). Next, an insulating film (TEOS film CTE1) is formed in the contact hole CCH1 (step CK3, FIG. 21). Then, the insulating film is subjected to CMP treatment (CMP treatment CA) (step CK4, FIG. 22).
之後，將導電膜(鎢膜CWF1)埋入接觸孔(步驟CK5、圖22)。接著，對導電膜進行CMP處理(CMP處理CB)，形成貫穿通路CV(步驟CK6、圖23)。然後，形成接觸孔CCH2，埋入導電膜(鎢膜CWF2)(步驟CK7、圖24)。之後，對導電膜進行CMP處理(CMP處理CC)，形成插塞CPG(步驟CK8、圖25)。Thereafter, a conductive film (tungsten film CWF1) is buried in the contact hole (step CK5, FIG. 22). Next, the conductive film is subjected to CMP treatment (CMP treatment CB) to form a through-passage CV (step CK6, FIG. 23). Then, the contact hole CCH2 is formed, and the conductive film (tungsten film CWF2) is buried (step CK7, FIG. 24). Thereafter, the conductive film is subjected to CMP treatment (CMP treatment CC) to form a plug CPG (step CK8, FIG. 25).
因而，比較例之攝影裝置CIS為了形成貫穿通路CV與插塞CPG，而進行3次CMP處理(CA、CB、CC)。Therefore, the imaging apparatus CIS of the comparative example performs the CMP process (CA, CB, CC) three times in order to form the through-channel CV and the plug CPG.
相對於此，第1實施形態之攝影裝置之製造方法如圖32所示，首先，於矽層SOI形成受光部(光電二極體PD)(步驟K1、圖4)。其次，於矽層SOI形成溝型貫穿孔TH2(步驟K2、圖6)。接著，將絕緣膜(第2層間絕緣膜IL2)埋入溝型貫穿孔TH2 (步驟K3、圖7)。然後，對絕緣膜進行CMP處理(CMP處理A)，將絕緣膜平坦化(步驟K4、圖7)。On the other hand, as shown in FIG. 32, the manufacturing method of the imaging apparatus of the first embodiment first forms a light receiving unit (photodiode PD) in the 矽 layer SOI (steps K1 and 4). Next, a groove-type through hole TH2 is formed in the 矽 layer SOI (step K2, FIG. 6). Next, the insulating film (the second interlayer insulating film IL2) is buried in the trench through-hole TH2 (step K3, FIG. 7). Then, the insulating film is subjected to CMP treatment (CMP treatment A) to planarize the insulating film (step K4, FIG. 7).
之後，於第2層間絕緣膜IL2等形成接觸孔CH(步驟K5、圖7)。接著，形成溝型貫穿孔TH3(步驟K6、圖8)。然後，將導電膜(鎢膜)埋入溝型貫穿孔TH3及接觸孔CH (步驟K7、圖9)。之後，對導電膜進行CMP處理(CMP處理B)，形成壁型導電性貫穿部TB1及導電性插塞PG(步驟K8、圖9)。Thereafter, a contact hole CH is formed in the second interlayer insulating film IL2 or the like (step K5, FIG. 7). Next, the groove-type through hole TH3 is formed (step K6, FIG. 8). Then, a conductive film (tungsten film) is buried in the trench through hole TH3 and the contact hole CH (step K7, FIG. 9). After that, the conductive film is subjected to CMP treatment (CMP treatment B) to form the wall-shaped conductive through portion TB1 and the conductive plug PG (step K8, FIG. 9).
因而，第1實施形態之攝影裝置IS為了形成壁型導電性貫穿部TB1與導電性插塞PG，而進行2次的CMP處理，比起比較例之攝影裝置CIS，可將CMP處理之次數刪減1次。藉CMP處理之次數減少，可抑制碟型凹陷或腐蝕等過度研磨，而可抑制加工形狀之惡化或電性連接不良等。Therefore, the imaging device IS of the first embodiment performs the CMP process twice in order to form the wall-shaped conductive through portion TB1 and the conductive plug PG, and the number of CMP processes can be deleted compared to the imaging device CIS of the comparative example. Decrease 1 time. When the number of times of CMP treatment is reduced, excessive polishing such as dishing or corrosion can be suppressed, and deterioration of the processed shape or electrical connection failure can be suppressed.
又，比較例之攝影裝置之製造方法於形成濾色片CCF或微透鏡CML等之際，利用貫穿通路CV作為校準標記。而貫穿通路CV為了以CMP處理形成，所露出之貫穿通路CV之表面與矽基板CSUB之表面大約在同一平面。因此，推想貫穿通路CV不易辨識為校準標記。Further, in the method of manufacturing the image forming apparatus of the comparative example, the through-passage CV is used as a calibration mark when the color filter CCF or the microlens CML or the like is formed. The through-via CV is formed by CMP processing, and the surface of the exposed through-channel CV is approximately flush with the surface of the germanium substrate CSUB. Therefore, it is assumed that the through-passage CV is not easily recognized as a calibration mark.
相對於此，第1實施形態之攝影裝置之製造方法在作為校準標記之壁型導電性貫穿部TB1方面，其一部分形成為從矽層SOI突出。藉此，可使將壁型導電性貫穿部TB1辨識為校準標記之精確度提高。結果，可有助於提高形成從矽層SOI突出之壁型導電性貫穿部TB1後之圖形化精確度。On the other hand, in the method of manufacturing the image forming apparatus according to the first embodiment, a part of the wall-shaped conductive penetration portion TB1 as a calibration mark is formed so as to protrude from the 矽 layer SOI. Thereby, the accuracy of recognizing the wall-shaped conductive penetration portion TB1 as a calibration mark can be improved. As a result, it is possible to contribute to the improvement of the patterning accuracy after forming the wall-shaped conductive through portion TB1 protruding from the 矽 layer SOI.
再者，在比較例之攝影裝置之製造方法中，貫穿通路CV係在一製程(參照圖23)中形成，而插塞CPG則是在另一製程(參照圖25)中形成。相對於此，在第1實施形態之攝影裝置之製造方法中，壁型導電性貫穿部TB1與導電性插塞PG係在同一製程(參照圖9)中形成。藉此，可謀求製程刪減。Further, in the manufacturing method of the photographing apparatus of the comparative example, the through-passage CV is formed in one process (refer to FIG. 23), and the plug CPG is formed in another process (refer to FIG. 25). On the other hand, in the manufacturing method of the imaging device of the first embodiment, the wall-shaped conductive penetrating portion TB1 and the conductive plug PG are formed in the same process (see FIG. 9). In this way, the process can be reduced.
又，在比較例之攝影裝置中，將接觸墊CCP與配線電極CIC電性連接之貫穿通路CV係形成作為圓柱形導電膜(鎢膜CWF1)。相對於此，在第1實施形態之攝影裝置中，將電極墊PAD與第1配線M1等電性連接之壁型導電性貫穿部TB1則係形成對應溝型貫穿孔TH3之溝狀的壁狀。藉此，可抑制連接阻力。Further, in the photographing apparatus of the comparative example, the through via CV electrically connecting the contact pad CCP and the wiring electrode CIC is formed as a cylindrical conductive film (tungsten film CWF1). On the other hand, in the image forming apparatus of the first embodiment, the wall-shaped conductive penetration portion TB1 that electrically connects the electrode pad PAD to the first wiring M1 or the like is formed into a groove-like wall shape corresponding to the groove-shaped through hole TH3. . Thereby, the connection resistance can be suppressed.
(第1變形例) 在上述攝影裝置IS中，舉了形成5個壁型導電性貫穿部TB1作為形成於配置電極墊PAD之區域的壁型導電性貫穿部TB1之情形為例來說明。壁型導電性貫穿部TB1之數量不限5個，亦可如圖33所示，形成更多之壁型導電性貫穿部TB1。(First Modification) In the above-described imaging device IS, a case where five wall-shaped conductive penetrating portions TB1 are formed as the wall-shaped conductive penetrating portion TB1 formed in the region where the electrode pad PAD is disposed will be described as an example. The number of the wall-type conductive penetration portions TB1 is not limited to five, and as shown in FIG. 33, a plurality of wall-type conductive penetration portions TB1 may be formed.
藉此，在第1變形例之攝影裝置中，可更提高配置電極墊PAD之區域的機械強度。又，可更減低電極墊PAD與第1配線M1等(參照圖2)之連接阻力。Thereby, in the imaging apparatus of the first modification, the mechanical strength of the region where the electrode pad PAD is placed can be further improved. Further, the connection resistance between the electrode pad PAD and the first wiring M1 (see FIG. 2) can be further reduced.
(第2變形例) 如圖1所示，在攝影裝置IS，為確保耐濕性，而將密封環SLR形成為包圍配置晶片形成區域TFR及電極墊PAD之區域。如圖34所示，該密封環SLR之構造亦可為與形成配置電極墊PAD之區域的壁型導電性貫穿部TB1等之製程同時形成的構造。(Second Modification) As shown in FIG. 1, in the imaging device IS, in order to ensure moisture resistance, the seal ring SLR is formed so as to surround the region where the wafer formation region TFR and the electrode pad PAD are disposed. As shown in FIG. 34, the structure of the seal ring SLR may be formed at the same time as the process of forming the wall-shaped conductive through portion TB1 or the like in the region where the electrode pad PAD is disposed.
此外，在圖34中，構成密封環SLR之各部的符號附上與構成配置電極墊PAD之區域的各部之符號相同的符號，但並非具有對應之功能。In addition, in FIG. 34, the code|symbol of each part which comprises the sealing ring SLR is attached with the code|symbol same as the code|symbol of each part which comprises the area|region which arrange|positions the electrode pad PAD, but does not have the corresponding function.
第2實施形態 在此，就以組合了壁型導電性貫穿部而呈框狀之框型導電性貫穿部電性連接電極墊與配線之攝影裝置作說明。Second Embodiment Here, an image forming apparatus in which an electrode pad and a wiring are electrically connected to each other in a frame-shaped conductive penetrating portion in which a wall-shaped conductive penetrating portion is combined will be described.
如圖35及圖36所示，在攝影裝置IS之配置電極墊PAD的區域中，形成組合了溝型貫穿孔TH3而呈框狀之框型貫穿孔，藉將導電膜埋入該框型貫穿孔，而形成對應框之形狀的框型導電性貫穿部TB2。此外，關於此以外之結構，由於與在第1實施形態所說明之圖2及圖3所示的攝影裝置IS相同，故對同一構件附上同一符號，除了必要情形外，並不重複其說明。As shown in FIG. 35 and FIG. 36, in the region where the electrode pad PAD is disposed in the image forming apparatus IS, a frame-shaped through hole having a groove-shaped through hole TH3 combined in a frame shape is formed, and the conductive film is buried in the frame type. The hole forms a frame-shaped conductive penetration portion TB2 corresponding to the shape of the frame. In addition, the configuration other than this is the same as that of the imaging device IS shown in FIG. 2 and FIG. 3 described in the first embodiment, and therefore the same reference numerals are attached to the same members, and the description thereof is not repeated except for the case where necessary. .
接著，就上述攝影裝置之製造方法作說明。首先，經由與前述圖4所示之製程相同之製程，形成圖5所示之第1層間絕緣膜IL1後，如圖37所示，藉進行預定之光刻處理，而形成光阻圖形PR6。接著，將該光阻圖形PR6作為蝕刻遮罩，對第1層間絕緣膜IL1進行蝕刻處理，藉此，形成貫穿第1層間絕緣膜IL1而使矽層SOI露出並配置成框狀之溝型貫穿孔TH1。之後，去除光阻圖形PR6。Next, a description will be given of a method of manufacturing the above-described photographing apparatus. First, after forming the first interlayer insulating film IL1 shown in FIG. 5 by the same process as the process shown in FIG. 4 described above, as shown in FIG. 37, a predetermined photolithography process is performed to form a photoresist pattern PR6. Then, the photoresist pattern PR6 is used as an etching mask, and the first interlayer insulating film IL1 is etched to form a trench through which the first interlayer insulating film IL1 is formed to expose the germanium layer SOI and arranged in a frame shape. Hole TH1. Thereafter, the photoresist pattern PR6 is removed.
接著，如圖38所示，將露出之第1層間絕緣膜IL1作為蝕刻遮罩，對矽層SOI進行蝕刻處理，藉此，形成貫穿矽層SOI而使埋入用氧化膜BOX露出並配置成框狀之溝型貫穿孔TH2。然後，經由與圖7所示之製程相同的製造，如圖39所示，形成使浮置擴散區域FD露出之接觸孔CH。之後，去除光阻圖形PR7。Next, as shown in FIG. 38, the exposed first interlayer insulating film IL1 is used as an etching mask, and the ruthenium layer SOI is etched, whereby the ruthenium layer SOI is formed and the buried oxide film BOX is exposed and arranged. The frame-shaped groove type through hole TH2. Then, through the same manufacturing as the process shown in FIG. 7, as shown in FIG. 39, the contact hole CH which exposes the floating diffusion region FD is formed. Thereafter, the photoresist pattern PR7 is removed.
接著，如圖40所示，藉進行預定之光刻處理，而形成光阻圖形PR8。然後，將光阻圖形PR8作為蝕刻遮罩，對第2層間絕緣膜IL2進行蝕刻處理，藉此，形成配置成框狀之溝型貫穿孔TH3。Next, as shown in FIG. 40, a photoresist pattern PR8 is formed by performing a predetermined photolithography process. Then, the photoresist pattern PR8 is used as an etching mask, and the second interlayer insulating film IL2 is etched to form a groove-shaped through hole TH3 arranged in a frame shape.
此時，與圖8所示之製程同樣地，去除埋入用氧化膜BOX數十nm左右。又，將溝型貫穿孔TH3之尺寸與蝕刻條件預先設定成於溝型貫穿孔TH3與矽層SOI之間保留第1層間絕緣膜IL1(及第2層間絕緣膜IL2)數十nm左右。之後，去除光阻圖形PR8。At this time, in the same manner as the process shown in FIG. 8, the buried oxide film BOX is removed by several tens of nm. In addition, the size and etching conditions of the groove-type through-holes TH3 are set in advance so that the first interlayer insulating film IL1 (and the second interlayer insulating film IL2) is left at about tens of nm between the groove-type through-hole TH3 and the 矽 layer SOI. Thereafter, the photoresist pattern PR8 is removed.
接著，經由圖9所示之製程相同的製程，如圖41所示，於配置成框狀之溝型貫穿孔TH3形成對應框之形狀的框型導電性貫穿部TB2。又，於接觸孔CH形成導電性插塞PG。然後，經由與圖10所示之製程相同的製程，如圖42所示，形成具有第1配線M1、第1通路V1、第2配線M2、第2通路V2、第3配線M3之多層配線構造。Next, as shown in FIG. 41, the frame-shaped conductive penetration portion TB2 having a shape corresponding to the frame is formed in the groove-shaped through hole TH3 arranged in a frame shape, as shown in FIG. Further, a conductive plug PG is formed in the contact hole CH. Then, as shown in FIG. 42 , a multilayer wiring structure including the first wiring M1, the first via V1, the second wiring M2, the second via V2, and the third wiring M3 is formed through the same process as the process shown in FIG. .
接著，如圖43所示，將支撐基板SUB2貼附於層間絕緣膜IL3。然後，藉進行CMP處理、乾蝕刻處理或濕蝕刻處理，而如圖44所示，去除支撐基板SUB1。之後，如圖45所示，藉進行乾蝕刻處理等，去除埋入用氧化膜BOX。藉此，可使從矽層SOI突出之框型導電性貫穿部TB2之部分露出。Next, as shown in FIG. 43, the support substrate SUB2 is attached to the interlayer insulating film IL3. Then, by performing a CMP process, a dry etching process, or a wet etching process, as shown in FIG. 44, the support substrate SUB1 is removed. Thereafter, as shown in FIG. 45, the buried oxide film BOX is removed by dry etching or the like. Thereby, a portion of the frame-shaped conductive through portion TB2 protruding from the 矽 layer SOI can be exposed.
接著，如圖46所示，將氧化矽膜SOF1形成為覆蓋矽層SOI之表面。然後，依序將氮化矽膜SNF及氧化矽膜SOF2(參照圖47)形成為覆蓋氧化矽膜SOF1。之後，如圖47所示，藉將突出之框型導電性貫穿部TB2作為校準標記來進行預定之光刻處理，而形成光阻圖形PR9。Next, as shown in FIG. 46, the hafnium oxide film SOF1 is formed to cover the surface of the SOI layer. Then, a tantalum nitride film SNF and a hafnium oxide film SOF2 (see FIG. 47) are sequentially formed to cover the hafnium oxide film SOF1. Thereafter, as shown in FIG. 47, a predetermined photolithography process is performed by using the protruding frame-shaped conductivity penetrating portion TB2 as a calibration mark to form a photoresist pattern PR9.
接著，將該光阻圖形PR9作為蝕刻遮罩，對氧化矽膜SOF2及氮化矽膜SNF進行蝕刻處理，藉此，形成使框型導電性貫穿部TB2露出之開口部SOH1。之後，去除光阻圖形PR9。Then, the photoresist pattern PR9 is used as an etching mask, and the yttrium oxide film SOF2 and the tantalum nitride film SNF are etched to form an opening portion SOH1 in which the frame-shaped conductive through portion TB2 is exposed. Thereafter, the photoresist pattern PR9 is removed.
然後，如圖48所示，將作為遮光膜之鋁膜AF形成為覆蓋露出之框型導電性貫穿部TB2及氧化矽膜SOF2等。接著，藉將突出之框型導電性貫穿部TB2作為校準標記來進行預定之光刻處理，而形成光阻圖形PR10。然後，將該光阻圖形PR10作為蝕刻遮罩，對鋁膜AF進行蝕刻處理，藉此，同時形成電極墊PAD及遮光膜SF。電極墊PAD藉由框型導電性貫穿部TB2與第1配線M1等電性連接。之後，去除光阻圖形PR10。Then, as shown in FIG. 48, the aluminum film AF as a light-shielding film is formed so as to cover the exposed frame-shaped conductive penetration portion TB2, the ruthenium oxide film SOF2, and the like. Next, a predetermined photolithography process is performed by using the protruding frame-type conductivity penetrating portion TB2 as a calibration mark to form a photoresist pattern PR10. Then, the photoresist pattern PR10 is used as an etching mask, and the aluminum film AF is etched, whereby the electrode pad PAD and the light shielding film SF are simultaneously formed. The electrode pad PAD is electrically connected to the first wiring M1 or the like by the frame-shaped conductive penetration portion TB2. Thereafter, the photoresist pattern PR10 is removed.
接著，將氧化矽膜SOF3(參照圖49)形成為覆蓋電極墊PAD及遮光膜SF。然後，如圖49所示，藉將突出之框型導電性貫穿部TB2作為校準標記來進行預定之光刻處理，而形成光阻圖形PR11。接著，將該光阻圖形PR11作為蝕刻遮罩，對氧化矽膜SOF3進行蝕刻處理，藉此，形成使電極墊PAD露出之開口部SOH2。之後，去除光阻圖形PR11。Next, the hafnium oxide film SOF3 (see FIG. 49) is formed to cover the electrode pad PAD and the light shielding film SF. Then, as shown in FIG. 49, a predetermined photolithography process is performed by using the protruding frame-shaped conductivity penetrating portion TB2 as a calibration mark to form a photoresist pattern PR11. Then, the photoresist pattern PR11 is used as an etching mask, and the ruthenium oxide film SOF3 is etched to form an opening portion SOH2 through which the electrode pad PAD is exposed. Thereafter, the photoresist pattern PR11 is removed.
接著，與圖18所示之製程同樣地，將藉將框型導電性貫穿部TB2作為校準標記來進行預定之光刻處理而形成的光阻圖形(圖中未顯示)作為蝕刻遮罩，對樹脂膜進行蝕刻處理，藉此，形成濾色片CF(參照圖50)。Then, similarly to the process shown in FIG. 18, a photoresist pattern (not shown) formed by performing a predetermined photolithography process using the frame-type conductive penetrating portion TB2 as a alignment mark is used as an etching mask. The resin film is subjected to an etching treatment, whereby the color filter CF is formed (see FIG. 50).
然後，將藉將框型導電性貫穿部TB2作為校準標記來進行預定之光刻處理而形成的光阻圖形(圖中未顯示)作為蝕刻遮罩，對樹脂膜進行蝕刻處理，藉此，形成微透鏡ML(參照圖50)。之後，去除光阻圖形。藉此，如圖50所示，包含有背面照射型CMOS感測器之攝影裝置的主要部分便完成。Then, a photoresist pattern (not shown) formed by performing a predetermined photolithography process using the frame-type conductive penetrating portion TB2 as a calibration mark is used as an etching mask, and the resin film is etched, thereby forming Microlens ML (see Fig. 50). After that, the photoresist pattern is removed. Thereby, as shown in FIG. 50, the main part of the photographing apparatus including the back side illumination type CMOS sensor is completed.
在上述攝影裝置IS中，首先，於配置有電極墊PAD之區域形成配置成框狀之溝型貫穿孔TH3，並藉將導電膜埋入該溝型貫穿孔TH3，而形成對應框之形狀的框型導電性貫穿部TB2。In the above-described imaging device IS, first, a groove-shaped through hole TH3 arranged in a frame shape is formed in a region where the electrode pad PAD is disposed, and a conductive film is buried in the groove-shaped through hole TH3 to form a shape of a corresponding frame. The frame type conductive penetration portion TB2.
藉此，比起形成有圓柱狀導電膜之比較例的攝影裝置CIS(參照圖30)，可使配置有電極墊PAD之區域的機械強度提高。結果，使探針接觸電極墊PAD來進行電氣測試時，或於電極墊PAD連結金屬線時，可抑制第1層間絕緣膜IL1或第2層間絕緣膜IL2產生裂縫。若產生裂縫，也可以框型導電性貫穿部TB2確實地阻止裂縫擴大。Thereby, the mechanical strength of the region in which the electrode pad PAD is disposed can be improved as compared with the imaging device CIS (see FIG. 30) of the comparative example in which the columnar conductive film is formed. As a result, when the probe is brought into contact with the electrode pad PAD for electrical testing, or when the electrode pad PAD is connected to the metal wire, cracking of the first interlayer insulating film IL1 or the second interlayer insulating film IL2 can be suppressed. If a crack is generated, the frame-shaped conductive penetration portion TB2 can surely prevent the crack from expanding.
此外，上述攝影裝置IS可獲得如下之效果。 首先，電極墊PAD係藉將形成為埋入形成於反射防止膜ARC之開口部SOH1(參照圖47)的鋁膜圖形化而形成。另一方面，在第1實施形態之攝影裝置IS中，電極墊PAD係藉將形成為埋入形成在反射防止膜ARC及氧化矽膜SOF3之開口部SOH(參照圖16)的鋁膜圖形化而形成。Further, the above-described photographing apparatus IS can obtain the following effects. First, the electrode pad PAD is formed by patterning an aluminum film formed to be embedded in the opening portion SOH1 (see FIG. 47) formed in the anti-reflection film ARC. On the other hand, in the imaging device IS of the first embodiment, the electrode pad PAD is patterned by embedding an aluminum film which is formed in the opening portion SOH (see FIG. 16) formed in the anti-reflection film ARC and the yttria film SOF3. And formed.
此時，比較開口部之階差，開口部SOH1比開口部SOH之階差低氧化矽膜SOF3之膜厚量。藉此，在相當於電極墊之中央附近的開口部之中央部分的鋁膜之平坦性方面，開口部SOH1之中央附近的平坦性比開口部SOH之中央附近的平坦性改善許多。結果，可更穩定地進行金屬線之連結。At this time, the step difference of the opening portion is compared, and the opening portion SOH1 is lower than the step portion SOH by the film thickness of the ruthenium oxide film SOF3. Thereby, the flatness of the vicinity of the center of the opening portion SOH1 is much improved in flatness in the vicinity of the center of the opening portion SOH in terms of the flatness of the aluminum film in the central portion of the opening portion near the center of the electrode pad. As a result, the connection of the metal wires can be performed more stably.
再者，在上述攝影裝置IS中，該電極墊PAD係與遮光膜SF同時形成(參照圖48)。藉此，比起將形成電極墊PAD之製程與形成遮光膜SF之製程分開的情形，可謀求刪減製程。Further, in the above-described imaging device IS, the electrode pad PAD is formed simultaneously with the light shielding film SF (see FIG. 48). Thereby, the process can be reduced as compared with the case where the process of forming the electrode pad PAD is separated from the process of forming the light shielding film SF.
除了以上外，上述攝影裝置IS與第1實施形態之攝影裝置同樣地，比起比較例之攝影裝置，可減少為了形成框型導電性貫穿部TB2與導電性插塞PG而進行之CMP處理的次數。藉此，可抑制碟型凹陷或腐蝕等過度研磨，而可抑制加工形狀之惡化或電性連接不良等。In the same manner as the imaging device of the first embodiment, the imaging device IS can reduce the CMP process for forming the frame-shaped conductive through portion TB2 and the conductive plug PG, as compared with the imaging device of the comparative example. frequency. Thereby, excessive polishing such as dishing or corrosion can be suppressed, and deterioration of the processed shape, electrical connection failure, and the like can be suppressed.
又，作為校準標記之框型導電性貫穿部TB2藉其一部分形成為從矽層SOI突出，而可使將框型導電性貫穿部TB2辨識作為校準標記之精確度提高。藉此，可有助於提高形成從矽層SOI突出之框型導電性貫穿部TB2後的圖形化精確度。再者，藉框型導電性貫穿部TB2與導電性插塞PG可在同一製程(參照圖41)中形成，可謀求刪減製程。Further, the frame-shaped conductive through portion TB2 as a calibration mark is formed so as to protrude from the 矽 layer SOI, and the accuracy of recognizing the frame-shaped conductive penetration portion TB2 as a calibration mark can be improved. Thereby, it is possible to contribute to an improvement in the patterning accuracy after forming the frame-shaped conductive through portion TB2 protruding from the 矽 layer SOI. Further, the frame-type conductive penetration portion TB2 and the conductive plug PG can be formed in the same process (see FIG. 41), and the process can be reduced.
(各實施形態之變形例) 在第1實施形態中，就於配置電極墊PAD之區域形成有壁型導電性貫穿部TB1之構造作了說明。又，在第2實施形態中，就於配置電極墊PAD之區域形成有壁型導電性貫穿部配置成框狀之框型導電性貫穿部TB2的構造作了說明。(Modification of each embodiment) In the first embodiment, the structure in which the wall-shaped conductive penetration portion TB1 is formed in the region where the electrode pad PAD is disposed has been described. In the second embodiment, a structure in which the frame-shaped conductive penetration portion TB2 in which the wall-shaped conductive penetrating portion is arranged in a frame shape is formed in the region where the electrode pad PAD is disposed.
再者，就該壁型導電性貫穿部TB1及框型導電性貫穿部TB2分別具有校準標記之功能的情形作了說明。從校準標記係使調正精確度提高之觀點來說，於以下舉出壁型導電性貫穿部或框型導電性貫穿部之變形例。In addition, the case where the wall-shaped conductive penetration portion TB1 and the frame-shaped conductive penetration portion TB2 each have a function of a calibration mark has been described. From the viewpoint of improving the alignment accuracy from the calibration mark, a modification of the wall-shaped conductive penetration portion or the frame-shaped conductive penetration portion will be described below.
首先，圖36所示之壁型導電性貫穿部配置成框狀之框型導電性貫穿部TB2的變形例係如圖51所示，亦可為在角部使壁型導電性貫穿部交叉之框型導電性貫穿部TB3。又，亦可如圖52所示，為從壁型導電性貫穿部使複數之突出部隔開間隔配置之框型導電性貫穿部TB4。再者，圖3所示之壁型導電性貫穿部TB1的變形例亦可如圖53所示，為複數之壁型導電性貫穿部配置成分別沿著電極墊PAD之4邊的壁型導電性貫穿部TB5。First, a modification of the frame-shaped conductive penetration portion TB2 in which the wall-shaped conductive penetrating portion shown in FIG. 36 is arranged in a frame shape is as shown in FIG. 51, and the wall-shaped conductive penetration portion may be intersected at the corner portion. The frame type conductive penetration portion TB3. Further, as shown in FIG. 52, the frame-shaped conductive penetration portion TB4 in which a plurality of protruding portions are spaced apart from each other from the wall-shaped conductive penetrating portion may be used. Further, as shown in FIG. 53, a modification of the wall-shaped conductive penetration portion TB1 shown in FIG. 3 may be such that the plurality of wall-shaped conductive penetrating portions are disposed so as to be electrically conductive along the four sides of the electrode pad PAD. Sexual penetration TB5.
藉形成此種具有框型導電性貫穿部TB3、TB4或壁型導電性貫穿部TB5之導電性貫穿部，可使校準標記之調正精確度提高。又，可發揮可使配置有電極墊之區域的機械強度提高等之效果。By forming such a conductive penetrating portion having the frame-shaped conductive penetrating portions TB3 and TB4 or the wall-shaped conductive penetrating portion TB5, the alignment accuracy of the alignment mark can be improved. Moreover, the effect of improving the mechanical strength of the region in which the electrode pads are placed can be exhibited.
此外，在各實施形態中所說明之攝影裝置可依需要作各種組合。又，膜厚等數值為一例，並不限該等。Further, the photographing apparatuses described in the respective embodiments can be variously combined as needed. Further, the numerical values such as the film thickness are an example, and are not limited thereto.
以上，依據實施形態，具體地說明了本發明人所發明的發明，本發明不限於前述實施形態，在不脫離其要旨下可作各種變更是無須贅言的。 就本發明之實施形態作了說明，此次所揭示之實施形態應視為所有點皆是例示並非給予限制。本發明之範圍以申請專利範圍顯示，意在包含與申請專利範圍均等之涵義及範圍內之所有變更。The invention made by the inventors of the present invention has been specifically described above, and the present invention is not limited to the embodiments described above, and it is needless to say that various modifications can be made without departing from the spirit and scope of the invention. The embodiments of the present invention have been described, and the embodiments disclosed herein are to be considered as illustrative and not restrictive. The scope of the present invention is intended to be embraced by the scope of the claims
AF‧‧‧鋁膜
ALM‧‧‧校準標記
ARC‧‧‧反射防止膜
BOX‧‧‧埋入用氧化膜
CARC‧‧‧反射防止膜
CCF‧‧‧濾色片
CCH1‧‧‧接觸孔
CCH2‧‧‧接觸孔
CCP‧‧‧接觸墊
CF‧‧‧濾色片
CH‧‧‧接觸孔
CIC‧‧‧配線電極
CIS‧‧‧攝影裝置
CK1‧‧‧步驟
CK2‧‧‧步驟
CK3‧‧‧步驟
CK4‧‧‧步驟
CK5‧‧‧步驟
CK6‧‧‧步驟
CK7‧‧‧步驟
CK8‧‧‧步驟
CLR‧‧‧受光部
CM‧‧‧配線
CML‧‧‧微透鏡
CPG‧‧‧插塞
CSO1‧‧‧矽基板
CSO2‧‧‧氧化矽膜
CSO3‧‧‧氧化矽膜
CSO4‧‧‧氧化矽膜
CSS‧‧‧支撐基板
CSUB‧‧‧矽基板
CTE1‧‧‧TEOS膜
CTE2‧‧‧TEOS膜
CV‧‧‧貫穿通路
CWF1‧‧‧鎢膜
CWF2‧‧‧鎢膜
FD‧‧‧浮置擴散區域
IL1‧‧‧第1層間絕緣膜
IL2‧‧‧第2層間絕緣膜
IL3‧‧‧層間絕緣膜
IS‧‧‧攝影裝置
K1‧‧‧步驟
K2‧‧‧步驟
K3‧‧‧步驟
K4‧‧‧步驟
K5‧‧‧步驟
K6‧‧‧步驟
K7‧‧‧步驟
K8‧‧‧步驟
M1‧‧‧第1配線
M2‧‧‧第2配線
M3‧‧‧第3配線
ML‧‧‧微透鏡
PAD‧‧‧電極墊
PD‧‧‧光電二極體
PG‧‧‧導電性插塞
PR1‧‧‧光阻圖形
PR2‧‧‧光阻圖形
PR3‧‧‧光阻圖形
PR4‧‧‧光阻圖形
PR5‧‧‧光阻圖形
PR6‧‧‧光阻圖形
PR7‧‧‧光阻圖形
PR8‧‧‧光阻圖形
PR9‧‧‧光阻圖形
PR10‧‧‧光阻圖形
PR11‧‧‧光阻圖形
SBS‧‧‧SOI基板
SF‧‧‧遮光膜
SLR‧‧‧密封環
SNF‧‧‧氮化矽膜
SOF1‧‧‧氧化矽膜
SOF2‧‧‧氧化矽膜
SOF3‧‧‧氧化矽膜
SOH‧‧‧開口部
SOH1‧‧‧開口部
SOH2‧‧‧開口部
SOI‧‧‧矽層
SRL‧‧‧切割線
STI‧‧‧分割區域
SUB1‧‧‧支撐基板
SUB2‧‧‧支撐基板
TB1‧‧‧壁型導電性貫穿部
TB2‧‧‧框型導電性貫穿部
TB3‧‧‧框型導電性貫穿部
TB4‧‧‧框型導電性貫穿部
TB5‧‧‧框型導電性貫穿部
TFR‧‧‧晶片形成區域
TGE‧‧‧閘極
TH1‧‧‧溝型貫穿孔
TH2‧‧‧溝型貫穿孔
TH3‧‧‧溝型貫穿孔
TT‧‧‧傳送電晶體
V1‧‧‧第1通路
V2‧‧‧第2通路AF‧‧‧Aluminum film
ALM‧‧‧ calibration mark
ARC‧‧‧Anti-reflection film
BOX‧‧‧Embedded oxide film
CARC‧‧‧Anti-reflection film
CCF‧‧‧ color filter
CCH1‧‧‧ contact hole
CCH2‧‧‧ contact hole
CCP‧‧‧Contact pads
CF‧‧‧ color filter
CH‧‧‧Contact hole
CIC‧‧‧ wiring electrode
CIS‧‧‧Photographic device
CK1‧‧‧ steps
CK2‧‧‧ steps
CK3‧‧‧ steps
CK4‧‧‧ steps
CK5‧‧‧ steps
CK6‧‧‧ steps
CK7‧‧‧ steps
CK8‧‧‧ steps
CLR‧‧‧Receiving Department
CM‧‧‧ wiring
CML‧‧‧microlens
CPG‧‧‧ plug
CSO1‧‧‧矽 substrate
CSO2‧‧‧Oxide film
CSO3‧‧‧Oxide film
CSO4‧‧‧Oxide film
CSS‧‧‧Support substrate
CSUB‧‧‧矽 substrate
CTE1‧‧‧TEOS film
CTE2‧‧‧TEOS film
CV‧‧‧through path
CWF1‧‧‧Tungsten film
CWF2‧‧‧Tungsten film
FD‧‧‧Floating diffusion area
IL1‧‧‧1st interlayer insulating film
IL2‧‧‧Second interlayer insulating film
IL3‧‧‧ interlayer insulating film
IS‧‧‧Photographic device
K1‧‧‧ steps
K2‧‧‧ steps
K3‧‧‧ steps
K4‧‧‧ steps
K5‧‧‧ steps
K6‧‧‧ steps
K7‧‧‧ steps
K8‧‧‧ steps
M1‧‧‧1st wiring
M2‧‧‧2nd wiring
M3‧‧‧3rd wiring
ML‧‧‧microlens
PAD‧‧‧electrode pad
PD‧‧‧Photoelectric diode
PG‧‧‧conductive plug
PR1‧‧‧ photoresist pattern
PR2‧‧‧ photoresist pattern
PR3‧‧‧ photoresist pattern
PR4‧‧‧ photoresist pattern
PR5‧‧‧ photoresist pattern
PR6‧‧‧ photoresist pattern
PR7‧‧‧ photoresist pattern
PR8‧‧‧ photoresist pattern
PR9‧‧‧ photoresist pattern
PR10‧‧‧ photoresist pattern
PR11‧‧‧ photoresist pattern
SBS‧‧‧SOI substrate
SF‧‧‧shade film
SLR‧‧‧Seal ring
SNF‧‧‧ nitride film
SOF1‧‧‧Oxide film
SOF2‧‧‧Oxide film
SOF3‧‧‧Oxide film
SOH‧‧‧ openings
SOH1‧‧‧ openings
SOH2‧‧‧ openings
SOI‧‧‧ layer
SRL‧‧‧ cutting line
STI‧‧‧ segmented area
SUB1‧‧‧Support substrate
SUB2‧‧‧Support substrate
TB1‧‧‧ wall-type conductive penetration
TB2‧‧‧Frame type conductive penetration
TB3‧‧‧Frame type conductive penetration
TB4‧‧‧Frame type conductive penetration
TB5‧‧‧Frame type conductive penetration
TFR‧‧‧ wafer formation area
TGE‧‧‧ gate
TH1‧‧‧ groove type through hole
TH2‧‧‧ groove type through hole
TH3‧‧‧ groove type through hole
TT‧‧‧Transmission transistor
V1‧‧‧1st pathway
V2‧‧‧2nd pathway
圖1係顯示第1實施形態之攝影裝置切割前的狀態之部分平面圖。 圖2係該第1實施形態中圖1所示之截面線II-II的截面圖。 圖3係顯示該第1實施形態中配置有電極墊之區域的部分放大平面圖。 圖4係顯示該第1實施形態中攝影裝置之製造方法的一製程之截面圖。 圖5係顯示該第1實施形態中在圖4所示之製程後進行的製程之截面圖。 圖6係顯示該第1實施形態中在圖5所示之製程後進行的製程之截面圖。 圖7係顯示該第1實施形態中在圖6所示之製程後進行的製程之截面圖。 圖8係顯示該第1實施形態中在圖7所示之製程後進行的製程之截面圖。 圖9係顯示該第1實施形態中在圖8所示之製程後進行的製程之截面圖。 圖10係顯示該第1實施形態中在圖9所示之製程後進行的製程之截面圖。 圖11係顯示該第1實施形態中在圖10所示之製程後進行的製程之截面圖。 圖12係顯示該第1實施形態中在圖11所示之製程後進行的製程之截面圖。 圖13係顯示該第1實施形態中在圖12所示之製程後進行的製程之截面圖。 圖14係顯示該第1實施形態中在圖13所示之製程後進行的製程之截面圖。 圖15係顯示該第1實施形態中在圖14所示之製程後進行的製程之截面圖。 圖16係顯示該第1實施形態中在圖15所示之製程後進行的製程之截面圖。 圖17係顯示該第1實施形態中在圖16所示之製程後進行的製程之截面圖。 圖18係顯示該第1實施形態中在圖17所示之製程後進行的製程之截面圖。 圖19係顯示比較例之攝影裝置之製造方法的一製程之截面圖。 圖20係顯示在圖19所示之製程後進行的製程之截面圖。 圖21係顯示在圖20所示之製程後進行的製程之截面圖。 圖22係顯示在圖21所示之製程後進行的製程之截面圖。 圖23係顯示在圖22所示之製程後進行的製程之截面圖。 圖24係顯示在圖23所示之製程後進行的製程之截面圖。 圖25係顯示在圖24所示之製程後進行的製程之截面圖。 圖26係顯示在圖25所示之製程後進行的製程之截面圖。 圖27係顯示在圖26所示之製程後進行的製程之截面圖。 圖28係顯示在圖27所示之製程後進行的製程之截面圖。 圖29係顯示在圖28所示之製程後進行的製程之截面圖。 圖30係顯示在圖29所示之製程後進行的製程之截面圖。 圖31係將比較例之攝影裝置之製程的一部分顯示為流程圖之圖。 圖32係將該第1實施形態中攝影裝置之製程的一部分顯示為流程圖之圖。 圖33係顯示該第1實施形態中配置有第1變形例之攝影裝置的電極墊之區域的部分放大平面圖。 圖34係顯示該第1實施形態中該第2變形例之攝影裝置的截面圖，其係對應圖1所示之截面線XXXIV-XXXIV的截面線之截面圖。 圖35係第2實施形態之攝影裝置的截面圖。 圖36係顯示該第2實施形態中配置有電極墊之區域的部分放大平面圖。 圖37係顯示該第2實施形態中攝影裝置之製造方法的一製程之截面圖。 圖38係顯示該第2實施形態中在圖37所示之製程後進行的製程之截面圖。 圖39係顯示該第2實施形態中在圖38所示之製程後進行的製程之截面圖。 圖40係顯示該第2實施形態中在圖39所示之製程後進行的製程之截面圖。 圖41係顯示該第2實施形態中在圖40所示之製程後進行的製程之截面圖。 圖42係顯示該第2實施形態中在圖41所示之製程後進行的製程之截面圖。 圖43係顯示該第2實施形態中在圖42所示之製程後進行的製程之截面圖。 圖44係顯示該第2實施形態中在圖43所示之製程後進行的製程之截面圖。 圖45係顯示該第2實施形態中在圖44所示之製程後進行的製程之截面圖。 圖46係顯示該第2實施形態中在圖45所示之製程後進行的製程之截面圖。 圖47係顯示該第2實施形態中在圖46所示之製程後進行的製程之截面圖。 圖48係顯示該第2實施形態中在圖47所示之製程後進行的製程之截面圖。 圖49係顯示該第2實施形態中在圖48所示之製程後進行的製程之截面圖。 圖50係顯示該第2實施形態中在圖49所示之製程後進行的製程之截面圖。 圖51係顯示各實施形態中配置有第1變形例之攝影裝置的電極墊之區域的部分放大平面圖。 圖52係顯示各實施形態中配置有第2變形例之攝影裝置的電極墊之區域的部分放大平面圖。 圖53係顯示各實施形態中配置有第3變形例之攝影裝置的電極墊之區域的部分放大平面圖。Fig. 1 is a partial plan view showing a state before cutting of the image pickup apparatus of the first embodiment. Fig. 2 is a cross-sectional view taken along line II-II of Fig. 1 in the first embodiment. Fig. 3 is a partially enlarged plan view showing a region in which an electrode pad is placed in the first embodiment. Fig. 4 is a cross-sectional view showing a process of the manufacturing method of the image pickup apparatus in the first embodiment. Fig. 5 is a cross-sectional view showing a process performed after the process shown in Fig. 4 in the first embodiment. Fig. 6 is a cross-sectional view showing a process performed after the process shown in Fig. 5 in the first embodiment. Fig. 7 is a cross-sectional view showing a process performed after the process shown in Fig. 6 in the first embodiment. Fig. 8 is a cross-sectional view showing a process performed after the process shown in Fig. 7 in the first embodiment. Fig. 9 is a cross-sectional view showing a process performed after the process shown in Fig. 8 in the first embodiment. Fig. 10 is a cross-sectional view showing a process performed after the process shown in Fig. 9 in the first embodiment. Fig. 11 is a cross-sectional view showing a process performed after the process shown in Fig. 10 in the first embodiment. Fig. 12 is a cross-sectional view showing a process performed after the process shown in Fig. 11 in the first embodiment. Fig. 13 is a cross-sectional view showing a process performed after the process shown in Fig. 12 in the first embodiment. Fig. 14 is a cross-sectional view showing a process performed after the process shown in Fig. 13 in the first embodiment. Fig. 15 is a cross-sectional view showing a process performed after the process shown in Fig. 14 in the first embodiment. Fig. 16 is a cross-sectional view showing a process performed after the process shown in Fig. 15 in the first embodiment. Fig. 17 is a cross-sectional view showing a process performed after the process shown in Fig. 16 in the first embodiment. Fig. 18 is a cross-sectional view showing a process performed after the process shown in Fig. 17 in the first embodiment. Figure 19 is a cross-sectional view showing a process of a manufacturing method of a photographing apparatus of a comparative example. Figure 20 is a cross-sectional view showing the process performed after the process shown in Figure 19. Figure 21 is a cross-sectional view showing a process performed after the process shown in Figure 20. Figure 22 is a cross-sectional view showing the process performed after the process shown in Figure 21. Figure 23 is a cross-sectional view showing the process performed after the process shown in Figure 22. Figure 24 is a cross-sectional view showing the process performed after the process shown in Figure 23. Figure 25 is a cross-sectional view showing the process performed after the process shown in Figure 24. Figure 26 is a cross-sectional view showing the process performed after the process shown in Figure 25. Figure 27 is a cross-sectional view showing the process performed after the process shown in Figure 26. Figure 28 is a cross-sectional view showing the process performed after the process shown in Figure 27. Figure 29 is a cross-sectional view showing the process performed after the process shown in Figure 28. Figure 30 is a cross-sectional view showing the process performed after the process shown in Figure 29. Fig. 31 is a view showing a part of the process of the photographing apparatus of the comparative example as a flowchart. Fig. 32 is a view showing a part of the process of the image forming apparatus in the first embodiment as a flowchart. Fig. 33 is a partially enlarged plan view showing a region in which the electrode pads of the imaging device according to the first modification are arranged in the first embodiment. Fig. 34 is a cross-sectional view showing the image forming apparatus according to the second modification of the first embodiment, which is a cross-sectional view corresponding to the cross-sectional line XXXIV-XXXIV shown in Fig. 1. Figure 35 is a cross-sectional view showing a photographing apparatus of a second embodiment. Fig. 36 is a partially enlarged plan view showing a region in which an electrode pad is disposed in the second embodiment. Fig. 37 is a cross-sectional view showing a process of the manufacturing method of the image pickup apparatus in the second embodiment. Fig. 38 is a cross-sectional view showing the process performed after the process shown in Fig. 37 in the second embodiment. Fig. 39 is a cross-sectional view showing the process performed after the process shown in Fig. 38 in the second embodiment. Fig. 40 is a cross-sectional view showing a process performed after the process shown in Fig. 39 in the second embodiment. Fig. 41 is a cross-sectional view showing the process performed after the process shown in Fig. 40 in the second embodiment. Fig. 42 is a cross-sectional view showing the process performed after the process shown in Fig. 41 in the second embodiment. Fig. 43 is a cross-sectional view showing the process performed after the process shown in Fig. 42 in the second embodiment. Fig. 44 is a cross-sectional view showing the process performed after the process shown in Fig. 43 in the second embodiment. Fig. 45 is a cross-sectional view showing the process performed after the process shown in Fig. 44 in the second embodiment. Fig. 46 is a cross-sectional view showing the process performed after the process shown in Fig. 45 in the second embodiment. Fig. 47 is a cross-sectional view showing the process performed after the process shown in Fig. 46 in the second embodiment. Fig. 48 is a cross-sectional view showing the process performed after the process shown in Fig. 47 in the second embodiment. Fig. 49 is a cross-sectional view showing the process performed after the process shown in Fig. 48 in the second embodiment. Fig. 50 is a cross-sectional view showing a process performed after the process shown in Fig. 49 in the second embodiment. Fig. 51 is a partially enlarged plan view showing a region in which the electrode pads of the imaging device according to the first modification are arranged in the respective embodiments. Fig. 52 is a partially enlarged plan view showing a region in which electrode pads of the imaging device according to the second modification are arranged in the respective embodiments. Fig. 53 is a partially enlarged plan view showing a region in which the electrode pads of the imaging device according to the third modification are arranged in the respective embodiments.
無。no.
ARC‧‧‧反射防止膜 ARC‧‧‧Anti-reflection film
CF‧‧‧濾色片 CF‧‧‧ color filter
FD‧‧‧浮置擴散區域 FD‧‧‧Floating diffusion area
IL1‧‧‧第1層間絕緣膜 IL1‧‧‧1st interlayer insulating film
IL2‧‧‧第2層間絕緣膜 IL2‧‧‧Second interlayer insulating film
IL3‧‧‧層間絕緣膜 IL3‧‧‧ interlayer insulating film
IS‧‧‧攝影裝置 IS‧‧‧Photographic device
M1‧‧‧第1配線 M1‧‧‧1st wiring
M2‧‧‧第2配線 M2‧‧‧2nd wiring
M3‧‧‧第3配線 M3‧‧‧3rd wiring
ML‧‧‧微透鏡 ML‧‧‧microlens
PAD‧‧‧電極墊 PAD‧‧‧electrode pad
PD‧‧‧光電二極體 PD‧‧‧Photoelectric diode
PG‧‧‧導電性插塞 PG‧‧‧conductive plug
SBS‧‧‧SOI基板 SBS‧‧‧SOI substrate
SF‧‧‧遮光膜 SF‧‧‧shade film
SNF‧‧‧氮化矽膜 SNF‧‧‧ nitride film
SOF1‧‧‧氧化矽膜 SOF1‧‧‧Oxide film
SOF2‧‧‧氧化矽膜 SOF2‧‧‧Oxide film
SOF3‧‧‧氧化矽膜 SOF3‧‧‧Oxide film
SOI‧‧‧矽層 SOI‧‧‧ layer
STI‧‧‧分割區域 STI‧‧‧ segmented area
SUB2‧‧‧支撐基板 SUB2‧‧‧Support substrate
TB1‧‧‧壁型導電性貫穿部 TB1‧‧‧ wall-type conductive penetration
TFR‧‧‧晶片形成區域 TFR‧‧‧ wafer formation area
TGE‧‧‧閘極 TGE‧‧‧ gate
TH3‧‧‧溝型貫穿孔 TH3‧‧‧ groove type through hole
TT‧‧‧傳送電晶體 TT‧‧‧Transmission transistor
V1‧‧‧第1通路 V1‧‧‧1st pathway
V2‧‧‧第2通路 V2‧‧‧2nd pathway
Claims (12)
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| JP2014251855A JP6353354B2 (en) | 2014-12-12 | 2014-12-12 | Imaging device and manufacturing method thereof |
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| TW201633520A true TW201633520A (en) | 2016-09-16 |
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| JP (1) | JP6353354B2 (en) |
| KR (1) | KR20160072028A (en) |
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| JP6200835B2 (en) | 2014-02-28 | 2017-09-20 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| TWI655753B (en) * | 2015-03-11 | 2019-04-01 | 日商新力股份有限公司 | Solid-state imaging device and manufacturing method, semiconductor wafer, and electronic device |
| FR3037720A1 (en) * | 2015-06-19 | 2016-12-23 | St Microelectronics Crolles 2 Sas | ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME |
| KR102646901B1 (en) * | 2016-12-23 | 2024-03-12 | 삼성전자주식회사 | Image sensor and method of manufacturing the same |
| CN107634074B (en) * | 2017-08-16 | 2020-02-21 | 上海微阱电子科技有限公司 | CMOS image sensor structure for preventing scribing damage and manufacturing method thereof |
| EP3719841B1 (en) * | 2019-04-01 | 2022-02-16 | Detection Technology Oy | Radiation sensor element and method |
| US20220384515A1 (en) * | 2019-11-08 | 2022-12-01 | Sony Semiconductor Solutions Corporation | Imaging element and imaging device |
| JP2023144526A (en) * | 2022-03-28 | 2023-10-11 | ソニーセミコンダクタソリューションズ株式会社 | Light detecting device and electronic apparatus |
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| US7453158B2 (en) * | 2003-07-31 | 2008-11-18 | Nvidia Corporation | Pad over active circuit system and method with meshed support structure |
| JP3962402B2 (en) * | 2003-11-10 | 2007-08-22 | 松下電器産業株式会社 | Semiconductor device |
| CN1617312A (en) * | 2003-11-10 | 2005-05-18 | 松下电器产业株式会社 | Semiconductor device and method for fabricating the same |
| JP4046069B2 (en) | 2003-11-17 | 2008-02-13 | ソニー株式会社 | Solid-state imaging device and manufacturing method of solid-state imaging device |
| JPWO2009113262A1 (en) * | 2008-03-11 | 2011-07-21 | パナソニック株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| KR20090128899A (en) * | 2008-06-11 | 2009-12-16 | 크로스텍 캐피탈, 엘엘씨 | Backside illuminated image sensor and method for manufacturing the same |
| JP2011014674A (en) | 2009-07-01 | 2011-01-20 | Panasonic Corp | Method for manufacturing solid-state image pickup device |
| JP2011086709A (en) * | 2009-10-14 | 2011-04-28 | Toshiba Corp | Solid-state imaging device and method for manufacturing same |
| JP2011243656A (en) * | 2010-05-14 | 2011-12-01 | Toshiba Corp | Solid-state imaging device and manufacturing method thereof |
| US8435824B2 (en) * | 2011-07-07 | 2013-05-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside illumination sensor having a bonding pad structure and method of making the same |
| JP2013041878A (en) * | 2011-08-11 | 2013-02-28 | Sony Corp | Imaging apparatus and camera module |
| JP5696081B2 (en) * | 2012-03-23 | 2015-04-08 | 株式会社東芝 | Solid-state imaging device |
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| US20170345863A1 (en) | 2017-11-30 |
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| CN105702693A (en) | 2016-06-22 |
| JP6353354B2 (en) | 2018-07-04 |
| KR20160072028A (en) | 2016-06-22 |
| JP2016115757A (en) | 2016-06-23 |
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