TW201631617A - Sub-pulsing during a state - Google Patents

Abstract

A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.

Description

Secondary pulsation during a state

Embodiments of the invention relate to generating a plurality of pulsations during a state of a radio frequency (RF) generator.

The plasma chamber is used for various processes such as etching, deposition, and the like. For example, when energy is supplied to the plasma chamber, gas is supplied to the plasma chamber. When the gas is in the plasma chamber and the energy is supplied at the same time, the slurry is hit. The plasma is used to etch the substrate or to clean the plasma chamber. Also, using a liquid or gas to flow into the plasma chamber, the material can be deposited onto the substrate.

However, controlling the process is difficult. For example, the material on the substrate may be over-etched or under-etched. As another example, the thickness of the plurality of film layers deposited on the substrate may be thicker than the desired thickness or thinner than the desired thickness.

The examples in this application are produced in this context.

Embodiments of the present invention provide apparatus, methods, and computer programs for secondary pulsations during a state. It will be appreciated that embodiments of the invention may be implemented in various ways, such as in a process, apparatus, system, apparatus, or computer readable medium. Several embodiments are described below.

In certain embodiments, a method of achieving a secondary pulsation during a state is disclosed. The method includes receiving a clock signal from a clock source and generating a pulse signal from the clock signal, the clock signal having two states. The pulsation signal has a plurality of states in one of the states of the complex state. The plurality of states alternate with respect to each other at a frequency greater than one of the states. The method includes providing the pulsation signal to control a power of a radio frequency (RF) signal generated by an RF generator. The power is controlled to be synchronized with the pulsation signal.

In various embodiments, an RF generator is disclosed. The RF generator includes a processor. The processor receives a clock signal from a clock source. The clock signal has two states. The processor generates a pulse signal from the clock signal. The pulsation signal has a plurality of states in one of the states of the complex state. The plurality of states have a frequency greater than one of the states. The processor provides the pulse signal to control a power of an RF signal. This power is controlled to synchronize with the pulsation signal. The RF generator includes an RF power source coupled to the processor. The RF power source generates the RF signal having the power to provide the RF signal to a plasma chamber by an impedance matching circuit.

In various embodiments, a plasma system is disclosed. The plasma system includes a processor that receives a clock signal from a clock source. The clock signal has two states. The processor generates a pulse signal from the clock signal. The pulsation signal has a plurality of states in one of the states of the complex state and the plurality of states have a frequency greater than a frequency of the states. The processor provides a pulse signal to control a power of a radio frequency (RF) signal. This power is controlled to synchronize with the pulsation signal. The plasma system further includes an RF power source for generating the RF signal having the power. The plasma system also includes an RF cable coupled to one of the RF power sources. The plasma system includes an impedance matching circuit coupled to the RF power source for receiving the RF signal by the RF cable. The impedance matching circuit matches an impedance coupled to a load of one of the impedance matching circuits and an impedance coupled to a source of the impedance matching circuit to generate a modified RF signal from the RF signal. The plasma system includes a plasma chamber coupled to the impedance matching circuit for receiving the modified RF signal to change an impedance of a plasma.

Some of the advantages of the above embodiments use a secondary pulsation in a state to produce a plurality of states within the state. When the pulsation system is used by a low frequency RF generator (such as a 2 MHz RF generator, etc.), the wafer processing can be roughly controlled, such as a substrate, a substrate on which one or more materials or one or more layers are deposited. Wait. For example, when the RF signal generated by the low frequency RF generator is pulsed in a state compared to the RF signal that is not pulsed, the material etching or deposition on the substrate can be further roughly controlled. Also, when the secondary pulsation system is used by a high frequency RF generator such as a 60 MHz RF generator, the wafer processing can be finely controlled. For example, when the RF signal generated by the high frequency RF generator is pulsed in a state, the material etching or deposition on the substrate can be further finely controlled, for example, compared to the RF signal that is not pulsed. It should be noted that in some embodiments, the meticulous control is to achieve a range of rates that fall within a range of rates associated with coarse control.

Other aspects of the invention will be apparent from the accompanying drawings and appended claims.

The following embodiments illustrate systems and methods for secondary pulsations in a state. It will be appreciated that embodiments of the invention may be practiced without some or all of the specific details. In other instances, well-known process operations are not described in detail to avoid unnecessarily obscuring embodiments of the invention.

1 shows an embodiment of a radio frequency (RF) generator 100 for illustrating a secondary pulsation within a state. The RF generator 100 receives a clock signal (such as a transistor-transistor logic (TTL) signal, etc.) or generates a clock signal. For example, the RF generator 100 receives a clock signal from a clock source or includes a clock source capable of generating a clock signal. Examples of clock sources include oscillators (such as quartz oscillators, etc.) or oscillators coupled to a phase-locked loop. The clock signal has a state Sm, where m is 1 or 0. For example, the clock signal has a high state and a low state, and the low state is lower than the high state. For another example, the clock signal has a logic level 1 and a logic level 0.

The RF generator 100 generates a pulsation signal from a clock signal having a state Sm. For example, RF generator 100 generates a pulsation signal that is switched from state Sm to state Sna and then further to state Snb, where n is 0 or 1. The frequency of the pulsation signal generated by the RF generator 100 is higher than the frequency of the clock signal having the state Sm. For example, the frequency signal of the pulsation signal during the state S1 or S0 is higher than the frequency that the clock signal has during the state S1 and the state S0. For another example, the frequency signal of the pulsation signal during the states S1 and S0 is higher than the frequency that the clock signal has during the state S1 and the state S0.

In some embodiments, state S1 has a power level that is higher than the power level of state S0. For example, the power level of the RF signal with state S1 is 2000 watts, and the power level of the RF signal during state S0 is 0 watts. For another example, the power level of the RF signal having state S1 is higher than 0 watts, and the power level of the RF signal during state S0 is 0 watt. For example, the power level of the RF signal during the state S0 is higher than 0 watts, and the power level of the RF signal during the state S1 is higher than the power level of the RF signal during the state S0.

The states Sna and Snb are embedded in the state S1 or the state S0 of the clock signal. For example, states Sna and Snb occupy one of the complex states Sm. For another example, states S1a and S1b occupy state S1 but do not occupy state S0. Still more, for example, states S0a and S0b occupy state S0 but do not occupy state S1.

As illustrated in FIG. 102, the pulsation signal having the states Sna and Snb transitions from the state Sna to the state Snb, and then further transitions from the state Snb to the state Sna, then from the state Sna to the state Snb, and then to the state Sm.

2A is an embodiment of FIG. 200, and is used to illustrate a secondary pulsation in one of the states of an x-megahertz (MHz) RF generator, where x is two. In some embodiments the x system falls within the predetermined range 2. For example, x is falling within 2 MHz. As another example, x is 2.5. Still more, for example, x is 1.5.

In various embodiments, x is 27. In various embodiments, the x system falls within a predetermined range 27. For example, x is falling within 2 MHz of 27. As another example, x is 25.5. Still more, for example, x is 29. Still more, for example, the x system falls within 5 MHz of 27.

The graph 200 shows the relationship between the logic level of the pulse signal 202 and the like, and the time unit is seconds. The pulsation signal 202 is generated by a clock signal 204 such as a TTL1 signal. For example, the pulsation signal 202 is generated from the clock signal 204 by modulating the clock signal 204 with a modulation signal such as a TTL2 signal. For another example, when the amplitude (such as the power level) of the pulse signal 204 is multiplied by the same signal amplitude as the amplitude of the pulsation signal 202, the pulsation signal 202 is generated. The pulsation signal 202 is an example of the digital pulsation signal TTL3.

During the state S0 of the clock signal 204, the pulsation signal 202 has a logic level such as a logic level 0, a logic level 0.5, a logic level 0.2, and the like. During the state S1 of the clock signal 204, the pulsation signal 202 has a complex logic level, such as logic level 1 and logic level 0, logic level 0.5 and logic level 1, logic level 0.9, logic level 0, etc. . During state S1 of clock signal 204, pulsation signal 202 transitions between states S1a and S1b, for example, alternate. The switching frequency between states S1a and S1b of the pulsation signal 202 is higher than the switching frequency between states S1 and S0 of the clock signal 204. For example, the switching frequency between states S1b and S1a is four times the switching frequency between states S0 and S1. For another example, the switching frequency between states S1b and S1a is five times the switching frequency between states S0 and S1. Still more, for example, the switching frequency between states S1b and S1a is between two and 100 times the switching frequency between states S0 and S1.

It should be noted that in various embodiments, the pulsation of the signal 202 between the states S1a and S1b may promote chemical deadlock (such as the time of gas entry, etc.) to occur in the plasma chamber, or to achieve a pressure within the plasma chamber, or to reach The plasma chamber is brought to a temperature or a gap is formed between the electrode below the plasma chamber and the upper electrode. Again, in some embodiments, pulsing of the signal 202 between states S1a and S1b is performed to control etching of the substrate or film deposition on the substrate. In several embodiments, the pulsation energy of the signal 202 between the states S1a and S1b is reduced to the features of the deposited film layer, germanium, wiring, etc. of the wafer or the substrate having the integrated circuit thereon (eg, circuit components) The opportunity to create energy that causes damage. Also, in some embodiments, state S1a can promote the generation of ions in the plasma chamber, while state S1b can promote the movement of ions within the plasma chamber to enhance, for example, etching, cleaning, and reducing deposition rates (and phase S0). Than) and other processes.

It should be noted that the amount of power generated by the x MHz RF generator during state S0 of clock signal 204 is less than the amount of power generated during states S1a and S1b of pulse signal 204. A smaller amount of power causes the ion energy of the plasma ions to be less than the ion energy and/or ion density generated during the states S1a and S1b less than the ion density generated during the states S1a and S1b.

2B is an embodiment of FIG. 210 illustrating the use of an x MHz RF generator and a y MHz RF generator. Examples of y include 27 and 60. In certain embodiments, the y system falls within a predetermined range 27. For example, the y system is between 25 and 29 MHz. As another example, the y system is between 57 and 63 MHz. Still more, for example, the y system is between 24 and 30 MHz. As another example, the y is between 55 and 65 MHz.

In certain embodiments, when x is 2, y is 27. In various embodiments, when x is 27, y is 60. In several embodiments, when x is 2, y is 60.

Figure 210 illustrates the relationship between the delivered power of the RF signal generated by the RF generator and time. It should be noted that the delivered power is the difference between the feed forward power and the reflected power. In some embodiments, the feed forward power is the power generated by the RF generator and supplied to the plasma chamber, the reflected power being the power reflected from the plasma chamber toward the RF generator.

The map 210 includes an RF signal 212 that is similar to the pulsation signal 202 (Fig. 2A). For example, RF signal 212 has states S0, S1a, and S1b and transitions between states S0, S1a, and S1b in a manner that pulsation signal 202 transitions between such states. The frequency of the RF signal 212 and the frequency of the pulsation signal 202 are the same as the frequency of the TTL3 signal. The RF signal 212 is generated from the delivered power, and the transmitted power is generated based on the RF signal supplied by the x MHz RF generator and the RF signal reflected toward the x MHz RF generator.

During state S0 of RF signal 212, the y MHz generator supplies an RF signal. When the y MHz RF generator supplies the RF signal, power is reflected from the plasma chamber toward the y MHz RF generator to further produce the delivered power RF signal 214. The RF signal 214 has a state S0 and has a frequency that is the same as the frequency of the TTL1 signal. Also, during states S1a and S1b of RF signal 212, RF signal 214 has state S1. The RF signal 212 is switched between states S1 and S0. For example, when RF signal 212 transitions between states S0, S1a, and S1b, RF signal 214 transitions between states S1 and S0.

2C is an embodiment of FIG. 220, and FIG. 220 is used to illustrate a pulse signal 222 having a non-zero logic level during state S1b. The pulsation signal 222 is similar to the pulsation signal 202 (FIG. 2B) except that the pulsation signal 222 has a non-zero logic level during state S1b. For example, the pulsation signal 222 is generated in a manner similar to the pulsation signal 202 except that the pulsation signal 222 drops from the state S1a to the state S1b (the level of the state S1b is higher than the state of the sway signal 204 state S0). Then, the pulsation signal 222 is dropped from the level of the state S1b to the level of the state S0 to transition from the state S1b to the state S0. The pulsation signal 222 has a frequency that is the same as the frequency of the digital pulsation signal TTL3.

2D is an embodiment of FIG. 230, and is used to illustrate a pulse signal 232 having a non-zero logic level during state S1b in conjunction with the pulse signal 214 generated by the y MHz RF generator. The pulsation signal 232 is similar to the pulsation signal 212 (FIG. 2B) except that the pulsation signal 232 has a non-zero logic level during state S1b. For example, the pulsation signal 232 is generated in a manner similar to the pulsation signal 212, except that the pulsation signal 232 transitions from the state S1a to a higher level than the transmitted power level of the state S0 of the pulsation signal 214. The higher level is reached during state S1b. After reaching a higher level during state S1b, the pulsation signal 232 transitions to the level of the pulsation signal 214 during state S0. The pulsation signal 232 has the same frequency as the digital pulsation signal TTL3.

It should be noted that although the pulsation signal 214 generated based on the RF signal supplied by the y MHz RF generator is shown to have a high amount of delivered power level of about 100 watts and a low amount of delivered power level of about 10 watts. However, in some embodiments, the pulsation signal 214 has a high power level between 60 watts and 160 watts during state S1 and a low power level between 1 watt and 55 watts during state S0. In various embodiments, the highest power level of the pulsating transmitted power signal generated by the RF signal supplied by the x MHz RF generator during state S1a is higher than that provided by the y MHz RF generator during state S1. The pulsation generated by the RF signal is the highest power level of the transmitted power signal. In some embodiments, the lowest power level of the transmitted power pulsation signal generated based on the RF signal supplied by the x MHz RF generator during state S0 is lower than the y MHz based RF generator during state S0. The lowest power level of the delivered power pulsation signal generated by the supplied RF signal.

In various embodiments, the period of time occupied by state S0 is the same as the period of time occupied by both states S1a and S1b. For example, state S0 occupies half a clock cycle of clock signal TTL1, and states S1a and S1b occupy the remaining half of the clock cycle. In several embodiments, the period of time occupied by state S0 is less than or greater than half of the clock period of clock signal TTL1, and states S1a and S1b occupy the remainder of the clock period.

2E shows an embodiment of FIG. 240, which is used to illustrate a different duty cycle for a non-50% duty cycle during state S1. Figure 240 illustrates the power delivered by a 2 MHz RF generator versus time t. The delivered power is shown as a pulsation signal 242. It should be noted that the duty cycle of signal 242 during state S1 is greater than 50%, and the time occupied during state S1 is equal to the time occupied during state S0. For example, signal 242 occupies more time during state S1a than during state S1b. In some embodiments, the duty cycle of signal 242 during state S1 is less than 50%. For example, the transmitted RF signal occupies less time during state S1a than during state S1b.

It should be noted that each of the signals 202, 212, 222, and 232 (Figs. 2A through 2D) has a duty cycle of 50% during the state S1.

In several embodiments, the state S1 of the power delivered by the x MHz RF generator occupies a state in which the time is less than the power delivered by the x MHz RF generator. In such embodiments, the delivered power has a duty cycle of 50% during state S1.

In various embodiments, state S1 of the power delivered by the x MHz RF generator occupies a state in which the time is less than or more than the power delivered by the x MHz RF generator. In such embodiments, the duty cycle of the delivered power during state S1 is greater than or less than 50%.

In some embodiments, the TTL signal has a frequency equal to the frequency that the pulsation signal 242 has during state S1. The TTL signal is generated by a device that generates a TTL3 signal. For example, the digital signal processor (DSPx) of the x MHz RF generator described below generates a TTL signal from the TTL1 signal and the modulated signal. The modulation signal modulates the TTL1 signal to generate a TTL signal.

3A shows an embodiment of a system 300 for controlling ion energy during a state S1 of a TTL1 signal. System 300 includes an x MHz RF generator and a y MHz RF generator. System 300 further includes an impedance matching circuit 302, a plasma chamber 304, and a tool user interface (UI) system 306. Examples of the tool UI system 306 include a desktop computer, a server, a virtual machine, a notebook computer, a tablet computer, a mobile phone, a smart phone, and the like. In various embodiments, the tool UI system 306 includes a processor and a memory device, examples of which are provided below. In some embodiments, the tool UI system 306 is coupled to the x and y MHz RF generators by a computer network such as a wide area network (WAN), a local area network (LAN), the Internet, an internal network, and the like.

Impedance matching circuit 302 is coupled to the output of the x MHz RF generator by RF cable 308. Similarly, impedance matching circuit 302 is coupled to the output of the y MHz RF generator by RF cable 310. The impedance matching network 302 matches the impedance of one of the plasma systems 304 coupled to one side of the impedance matching network 302 to the impedance coupled to one of the sources of the other side of the impedance matching network 302. For example, impedance matching network 302 matches the impedance of RF transmission line 312 and plasma system 304 with the impedance of the x MHz RF generator, y MHz RF generator, RF cable 308, and RF cable 310.

The plasma chamber 304 is coupled to the impedance matching circuit 302 by an RF transmission line 312. The plasma chamber 304 includes a collet 314, an upper electrode 316, and other components (not shown), such as an upper dielectric ring surrounding the upper electrode 316, an upper electrode extension surrounding the upper dielectric ring, and an electrode surrounding the lower electrode of the collet 314. The lower dielectric ring, the lower electrode extension surrounding the lower dielectric ring, the upper plasma exclusion zone (PEZ) ring, the lower PEZ ring, and the like. The upper electrode 316 faces the collet 314 and faces it. Wafer 318 (eg, dummy substrate, semiconductor wafer, etc.) is supported on upper surface 320 of chuck 314. Various processes are performed on the semiconductor wafer during fabrication, such as chemical vapor deposition, cleaning, deposition, sputtering, etching, ion implantation, photoresist stripping, and the like. Integral circuits are built on semiconductor wafers, such as special application integrated circuits (ASICs), programmable logic devices (PLDs), etc., and integrated circuits are used in various electronic devices, such as mobile phones, tablets, smart phones, Computers, notebook computers, network devices, etc.

Each of the lower electrode and the upper electrode 316 is made of a metal such as aluminum, aluminum alloy, copper, or the like. The collet 314 can be an electrostatic chuck (ESC) or a magnetic chuck.

The tool UI system 306 includes a clock source capable of generating a clock signal (e.g., a digital pulse signal, a TTL1 signal, etc.), and the clock signal is supplied to the DSPx of the x MHz RF generator by a cable 313. The processor referred to herein may be a central processing unit (CPU), a microprocessor, an ASIC, a PLD, a controller, or the like. The tool UI system 306 also provides the clock signal TTL1 to the DSP (DSPy) of the y MHz RF generator via cable 314. Each of the cables 313 and 314 includes a universal serial bus (USB) cable, a serial cable, a parallel cable, an Ethernet cable, and the like.

The tool UI system 306 provides recipes (eg, data files, etc.) containing performance parameters to each of the x and y MHz RF generators, such as a state duty cycle, an occupation duration interval, and power bits. Quasi, frequency level, etc. For example, the tool UI system 306 provides a recipe to operate the x MHz RF generator to the DSPx and provides a recipe to operate the y MHz RF generator to the DSPy. The recipe is stored in each of DSPx and DSPy.

The DSPx receives the clock signal TTL1 and generates a digital pulse signal such as a TTL3 signal from the clock signal TTL1. For example, the DSPx receives the clock signal TTL1 and modifies the clock signal TTL1 during the state S1 to increase the secondary pulsation during the state S1 of the TTL1 signal. For another example, the DSPx receives the clock signal TTL1 and modifies the clock signal TTL1 during the state S1 to increase the frequency of the clock signal TTL1 during the state S1 to generate the digital pulse signal TTL3. In this example, DSPx does not modify the clock signal TTL1 during state S0. For example, the DSPx receives the clock signal TTL1 and includes a clock source that can generate the clock signal TTL2. The clock signal TTL2 has a frequency that is the same as the frequency of the digital pulse signal TTL3 during the state S1. Moreover, the clock signal TTL1 has a frequency that is the same as the frequency of the clock signal TTL3 during the state S0. The DSPx multiplies the clock signal TTL1 by the clock signal TTL2 to generate the clock signal TTL3.

In several embodiments, the DSPx includes a clock source capable of generating the clock signal TTL1, rather than receiving the clock signal TTL1 from the tool UI system 306. In various embodiments, the x MHz RF generator includes a clock source capable of generating a clock signal TTL1, rather than receiving a clock signal TTL1 from the tool UI system 306.

In various embodiments, the clock signal TTL2 is received by a clock source located within the tool UI system 306. In some embodiments the clock signal TTL2 is generated by a clock source within the x MHz RF generator.

During the state S1b, the digital pulse signal TTL3 and the clock signal TTL1 for the state S1b are supplied from the DSPx to the power controller PWRS1bx, and the digital pulse signal TTL3 and the clock signal TTL1 for the state S1b are supplied to the automatic frequency adjuster ( AFT) AFTS1bx. For example, the portion of the TTL3 signal having the state S1b from the DSPx is supplied to the power controller PWRS1bx and the regulator AFTS1bx.

In some embodiments, both the power controller of the RF generator and the AFT of the RF generator are components of the DSP of the RF generator. For example, the auto frequency adjusters AFTS0x, AFTS1ax and AFTS1bx of the x MHz RF generator and the power controllers PWRS1ax, PWRS1bx and PWRS0x are all circuits integrated into the circuitry of the DSPx. For another example, the adjusters AFTS0x, AFTS1ax, and AFTS1bx and the power controllers PWRS1ax, PWRS1bx, and PWRS0x are all part of the computer program executed by the DSPx.

The power controller PWRS1bx receives the digital ripple signal TTL3 for state S1b and receives the clock signal TTL1 for state S1 and determines or identifies the power level of the RF signal to be generated and supplied by the x MHz RF generator. The power level of the RF signal to be generated and supplied by the x MHz RF generator has a frequency that is the same as the frequency of the digital ripple signal TTL3 during state S1b. In some embodiments, the power level corresponding to, mapped to, coupled to the TTL3 signal state S1b and to the TTL1 clock signal state S1 is stored in the memory device of the power controller PWRS1bx. Examples of memory devices include read only memory (ROM), random access memory (RAM), or a combination thereof. In some embodiments, the memory device is a flash memory, a redundant array of independent disks (RAID), a hard disk, or the like.

In various embodiments, the power level of the state S1b of the TTL3 signal and the state S1 of the TTL1 signal is based on the processing rate to be achieved (eg, the etch rate to be achieved, the deposition rate to be achieved, the cleaning rate to be achieved, the desired cleaning rate). The sputtering rate, etc. is determined. The etch rate is the etch rate of the wafer 318. The deposition rate is the deposition rate of materials such as polymers, photomasks, monomers, etc. deposited on the wafer 318. The cleaning rate is, for example, the cleaning rate of the wafer 318 by etching, by deposition, by deposition and etching, and the like. The sputtering rate is the sputtering rate of the sputter wafer 318 or the material sputter deposited on the wafer 318.

Moreover, the adjuster AFTS1bx receives the digital pulse signal TTL3 for the state S1b and receives the clock signal TTL1 for the state S1, and determines or identifies the amount of a radio frequency or a series of radio frequencies of the RF signal to be generated by the x MHz RF generator. The number of complex frequencies. In some embodiments, the amount of a radio frequency corresponding to the state S1b of the TTL3 signal and the state S1 corresponding to the TTL1 clock signal or a complex number of radio frequency frequencies is stored in the memory device of the adjuster AFTS1bx.

The power level corresponding to the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal is supplied from the power controller PWRS1bx to the RF power source 322 of the x MHz RF generator. Again, an amount of radio frequency or a complex number of radio frequency frequencies is provided by the regulator AFTS1bx to the RF power source 322. After receiving the power level of the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal and the amount of a radio frequency or a complex number of radio frequency frequencies, the RF power source 322 generates the power level and the radio frequency. A quantity or a number of RF signals of the series of RF frequencies. The RF signal generated by the RF power source 322 is supplied to the impedance matching circuit 302 via the RF cable 308.

Also, during state S1 of the TTL1 signal, DSPy of the y MHz RF generator supplies the clock signal TTL1 to the power controller PWRS1y of the y MHz RF generator. In addition, the DSPy of the y MHz RF generator provides the clock signal TTL1 to the regulator AFTS1y of the y MHz RF generator. After receiving the clock signal TTL1, the power controller PWRS1y determines or recognizes the power level of the RF signal to be generated by the y MHz RF generator. For example, the correspondence between the state of one of the clock signals TTL1 and the power level of one of the RF signals to be generated by the y MHz RF generator (such as matching, linking, one-to-one relationship, etc.) is stored in the memory of the power controller PWRS1y. In the body device.

Moreover, after receiving the clock signal TTL1, the adjuster AFTS1y determines or recognizes the amount of a radio frequency or a complex number of radio frequency frequencies of the RF signal to be generated by the y MHz RF generator. For example, the correspondence between the state of one of the clock signals TTL1 and the amount of a radio frequency of the RF signal to be generated by the y MHz RF generator or the complex number of radio frequency frequencies is stored in the memory device of the adjuster AFTS1y.

The power level corresponding to state S1 is provided from power controller PWRS1y to RF power source 324 of the y MHz RF generator. Again, an amount of radio frequency or a complex number of radio frequency frequencies is provided by the regulator AFTS1y to the RF power source 324. Upon receiving the power level of state S1 and the amount of the radio frequency or the complex number of the series of radio frequencies, RF power source 324 generates a plurality of RFs having the power level and the amount of the radio frequency or the series of radio frequencies. Signal. The RF signal generated by the RF power source 324 is supplied to the impedance matching circuit 302 by the RF cable 310.

It should be noted that in some embodiments DSPx provides TTL3 signals to DSPy by a cable. During state S1, DSPy determines the transition time from state S1a to state S1b and the transition time from state S1b to state S1a based on the TTL3 signal. Also, during state S1, DSPy sends a signal to power controller PWRS1y to adjust at the transition time from state S1a to state S1b or at transition time from state S1b to state S1a, as determined by power controller PWRS1y Power. The determined power is adjusted based on the change in plasma impedance that occurs when the power delivered or supplied by the x MHz RF generator transitions between states S1a and S1b. To compensate for the adjustment of the power delivered or supplied by the x MHz RF generator during transitions between states S1a and S1b, a TTL3 signal is sent from DSPx to DSPy. The adjustment of the power delivered or supplied by the x MHz RF generator causes a change in the impedance of the plasma.

Also, during state S1, DSPy sends a signal to adjuster AFTS1y to adjust the frequency determined by regulator AFTS1y at the transition time from state S1a to state S1b or transition time from state S1b to state S1a. The determined frequency is adjusted based on the change in plasma impedance that occurs when the power supplied by the x MHz RF generator is switched between states S1a and S1b. In order to compensate for the adjustment of the frequency of the RF signal generated by the x MHz RF generator during the transition between states S1a and S1b, a TTL3 signal is sent from DSPx to DSPy. The adjustment of the frequency of the RF signal generated by the x MHz RF generator causes a change in the impedance of the plasma.

It should be further noted that in some embodiments the tool UI system 306 will correlate information related to the TTL3 signal via the cable 314 or another cable similar to the cable 314 (eg, the frequency of the TTL3 signal, the TTL3 signal during the state S1) The duty cycle, the time when the state S1a appears in the TTL3 signal, the time when the state S1b appears in the TTL3 signal, etc.) is supplied to the DSPy instead of the TTL3 signal sent from the DSPx to the DSPy. Another cable connects the tool UI system 306 to the DSPy. For example, the tool UI system 306 provides a data file containing information related to the TTL3 signal to the DSPy. The DSPy includes a virtual phase-locked loop. The signal generated by the virtual phase-locked loop is locked to the frequency of the TTL3 signal and used to adjust the power determined by the power controller PWRS1y and/or to adjust the frequency determined by the adjuster AFTS1y.

The impedance matching circuit 302 matches the impedance of the load and the source to generate RF signals received from the x MHz RF generator during the state S1 of the TTL3 signal state S1b and the TTL1 clock signal and from the y MHz RF during the state S1. The RF signal received by the device produces a modified RF signal. For example, the impedance matching circuit 302 generates a partially modified RF signal corresponding to the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal during the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal. The modified RF signal generated during the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal is transmitted to the lower electrode of the chuck 314 via the RF transmission line 312. Upper electrode 316 includes one or more gas inlets (e.g., holes, etc.) coupled to a central gas feed (not shown). The central gas feed receives one or more process gases from a gas reservoir (not shown). Examples of process gases include oxygen containing gases such as O ₂ . Other examples of process gases include fluorine-containing gases such as tetrafluoromethane, sulfur hexafluoride, hexafluoroethane (C ₂ F ₆ ), and the like. The upper electrode 316 is grounded. Collet 314 is coupled to the x MHz RF generator by RF transmission line 312, impedance matching circuit 302, and RF cable 308. Again, the collet 314 is coupled to the y MHz RF generator by an RF transmission line 312, an impedance matching circuit 302, and an RF cable 310.

In some embodiments, the process gas is supplied between the upper electrode 316 and the chuck 314 and when the x MHz RF generator and/or the y MHz RF generator is in the state S1b by the impedance matching circuit 302 and the RF transmission line 312 When the RF signal is supplied to the chuck 314, the impedance of the plasma in the plasma chamber 304 is affected, such as increase, decrease, and the like. The plasma affected during the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal has ion energy of the plasma ions. The ion energy during the state S1b of the TTL3 signal and the state S1 of the TTL1 clock signal is used to increase the deposition rate of the deposition rate during the state S0 or the state S1a, or to perform etching during the state S0 instead of performing Depositing, or etching the wafer 318 during state S0 rather than not processing wafer 318, or to reduce the etch rate compared to the etch rate during state S1a, or to deposit during state S1a Etching is performed.

Moreover, during the state S1 of the TTL3 signal and the state S1 of the TTL1 signal, the DSPx supplies the digital pulse signal TTL3 and the clock signal TTL1 to the power controller PWRS1ax of the x MHz RF generator. For example, DSPx provides a partial digital pulse signal TTL3 for state S1a and a clock signal TTL1 for state S1 to power controller PWRS1ax. After receiving the digital pulsation signal TTL3 of the state S1a and the clock signal TTL1 of the state S1, the power controller PWRS1ax determines or identifies the power level of the RF signal to be generated by the x MHz RF generator. The power level of the RF signal corresponding to the state S1a of the TTL3 signal and the state S1 of the clock signal TTL1 is stored in the memory device of the power controller PWRS1ax. The power level is supplied to the RF power source 322 during the state S1a of the digital pulse signal TTL3 and the state S1 of the clock signal TTL1.

Moreover, during the state S1 of the TTL3 signal and the state S1 of the TTL1 signal, the DSPx supplies the digital pulse signal TTL3 and the clock signal TTL1 to the adjuster AFTS1ax of the x MHz RF generator. After receiving the digital pulsation signal TTL3 of the state S1a and the clock signal TTL1 of the state S1, the frequency controller AFTS1ax determines or recognizes the amount of the radio frequency of one of the state S1a corresponding to the digital pulsation signal TTL3 and the state S1 of the clock signal TTL1. Or a complex number of RF frequencies. For example, the state S1a of the digital pulse signal TTL3, the state S1 of the clock signal TTL1 and the amount of a radio frequency or a complex number of radio frequency frequencies are stored in the memory device of the adjuster AFTS1ax.

The adjuster AFTS1ax provides the amount of radio frequency or a complex number of the series of radio frequencies to the RF power source 322. The power level of the state S1 of the state S1a and the clock signal TTL1 of the digital pulse signal TTL3 and the state of the radio frequency of the state S1 of the state signal S1a and the clock signal TTL1 of the digital pulse signal TTL3 or After the complex number of series RF frequencies, the RF power source 322 generates the power level with the state S1a of the digital pulse signal TTL3 and the state S1 of the clock signal TTL1 and the amount of the RF frequency or the complex number of RF signals of the series of RF frequencies. .

The impedance matching circuit 302 receives the RF signal generated by the x MHz RF generator for the state S1a of the digital pulse signal TTL3 and the state S1 of the clock signal TTL1 and receives the RF signal generated by the y MHz RF generator for the state S1, and matches the state. The impedance of the load and source during S1a produces a modified RF signal from the RF signal of state S1a. For example, the impedance matching circuit 302 generates a partially modified RF signal corresponding to the state S1a of the TTL3 signal and the state S1 of the TTL1 clock signal during the state S1a. The modified RF signal associated with the state S1a of the digital pulse signal TTL3 and the state S1 of the clock signal TTL1 is transmitted to the chuck 314 via the RF transmission line 312.

After receiving the modified RF signal corresponding to the state S1a of the digital pulse signal TTL3 and the state S1 of the clock signal TTL1, the plasma ions in the plasma chamber 304 are excited for processing, such as increasing compared to the state S0. Or the etching rate of the etching rate during the state S1b, the deposition rate of the deposition rate compared to the state S0 or the state S1b, the cleaning rate of the cleaning rate during the period S0 or the state S1b, the increase compared to the state The sputtering rate of the sputtering rate on the wafer 318 during S0 or state S1b.

During state S0, DSPx provides a digital pulse signal TTL3 to the power controller PWRS0x of the x MHz RF generator. For example, DSPx sends a portion of the digital pulse signal TTL3 corresponding to state S0 to power controller PWRS0x. It should be noted that during state S0, the TTL3 signal is the same as the TTL1 signal. After receiving the digital pulse signal TTL3 associated with state S0, power controller PWRS0x determines or recognizes the power level of state S0. For example, the power level corresponding to state S0 is stored in the memory device of power controller PWRS0x and is recognized from the memory device. The power level is provided by the power controller PWRS0x to the RF power source 322. Upon receiving the power level of state S0, RF power source 322 generates an RF signal having a power level associated with state S0. [00100] Also, during state S0, DSPx provides digital pulse signal TTL3 to regulator AFTS0x of the x MHz RF generator. For example, DSPx provides a portion of the digital pulse signal TTL3 with state S0 to the regulator AFTS0x. After receiving the digital pulsation signal TTL3 corresponding to state S0, the adjuster AFTS0x determines or recognizes the amount of a radio frequency or a complex number of radio frequency frequencies. For example, the adjuster AFTS0x recognizes the amount of the RF frequency or the complex number of the RF frequencies from the memory device of the adjuster AFTS0x. The adjuster AFTS0x provides the amount of radio frequency or a complex number of the series of radio frequencies to the RF power source 322. [00101] During state S0, upon receiving the amount of power associated with state S0 and the amount of the radio frequency or the complex number of radio frequencies, RF power source 322 generates an RF signal corresponding to state S0. The RF signal corresponding to state S0 has the power level associated with state S0 and the amount of the radio frequency or a complex number of the series of radio frequencies. [00102] Also, during the state S0, the DSPy provides the clock signal TTL1 to the power controller PWRS0y and the adjuster AFTS0y of the y MHz RF generator. For example, DSPy sends a portion of the clock signal TTL1 with state S0 to the power controller PWRS0x and the regulator AFTS0y. After receiving the clock signal TTL1 related to the state S0, the power controller PWRS0y determines or recognizes the power level of the RF signal to be generated by the y MHz RF generator, and the adjuster AFTS0y determines or recognizes the RF frequency of the RF signal. Quantity or a complex number of RF frequencies. The power controller PWRS0y provides the power level associated with state S0 to the RF power source 324, and the adjuster AFTS0y provides the amount of the radio frequency or the complex number of the series of radio frequencies to the RF power source 324. After receiving the power level of the state S0 from the power controller PWRS0y and receiving the amount of the radio frequency or the complex quantity of the series of radio frequencies from the adjuster AFTS0y, the RF power source 324 generates the power level and the radio frequency. A quantity or a number of RF signals of the series of RF frequencies. [00103] The impedance matching circuit 302 receives the RF signal supplied by the RF power source 322 by the RF cable 308 during the state S0, and receives the RF signal supplied by the RF power source 324 during the state S0 by the RF cable 310, and is based on These RF signals match the impedance of the load to the source to produce a modified RF signal of state S0. The modified RF signal associated with state S0 is provided to chuck 304 by RF transmission line 312. [00104] In some embodiments, the modified RF signal corresponding to state S0 can increase the deposition rate of deposited material on wafer 318 compared to the deposition rate on wafer 318 during state S1a or state S1b. In various embodiments, the modified RF signal corresponding to state S0 can reduce the film of wafer 318 compared to the etch rate of the film layer of wafer 318 or film layer 318 during state S1a or state S1b. The etch rate of the film layer on the layer or wafer 318. In several embodiments, the modified RF signal corresponding to state S0 is used to deposit material on wafer 318, the modified RF signal generated during state S1a or modified during state S1b. The RF signal is used to etch the film layer of wafer 318 or the film layer on wafer 318. In some embodiments, a portion of the modified RF signal generated during state S0 is used to generate a plasma slurry or the like within plasma chamber 304. For example, when process gas is supplied to the plasma chamber 304 and one or more of the x and y MHz RF generators are supplied with one or more RF signals, the process gas is ignited to generate electricity in the plasma chamber 304. Pulp. [00105] In various embodiments, the power controllers PWRS0x, PWRS1ax, and PWRS1bx of the x MHz RF generator are connected to a single identical output of DSPx by switches (eg, multiplexers, etc.) rather than generating x MHz RF Each of the power controllers PWRS0x, PWRS1ax, and PWRS1bx is coupled to a different output of DSPx. The switch connects DSPx to power controller PWRS0x during state S0, DSPx to power controller PWRS1ax during state S1a, and DSPx to power controller PWRS1bx during state S1b. [00106] Similarly, in several embodiments, the power controllers PWRS0y and PWRS1y of the y MHz RF generator are connected to a single identical output of DSPy by a switch instead of each power of the y MHz RF generator. Controllers PWRS0y and PWRS1y are coupled to different outputs of DSPy. The switch connects DSPy to power controller PWRS0y during state S0 and DSPy to power controller PWRS1y during state S1. [00107] Again, in various embodiments, the adjusters AFTS0x, AFTS1ax, and AFTS1bx of the x MHz RF generator are connected to a single identical output of DSPx by a switch (such as a multiplexer, etc.) rather than generating an x MHz RF. Each of the adjusters AFTS0x, AFTS1ax and AFTS1bx is coupled to a different output of DSPx. The switch connects DSPx to regulator AFTS0x during state S0, DSPx to regulator AFTS1ax during state S1a, and DSPx to regulator AFTS1bx during state S1b. [00108] Similarly, in several embodiments, the adjusters AFTS0y and AFTS1y of the y MHz RF generator are connected to a single identical output of DSPy by a switch instead of each regulator of the y MHz RF generator. AFTS0y and AFTS1y are coupled to different outputs of DSPy. The switch connects DSPy to regulator AFTS0y during state S0 and DSPy to regulator AFTS1y during state S1. [00109] FIG. 3B is an embodiment of a system 350 for controlling ion energy during state S1. System 350 includes an x MHz RF generator, a y MHz RF generator, an impedance matching circuit 302, a plasma chamber 304, and a tool UI system 307. System 350 operates in a manner similar to system 300 (FIG. 3A) except that DSPx generates clock signal TTL1 and digital ripple signal TTL3 in system 350. The x MHz RF generator is the primary RF generator and the y MHz RF generator is the secondary RF generator. The TTL1 and TTL3 signals from the clock signal are routed from the DSPx of the x MHz RF generator to the DSPy of the y MHz RF generator.

Tool UI system 307 provides a corresponding recipe containing performance parameters to each of the x and y MHz RF generators. The corresponding recipes are stored in each of DSPx and DSPy.

In some embodiments, the frequency of the power of the RF signal supplied by the x MHz RF generator is between signal 202 (FIG. 2A) or signal 212 (FIG. 2B) or signal 222 (FIG. 2C) or signal 232 (FIG. 2D). The frequency is the same.

In various embodiments, the TTL3 signal related information is provided from DSPx to the DSPy by connecting the DSPx to the DSPy cable, rather than the TTL3 signal being sent from the DSPx to the DSPy by the cable. For example, from DSPx, a message related to a TTL3 signal in a data file is provided to DSPy. The DSPy includes a virtual phase-locked loop that generates a signal that is locked to the frequency of the TTL3 signal. This signal is used to adjust the power determined by the power controller PWRS1y and/or the frequency determined by the regulator AFTS1y.

4A is an embodiment of a diagram 400 for illustrating an x MHz RF generator operating in two states S1 and S0 and a y MHz RF generator operating in state S1, state S0a, and state S0b. The diagram 400 includes the transmitted power signal 402 generated from the RF signal supplied by the x MHz RF generator and the transmitted power signal 404 generated from the RF signal supplied from the y MHz RF generator. Graph 400 depicts the delivered power versus time. The transmitted power signal 404 has the same frequency as the digital pulsation signal TTL3.

During the time that the transmitted power signal 402 is in state S0, the transmitted power signal 404 transitions between states S0a and S0b, for example, alternates. During the time that the transmitted power signal 402 is in state S1, the transmitted power signal 404 does not transition between the two states. During the time that the transmitted power signal 402 is in state S1, the transmitted power signal 404 is also in state S1.

The power level of the transmitted power signal 402 during the state S0 (such as zero power level, power level less than 5 watts, etc.) can promote the increase of the deposition rate, or the reduction of the etching rate, or the reduction of the sputtering rate. . The power level of the transmitted power signal 402 during state S0 is less than the power level of the transmitted power signal 402 during state S1.

Moreover, the transition of the transmitted power signal 404 between states S0a and S0b during the state S0 of the transmitted power signal 402 can facilitate control of the impedance of the plasma generated in the plasma chamber 304 (Fig. 3A) ( Such as increase, decrease, etc.). Impedance control increases the stability of the plasma. For example, when the x MHz RF generator generates an RF signal to further provide the delivered power signal 402 to the plasma chamber 304 to achieve a coarse etch rate, the y MHz RF generator generates an RF signal to provide further The transmitted power signal 404 converted between states S0a and S0b. A fine etch rate can be achieved by switching the transmitted power signal 404 between states S0a and S0b. For another example, when the x MHz RF generator generates an RF signal to further provide the delivered power signal 402 to the plasma chamber 304 to achieve a coarse deposition rate, the y MHz RF generator generates an RF signal to provide further The transmitted power signal 404 is converted between states S0a and S0b. A fine deposition rate can be achieved by switching the transmitted power signal 404 between states S0a and S0b. For another example, when the x MHz RF generator generates an RF signal to further provide the delivered power signal 402 to the plasma chamber 304 to achieve a coarse sputtering rate, the y MHz RF generator generates an RF signal to further A delivered power signal 404 is provided that transitions between states S0a and S0b. A fine sputtering rate can be achieved by switching the transmitted power signal 404 between states S0a and S0b.

In some embodiments, the coarse rate has a larger range than the fine rate. For example, the coarse etch rate has an etch rate range between D Å/min to E Å/min, while the fine etch rate has an etch rate range between F Å/min to G Å/min. A range between F Å/min and G Å/min falls within a range between D Å/min and E Å/min. In various embodiments, the range between F Å/min and G Å/min is less than a range between D Å/min to E Å/min.

In various embodiments, during the state S0b of the transmitted power signal 404, the amount of ion energy within the plasma chamber 304 (FIG. 3A) is less than the plasma chamber 304 during the state S0a of the delivered power signal 404. The amount of ion energy inside. The smaller amount of ion energy generated by the RF signal generated by the y MHz RF generator can facilitate the control of the plasma in the plasma chamber 304 to further achieve the rate (etch rate, deposition rate, cleaning rate, sputtering). Rate, etc.) Repetitive and achieve plasma stability. Again, a relatively small amount of ion energy is generated during the time that the transmitted power signal 402 is in state S0 such that most of the energy supplied by the x and y MHz RF generators produces RF energy that is reflected toward the generator. Most of the power reflection improves the plasma stability within the plasma chamber 304.

4B is an embodiment of FIG. 410, and is used to illustrate the level of the transmitted power signal 412 derived from the RF signal generated by the y MHz RF generator. Figure 410 depicts the delivered power versus time. The transmitted power signal 412 during state S0a has a higher level than the transmitted power signal 404 (Fig. 4A) during state S0b. The transmitted power signal 412 has the same frequency as the digital pulsation signal TTL3.

In various embodiments, the transmitted power signal 412 during state S0a has a level that is higher than the level of the transmitted power signal 404. In various embodiments, the level of the transmitted power signal 412 during the state S0a is lower than the level of the transmitted power signal 404.

4C is an embodiment of FIG. 420 for illustrating the level of the transmitted power signal 422 derived from the RF signal generated by the y MHz RF generator. Figure 420 depicts the delivered power versus time. The transmitted power signal 422 during state S0b has a level that is lower than the level that the transmitted power signal 404 (Fig. 4A) has during state S0a. Again, the transmitted power signal 422 during state S0a has a level that is lower than the level of the transmitted power signal 422 during state S1. The transmitted power signal 422 has the same frequency as the digital pulsation signal TTL3.

4D is an embodiment of FIG. 430, which is used to illustrate the use of transmitted power signals 432 having different levels as compared to the levels shown in FIG. 400 (FIG. 4A). The transmitted power signal 432 has the same frequency as the TTL3. The transmitted power signal 432 is a function of the RF signal supplied by the y MHz RF generator and from the plasma chamber 304 to the y MHz by the RF transmission line 312, the impedance matching circuit 302 and the RF cable 310 (Fig. 3A). RF signal reflected by the RF generator. The power level of the transmitted power signal 432 during state S0a is lower than the power level of the transmitted power signal 404 (FIG. 4A) during state S0a. Moreover, the power level of the transmitted power signal 432 during the state S0a is lower than the power level of the transmitted power signal 402 during the state S1. Moreover, the power level of the transmitted power signal 432 during the state S0b is higher than the power level of the transmitted power signal 402 during the state S0b. The power level of the transmitted power signal 432 during the state S0b is lower than the power level of the transmitted power signal 402 during the state S1 and higher than the power level of the transmitted power signal 402 during the state S0.

In various embodiments, the power level of the transmitted power signal 402 during state S0 is higher than the power level of the transmitted power signal 432 during state S0b. In some embodiments, the power level of the transmitted power signal 402 during state S1 is lower than the power level of the transmitted power signal 432 during state S0a.

In some embodiments, the period of time occupied by state S1 is the same as the period of time occupied by both states S0a and S0b. For example, state S1 occupies half a clock cycle of clock signal TTL1, and states S0a and S0b occupy the remaining half of the clock cycle. In several embodiments, state S1 occupies a period of time less than or greater than half of the clock period of clock signal TTL1, and states S0a and S0b occupy the remainder of the clock period.

4E is an embodiment of FIG. 440, and FIG. 440 is used to illustrate that the duty cycle during state S0 is different from the 50% duty cycle. Figure 440 illustrates the power delivered by a 60 MHz RF generator versus time t. The delivered power is shown as a pulsation signal 442. It should be noted that the duty cycle of signal 442 during state S0 is greater than 50%, and the time occupied during state S1 is equal to the time occupied during state S0. For example, signal 442 occupies more time during state S0a than during state S0b. In some embodiments, the duty cycle of signal 442 during state S0 is less than 50%. For example, the transmitted signal occupies less time during state S0a than during state S0b.

It should be further noted that each signal 404, 412, 422, and 432 (Figs. 4A through 4D) has a duty cycle of 50% during state S0.

In several embodiments, the state S0 of the power delivered by the y MHz RF generator occupies a state in which the time is less than or more than the power delivered by the y MHz RF generator. In such embodiments, the delivered power has a duty cycle of 50% during state S0.

In various embodiments, the state S0 of the power delivered by the y MHz RF generator occupies a state in which the time is less than or more than the power delivered by the y MHz RF generator. In such embodiments, the duty cycle of the delivered power during state S0 is greater than or less than 50%.

In some embodiments, the TTL signal has a frequency equal to the frequency of the pulsation signal 442. The TTL signal is generated by a device that generates a TTL3 signal. For example, DSPx generates TTL signals from TTL1 signals and modulation signals. The modulation signal modulates the TTL1 signal to generate a TTL signal.

5A shows an embodiment of a system 500 for illustrating that a y MHz RF generator generates RF signals having states S1, S0a, and S0b. System 500 includes a plasma chamber 304, an x MHz RF generator, a y MHz RF generator, and a tool UI system 306. The clock source of the tool UI system 306 provides the clock signal TTL1 to the DSPx of the x MHz RF generator and the DSPy of the y MHz RF generator. The DSPx generates a digital pulsation signal TTL3 signal based on the clock signal TTL1 and provides the TTL3 signal to the DSPy. For example, DSPx provides a portion of the digital pulse signal TTL3 with state S0b to DSPy.

In some embodiments, DSPy generates a TTL3 signal based on the clock signal TTL1, while the non-DSPx generates a TTL3 signal and provides a TTL3 signal to the DSPy. For example, the DSPy generates a TTL3 signal from the clock signal, and the clock signal is received from the clock source of the tool UI system 306 or received from a clock source inside the DSPx. For example, DSPy generates a TTL3 signal from the clock signal TTL1, and the clock signal TTL1 is generated by the clock source inside the DSPy. For example, DSPy generates a TTL3 signal from the clock signal TTL1, and the clock signal TTL1 is generated by a clock source inside the y MHz RF generator.

During state S0b, DSPx provides digital pulse signal TTL3 to DSPy via a cable. The DSPy supplies the digital pulse signal TTL3 and the pulse signal TTL1 to the power controller PWRS0by of the y MHz RF generator during the state S0b. For example, DSPy provides a portion of the digital pulse signal TTL3 with state S0b and a clock signal TTL1 with state S0. The power controller PWRS0by determines or recognizes the power level of the RF signal to be generated by the y MHz RF generator in response to the reception of the digital pulse signal TTL3 and the clock signal TTL1. For example, the power controller PWRS0by identifies a power level in the memory device of the power controller PWRS0by, which is mapped to the state S0b of the digital pulse signal TTL3 and the state S0 of the clock signal TTL1. The power controller PWRS0by sends the power level to the RF power source 324.

Moreover, during the state S0 of the TTL3 signal and the state S0 of the TTL1 signal, the DSPy supplies the digital pulse signal TTL3 and the clock signal TTL1 to the adjuster AFTS0by of the y MHz RF generator. The adjuster AFTS0by determines or recognizes the frequency level of the RF signal to be generated by the y MHz RF generator in response to the reception of the digital pulse signal TTL3 and the pulse signal TTL1. For example, the adjuster AFTS0by recognizes a frequency level from the memory device of the adjuster AFTS0by, and the frequency level is mapped to the state S0 of the digital pulse signal TTL3 and the state S0 of the pulse signal TTL1. The adjuster AFTS0by provides the frequency level to the RF power source 324. After receiving the power level from the power controller PWRS0by during the state S0b of the digital pulsation signal TTL3 and the frequency level from the state of the regulator AFTS0by during the state S0b of the digital pulsation signal TTL3 and the state S0 of the clock signal TTL1, The RF power source 324 generates an RF signal having the frequency level and the power level.

The power level and the frequency level during the state S0b of the digital pulse signal TTL3 and the state S0 of the clock signal TTL1 are related to achieving a process rate such as an etching rate, a deposition rate, a cleaning rate, or a sputtering rate. . For example, during the state S0b of the digital pulse signal TTL3 and the state S0 of the clock signal TTL1, the RF signal generated by the y MHz RF generator can assist in the fine adjustment of the deposited material on the etched wafer 318 or on the wafer 318. A balance between the complex etch rates is achieved. One of the complex etch rates is associated with state S0b and the other of the complex etch rates is associated with state S0a.

Again, during state S0b of the y MHz RF generator, the x MHz RF generator operates in state S0. During state S0, DSPx sends the clock signal TTL1 to the power controller PWRS0x and regulator AFTS0x of the x MHz RF generator. After receiving the clock signal TTL1, the power controller PWRS0x determines or recognizes a power level. This power level is recognized by the memory device of the power controller PWRS0x. This power level is provided to the RF power source 322.

Moreover, after receiving the clock signal TTL1, the adjuster AFTS0x determines or recognizes a frequency level. This frequency level is recognized by the memory device of the regulator AFTS0x. The adjuster AFTS0x provides this frequency level to the RF power source 322. After receiving the power level and frequency level during state S0, RF power source 322 generates an RF signal having the frequency level and the power level.

It should be noted that the frequency level and power level during the state S0 of the RF signal generated by the x MHz RF generator can assist in achieving a process rate such as deposition rate, etch rate, cleaning rate, sputtering rate, and the like. For example, during state S0, the x MHz RF generator generates an RF signal having the power level, the power level being mapped to a coarse etch level and/or mapped to a coarse frequency level.

The impedance matching circuit 302 receives the RF signal generated by the x MHz RF generator during state S0 and receives the RF signal generated by the y MHz RF generator during state S0b and matches the impedance of the load to the source to produce a modified RF. Signal. The modified RF signal is provided by impedance matching circuit 302 to chuck 314 to produce or modify the plasma to process wafer 318 to achieve a process rate.

Moreover, during the state S0a, the DSPx supplies the digital pulse signal TTL3 to the DSPy by a cable, and supplies the clock signal TTL1 to the DSPy through the cable. The DSPy supplies the digital pulse signal TTL3 and the clock signal TTL1 to the power controller PWRS0ay of the y MHz RF generator during the state S0a. For example, DSPy provides a portion of the digital pulse signal TTL3 with state S0a and provides a clock signal TTL1 with state S0. The power controller PWRS0ay determines or recognizes the power level of the RF signal to be generated by the y MHz RF generator in response to the reception of the digital pulse signal TTL3 and the pulse signal TTL1. For example, the power controller PWRS0ay identifies a power level in the memory device of the power controller PWRS0ay, and the power level is mapped to the state S0 of the digital pulse signal TTL3 and the state S0 of the time pulse signal TTL1. The power controller PWRS0ay sends this power level to the RF power source 324.

Moreover, during the state S0 of the TTL3 signal and the state S0 of the TTL1 signal, DSPy supplies the digital pulse signal TTL3 to the adjuster AFTS0ay of the y MHz RF generator. The adjuster AFTS0ay determines or recognizes the frequency level of the RF signal to be generated by the y MHz RF generator in response to the reception of the digital pulse signal TTL3 having the state S0a and the clock signal TTL1 having the state S0. The memory device of the adjuster AFTS0ay self-adjuster AFTS0ay recognizes a frequency level, which is mapped to the state S0 of the digital pulse signal TTL3 and the state S0 of the time pulse signal TTL1. The adjuster AFTS0ay provides this frequency level to the RF power source 324. Upon receiving the power level from the power controller PWRS0ay during state S0a and the frequency level from the regulator AFTS0ay during state S0a, the RF power source 324 generates an RF signal having the frequency level and the power level.

The power level and frequency level during the state S0a of the digital pulse signal TTL3 and the state S0 of the clock signal TTL1 are related to achieving a process rate such as an etch rate, a deposition rate, or a cleaning rate, or a sputtering rate. . For example, during the state S0a of the digital pulse signal TTL3 and the state S0 of the clock signal TTL1, the RF signal generated by the y MHz RF generator can assist in the fine adjustment of the deposited material on the etched wafer 318 or on the wafer 318. Achieve balance. During the state S0a of the digital pulse signal TTL3 and the state S0 of the clock signal TTL1, the RF signal generated by the y MHz RF generator can assist in increasing the etch rate of the etched wafer 318 or etching the material deposited on the wafer 318. The balance between increasing the etching rate and decreasing the etching rate is further achieved during the state S0b.

Again, during state S0a of the y MHz RF generator, the x MHz RF generator operates in state S0. The operation of the x MHz RF generator during state S0 has been previously described. The impedance matching circuit 302 receives the RF signal generated by the x MHz RF generator during state S0 and receives the RF signal generated by the y MHz RF generator during state S0a and matches the impedance of the load to the source to produce a modified RF. Signal. The modified RF signal is supplied to the chuck 314 by the impedance matching circuit 302 to modify the plasma to process the wafer 318, such as etching the wafer 318, depositing material onto the wafer 318, or processing the deposition on the wafer 318. material.

During state S1, DSPy provides a TTL3 signal to power controller PWRS1y. For example, DSPy provides a portion of the TTL3 signal with state S1 to power controller PWRS1y. It should be noted that during state S1, the TTL3 signal is the same as the TTL1 signal. After receiving the TTL3 signal, the power controller PWRS1y determines or recognizes a power level and provides the power level to the RF power source 324. Also, during state S1, DSPy provides the TTL3 signal to the adjuster AFTS1y. After receiving the TTL3 signal, the adjuster AFTS1y determines or recognizes a frequency level and provides the frequency level to the RF power source 324. The RF power source 324 generates an RF signal having the power level and the frequency level during the state S1 and provides the RF signal to the impedance matching circuit 302.

Also, during state S1, DSPx provides a TTL3 signal to power controller PWRS1x and regulator AFTS1x. After receiving the TTL3 signal, the power controller PWRS1x determines or identifies the power level associated with state S1. For example, the power controller PWRS1x identifies a power level stored in the memory device of the power controller PWRS1x. The power controller PWRS1x provides this power level to the RF power source 322. Moreover, after receiving the TTL3 signal, the adjuster AFTS1x determines or recognizes a frequency level associated with the state S1. For example, the adjuster AFTS1x recognizes a frequency level that is mapped to state S1 and stored in the memory device of the adjuster AFTS1x. This frequency level is supplied from the regulator AFTS1x to the power source 322. During state S1, power source 322 generates an RF signal having the frequency level associated with state S1 and the power level.

Impedance matching circuit 302 receives RF signals from RF power sources 322 and 324 during state S1 and matches the impedance of the load to the source to produce a modified RF signal. In some embodiments, the impedance of the source is based on one or more RF signals received by impedance matching circuit 302 from one or more RF generators that generate one or more RF signals. The self-impedance matching circuit 302 transmits the modified RF signal generated during the state S1 to the chuck 314 via the RF transmission line 312.

In various embodiments, the etch rate achieved during state S1 is higher than the etch rate achieved during state S0, or the deposition rate achieved during state S1 is lower than the deposition rate achieved during state S0. The sputtering rate achieved during the state S1 is higher than the sputtering rate achieved during the state S0, or the cleaning rate achieved during the state S1 is higher than the cleaning rate achieved during the state S0.

It should be noted that in some embodiments, the power controller and regulator of the y MHz RF generator are components of DSPy. For example, the power controllers PWRS0ay, PWRS0by and PWRS1y and the adjusters AFTS1y, AFTS0ay and AFTS0by are all part of the computer program executed by DSPy. For another example, the power controllers PWRS0ay, PWRS0by and PWRS1y and the adjusters AFTS1y, AFTS0ay and AFTS0by are circuits integrated into the circuit of DSPy.

In various embodiments, the power controllers PWRS0ay, PWRS0by, and PWRS1y of the y MHz RF generator are connected to a single identical output of DSPy by a switch (eg, a multiplexer) instead of each of the y MHz RF generators. Power controllers PWRS0ay, PWRS0by, and PWRS1y are coupled to different outputs of DSPy. The switch connects DSPy to power controller PWRS1y during state S1, DSPy to power controller PWRS0ay during state S0a, and DSPy to power controller PWRS0by during state S0b.

Similarly, in several embodiments, the power controllers PWRS0x and PWRS1x of the x MHz RF generator are connected to a single identical output of DSPx by a switch instead of each power controller PWRS0x of the x MHz RF generator. A different output coupled to the DSPx with the PWRS1x. The switch connects DSPx to power controller PWRS0x during state S0 and DSPx to power controller PWRS1x during state S1.

In various embodiments, the adjusters AFTS1y, AFTS0ay, and AFTS0by of the y MHz RF generator are connected to a single identical output of DSPy by switches (eg, multiplexers, etc.) rather than each of the y MHz RF generators. The adjusters AFTS1y, AFTS0ay and AFTS0by are coupled to different outputs of DSPy. The switch connects DSPy to regulator AFTS1y during state S1, DSPy to regulator AFTS0ay during state S0a, and DSPy to regulator AFTS0by during state S0b.

Similarly, in several embodiments, the adjusters AFTS0x and AFTS1x of the x MHz RF generator are connected to a single identical output of DSPx by a switch instead of each of the adjusters AFTS0x and AFTS1x of the x MHz RF generator. Coupled to different outputs of DSPx. The switch connects DSPx to regulator AFTS0x during state S0 and DSPx to regulator AFTS1x during state S1.

FIG. 5B shows an embodiment of a system 510 for illustrating that the DSPx of the x MHz RF generator generates TTL1 and TTL3 signals. The clock signal TTL1 is generated by the clock source inside the DSPx, and the clock signal TTL1 is not received from the clock source of the tool UI system 306. The clock signal TTL1 is used to generate the digital pulse signal TTL3 by DSPx. TTL3 signal and clock signal TTL1 are provided by DSPx to DSPy. Again, tool UI system 307 provides the recipe associated with the x MHz RF generator to DSPx and provides the recipe associated with the y MHz RF generator to DSPy.

For example, the power of the RF signal supplied by the y MHz RF generator has a frequency of 404 (FIG. 4A), or signal 412 (FIG. 4B), or signal 432 (FIG. 4C), or signal 432 (FIG. 4D). The frequency is the same.

FIG. 6A shows an embodiment of FIG. 600 for illustrating the ripple of the RF signal generated by the x MHz RF generator during states S1 and S0. The ripple of the RF signal generated by the x MHz RF generator causes two secondary states S1a and S1b during state S1 and two secondary states S0a and S0b during state S0. 600 illustrates the power level versus time of the transmitted RF signal 602 as a function of the RF signal generated by the x MHz RF generator and reflected toward the RF generator.

During state S0 of the TTL1 signal, RF signal 602 varies between states S0a and S0b. Also, during the state S1 of the TTL1 signal, the RF signal 602 varies between states S1a and S1b.

In some embodiments, the power level of RF signal 602 during state S0b is lower than the power level of RF signal 602 during state S1b.

It should be noted that the states S0a and S0b using the RF signal 602 can assist in roughly adjusting the process rate during the state S0 of the TTL1 signal, such as the etch rate, deposition rate, sputtering rate, or cleaning rate.

6B shows an embodiment of FIG. 610 for illustrating an x MHz RF generator that uses the y MHz RF generator and cooperatively generates an RF signal 602 having four secondary states S0a, S0b, S1a, and S1b. When the x MHz RF generator generates an RF signal to further provide the RF signal 602 with states S0a and S0b, the y MHz RF generator generates an RF signal to further provide the transmitted power RF signal 604 with state S0. In some embodiments, when the fine control of the process rate is constant or substantially constant, the states S0a and S0b of the RF signal 602 generated using the x MHz RF generator can roughly control the process rate, such as etch rate, deposition rate. , sputtering rate, etc. In some embodiments, the fine control of the process rate is substantially constant when the y MHz RF generator is operating at a power level corresponding to state S0. Again, when the x MHz RF generator assists in providing the RF signal 602 with states S1a and S1b, the y MHz RF generator assists in providing the RF signal 604 with state S1.

6C shows an embodiment of the diagram 620. The diagram 620 is used to illustrate that the duty cycle during the state S0 of the TTL1 signal is different from the duty cycle during the state S1 of the TTL1 signal. Figure 620 illustrates the power delivered by the 2 MHz RF generator versus time. The delivered power is shown as a pulsation signal 622. It should be noted that the duty cycle of the pulsation signal 622 during state S0 is greater than 50% and the occupation period of state S1 is equal to the occupation period of state S0. For example, the occupancy of signal 622 during state S0a is greater than during the state S0b. It should be noted that the delivered power signal 622 has a duty cycle of 50% during state S1.

In some embodiments, the duty cycle of signal 622 during state S0 is less than 50%. For example, the occupancy time of the delivery signal during state S0a is less than the occupation time during state S0b.

It should be noted that the signal 602 is 50% in each of the states S0 and S1 (Figs. 6A to 6B). For example, the occupancy time of signal 622 during state S0a is equal to its occupation time during state S0b.

In some embodiments, the duty cycle of the pulsating power signal delivered by the 2 MHz RF generator during state S1 is greater than or less than 50%, and the duty cycle of the delivered pulsating power signal during state S0 is equal to 50%.

In various embodiments, the duty cycle of the pulsating power signal delivered by the 2 MHz RF generator during state S1 is greater than or less than 50%, and the duty cycle of the transmitted pulsating power signal during state S0 is greater than or less than 50%. .

In several embodiments, the state S0 of the power delivered by the x MHz RF generator takes up less than the state S1 of the power delivered by the x MHz RF generator. In such embodiments, the delivered power has a duty cycle of 50% during each state S0 and S1.

In various embodiments, the state S0 of the power delivered by the x MHz RF generator occupies a state that is less than or more than the power delivered by the x MHz RF generator. In such embodiments, the duty cycle of the delivered power during state S0 is greater than or less than 50%, and the duty cycle of the delivered power during state S1 is equal to 50%.

In some embodiments, the state S0 of the power delivered by the x MHz RF generator occupies a state that is less than or more than the power delivered by the x MHz RF generator. In such embodiments, the duty cycle of the delivered power during state S0 is equal to 50%, and the duty cycle of the delivered power during state S1 is greater than or less than 50%.

In various embodiments, the state S0 of the power delivered by the x MHz RF generator occupies a state that is less than or more than the power delivered by the x MHz RF generator. In such embodiments, the duty cycle of the delivered power during state S0 is greater than or less than 50%, and the duty cycle of the delivered power during state S1 is greater than or less than 50%.

In some embodiments, the TTL signal has a frequency equal to the frequency of the pulse signal 622. The TTL signal is generated by a device that generates a TTL5 signal. For example, DSPx generates TTL signals from TTL1 signals and modulation signals. The modulation signal modulates the TTL1 signal to generate a TTL signal.

Figure 7A shows an embodiment of a system 700 for illustrating the use of four secondary states S0a, S0b, S1a, and S1b in an x MHz RF generator. System 700 includes a plasma chamber 304, an x MHz RF generator, a y MHz RF generator, and a tool UI system 306. The clock source of the tool UI system 306 generates the clock signal TTL1 and provides the clock signal TTL1 to the DSPx and DSPy via the cable 313.

During state S0a, DSPx generates a TTL5 signal from the TTL1 signal and provides a TTL5 signal to DSPy. For example, DSPx generates TTL5 signals by modulating TTL1 signals with TTL4 signals. For another example, DSPx generates a TTL5 signal by multiplying the logic level of the clock signal TTL1 by the logic level of the TTL4 signal. In various embodiments, the RF signal 602 (Figs. 6A and 6B) has a frequency that is the same as the frequency of the TTL5 signal. In some embodiments, the RF signal 602 has a frequency that is the same as the frequency of the TTL4 signal.

During state S0b, DSPx provides TTL5 signals and TTL1 signals to the power controller PWRS0bx of the x MHz RF generator and AFTS0bx of the regulator x MHz RF generator. For example, during state S0b, DSPx provides a portion of the TTL5 signal having state S0b and a clock signal TTL1 having state S0 to power controller PWRS0bx and regulator AFTS0bx. After receiving the TTL5 signal, the power controller PWRS0bx determines or recognizes the power level corresponding to the state S0 of the TTL5 signal state S0b and the clock signal TTL1. For example, the power controller PWRS0bx recognizes a power level from the memory device of the power controller PWRS0bx, and the power level is mapped to the state S0b of the signal TTL5 and the state S0 of the clock signal TTL1. The power controller PWRS0bx provides a power level associated with the state S0b of the TTL5 signal and the state S0 of the clock signal TTL1 to the RF power source 322.

Moreover, during the state S0 of the TTL5 signal and the state S0 of the TTL1 signal, the adjuster AFTS0bx determines or recognizes a frequency level after receiving the TTL5 signal and the TTL1 signal. For example, the adjuster AFTS0bx recognizes the frequency level from the memory device of the adjuster AFTS0bx, and the frequency level is mapped to the state S0b of the TTL5 signal and the state S0 of the TTL1 signal. The adjuster AFTS0bx provides the frequency level to the RF power source 322.

After receiving the power level corresponding to the state S0b of the TTL5 signal and the state S0 of the TTL1 signal and the frequency level, the RF power source 322 generates an RF signal having the power level and the frequency level for the state S0b. The RF signal generated during the state S0b of the TTL5 signal and the state S0 of the TTL1 signal is supplied to the impedance matching circuit 302 via the RF cable 308.

It should be noted that in some embodiments, the power level and/or the frequency level during the state S0 of the TTL5 signal and the state S0 of the TTL1 signal are used to roughly control the process rate, such as deposition on the wafer 318. The deposition rate of the material, or the etch rate of the material on the etched wafer 318 or etched wafer 318, or the sputtering rate of the sputtered wafer 318 or material sputter deposited on the wafer 318, or the wafer 318 or Clean up the cleaning rate of the material deposited on the substrate, and the like.

Also, during state S0, DSPy receives the TTL1 signal from tool UI system 306 and provides the TTL1 signal to power controller PWRS0y. The remaining operation of the y MHz RF generator is similar to that described above with respect to Figure 3A for generating RF signals.

During state S0 of the y MHz RF generator and state S0b of the x MHz RF generator, impedance matching circuit 302 receives RF signals from the x and y MHz RF generators via RF cables 308 and 310, and then matches the load and source. Impedance to produce a modified RF signal. The modified RF signal is provided to the chuck 314 by the RF transmission line 312. In some embodiments, the modified RF signal generated during state S0b can control the process rate, such as the deposition rate of material deposited on wafer 318, or the etched wafer 318 or the material on etched wafer 318. The etch rate, or the sputtering rate of the sputtered wafer 318 or the material sputter deposited on the wafer 318, or the cleaning of the wafer 318 or the cleaning of the material deposited on the substrate, and the like.

Also, during state S0a, DSPx provides the TTL5 signal and the TTL1 signal to the power controller PWRS0ax of the x MHz RF generator and to the regulator AFTS0ax of the x MHz RF generator. For example, during state S0a, DSPx provides a portion of the TTL5 signal with state S0a and the TTL1 signal with state S0 to power controller PWRS0ax and regulator AFTS0ax. The power controller PWRS0ax determines or recognizes a power level after receiving the TTL5 signal and the TTL1 signal. For example, the power controller PWRS0ax recognizes the power level from the memory device of the power controller PWRS0ax, and the power level is mapped to the state S0a of the TTL5 signal and the state S0 of the clock signal TTL1. The power controller PWRS0ax provides this power level to the RF power source 322.

Moreover, during the state S0 of the TTL5 signal and the state S0 of the clock signal TTL1, the adjuster AFTS0ax determines or recognizes a frequency level after receiving the TTL5 signal. For example, the adjuster AFTS0ax recognizes the frequency level from the memory device of the adjuster AFTS0ax, and the frequency level is mapped to the state S0a of the TTL5 signal and the state S0 of the clock signal TTL1. The adjuster AFTS0ax provides this frequency level to the RF power source 322.

After receiving the power level corresponding to the state S0a and the frequency level, the RF power source 322 generates an RF signal having the power level and the frequency level for the state S0 of the TTL5 signal and the state S0 of the clock signal TTL1. . The RF signal generated during the state S0 of the TTL5 signal and the state S0 of the clock signal TTL1 is supplied to the impedance matching circuit 302 by the RF cable 308.

It should be noted that in some embodiments the power level and/or frequency level during the state S0 of the TTL5 signal and the state S0 of the clock signal TTL1 is used to roughly control the process rate, such as depositing material on the wafer 318. The deposition rate, or the etch rate of the material on the etched wafer 318 or etched wafer 318, or the sputtering rate of the sputtered wafer 318 or material sputter deposited on the wafer 318, or the wafer 318 or cleaned The cleaning rate of the material deposited on the wafer 318, and the like.

Again, the operation of the y MHz RF generator during state S0 has been described above.

During state S0 of the y MHz RF generator and state S0a of the x MHz RF generator, impedance matching circuit 302 receives RF signals from the x and y MHz RF generators via RF cables 308 and 310, and then matches the load and source. Impedance to produce a modified RF signal. The modified RF signal is provided to the chuck 314 by the RF transmission line 312. In some embodiments, the modified RF signal generated during state S0b can control the deposition rate of deposited material on wafer 318, or the etch rate of material etched on wafer 318 or etched wafer 318, or The sputtering rate of the sputter wafer 318 or sputter deposited material on the wafer 318.

During state S0, DSPy sends a signal to power controller PWRS0y to adjust at the transition time at which the x MHz RF generator transitions from state S0a to state S0b or at the transition time when x MHz RF generator transitions from state S0b to state S0a The power determined by the power controller PWRS0y. The determined power is adjusted based on the change in plasma impedance that occurs when the power delivered by the x MHz RF generator transitions between states S0a and S0b. To compensate for the adjustment of the power delivered by the x MHz RF generator during transitions between states S0a and S0b, a TTL5 signal is sent from DSPx to DSPy. The adjustment of the power delivered by the x MHz RF generator causes a change in the impedance of the plasma.

Also, during state S1, DSPy sends a signal to adjuster AFTS0y to adjust the transition time at the transition time of the x MHz RF generator transition from state S0a to state S0b or the transition of x MHz RF generator from state S0b to state S0a. The frequency determined by the regulator AFTS0y. The determined frequency is adjusted based on the change in plasma impedance that occurs when the frequency of the x MHz RF generator transitions between states S0a and S0b. To compensate for the adjustment of the frequency of the RF signal generated by the x MHz RF generator when transitioning between states S0a and S0b, a TTL5 signal is sent from DSPx to DSPy. The adjustment of the frequency of the RF signal supplied by the x MHz RF generator causes a change in the impedance of the plasma.

It should be further noted that in some embodiments the tool UI system 306 will correlate information related to the TTL5 signal via the cable 314 or another cable similar to the cable 314 (eg, the frequency of the TTL5 signal during state S1, the TTL5 signal). The duty cycle during state S1, the time when state S1a appears in TTL5 signal, the time when state S1b appears in TTL5 signal, the frequency of TTL5 signal during state S0, the duty cycle of TTL5 signal during state S0, and the TTL5 signal The time when the state S0a appears, the time when the state S0b appears in the TTL5 signal, etc.) is supplied to the DSPy instead of the TTL5 signal sent from the DSPx to the DSPy. For example, the tool UI system 306 provides a data file containing information related to the TTL5 signal to the DSPy. The DSPy includes a virtual phase-locked loop. The signal generated by the virtual phase-locked loop is locked to the frequency of the TTL5 signal and used to adjust the power determined by the power controller PWRS0y and/or to adjust the frequency determined by the adjuster AFTS0y.

Again, the operation of the x MHz RF generator during states S1a and S1b and the operation of the y MHz RF generator during state S1 are similar to those described with reference to FIG. 3A.

FIG. 7B shows an embodiment of system 710 in which clock signal TTL1 is generated by DSPx instead of tool UI system 306 (FIG. 7A). System 710 includes a tool UI system 307. The DSPx includes a DSPy that generates a clock source of the clock signal TTL1 and provides the clock signal TTL1 and TTL5 signals to the y MHz RF generator. The remaining operations of system 710 are similar to system 700 of Figure 7A.

In some embodiments, the frequency of the power supplied by the x MHz RF generator during states S1a, S1b, S0a, and S0b is the same as the frequency of signal 602 (FIG. 6A).

In various embodiments, the information associated with the TTL5 signal is provided to the DSPy by the DSPx by connecting the DSPx to the DSPy cable, rather than the TTL5 signal being sent to the DSPy by the cable from the DSPx. For example, a data file containing information related to TTL5 signals is provided from DSPx to DSPy. The DSPy includes a virtual phase-locked loop. The signal generated by the virtual phase-locked loop is locked to the frequency of the TTL5 signal and used to adjust the power determined by the power controller PWRS0y and/or to adjust the frequency determined by the adjuster AFTS0y.

8A shows an embodiment of FIG. 800, which is used to illustrate the ripple of the RF signal generated by the y MHz RF generator during states S1 and S0. The pulsation of the RF signal generated by the y MHz RF generator causes two secondary states S1a and S1b during state S1 and two secondary states S0a and S0b during state S0. Figure 800 illustrates the transmitted power (e.g., a power level) of the RF signal 802 versus time. The power level is the RF signal generated by the y MHz RF generator and the RF signal reflected toward the y MHz RF generator. function.

During state S0 of the TTL1 signal, RF signal 802 alternates between states S0a and S0b. Also, during state S1 of the TTL1 signal, RF signal 802 alternates between states S1a and S1b.

In some embodiments, the power level of RF signal 802 during state S0b is lower or higher than the power level of RF signal 802 during state S1b.

It should be noted that the states S1a and S1b using the RF signal 802 during the state S1 of the TTL1 signal can assist in fine adjustment of the etch rate, deposition rate, sputtering rate, or cleaning rate during the state S1.

8B shows an embodiment of FIG. 810, which is used to illustrate a y MHz RF generator that produces an RF signal 802 having four secondary states S0a, S0b, S1a, and S1b using an x MHz RF generator in concert. When the y MHz RF generator generates an RF signal 802 having states S1a and S1b, the x MHz RF generator generates an RF signal 812 having a state S1. In some embodiments, when the coarse control of the process rate is constant or substantially constant, the states S1a and S1b of the RF signal 802 generated using the y MHz RF generator can finely control the process rate, such as the etch rate, the cleaning rate. , deposition rate, sputtering rate, and the like. In some embodiments, when the x MHz RF generator is operating at a power level corresponding to state S1, the coarse control of the process rate is substantially constant. Again, when the y MHz RF generator generates an RF signal 802 having states S0a and S0b, the x MHz RF generator generates an RF signal 812 having a state S0.

8C shows an embodiment of the diagram 820. The diagram 820 is used to illustrate that the duty cycle during the state S0 of the TTL1 signal is different from the duty cycle during the state S1 of the TTL1 signal. Figure 820 illustrates the power delivered by a 60 MHz RF generator versus time t. The delivered power is shown as a pulsation signal 822. It should be noted that the duty cycle of the pulsation signal 822 during state S1 is greater than 50%, and the time occupied during state S1 is equal to the time occupied during state S0. For example, signal 822 occupies more time during state S1a than during state S1b. It should be noted that the delivered power signal 822 has a duty cycle of 50% during state S0.

In some embodiments, the duty cycle of signal 822 during state S1 is less than 50%. For example, the transmitted power signal occupies less time during state S1a than during state S1b.

It should be noted that the signal 802 (Figs. 8A through 8B) has a duty cycle of 50% during each of the states S0 and S1.

In some embodiments, the pulsating transmitted power signal generated by the 60 MHz RF generator has a duty cycle greater than or less than 50% during state S0, and the duty cycle of the pulsating transmitted power signal during state S1 is 50%.

In various embodiments, the pulsating transmitted power signal generated by the 60 MHz RF generator has a duty cycle greater than or less than 50% during state S0, and the duty cycle of the pulsating transmitted power signal during state S1 is greater than Or less than 50%.

In several embodiments, the state S1 of the power delivered by the y MHz RF generator takes up less than the state S0 of the power delivered by the y MHz RF generator. In such embodiments, the delivered power is 50% during each of the states S0 and S1.

In various embodiments, the state S1 of the power delivered by the y MHz RF generator occupies a state in which the time is less than or more than the power delivered by the y MHz RF generator. In such embodiments, the duty cycle of the delivered power during state S1 is greater than or less than 50% and the duty cycle of the delivered power during state S0 is equal to 50%.

In some embodiments, the state S1 of the power delivered by the y MHz RF generator occupies a state in which the time is less than or more than the power delivered by the y MHz RF generator. In such embodiments, the duty cycle of the delivered power during state S1 is equal to 50% and the duty cycle of the delivered power during state S0 is greater than or less than 50%.

In various embodiments, the state S1 of the power delivered by the y MHz RF generator occupies a state in which the time is less than or more than the power delivered by the y MHz RF generator. In such embodiments, the duty cycle of the delivered power during state S1 is greater than or less than 50% and the duty cycle of the delivered power during state S0 is greater than or less than 50%.

In some embodiments, the TTL signal has a frequency equal to the frequency of the pulsation signal 822. The TTL signal is generated by a device that generates a TTL5 signal. For example, DSPx generates TTL signals from TTL1 signals and modulation signals. The modulation signal modulates the TTL1 signal to generate a TTL signal.

Figure 9A shows an embodiment of a system 900 for illustrating the use of four secondary states S0a, S0b, S1a, and S1b in a y MHz RF generator. System 900 includes a plasma chamber 304, an x MHz RF generator, a y MHz RF generator, and a tool UI system 306. The clock source of the tool UI system 306 generates the clock signal TTL1 and provides the clock signal TTL1 to the DSPx and DSPy via the cable 313.

During state S1b. DSPx generates TTL5 signals from TTL1 signals. In various embodiments, the frequency of the RF signal 802 (Figs. 8A and 8B) is the same as the frequency of the TTL5 signal. In some embodiments, the RF signal 802 has a frequency that is the same as the frequency of the TTL4 signal.

Also, during state S1b, DSPx provides a TTL5 signal to DSPy. DSPy provides the received TTL5 signal and TTL1 signal to the power controller PWRS1by of the y MHz RF generator and the regulator AFTS1by of the y MHz RF generator. For example, during state S1b, DSPy provides a partial TTL5 signal with state S1b and a TTL1 signal with state S1 to power controller PWRS1by and regulator AFTS1by. The power controller PWRS1by determines or recognizes the power level after receiving the TTL5 signal and the TTL1 signal. For example, the power controller PWRS1by recognizes a power level from the memory device of the power controller PWRS1by, and the power level is mapped to the state S1b of the signal TTL5 and the state S1 of the clock signal TTL1. The power controller PWRS1by provides this power level to the RF power source 324.

Moreover, during the state S1 of the TTL5 signal and the state S1 of the TTL1 signal, the adjuster AFTS1by determines or recognizes a frequency level after receiving the TTL5 signal. For example, the adjuster AFTS1by recognizes the frequency level from the memory device of the adjuster AFTS1by, and the frequency level is mapped to the state S1b of the TTL5 signal and the state S1 of the TTL1 signal. The adjuster AFTS1by provides this frequency level to the RF power source 324.

After receiving the power level of the state S1 corresponding to the TTL5 signal and the state S1 of the TTL1 signal and the frequency level, the RF power source 324 generates an RF signal having the power level and the frequency level for the state S1b. The RF signal generated during the state S1b of the TTL5 signal and the state S1 of the TTL1 signal is supplied to the impedance matching circuit 302 via the RF cable 310.

It should be noted that in some embodiments the power level and/or the frequency level during the state S1 of the TTL5 signal and the state S1 of the TTL1 signal are used to fine control the process rate, such as depositing material on the wafer 318. The deposition rate, or the etch rate of the material on the etched wafer 318 or etched wafer 318, or the sputtering rate of the sputtered wafer 318 or material sputter deposited on the wafer 318, or the wafer 318 or cleaned The cleaning rate of the material on the wafer 318, and the like.

Also, during state S1, DSPx receives the TTL1 signal from tool UI system 306 and provides the TTL1 signal to power controller PWRS1x. The remainder of the operation of the x MHz RF generator is similar to that described above with respect to Figure 5A for generating RF signals.

During state S1 of the x MHz RF generator and state S1b of the y MHz RF generator, impedance matching circuit 302 receives RF signals from the x and y MHz RF generators via RF cables 308 and 310, and then matches the load and source. Impedance to produce a modified RF signal. The modified RF signal is provided to the chuck 314 by the RF transmission line 312. In some embodiments, the modified RF signal generated during state S1b can control the process rate, such as the deposition rate of material deposited on wafer 318, or the etched wafer 318 or the material on etched wafer 318. The etch rate, or the sputtering rate of the sputtered wafer 318 or the material sputter deposited on the wafer 318, or the cleaning rate of the material on the wafer 318 or the cleaned wafer 318, and the like.

Moreover, during the state S1 of the TTL5 signal and the state S1 of the TTL1 signal, the DSPy supplies the received TTL5 signal and the TTL1 signal to the power controller PWRS1ay of the y MHz RF generator and the adjuster AFTS1ay of the y MHz RF generator. For example, during the state S1 of the TTL5 signal and the state S1 of the TTL1 signal, the DSPy supplies a part of the TTL5 signal having the state S1a and the TTL1 signal having the state S1 to the power controller PWRS1ay and the adjuster AFTS1ay. The power controller PWRS1ay determines or recognizes a power level after receiving the TTL5 signal and the TTL1 signal. For example, the power controller PWRS1ay recognizes the power level from the memory device of the power controller PWRS1ay, and the power level is mapped to the state S1a of the TTL5 signal and the state S1 of the clock signal TTL1. The power controller PWRS1ay provides this power level to the RF power source 324.

Moreover, during the state S1 of the TTL5 signal and the state S1 of the clock signal TTL1, the adjuster AFTS1ay determines or recognizes a frequency level after receiving the TTL5 signal. For example, the adjuster AFTS1ay recognizes the frequency level from the memory device of the adjuster AFTS1ay, and the frequency level is mapped to the state S1a of the TTL5 signal and the state S1 of the clock signal TTL1. The adjuster AFTS1ay provides this frequency level to the RF power source 324.

After receiving the power level corresponding to the state S1a of the TTL5 signal and the state S1 of the clock signal TTL1 and the frequency level, the RF power source 324 generates an RF signal having the power level and the frequency level for the state S1a. . The RF signal generated during the state S1a of the TTL5 signal and the state S1 of the clock signal TTL1 is supplied to the impedance matching circuit 302 by the RF cable 310.

It should be noted that in some embodiments the power level and/or frequency level during the state S1a of the TTL5 signal and the state S1 of the clock signal TTL1 is used to fine control the process rate associated with the wafer 318, as in The deposition rate of the deposited material on wafer 318, or the etch rate of the material on etched wafer 318 or etched wafer 318, or the sputtering rate of sputtered wafer 318 or material sputter deposited on wafer 318, or The cleaning rate of the material on the wafer 318 or the cleaning wafer 318 is cleaned.

Again, the operation of the x MHz RF generator during state S1 has been described above.

During the state S1 of the x MHz RF generator and the state S1a of the y MHz RF generator, the impedance matching circuit 302 receives RF signals from the x and y MHz RF generators via RF cables 308 and 310, and then matches the load and source. Impedance to produce a modified RF signal. The modified RF signal is provided to the chuck 314 by the RF transmission line 312. In some embodiments, the modified RF signal generated during state S1b can control the process rate, such as the deposition rate of deposited material on wafer 318, or etch wafer 318 or etch deposited on wafer 318. The etch rate of the material, or the sputtering rate of the sputtered wafer 318 or material sputter deposited on the wafer 318, or the cleaning rate of the material on the wafer 318 or the cleaned wafer 318, and the like.

Again, the operation of the y MHz RF generator during states S0a and S0b and the operation of the x MHz RF generator during state S0 are similar to those described with reference to Figure 5A.

9B shows an embodiment of a system 910 in which a clock signal TTL1 is generated by DSPx instead of the tool UI system 306 (FIG. 7A). System 910 includes a tool UI system 307. DSPx contains a clock source that generates the clock signal TTL1. The DSPx generates a digital pulse signal TTL5 from the clock signal TTL1, and the digital pulse signal TTL5 is supplied to the DSPy of the y MHz RF generator by a cable, and the TTL1 signal is supplied to the DSPy through the cable. The remaining operation of system 910 is similar to system 900 of Figure 9A.

In some embodiments, the frequency of the power supplied by the y MHz RF generator during states S1a, S1b, S0a, and S0b is the same as the frequency of signal 802 (FIG. 8A).

FIG. 10A shows an embodiment of FIG. 1000, which is used to illustrate multiple secondary states of both x and y MHz RF generators. Diagram 1000 depicts the delivered power versus time. The power delivered by the x and y MHz RF generators is shown in Figure 1000. When the x MHz RF generator transitions from state S1bx to state S1ax during state S1 of the TTL1 signal, the y MHz generator transitions from state S1by to state S1ay. Also, when the x MHz RF generator transitions from state S1ax to state S1bx during state S1 of the TTL1 signal, the y MHz generator transitions from state S1ay to state S1by. Also, when the x MHz RF generator is in state S1ax during state S1 of the TTL1 signal, the y MHz RF generator is in state S1ay. Again, when the x MHz RF generator is in state S1bx during state S1 of the TTL1 signal, the y MHz RF generator is in state S1by.

When the x MHz RF generator transitions from state S0bx to state S0ax during state S0 of the TTL1 signal, the y MHz generator transitions from state S0by to state S0ay. Also, when the x MHz RF generator transitions from state S0ax to state S0bx during state S0 of the TTL1 signal, the y MHz generator transitions from state S0ay to state S0by. Also, when the x MHz RF generator is in state S0ax during state S0 of the TTL1 signal, the y MHz RF generator is in state S0ay. Also, when the x MHz RF generator is in state S0bx during state S0 of the TTL1 signal, the y MHz RF generator is in state S0by.

It should be noted that the power level delivered by the power of the signal 1002 delivered by the y MHz RF generator during state S1ay is greater than during the state S1by. Again, the transmitted power level of the power of the signal 1004 delivered by the x MHz RF generator during state S1ax is greater than during the state S1bx.

Again, it should be noted that the power level delivered by the power of the signal 1002 delivered by the y MHz RF generator during state S0ay is greater than during the state S0by. Again, the transmitted power level of the power of the signal 1004 delivered by the x MHz RF generator during state S0ax is greater than during the state S0bx.

In some embodiments, the transmitted power level of the power of the signal 1002 delivered by the y MHz RF generator during state S0by is less than the power of the signal 1004 delivered by the x MHz RF generator during state S0bx. The level of power delivered.

In several embodiments, the transmitted power level of the power of the signal 1002 delivered by the y MHz RF generator during state S1by is less than the power of the signal 1004 transmitted by the RF generator during state S1bx during the state S1bx. The level of power delivered.

FIG. 10B shows an embodiment of FIG. 1010, which is used to illustrate multiple secondary states of both x and y MHz RF generators. Figure 1010 illustrates the delivered power versus time. The power delivered by the x and y MHz RF generators is shown in Figure 1010. When the x MHz RF generator transitions from state S1bx to state S1ax during state S1 of the TTL1 signal, the y MHz generator transitions from state S1ay to state S1by. Also, when the x MHz RF generator transitions from state S1ax to state S1bx during state S1 of the TTL1 signal, the y MHz generator transitions from state S1by to state S1ay. Also, when the x MHz RF generator is in state S1ax during state S1 of the TTL1 signal, the y MHz RF generator is in state S1by. Also, when the x MHz RF generator is in state S1bx during state S1 of the TTL1 signal, the y MHz RF generator is in state S1ay.

When the x MHz RF generator transitions from state S0bx to state S0ax during state S0 of the TTL1 signal, the y MHz generator transitions from state S0ay to state S0by. Also, when the x MHz RF generator transitions from state S0ax to state S0bx during state S0 of the TTL1 signal, the y MHz generator transitions from state S0by to state S0ay. Also, when the x MHz RF generator is in state S0ax during state S0 of the TTL1 signal, the y MHz RF generator is in state S0by. Also, when the x MHz RF generator is in state S0bx during state S0 of the TTL1 signal, the y MHz RF generator is in state S0ay.

It should be noted that the transmitted power level of the transmitted power signal 1012 generated by the y MHz RF generator during state S1ay is greater than during the state S1by. Again, the transmitted power level of the transmitted power signal 1014 generated by the x MHz RF generator during state S1ax is greater than during the period S1bx.

Again, it should be noted that the transmitted power level of the transmitted power signal 1012 generated by the y MHz RF generator during state S0ay is greater than during the state S0by. Again, the transmitted power level of the transmitted power signal 1014 generated by the x MHz RF generator during state S0ax is greater than during the state S0bx.

In some embodiments, the transmitted power level of the transmitted power signal 1012 generated by the y MHz RF generator during state S0by is less than the delivered power generated by the x MHz RF generator during state S0bx. The transmitted power level of signal 1014.

In several embodiments, the transmitted power level of the transmitted power signal 1012 generated by the y MHz RF generator during state S1by is less than the delivered power generated by the x MHz RF generator during state S1bx. The transmitted power level of signal 1014.

11A shows an embodiment of a system 1100 for illustrating simultaneous use of secondary pulsations in both x and y MHz RF generators. The tool UI system 306 includes a clock source capable of generating a TTL1 signal and provides a TTL1 signal to DSPx and DSPy via a corresponding cable. The DSPx generates a TTL5 signal and provides a clock signal to the DSPy when receiving the clock signal TTL1. The remaining operation of the x MHz RF generator is similar to that described with reference to Figure 7A. Again, the remaining operation of the y MHz RF generator is similar to that described with reference to Figure 9A.

11B shows an embodiment of a system 1110 that is used to illustrate the simultaneous use of secondary ripple in both x and y MHz RF generators when the x MHz RF generator is acting as the primary generator. DSPx generates TTL1 and TTL5 signals and provides both signals TTL1 and TTL5 to DSPy via corresponding cables. The remaining operation of the x MHz RF generator is similar to the corresponding description of Figure 7B. Again, the remaining operation of the y MHz RF generator is similar to the corresponding description of Figure 9B.

12 shows an embodiment of a system 1200 for illustrating the selection of one of four sub-states S1a, S1b, S0a, and S0b using switch 1202 in an x MHz RF generator or a y MHz RF generator. An example of switch 1202 includes a multiplexer. In some embodiments switch 1202 is implemented as a computer program or hardware within a DSP (such as DSPx or DSPy). Switch 1202 is coupled to the DSP. For example, when switch 1202 is within the x MHz RF generator, switch 1202 is coupled to DSPx, and when switch 1202 is within the y MHz RF generator, switch 1202 is coupled to DSPy.

When a state of the TTL signal (such as the digital pulse signal TTL3, the digital pulse signal TTL5, etc.) is S0a, the DSP generates the bit "00". When a state of the TTL signal is S0b, the DSP generates the bit "01". When a state of the TTL signal is S1a, the DSP generates the bit "10". When a state of the TTL signal is S1b, the DSP generates the bit "11". The TTL signal is generated by the DSP or received by the DSP. For example, DSPx generates a digital pulse signal TTL3 or a TTL signal TTL5, and DSPy receives a digital pulse signal TTL3 or a digital pulse signal TTL5.

When the switch 1202 of the RF generator receives the bit "00", the switch 1202 sends a signal to the parameter controller PRS0a of the RF generator, such as a power controller, an automatic frequency adjuster, and the like. After receiving the signal indicating the bit "00" from the switch 1202, the parameter controller PRS0a recognizes a parameter level, such as a frequency level, a power level, etc., from the mapping between the bit "00" and the parameter level.

Similarly, when the switch 1202 of the RF generator receives the bit "01", the switch 1202 sends a signal to the parameter controller PRS0b of the RF generator. After receiving the signal indicating the bit "01" from the switch 1202, the parameter controller PRS0b recognizes a parameter level from the mapping between the bit "01" and the parameter level.

Also, when the switch 1202 of the RF generator receives the bit "10", the switch 1202 sends a signal to the parameter controller PRS1a of the RF generator. After receiving the signal indicating the bit "10" from the switch 1202, the parameter controller PRS1a recognizes a parameter level from the mapping between the bit "10" and the parameter level.

Also, when the switch 1202 of the RF generator receives the bit "11", the switch 1202 sends a signal to the parameter controller PRS1b of the RF generator. After receiving the signal indicating the bit "11" from the switch 1202, the parameter controller PRS1b recognizes a parameter level from the mapping between the bit "11" and the parameter level.

FIG. 13A shows an embodiment of a DSP 1300 for illustrating the generation of a TTL3 digital pulse signal. The DSP 1300 includes an internal clock source 1302 and processing logic 1104, such as a computer program, an ASIC, a PLD, and the like. In some embodiments, DSP 1300 includes a memory device to store processor logic 1104.

The TTL1 signal is generated by an external clock source (such as the clock source of tool UI system 306 (Fig. 3A), another clock source external to tool UI system 306, etc.). Again, the TTL2 signal is generated by internal clock source 1302. For example, the frequency of a TTL2 signal is higher than the frequency of a TTL1 signal.

The processing logic 1104 receives the TTL1 clock signal and the TTL2 signal, multiplies the signal TTL1 by TTL2 to generate a TTL3 signal, and supplies the obtained TTL3 signal to the RF generator where the DSP 1300 is located, such as an x MHz RF generator, y MHz RF generation. A parameter controller such as a device or another RF generator such as a y MHz RF generator, a parameter controller such as an x MHz RF generator.

In various embodiments, DSP 1300 includes a switch that can select between a TTL1 signal and a TTL2 signal based on the state of the TTL1 signal. For example, when the TTL1 signal is in state S0, the switch selects the TTL1 signal to provide a parameter controller for the RF generator in which the DSP 1300 is located or a parameter controller that provides another RF generator. Also, in this example, when the TTL1 signal is in state S1, the switch selects the TTL2 signal to provide a parameter controller for the RF generator in which the DSP 1300 is located or a parameter controller that provides another RF generator. In this example, a portion of the TTL2 signal having states S1a and S1b is selected during state S1 of the TTL1 signal.

FIG. 13B is an embodiment of a DSP 1320 for generating a TTL5 signal. The DSP 1320 includes an internal clock source 1302, an inverter 1322, another internal clock source 1324, processing logic 1326, and an adder 1328.

In some embodiments, adder 1328, processing logic 1326, and inverter 1322 are implemented in hardware, for example, using logic gates or the like. In various embodiments, adder 1328, processing logic 1326, and inverter 1322 are implemented as a computer program (eg, processing logic, etc.) and are executable by DSP 1320.

The internal clock source 1302 generates a TTL4-2 signal, such as a clock signal such as a TTL2 signal. Processing logic 1326 processes the TTL 4-2 signal and the time pulse signal TTL1 to generate a TTL3 signal. For example, processing logic 1326 multiplies the TTL4-2 signal by the clock signal TTL1 to generate a TTL3 digital pulse signal. The digital pulse signal TTL3 is supplied to the adder 1328.

In addition, the inverter 1322 receives the TTL1 signal and inverts the logic level of the TTL1 signal. For example, the logic level 1 of the TTL1 signal is inverted to logic level 0, and the logic level 0 of the TTL1 signal is inverted to logic level 1. Processing logic 1326 receives the already inverted TTL1 signal generated by inverter 1322. Again, internal clock source 1324 generates a clock signal TTL4-1 and provides it to processing logic 1326. The processing logic 1326 processes the clock signal TTL4-1 and the TTL1 clock signal to generate a TTL signal, and the adder 1328 adds the TTL signal to the TTL3 signal to generate a TTL5 signal.

It should be noted that in some embodiments, the frequency of each TTL 4-1 signal and the TTL 4-2 signal is greater than the frequency of the TTL 1 signal. In various embodiments, the frequency of the TTL4-1 signal is equal to the frequency of the TTL4-2 signal.

In some embodiments, the DSP 1320 includes a clock source, where the frequency of the pulse source is the same as the frequency of the pulsation signal 602 (FIG. 6A) or the pulsation signal 802 (FIG. 8A).

Figure 14 shows an embodiment of a DSP 1400 that uses a modulation signal 1203 to determine whether to generate a plurality of secondary states Sna and Snb or to generate a state Sm. Each of DSPx and DSPy is an example of a DSP 1400. The DSP 1400 receives the clock signal Clk having the states Sm and Sn, such as a TTL1 signal. In some embodiments, state Sm is a high logic level state and state Sn is a low logic level state. The high logic level is higher than the low logic level.

The DSP 1400 also receives a modulated signal 1203 having three logic levels (i.e., a high logic level, a medium logic level, and a low logic level). The medium logic level is higher than the low logic level, and the high logic level is higher than the medium logic level. Moreover, the middle logic level is achieved by a low level conversion, and the time period from the low level to the middle level is longer than the time from the middle logic level to the high logic level.

The DSP 1400 determines that the conversion of the modulation signal 1203 from the state Sn to the state Sm for the clock signal Clk is slower than the transition from the state Sm to the state Sn of the clock signal Clk. Moreover, the DSP 1400 determines that the modulation signal 1203 has reached the middle logic level during the state Sm of the clock signal Clk. The DSP 1400 generates the clock 1 signal Clk1, such as the TTL3 signal, etc., when it is determined that the transition of the clock signal Clk from the state Sn to the state Sm is slower than the transition of the clock signal Clk from the state Sm to the state Sn, and When it is determined that the modulation signal 1203 has reached the middle logic level during the state Sm of the clock signal Clk, the signal Clk1 has the state Sm.

Moreover, the DSP 1400 determines that the conversion signal 1203 has a transition from the state Sm to the state Sn of the clock signal Clk, which is faster than the transition of the clock signal Clk from the state Sn to the state Sm. Moreover, the DSP 1400 determines that the modulation signal 1203 has reached a high logic level during the state Sn of the clock signal Clk. When it is determined that the transition from the state Sm to the state Sn of the clock signal Clk is faster than the transition of the clock signal Clk from the state Sn to the state Sm and it is determined that the modulation signal 1203 is in the state Sn of the clock signal Clk When the high logic level has been reached, the DSP 1400 generates a Clk1 signal having a plurality of states Sna and Snb.

It should be further noted that the single clock source, such as the clock source that generates the clock signal Clk, is used in the description of FIG.

In various embodiments, the term "level" as used herein encompasses a range. For example, a power level includes a range of power levels, such as between 1950 watts and 2050 watts, between 1900 watts and 2100 watts, between 950 watts and 1050 watts, In the range between 900 watts and 1300 watts, etc. The other quasi-frequency level contains a range of frequencies such as a range between 1.9 MHz and 2.1 MHz, a range between 1.7 MHz and 2.3 MHz, and a range between 58 MHz and 62 MHz. , a range between 55 MHz and 65 MHz, a range between 25 MHz and 29 MHz, and a range between 23 MHz and 31 MHz.

Moreover, in various embodiments, the one-bit system identified from the memory device of the controller or the memory device of the self-regulator is related to such as mapping, bonding, etc. to a process rate such as etch rate, or deposition rate, or sputtering. Rate or process wafer 318.

It should be further noted that although the above operations are described with reference to a parallel plate plasma chamber such as a capacitively coupled plasma chamber, etc., in some embodiments, the above operations may be applied to other types of plasma chambers, such as including inductively coupled plasma ( ICP) A plasma chamber of a reactor, a plasma chamber containing a transformer coupled plasma (TCP) reactor, a plasma chamber containing a dielectric tool, a plasma chamber containing an electron cyclotron resonance (ECR) reactor, and the like. For example, an x MHz RF generator is coupled to a y MHz RF generator to an inductor within the ICP plasma chamber.

It should also be noted that while the above operations are performed by a DSP, in some embodiments such operations may be performed by one or more processors of the tool UI system 306 (FIG. 3A), or a plurality of processors of a plurality of tool UI systems, or The combination of the DSP and processor of the RF generator of the tool UI system 306 is performed.

It should be noted that while the above embodiments are directed to providing one or more RF signals to the lower electrode of the chuck 314 of the plasma chamber 304 and the upper electrode 316 of the ground plasma chamber 304, in several embodiments, the one or A plurality of RF signals are supplied to the upper electrode 316 but the lower electrode is grounded.

The embodiments described herein can be implemented using a variety of computer system configurations, including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, mini-computers, host computers, and the like. Such embodiments can also be implemented in a decentralized computing environment where tasks are performed by remote processing hardware units connected via a network.

In some embodiments, the controller is part of a system that is part of the above examples. Such systems include semiconductor processing equipment including processing tools or complex tools, process chambers or complex processing chambers, processing platforms or complex platforms, and/or specific processing components (wafer mounts, gas flow systems, etc.). Such systems are integrated with electronic devices that control the operation of the system before, during, and after processing of the semiconductor wafer or substrate. Such electronic devices are referred to as "controllers" that can control various components or sub-components of the system or complex systems. Depending on the processing requirements and/or system type, the controller is programmed to control any of the processes disclosed herein including conveying process gases, temperature settings (eg, heating and/or cooling), pressure settings, vacuum settings, flow rate settings, fluids Delivery settings, position and operational settings, wafer transfer into or out of the device, and other transfer devices and/or load lock mechanisms that are connected to or interfaced with the system.

In general terms, in various embodiments, a controller is defined as an electronic device having various integrated circuits, logic, memory, and/or software that can receive instructions, issue instructions, control operations, enable cleaning operations, Can measure the end point, etc. The integrated circuit includes a firmware-formatted chip, a digital signal processor (DSP), a chip defined as an ASIC, a PLD, and/or one or more microprocessors capable of executing program instructions (such as software). Or microcontroller. The program instructions are instructions in communication with the controller in the form of various independent settings (or program files) that define operational parameters for specific processing or specific processing of the system on a semiconductor wafer or for a semiconductor wafer. In some embodiments, the operating parameters are ones during which the process engineer manufactures the die of one or more layers, materials, metals, oxides, tantalum, hafnium, surfaces, circuits, and/or wafers. Part of a recipe defined by multiple process steps.

In some embodiments the controller is part of a computer that is integrated into, coupled to, connected to, or combined with the system. For example, the controller is located in the cloud or all or part of the factory host computer system is in the cloud, which allows the user to access the wafer processing remotely. The computer enables a remote access system to monitor the current progress of manufacturing operations, review the history of past manufacturing operations, review performance drivers from multiple manufacturing operations, change existing processing parameters, set processing steps to comply with existing processing, or start a new one. Process.

In some embodiments, the remote computer (or server) provides a recipe for the system via the network, the network including the regional network or the internet. The remote computer includes a user interface that allows the user to enter or program parameters and/or settings and then communicate with the system from the remote computer. In some instances, the controller receives instructions in the form of data indicating parameters of each process step to be performed during one or more operations. It should be understood that the parameters are specific to the type of process to be performed and the type of equipment that the controller uses to interface or control. Thus, as described above, the decentralized controller is such as by a discrete controller that includes one or more processes and controls that are interconnected by a network and that are oriented toward a common purpose, as described herein. A decentralized controller for such purposes includes one or more integrated circuits on the process chamber that communicate with one or more integrated circuits located at a remote end (eg, at a platform level or a portion of a remote computer) Joint control of the process on the process chamber.

Without limitation, in various embodiments, an exemplary system includes a plasma etch chamber or module, a deposition chamber or module, a rotary rinsing chamber or module, a metal plating chamber or module, a cleaning chamber or module, Edge etch chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or Modules, ion implantation chambers or modules, track chambers or modules, and any other semiconductor processing system associated with the manufacture of semiconductor wafers or for fabrication.

As described above, depending on the process steps or multiple steps performed by the device, the controller can communicate with one or more of the following: circuits or modules of other devices, components of other devices, cluster devices, interfaces of other devices, A material transport device used to load a wafer container into and out of a device location and/or a load interface in an adjacent device, a neighboring device, a device located in a factory, a host computer, another controller, or a semiconductor manufacturing facility.

In view of the above-described embodiments, it should be appreciated that embodiments can perform various computer operations involving data stored in a computer system. These operations require substantial manipulation of the physical quantity. Any of the operations described to form part of the embodiment are useful mechanical operations.

Some embodiments are also directed to hardware units or devices that perform such operations. Equipment can be built specifically for specialized computers. When a computer is defined as a dedicated computer, the computer can be used for other purposes, other processing, program execution or other non-special purpose subprograms.

In some embodiments, the operations may be performed by a computer that is selectively activated or configured by one or more computer programs stored in computer memory, cache memory, or from a network. When data is obtained from a computer network, the data can be processed by other computers on the computer network, such as computing resources.

One or more embodiments can be fabricated as computer readable code on a non-transitory computer readable medium. A non-transitory computer readable medium is any data storage hardware unit such as a memory device that can store data and subsequently be readable by a computer system. Examples of non-transitory computer readable media include hard disk, network attached storage (NAS), ROM, RAM, compact disk-ROM (CD-ROM), recordable CD (CD-R), re-writable CD (CD-RW), magnetic tape and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer readable medium can comprise a computer readable physical medium distributed over a network coupled computer system such that the computer readable code is stored and executed in a distributed fashion.

Although the foregoing method operations are described in a particular order, it should be appreciated that in various embodiments, other idle operations may be performed between operations or that the method operations may be adjusted to occur slightly differently, or that method operations may be assigned to The method operations are allowed to operate at various intervals or allow the method operations to be performed in a different order than the order described above.

It is further noted that in an embodiment, one or more features from any embodiment can be combined with one or more features of any other embodiment without departing from the scope of the various embodiments described herein.

Although the foregoing embodiments have been described in detail for the purpose of the invention, the invention Therefore, the present embodiments are to be considered as illustrative and not restrictive

100‧‧‧RF generator
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202‧‧‧pulse signal
204‧‧‧clock signal
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1002‧‧‧ Signal
1004‧‧‧ Signal
1010‧‧‧ Figure
1012‧‧‧ transmitted power signal
1014‧‧‧ transmitted power signal
1100‧‧‧ system
1104‧‧‧ Processing logic
1110‧‧‧System
1200‧‧‧ system
1202‧‧‧Switch
1300‧‧‧DSP
1302‧‧‧Internal clock source
1320‧‧‧DSP
1322‧‧‧Inverter
1324‧‧‧Another internal clock source
1326‧‧‧ Processing logic
1328‧‧‧Adder
1400‧‧‧DSP
AFTS0x‧‧‧Automatic frequency adjuster
AFTS0ax‧‧‧Automatic frequency adjuster
AFTS0bx‧‧‧Automatic frequency adjuster
AFTS0y‧‧‧Automatic frequency adjuster
AFTS0ay‧‧‧Automatic frequency adjuster
AFTS0by‧‧‧Automatic frequency adjuster
AFTS1x‧‧‧Automatic frequency adjuster
AFTS1ax‧‧‧Automatic frequency adjuster
AFTS1bx‧‧‧Automatic frequency adjuster
AFTS1y‧‧‧Automatic frequency adjuster
AFTS1ay‧‧‧Automatic frequency adjuster
AFTS1by‧‧‧Automatic frequency adjuster
Clk‧‧‧ clock signal
Clk1‧‧‧ signal
DSPx‧‧‧ digital signal processor
DSPy‧‧‧Digital Signal Processor
PRS0a‧‧‧ parameter controller
PRS1a‧‧‧ parameter controller
PRS0b‧‧‧ parameter controller
PRS1b‧‧‧ parameter controller
PWRS0x‧‧‧ power controller
PWRS0ax‧‧‧Power Controller
PWRS0bx‧‧‧Power Controller
PWRS0y‧‧‧Power Controller
PWRS0ay‧‧‧Power Controller
PWRS0by‧‧‧Power Controller
PWRS1x‧‧‧ power controller
PWRS1ax‧‧‧Power Controller
PWRS1bx‧‧‧ power controller
PWRS1y‧‧‧ power controller
PWRS1ay‧‧‧Power Controller
PWRS1by‧‧‧Power Controller
S0‧‧‧ Status
S0a‧‧‧ Status
S0ax‧‧‧ Status
S0ay‧‧‧ Status
S0b‧‧‧ Status
S0bx‧‧‧ Status
S0by‧‧‧ Status
S1‧‧‧ Status
S1a‧‧‧ Status
S1ax‧‧‧ Status
S1ay‧‧‧ Status
S1b‧‧‧ Status
S1bx‧‧‧ Status
S1by‧‧‧ Status
Sm‧‧‧ Status
Sna‧‧‧ Status
Snb‧‧ state
TTL‧‧‧ signal
TTL1‧‧‧ signal
TTL2‧‧‧ signal
TTL4‧‧‧ signal
TTL4-1‧‧‧ signal
TTL4-2‧‧‧ signal
TTL5‧‧‧ signal

Embodiments of the present invention are best understood by reference to the drawings and the following description.

1 illustrates a secondary pulsation in one of the states of a radio frequency (RF) signal generated by an RF generator in accordance with some embodiments of the present invention.

2A illustrates secondary pulsations in one state of a x megahertz (MHz) RF generator in accordance with certain embodiments of the present invention.

2B illustrates the secondary pulsations generated by the x MHz RF generator achieved using the pulsations generated by the y MHz RF generator, in accordance with various embodiments of the present invention.

2C illustrates signals having non-zero logic levels during the secondary pulsation state S1b in accordance with various embodiments of the present invention.

2D illustrates the use of a signal having a non-zero logic level during the secondary pulsation state S1b and a pulsation signal generated by the y MHz RF generator, in accordance with certain embodiments of the present invention.

2E is a diagram illustrating a duty cycle having a different duty cycle than 50% during state S1 in accordance with several embodiments of the present invention.

FIG. 3A illustrates a system for controlling ion energy during states S0, S1a, and S1b in accordance with various embodiments of the present invention.

3B illustrates another system for controlling ion energy during states S0, S1a, and S1b when the x MHz RF generator is the primary generator, in accordance with several embodiments of the present invention.

4A illustrates an x MHz RF generator operating in two states S1 and S0 and a y MHz RF generator operating in state S1, state S0a, and state S0b, in accordance with certain embodiments of the present invention.

Figure 4B illustrates a y MHz RF generator operating in state S1, state S0a and state S0b, and a bit different from the power signal shown in Figure 4A during state S0b, in accordance with various embodiments of the present invention.

Figure 4C illustrates a y MHz RF generator operating in state S1, state S0a and state S0b in accordance with certain embodiments of the present invention and differing from the one shown in Figure 4A during state S0a.

4D illustrates the use of different levels of transmitted power signals during states S0a and S0b, in accordance with various embodiments of the present invention, as compared to the level of the transmitted power signals shown in FIG. 4A.

4E illustrates a distinct duty cycle that is not 50% duty cycle during state S0, in accordance with various embodiments of the present invention.

5A shows a system for illustrating that a y MHz RF generator generates RF signals having states S1, S0a, and S0b, in accordance with certain embodiments of the present invention.

5B shows a system for exemplifying an RF signal having states S1, S0a, and S0b when the x MHz RF generator is the master generator, in accordance with various embodiments of the present invention. .

6A illustrates a secondary pulsation of an RF signal generated by an x MHz RF generator in accordance with certain embodiments of the present invention during states S1 and S0.

6B illustrates an x MHz RF generator that produces an RF signal having four secondary states S0a, S0b, S1a, and S1b using a y MHz RF generator in conjunction with various embodiments in accordance with the present invention.

Figure 6C illustrates that the duty cycle during state S0 is different from the duty cycle during state S1 in accordance with several embodiments of the present invention.

Figure 7A shows a system in accordance with some embodiments of the present invention for illustrating the use of four secondary states S0a, S0b, S1a, and S1b in an x MHz RF generator.

7B shows a system for illustrating the use of four secondary states S0a, S0b in an x MHz RF generator when the x MHz RF generator is the primary generator, in accordance with various embodiments of the present invention. S1a and S1b.

Figure 8A illustrates the secondary pulsations of the RF signals generated by the y MHz RF generator in states S1 and S0, in accordance with certain embodiments of the present invention.

Figure 8B illustrates a y MHz RF generator that produces an RF signal having four secondary states S0a, S0b, S1a, and S1b using an x MHz RF generator in conjunction with various embodiments in accordance with the present invention.

Figure 8C illustrates that the duty cycle during state S0 is different from the duty cycle during state S1 in accordance with various embodiments of the present invention.

Figure 9A shows a system in accordance with some embodiments of the present invention for illustrating the use of four secondary states S0a, S0b, S1a, and S1b in a y MHz RF generator.

9B shows a system for illustrating the use of four secondary states S0a, S0b in a y MHz RF generator when the x MHz RF generator is the primary generator, in accordance with various embodiments of the present invention. S1a and S1b.

Figure 10A illustrates multiple secondary states of both x and y MHz RF generators in accordance with various embodiments of the present invention.

Figure 10B illustrates multiple secondary states of both x and y MHz RF generators in accordance with several embodiments of the present invention.

Figure 11A shows a system in accordance with some embodiments of the present invention for illustrating simultaneous use of secondary pulsations in both x and y MHz RF generators.

Figure 11B shows a system in accordance with various embodiments of the present invention for illustrating simultaneous use of secondary ripple in both x and y MHz RF generators when the x MHz RF generator is acting as the primary generator.

Figure 12 shows a system according to several embodiments of the present invention for illustrating the use of switches in an x MHz RF generator or a y MHz RF generator to select four secondary states S1a, S1b, S0a and S0b One of them.

FIG. 13A shows a digital signal processor (DSP) for illustrating the use of an internal clock source to generate a digital pulse signal in accordance with some embodiments of the present invention.

Figure 13B shows a DSP for illustrating the use of a plurality of internal clock sources to generate digital pulse signals in accordance with various embodiments of the present invention.

Figure 14 shows a DSP in accordance with some embodiments of the present invention that uses a modulation signal to determine whether to generate a plurality of secondary states Sna and Snb or to generate a state Sm.

100‧‧‧RF generator

Sm‧‧‧ Status

Sna‧‧‧ Status

Snb‧‧ state

Claims (20)

A method includes: receiving a clock signal having two states from a clock source; generating a pulse signal from the clock signal, the pulse signal having a plurality of states in a state of the plurality of states, the plurality of states being greater than a frequency of one of the states alternating with respect to each other; and providing the pulsation signal to control the power of a radio frequency (RF) signal generated by an RF generator, the power being controlled to be synchronized with the pulsation signal . The method of claim 1, wherein the power controlled to synchronize with the pulsation signal has a frequency that is the same as a frequency of one of the pulsation signals. The method of claim 1, wherein the clock source comprises a quartz oscillator or a quartz oscillator coupled to a phase locked loop. The method of claim 1, wherein the RF generator is a 2 megahertz RF generator or a 60 megahertz RF generator. The method of claim 1, wherein the two states comprise a high state and a low state, the high state having one of the logic levels being higher than the low state having one of the logic levels. The method of claim 1, wherein the pulsation signal is switched from one state of the two states to a first state of the two states, and then the first state transitions to one of the two states a secondary state, then transitioning from the second state to the first state, then transitioning from the first state to the second state, and then transitioning from the second state to the state of the two states . The method of claim 6, wherein the power of the RF signal comprises a complex power level, wherein the power level of the complex power level during a low-order state of the plurality of times is equal to or higher than a power level The complex power level is at another power level during one of the low states of the complex state. The method of claim 1, further comprising: providing the clock signal to an additional RF generator to generate an additional RF signal synchronized with the clock signal. The method of claim 8, wherein the RF signal generated by the RF generator and the additional RF signal generated by the additional RF generator are supplied to an impedance matching circuit based on the RF signal and the additional RF a signal that produces a modified RF by matching the impedance of one of the plasma chamber and an RF transmission line with the impedance of the RF generator, the additional RF generator, an RF cable, and an additional RF cable. a signal, the RF transmission line coupling the plasma chamber to the impedance matching circuit, the RF cable coupling the RF generator to the impedance matching circuit, and the additional RF cable coupling the additional RF generator to the impedance matching Circuit. The method of claim 1, wherein the RF signal has four complex states, that is, a first state, a second state, a third state, and a fourth state, the RF signal The power has a complex power level, and a first power level of the complex power level is switched from the first state to a second power level of the complex power level in the second state, and then the Converting the second power level to the first power level in the first state, and then converting the first power level to the second power level in the second state, and then the second power level Converting to a third power level of the complex power level in the third state, and then converting the third power level to a fourth power level of the complex power level to achieve the fourth state Then, the fourth power level is switched to the third power level to reach the third state, and then the third power level is switched to the fourth power level. The method of claim 10, wherein the second power level is equal to, or less than, or greater than the fourth power level, wherein the first power level is less than the third power level. The method of claim 10, wherein the second power level is equal to, or less than, or greater than the fourth power level, wherein the first power level is greater than the third power level. The method of claim 10, wherein the source of the clock is located in a digital signal processor of the RF generator. The method of claim 10, wherein the source of the clock is external to the RF generator. A radio frequency (RF) generator includes: a processor, configured to: receive a clock signal having two states from a clock source; generate a pulse signal from the clock signal, and the pulse signal is in a state of the complex state Having a plurality of times, the plurality of states having a frequency greater than a frequency of the states; and providing the pulsation signal to control the power of an RF signal, the power being controlled to synchronize with the pulsation signal; An RF power source is coupled to the processor, the RF power source for generating the RF signal having the power to provide the RF signal to a plasma chamber by an impedance matching circuit. A radio frequency (RF) generator as claimed in claim 15 further comprising: a power controller coupled to the processor, the power controller being configured to map based on the complex state and the complex power level Identifying a power level based on a mapping between the plurality of states and the complex power level; and a frequency adjuster coupled to the processor, the frequency adjuster for determining the complex state and the complex frequency level based on the complex A mapping between the plurality of states and the complex frequency level identifies a frequency level. The radio frequency (RF) generator of claim 15, wherein the plasma chamber comprises an upper electrode and a collet, the collet faces the upper electrode, and the power of the RF signal has the complex power level Each of the power levels is mapped to an etch rate or a deposition rate. A system comprising: a processor, configured to: receive a clock signal having two states from a clock source; generate a pulse signal from the clock signal, the pulse signal having a plurality of states in one state of the complex state And the frequency of the plurality of states is greater than a frequency of the states; and the pulse signal is provided to control the power of a radio frequency (RF) signal, the power is controlled to be synchronized with the pulse signal; and an RF a power source for generating the RF signal having the power; an RF cable coupled to the RF power source; an impedance matching circuit coupled to the RF power source for receiving the RF signal by the RF cable, the impedance matching The circuit is configured to match an impedance coupled to a load of the impedance matching circuit and an impedance coupled to a source of the impedance matching circuit to generate a modified RF signal from the RF signal; and a plasma chamber coupled To the impedance matching circuit, an impedance of a plasma is changed to receive the modified RF signal. A system as claimed in claim 18, further comprising an RF transmission line coupling the plasma chamber to the impedance matching circuit, wherein the load comprises the plasma chamber and the RF transmission line, wherein the source comprises the RF cable The RF generator. The system of claim 18, wherein the pulsation signal transitions from a state of the two states to a first state of the two states, and then transitions from the first state to a state of the two states a secondary state, then transitioning from the second state to the first state, then transitioning from the first state to the second state, and then transitioning from the second state to the state of the two states .