TW201622105A - Semiconductor device, and production method therefor - Google Patents

Semiconductor device, and production method therefor Download PDF

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TW201622105A
TW201622105A TW104133915A TW104133915A TW201622105A TW 201622105 A TW201622105 A TW 201622105A TW 104133915 A TW104133915 A TW 104133915A TW 104133915 A TW104133915 A TW 104133915A TW 201622105 A TW201622105 A TW 201622105A
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gate electrode
memory
contact
gate
sidewall
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TW104133915A
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TWI610418B (en
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Yasuhiro Taniguchi
Yasuhiko Kawashima
Hideo Kasai
Ryotaro Sakurai
Yutaka Shinagawa
Kosuke Okuyama
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Floadia Corp
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Abstract

Provided is a semiconductor device (1) in which a contact (C5a) is provided so as to extend to a first selection gate electrode (G2a) from the top of a contact installation structure (10a) having the same configuration as a memory gate structure (4a). Accordingly, a conventional mounting section (102b) mounting the top of the memory gate structure (110) is not formed (fig. 13), and thus the distance to an upper-layer wiring layer can be shortened, the aspect ratio can be reduced, and, as a result, an increase in the contact resistance value can be inhibited. Furthermore, the conventional mounting section (102b) mounting the top of the memory gate structure (110) is not formed, and thus the contact installation structure (10a) and the upper-layer wiring layer can be kept apart, and, as a result, contact failure with the upper-layer wiring layer can be inhibited. Also provided is a production method for said semiconductor device.

Description

半導體裝置及其製造方法 Semiconductor device and method of manufacturing same

本發明係關於一種半導體裝置及其製造方法。 The present invention relates to a semiconductor device and a method of fabricating the same.

先前，半導體裝置一般為如下構成，即，於將設置於基板上之閘極電極與配置於該閘極電極之上層之配線層連接時設置柱狀之接點，使用該接點將閘極電極與配線層電性連接(例如參照非專利文獻1)。作為設置有複數個接點之半導體裝置，例如考慮如下構成：於活性區域上(基板表面上)設置依次積層有下部閘極絕緣膜、電荷儲存層、上部閘極絕緣膜、及記憶體閘極電極之記憶體閘極構造體及介隔側壁間隔件設置於該記憶體閘極構造體之側壁之選擇閘極構造體，於各部位設置接點。 Conventionally, a semiconductor device is generally configured to provide a columnar contact when a gate electrode provided on a substrate is connected to a wiring layer disposed on an upper layer of the gate electrode, and the gate electrode is used to connect the gate electrode with the contact point. The wiring layer is electrically connected (see, for example, Non-Patent Document 1). As a semiconductor device provided with a plurality of contacts, for example, a configuration is described in which a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate are sequentially laminated on an active region (on the surface of the substrate). The memory gate structure of the electrode and the spacer sidewall spacer are disposed on the sidewall of the memory gate structure, and contacts are provided at the respective portions.

例如，此種半導體裝置係自各種配線層經由接點對記憶體閘極電極或選擇閘極構造體之選擇閘極電極等各部位施加特定之電壓，藉此，可藉由因基板表面與記憶體閘極電極G100之電壓差產生之量子穿隧效應而對電荷儲存層EC注入電荷。 For example, such a semiconductor device applies a specific voltage to each portion of the memory gate electrode or the selected gate electrode of the gate structure from the various wiring layers via the contact, whereby the substrate surface and the memory can be used. The quantum tunneling effect generated by the voltage difference of the body gate electrode G100 injects charges into the charge storage layer EC.

於該情形時，介隔側壁間隔件設置於記憶體閘極構造體之側壁之選擇閘極構造體係與記憶體閘極電極分開地另外自接點設置部對選擇閘極電極施加特定之電壓，藉此，可獨立於記憶體閘極電極而控制該選擇閘極電極。 In this case, the selective gate structure in which the sidewall spacer is disposed on the sidewall of the memory gate structure is separately from the memory gate electrode, and a specific voltage is applied to the selected gate electrode from the contact portion. Thereby, the selective gate electrode can be controlled independently of the memory gate electrode.

例如，如圖13所示，於此種半導體裝置100，可於與活性區域(未圖示)鄰接之元件分離層101上設置與選擇閘極電極(未圖示)一體形成 之接點設置部102。於該情形時，於半導體裝置100，記憶體閘極構造體之電荷儲存層EC、上部閘極絕緣膜23b、及記憶體閘極電極G100延設至元件分離層101上為止，可於該等電荷儲存層EC、上部閘極絕緣膜23b、記憶體閘極電極G100之側壁介隔側壁間隔件105形成接點設置部102。再者，該等記憶體閘極電極G100或接點設置部102等各部位由層間絕緣層120覆蓋，於位於層間絕緣層120之上層之另一層間絕緣層121設置有上層之配線層112。 For example, as shown in FIG. 13, the semiconductor device 100 can be formed integrally with a selective gate electrode (not shown) on the element isolation layer 101 adjacent to an active region (not shown). The contact setting unit 102. In this case, in the semiconductor device 100, the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G100 of the memory gate structure are extended to the element isolation layer 101. The sidewalls of the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G100 are separated by a sidewall spacer 105 to form a contact placement portion 102. Further, each of the memory gate electrode G100 or the contact portion 102 is covered with an interlayer insulating layer 120, and the other interlayer insulating layer 121 located above the interlayer insulating layer 120 is provided with an upper wiring layer 112.

接點設置部102係於平坦之接點設置面102c豎立設置有接點C100，藉由該接點C100而與上層之配線層112電性連接。藉此，接點設置部102可將自上層之配線層112施加之電壓施加至形成於活性區域之選擇閘極電極。 The contact setting unit 102 is provided with a contact C100 erected on the flat contact mounting surface 102c, and is electrically connected to the wiring layer 112 of the upper layer by the contact C100. Thereby, the contact setting portion 102 can apply a voltage applied from the wiring layer 112 of the upper layer to the selection gate electrode formed in the active region.

此種半導體裝置100具有如下構成：接點設置部102與上層之一配線層112藉由接點C100而電性連接，除此以外，例如於未圖示之活性區域，形成於活性區域上之雜質擴散區域(未圖示)與上層之另一配線層113亦藉由另一接點C101而電性連接。 The semiconductor device 100 has a configuration in which the contact portion 102 and the upper wiring layer 112 are electrically connected by a contact C100, and are formed on the active region, for example, in an active region (not shown). The impurity diffusion region (not shown) and the other wiring layer 113 of the upper layer are also electrically connected by another contact C101.

再者，於半導體裝置100，一般而言，亦於設置有配線層112、113之層間絕緣層121之上層形成有另一層間絕緣層123，而可於該層間絕緣層123配置另一配線層114。於該情形時，於半導體裝置100，配線層113、114間藉由接點C102而電性連接，例如施加至最上層之配線層114之電壓可依次經由接點C102、配線層113、及接點C101而施加至基板表面之雜質擴散層。 Further, in the semiconductor device 100, in general, another interlayer insulating layer 123 is formed on the interlayer insulating layer 121 provided with the wiring layers 112 and 113, and another wiring layer may be disposed in the interlayer insulating layer 123. 114. In this case, in the semiconductor device 100, the wiring layers 113 and 114 are electrically connected by the contact C102. For example, the voltage applied to the uppermost wiring layer 114 may sequentially pass through the contact C102, the wiring layer 113, and the connection. The impurity diffusion layer applied to the surface of the substrate was applied to point C101.

[先前技術文獻] [Previous Technical Literature] [非專利文獻] [Non-patent literature]

[非專利文獻1]「製作半導體Renesas Electronics」、[online]、2014年10月08日檢索、網際網路(URL：http://japan.renesas.com/company_info/fab/line/line12.html) [Non-Patent Document 1] "Production of Semiconductor Renesas Electronics", [online], October 08, 2014 Search, Internet (URL: http://japan.renesas.com/company_info/fab/line/line12.html )

然而，製造介隔側壁間隔件105與記憶體閘極電極G100鄰接之選擇閘極電極(未圖示)、及與該選擇閘極電極一體形成之接點設置部102時，首先，於活性區域上形成由側壁間隔件105覆蓋之記憶體閘極構造體時，亦於元件分離層101形成由側壁間隔件105覆蓋之電荷儲存層EC、上部閘極絕緣膜23b、記憶體閘極電極G100。 However, when a gate electrode (not shown) that is adjacent to the memory gate electrode G100 and a contact electrode portion 102 that is formed integrally with the gate electrode is formed, first, in the active region When the memory gate structure covered by the sidewall spacers 105 is formed thereon, the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G100 covered by the sidewall spacers 105 are also formed on the element isolation layer 101.

繼而，於該等活性區域或元件分離層101之整面形成層狀之導電層。繼而，於接點設置部102之形成預定位置即元件分離層101之區域形成抗蝕劑之後，對導電層進行回蝕，藉此，可沿著側壁間隔件105於活性區域上形成側壁狀之選擇閘極電極，與此同時，可使導電層原樣殘存於抗蝕劑之形成區域而於元件分離層101形成與選擇閘極電極連設之接點設置部102。 Then, a layered conductive layer is formed on the entire surface of the active regions or element isolation layers 101. Then, after forming a resist at a predetermined position of the contact portion setting portion 102, that is, the region of the element isolation layer 101, the conductive layer is etched back, whereby a sidewall shape can be formed on the active region along the sidewall spacer 105. At the same time, the gate electrode is selected, and the conductive layer remains in the formation region of the resist as it is, and the contact portion 102 is formed in the element isolation layer 101 to be connected to the selected gate electrode.

以此方式形成之接點設置部102係形成有包含可豎立設置接點C100之平坦之接點設置面102c之基台部102a，並且形成有自該基台部102a覆蓋至記憶體閘極電極G100之頂部之覆蓋部102b。因此，於半導體裝置100，形成有自記憶體閘極電極G100之頂部朝上方突出之覆蓋部102b，與此相應地，必須使配置記憶體閘極電極G100或接點設置部102之層間絕緣層120之膜厚較厚。 The contact setting portion 102 formed in this manner is formed with a base portion 102a including a flat contact mounting surface 102c on which the contact C100 can be erected, and is formed to cover the memory gate electrode from the base portion 102a. The cover portion 102b at the top of the G100. Therefore, in the semiconductor device 100, the cover portion 102b protruding upward from the top of the memory gate electrode G100 is formed, and accordingly, the interlayer insulating layer of the memory gate electrode G100 or the contact portion 102 must be disposed. The film thickness of 120 is thick.

藉此，於先前之半導體裝置100，使層間絕緣層120較厚，與此相應地，將記憶井之基板表面與上層之配線層113連接之接點C101之高度亦變高，因此，該接點C101之縱橫比(接點高度÷接點直徑)變大，其結果，有接觸電阻值增大之問題。 Therefore, in the conventional semiconductor device 100, the interlayer insulating layer 120 is made thicker, and accordingly, the height of the contact C101 connecting the substrate surface of the memory well and the wiring layer 113 of the upper layer is also increased, and therefore, the connection is made high. The aspect ratio (contact height ÷ contact diameter) of the point C101 becomes large, and as a result, there is a problem that the contact resistance value increases.

另一方面，若為了減小縱橫比以防止接點C101之接觸電阻值增大而使層間絕緣層120之膜厚較薄，則接點設置部102之頂部與上層之配線層112、113之距離變短，從而相應地，亦有於被施加不同電壓之 接點設置部102與上層之配線層113之間產生接觸不良之虞。 On the other hand, if the thickness of the interlayer insulating layer 120 is made thin in order to reduce the aspect ratio to prevent an increase in the contact resistance value of the contact C101, the top and the upper wiring layers 112, 113 of the contact portion 102 are provided. The distance is shortened, and accordingly, different voltages are applied A contact failure occurs between the contact setting portion 102 and the wiring layer 113 of the upper layer.

因此，本發明係考慮以上方面而完成者，其目的在於提出一種可防止接觸電阻值增大並且亦可防止與配線層之接觸不良的半導體裝置及其製造方法。 Accordingly, the present invention has been made in view of the above aspects, and an object thereof is to provide a semiconductor device capable of preventing an increase in contact resistance value and also preventing contact failure with a wiring layer, and a method of manufacturing the same.

為了解決上述問題，本發明之半導體裝置之特徵在於包括：閘極構造體，其設置有閘極電極；接點設置構造體，其包含由與上述閘極電極相同之層形成之分離閘極電極，且自上述閘極構造體電性分離；側壁型閘極電極，其介隔側壁間隔件呈側壁狀形成於上述閘極構造體之側壁，並且亦介隔上述側壁間隔件呈側壁狀形成於上述接點設置構造體之側壁，且自上述閘極構造體遍及上述接點設置構造體連設；及接點，其以自上述接點設置構造體之頂部跨至上述側壁間隔件及上述側壁型閘極電極之方式豎立設置。 In order to solve the above problems, a semiconductor device of the present invention is characterized by comprising: a gate structure provided with a gate electrode; and a contact arrangement structure including a separation gate electrode formed of the same layer as the gate electrode And electrically separating from the gate structure; the sidewall type gate electrode has a sidewall spacer formed on a sidewall of the gate structure in a sidewall shape, and is also formed in a sidewall shape via the sidewall spacer. The contact layer is provided with a side wall of the structure, and the gate structure is connected from the contact structure; and a contact is formed from the top of the contact structure to the side wall spacer and the side wall The type of gate electrode is erected.

又，本發明之半導體裝置之製造方法之特徵在於包括如下步驟：接點設置構造體形成步驟，其形成具備閘極電極之閘極構造體、及至少包含由與上述閘極電極相同之層形成之分離閘極電極且自上述閘極構造體電性分離的接點設置構造體；側壁間隔件形成步驟，其沿著上述閘極構造體及上述接點設置構造體之各側壁形成側壁間隔件；側壁型閘極電極形成步驟，其以覆蓋側壁由上述側壁間隔件覆蓋之上述閘極構造體及上述接點設置構造體之方式形成導電層之後，對該導電層進行回蝕，藉此，形成自上述閘極構造體介隔上述側壁間隔件呈側壁狀連設至上述接點設置構造體之各側壁的側壁型閘極電極；及接點形成步驟，其形成以自上述接點設置構造體之頂部跨至上述側壁型閘極電極之方式豎立設置之接點。 Further, a method of manufacturing a semiconductor device according to the present invention includes the step of forming a contact structure, forming a gate structure including a gate electrode, and forming at least a layer formed of the same electrode as the gate electrode a structure for separating a gate electrode and electrically separating from the gate structure; a sidewall spacer forming step of forming a sidewall spacer along each sidewall of the gate structure and the contact arrangement structure a sidewall type gate electrode forming step of forming a conductive layer so as to cover the gate structure covered by the sidewall spacer and the contact arrangement structure, and then etching back the conductive layer, thereby Forming a sidewall type gate electrode from which the sidewall spacer is connected to each side wall of the contact arrangement structure via a sidewall spacer; and a contact forming step of forming a structure from the contact The contact of the top of the body to the side wall type gate electrode is erected.

又，本發明之半導體裝置之製造方法之特徵在於包括如下步驟：接點設置構造體形成步驟，其使下部閘極絕緣膜、電荷儲存層、 上部閘極絕緣膜、及記憶體閘極電極依次分別呈層狀積層於基板上之後進行圖案化，藉此，形成依次積層有上述下部閘極絕緣膜、上述電荷儲存層、上述上部閘極絕緣膜、及上述記憶體閘極電極之記憶體閘極構造體，並且形成至少依次積層有上述電荷儲存層、上述上部閘極絕緣膜、及由與上述記憶體閘極電極相同之層形成之分離記憶體閘極電極且自上述記憶體閘極構造體電性分離的接點設置構造體；側壁間隔件形成步驟，其沿著上述記憶體閘極構造體及上述接點設置構造體之各側壁形成側壁間隔件；選擇閘極電極形成步驟，其以覆蓋側壁由上述側壁間隔件覆蓋之上述記憶體閘極構造體及上述接點設置構造體之方式形成導電層之後，對該導電層進行回蝕，藉此，形成自上述記憶體閘極構造體介隔上述側壁間隔件連設至上述接點設置構造體之各側壁之側壁狀之選擇閘極電極；及接點形成步驟，其形成以自上述接點設置構造體之頂部跨至上述選擇閘極電極之方式豎立設置之接點。 Further, the method of manufacturing a semiconductor device of the present invention is characterized by comprising the steps of: a contact setting structure forming step of causing a lower gate insulating film, a charge storage layer, The upper gate insulating film and the memory gate electrode are sequentially layered on the substrate and then patterned, thereby forming the lower gate insulating film, the charge storage layer, and the upper gate insulating layer in this order. a memory and a memory gate structure of the memory gate electrode, and forming at least a layer of the charge storage layer, the upper gate insulating film, and a layer formed by the same layer as the memory gate electrode a memory gate electrode and a contact structure electrically separated from the memory gate structure; a sidewall spacer forming step of providing sidewalls of the structure along the memory gate structure and the contact Forming a sidewall spacer; and selecting a gate electrode forming step of forming a conductive layer in such a manner as to cover the memory gate structure and the contact mounting structure covered by the sidewall spacer, and then returning the conductive layer Etching, whereby the memory gate structure is connected to the sidewalls of the contact arrangement structure via the sidewall spacers The wall-like selection gate electrode; and a step of forming contacts, which are formed in the contact point from the top of the structure is provided to span the junction erected gate electrode of the selection mode.

根據本發明，以自以與記憶體閘極構造體相同之構成形成之接點設置構造體之頂部跨至選擇閘極電極之方式設置有接點，因此，不存在如先前般覆蓋至記憶體閘極構造體之頂部之覆蓋部，可相應地縮短至上層之配線層為止之距離而使縱橫比較小，如此一來，可防止接觸電阻值增大。又，不存在如先前般覆蓋至記憶體閘極構造體之頂部之覆蓋部，亦可相應地使接點設置構造體與上層之配線層遠離，因此，可防止與配線層之接觸不良。 According to the present invention, the contact is provided in such a manner that the top of the contact-arranged structure formed by the same structure as the memory gate structure spans the selective gate electrode, and therefore, there is no cover to the memory as before. The covering portion at the top of the gate structure can be shortened to the distance from the wiring layer of the upper layer, and the aspect ratio is relatively small, so that the contact resistance value can be prevented from increasing. Further, since the cover portion covering the top of the memory gate structure as before is not present, the contact arrangement structure and the wiring layer of the upper layer can be separated from each other, so that contact failure with the wiring layer can be prevented.

1‧‧‧半導體裝置 1‧‧‧Semiconductor device

3a‧‧‧記憶胞 3a‧‧‧ memory cells

3b‧‧‧記憶胞 3b‧‧‧ memory cells

3c‧‧‧記憶胞 3c‧‧‧ memory cells

3d‧‧‧記憶胞 3d‧‧‧ memory cells

3e‧‧‧記憶胞 3e‧‧‧ memory cells

3f‧‧‧記憶胞 3f‧‧‧ memory cells

4a‧‧‧記憶體閘極構造體(閘極構造體) 4a‧‧‧Memory gate structure (gate structure)

4b‧‧‧記憶體閘極構造體(閘極構造體) 4b‧‧‧Memory gate structure (gate structure)

5a‧‧‧第1選擇閘極構造體 5a‧‧‧1st choice gate structure

5b‧‧‧第1選擇閘極構造體 5b‧‧‧1st choice gate structure

6a‧‧‧第2選擇閘極構造體 6a‧‧‧2nd choice gate structure

6b‧‧‧第2選擇閘極構造體 6b‧‧‧2nd choice gate structure

7a‧‧‧邏輯閘極構造體 7a‧‧‧Logic gate structure

7b‧‧‧邏輯閘極構造體 7b‧‧‧Logic Gate Structure

10a‧‧‧接點設置構造體 10a‧‧‧Contact setting structure

11a‧‧‧接點設置構造體 11a‧‧‧Contact setting structure

10b‧‧‧接點設置構造體 10b‧‧‧Contact setting structure

11b‧‧‧接點設置構造體 11b‧‧‧Contact setting structure

13‧‧‧選擇閘極電極切斷部 13‧‧‧Selecting the gate electrode cutting section

14‧‧‧選擇閘極電極切斷部 14‧‧‧Selecting the gate electrode cutting section

15‧‧‧選擇閘極電極切斷部 15‧‧‧Selecting the gate electrode cutting section

16‧‧‧選擇閘極電極切斷部 16‧‧‧Selecting the gate electrode cutting section

18‧‧‧周邊電路 18‧‧‧ peripheral circuits

19‧‧‧周邊電路 19‧‧‧ peripheral circuits

20‧‧‧元件分離層(基板) 20‧‧‧Component separation layer (substrate)

21‧‧‧層間絕緣層 21‧‧‧Interlayer insulation

23a‧‧‧下部閘極絕緣膜 23a‧‧‧Lower gate insulating film

23b‧‧‧上部閘極絕緣膜 23b‧‧‧Upper gate insulating film

25a‧‧‧閘極絕緣膜 25a‧‧‧gate insulating film

25b‧‧‧閘極絕緣膜 25b‧‧‧gate insulating film

27a‧‧‧側壁間隔件 27a‧‧‧ sidewall spacers

27b‧‧‧絕緣壁 27b‧‧‧Insulation wall

27c‧‧‧側壁間隔件 27c‧‧‧ sidewall spacers

29a‧‧‧閘極絕緣膜 29a‧‧‧Gate insulation film

29b‧‧‧閘極絕緣膜 29b‧‧‧Gate insulation film

30‧‧‧凹部 30‧‧‧ recess

30a‧‧‧犧牲氧化膜 30a‧‧‧Sacrificial oxide film

30b‧‧‧保護絕緣膜 30b‧‧‧Protective insulation film

30c‧‧‧保護絕緣膜 30c‧‧‧Protective insulation film

35‧‧‧記憶體閘極電極用導電層 35‧‧‧ Conductive layer for memory gate electrode

37‧‧‧導電層 37‧‧‧ Conductive layer

38‧‧‧逆導電層 38‧‧‧Reverse conductive layer

40‧‧‧缺損部 40‧‧‧Defects Department

100‧‧‧半導體裝置 100‧‧‧Semiconductor device

101‧‧‧元件分離層 101‧‧‧Component separation layer

102‧‧‧接點設置部 102‧‧‧Contact Setting Department

102a‧‧‧基台部 102a‧‧‧Base Department

102b‧‧‧覆蓋部 102b‧‧‧ Coverage

102c‧‧‧接點設置面 102c‧‧‧Contact setting surface

105‧‧‧側壁間隔件 105‧‧‧ sidewall spacers

112‧‧‧配線層 112‧‧‧Wiring layer

113‧‧‧配線層 113‧‧‧Wiring layer

114‧‧‧配線層 114‧‧‧Wiring layer

120‧‧‧層間絕緣層 120‧‧‧Interlayer insulation

121‧‧‧層間絕緣層 121‧‧‧Interlayer insulation

13‧‧‧層間絕緣層 13‧‧‧Interlayer insulation

C1‧‧‧接點 C1‧‧‧Contact

2‧‧‧接點 2‧‧‧Contacts

C3‧‧‧接點 C3‧‧‧Contact

C4a‧‧‧接點 C4a‧‧‧Contact

C4b‧‧‧接點 C4b‧‧‧Contact

C5a‧‧‧接點 C5a‧‧‧Contact

C5b‧‧‧接點 C5b‧‧‧Contact

C6a‧‧‧接點 C6a‧‧‧Contact

C6b‧‧‧接點 C6b‧‧‧Contact

C8‧‧‧接點 C8‧‧‧Contact

C9‧‧‧接點 C9‧‧‧Contact

C10‧‧‧接點 C10‧‧‧Contact

C12‧‧‧接點 C12‧‧‧Contact

C13‧‧‧接點 C13‧‧‧Contact

C14‧‧‧接點 C14‧‧‧Contact

C100‧‧‧接點 C100‧‧‧Contact

C101‧‧‧接點 C101‧‧‧Contact

C102‧‧‧接點 C102‧‧‧Contact

D1‧‧‧源極區域 D1‧‧‧ source area

D1a‧‧‧擴展區域 D1a‧‧‧Extended area

D2‧‧‧汲極區域 D2‧‧‧ bungee area

D2a‧‧‧擴展區域 D2a‧‧‧Extended area

D2b‧‧‧擴展區域 D2b‧‧‧Extended area

D3‧‧‧源極區域 D3‧‧‧ source area

D3a‧‧‧擴展區域 D3a‧‧‧Extended area

D4‧‧‧雜質擴散區域 D4‧‧‧ impurity diffusion area

D4a‧‧‧擴展區域 D4a‧‧‧Extended area

D5‧‧‧雜質擴散區域 D5‧‧‧ impurity diffusion area

D5a‧‧‧擴展區域 D5a‧‧‧Extended area

D6‧‧‧雜質擴散區域 D6‧‧‧ impurity diffusion area

D6a‧‧‧擴展區域 D6a‧‧‧Extended area

D7‧‧‧雜質擴散區域 D7‧‧‧ impurity diffusion area

D7a‧‧‧擴展區域 D7a‧‧‧Extended area

Dsw‧‧‧厚度 Dsw‧‧‧ thickness

Dsp‧‧‧厚度 Dsp‧‧‧ thickness

Dp‧‧‧距離 Dp‧‧‧ distance

EC‧‧‧電荷儲存層 EC‧‧‧Charge storage layer

ER1‧‧‧記憶體電路區域 ER1‧‧‧ memory circuit area

ER2‧‧‧周邊電路區域 ER2‧‧‧ peripheral circuit area

ER11‧‧‧記憶胞區域 ER11‧‧‧ memory cell area

ER12‧‧‧閘極接觸‧切斷區域 ER12‧‧‧ gate contact ‧ cut-off area

ER13‧‧‧閘極接觸‧切斷區域 ER13‧‧‧gate contact ‧cut area

ETa‧‧‧擴展區域 ETa‧‧‧Extended area

ETb‧‧‧擴展區域 ETb‧‧‧Extended area

Ga‧‧‧選擇閘極電極(側壁型閘極電極) Ga‧‧‧Selected gate electrode (sidewall type gate electrode)

Gb‧‧‧選擇閘極電極(側壁型閘極電極) Gb‧‧‧Selected gate electrode (sidewall type gate electrode)

G1a‧‧‧記憶體閘極電極(閘極電極 G1a‧‧‧ memory gate electrode (gate electrode

G1b‧‧‧記憶體閘極電極(閘極電極) G1b‧‧‧ memory gate electrode (gate electrode)

G2a‧‧‧第1選擇閘極電極(側壁型閘極電極) G2a‧‧‧1st selection gate electrode (sidewall type gate electrode)

G2b‧‧‧第1選擇閘極電極(側壁型閘極電極) G2b‧‧‧1st choice gate electrode (sidewall type gate electrode)

G3a‧‧‧第2選擇閘極電極(側壁型閘極電極) G3a‧‧‧2nd choice gate electrode (sidewall type gate electrode)

G3b‧‧‧第2選擇閘極電極(側壁型閘極電極) G3b‧‧‧2nd choice gate electrode (sidewall type gate electrode)

G8a‧‧‧記憶體閘極電極(分離記憶體閘極電極) G8a‧‧‧ memory gate electrode (separate memory gate electrode)

G8b‧‧‧記憶體閘極電極(分離記憶體閘極電極) G8b‧‧‧ memory gate electrode (separate memory gate electrode)

G9a‧‧‧記憶體閘極電極(分離記憶體閘極電極) G9a‧‧‧ memory gate electrode (separate memory gate electrode)

G9b‧‧‧記憶體閘極電極(分離記憶體閘極電極) G9b‧‧‧ memory gate electrode (separate memory gate electrode)

G5‧‧‧邏輯閘極電極 G5‧‧‧Logic gate electrode

G6‧‧‧邏輯閘極電極 G6‧‧‧Logic gate electrode

G100‧‧‧記憶體閘極電極 G100‧‧‧ memory gate electrode

GP1‧‧‧區域 GP1‧‧‧ area

GP2‧‧‧電極間區域 GP2‧‧‧Interelectrode area

H1‧‧‧開口部 H1‧‧‧ openings

H3‧‧‧開口部 H3‧‧‧ openings

Pf1‧‧‧形成預定位置 Pf1‧‧‧ formed a predetermined position

Pf2‧‧‧形成預定位置 Pf2‧‧‧ formed a predetermined location

Pf3‧‧‧形成預定位置 Pf3‧‧‧ formed a predetermined location

Pf4‧‧‧形成預定位置 Pf4‧‧‧ formed a predetermined location

Rm1‧‧‧抗蝕劑 Rm1‧‧‧Resist

Rm2‧‧‧抗蝕劑 Rm2‧‧‧Resist

Rm3‧‧‧抗蝕劑 Rm3‧‧‧Resist

Rm4‧‧‧抗蝕劑 Rm4‧‧‧Resist

Rr1a‧‧‧抗蝕劑 Rr1a‧‧‧Resist

Rr1b‧‧‧抗蝕劑 Rr1b‧‧‧Resist

S‧‧‧半導體基板 S‧‧‧Semiconductor substrate

SC‧‧‧矽化物 SC‧‧‧ Telluride

SW‧‧‧側壁 SW‧‧‧ side wall

W1‧‧‧記憶井(基板) W1‧‧‧ memory well (substrate)

W2‧‧‧邏輯井(基板) W2‧‧‧ Logical Well (Substrate)

W3‧‧‧邏輯井(基板) W3‧‧‧ Logical Well (Substrate)

圖1係表示利用本發明之製造方法製造之半導體裝置之平面佈局的概略圖。 Fig. 1 is a schematic view showing a planar layout of a semiconductor device manufactured by the manufacturing method of the present invention.

圖2係表示圖1中之A-A'部分之側剖面構成之剖視圖。 Fig. 2 is a cross-sectional view showing a side cross-sectional configuration of a portion A-A' in Fig. 1.

圖3係表示圖1中之B-B'部分之側剖面構成之剖視圖。 Fig. 3 is a cross-sectional view showing a side cross-sectional configuration of a portion BB' of Fig. 1.

圖4A係表示圖1中之C-C'部分之側剖面構成之剖視圖，圖4B係表示圖1中之D-D'部分之側剖面構成之剖視圖。 4A is a cross-sectional view showing a side cross-sectional configuration of a portion C-C' in FIG. 1, and FIG. 4B is a cross-sectional view showing a side cross-sectional configuration of a portion DD' in FIG. 1.

圖5A係表示半導體裝置之製造步驟(1)之概略圖，圖5B係表示半導體裝置之製造步驟(2)之概略圖，圖5C係表示半導體裝置之製造步驟(3)之概略圖。 5A is a schematic view showing a manufacturing step (1) of the semiconductor device, FIG. 5B is a schematic view showing a manufacturing step (2) of the semiconductor device, and FIG. 5C is a schematic view showing a manufacturing step (3) of the semiconductor device.

圖6A係表示半導體裝置之製造步驟(4)之概略圖，圖6B係表示半導體裝置之製造步驟(5)之概略圖，圖6C係表示半導體裝置之製造步驟(6)之概略圖。 6A is a schematic view showing a manufacturing step (4) of the semiconductor device, FIG. 6B is a schematic view showing a manufacturing step (5) of the semiconductor device, and FIG. 6C is a schematic view showing a manufacturing step (6) of the semiconductor device.

圖7係表示半導體裝置之製造步驟(4)時之圖1之D-D'部分之側剖面構成的剖視圖。 Fig. 7 is a cross-sectional view showing a side cross-sectional view of a portion DD' of Fig. 1 in a manufacturing step (4) of the semiconductor device.

圖8A係表示半導體裝置之製造步驟(7)之概略圖，圖8B係表示半導體裝置之製造步驟(8)之概略圖，圖8C係表示半導體裝置之製造步驟(9)之概略圖。 8A is a schematic view showing a manufacturing step (7) of the semiconductor device, FIG. 8B is a schematic view showing a manufacturing step (8) of the semiconductor device, and FIG. 8C is a schematic view showing a manufacturing step (9) of the semiconductor device.

圖9A係表示半導體裝置之製造步驟(10)之概略圖，圖9B係表示半導體裝置之製造步驟(11)之概略圖。 9A is a schematic view showing a manufacturing step (10) of the semiconductor device, and FIG. 9B is a schematic view showing a manufacturing step (11) of the semiconductor device.

圖10係使選擇閘極電極相對於圖1之平面佈局重合而進一步表示選擇閘極電極切斷部之形成預定位置的概略圖。 Fig. 10 is a schematic view showing a predetermined position at which the selective gate electrode cutting portion is formed by superposing the selection gate electrode with respect to the plane layout of Fig. 1;

圖11係表示圖10之D-D'部分之側剖面構成之剖視圖。 Figure 11 is a cross-sectional view showing a side cross-sectional configuration of a portion DD' of Figure 10 .

圖12A係表示半導體裝置之製造步驟(12)時之圖1之A-A'部分之側剖面構成的剖視圖，圖12B係表示半導體裝置之製造步驟(12)時之圖1之B-B'部分之側剖面構成的剖視圖。 12A is a cross-sectional view showing a side cross-sectional view of a portion A-A' of FIG. 1 in a manufacturing step (12) of the semiconductor device, and FIG. 12B is a B-B' of FIG. 1 showing a manufacturing step (12) of the semiconductor device. A cross-sectional view of a partial side section.

圖13係表示包含接點設置部之先前之半導體裝置之側剖面構成的剖視圖。 Fig. 13 is a cross-sectional view showing a side cross-sectional configuration of a conventional semiconductor device including a contact setting portion.

以下，對用以實施本發明之形態進行說明。再者，說明設為以下所示之順序。 Hereinafter, embodiments for carrying out the invention will be described. In addition, the description is set to the order shown below.

1.本發明之半導體裝置之構成 1. The composition of the semiconductor device of the present invention

1-1.半導體裝置之平面佈局 1-1. Planar layout of semiconductor devices

1-2.半導體裝置之各部位之剖面構成 1-2. Cross-sectional composition of each part of the semiconductor device

1-3.關於在寫入選擇記憶胞中使電荷注入至電荷儲存層之動作原理 1-3. Principle of action of injecting charge into the charge storage layer in the write select memory cell

1-4.關於在高電壓之電荷儲存閘極電壓施加至記憶體閘極電極之寫入非選擇記憶胞中不對電荷儲存層注入電荷的動作原理 1-4. The principle of not injecting charge into the charge storage layer in the write non-selective memory cell where the high voltage charge storage gate voltage is applied to the memory gate electrode

2.半導體裝置之製造方法 2. Method of manufacturing a semiconductor device

3.作用及效果 3. Function and effect

4.省略第3光罩加工步驟之其他實施形態之製造方法 4. Manufacturing method of another embodiment in which the third mask processing step is omitted

5.其他實施形態 5. Other embodiments

(1)本發明之半導體裝置之構成 (1) Composition of the semiconductor device of the present invention

(1-1)半導體裝置之平面佈局 (1-1) Planar layout of semiconductor devices

圖1係表示本發明之半導體裝置1之平面佈局之概略圖，以形成於記憶體電路區域ER1之記憶體閘極構造體4a、4b、第1選擇閘極構造體5a、5b、第2選擇閘極構造體6a、6b、接點設置構造體10a、11a、10b、11b、及選擇閘極電極切斷部13、14、15、16之平面佈局、以及形成於周邊電路區域ER2之邏輯閘極構造體7a、7b之平面佈局為中心進行圖示。再者，於圖1中，省略下述之形成於記憶體閘極構造體4a、4b及接點設置構造體10a、11a、10b、11b之各側壁之側壁間隔件、或形成於第1選擇閘極構造體5a、5b及第2選擇閘極構造體6a、6b之側壁、形成於記憶井W1及邏輯井W2、W3之元件分離層等。 1 is a schematic view showing a planar layout of a semiconductor device 1 of the present invention, in which memory gate structures 4a and 4b, first selection gate structures 5a and 5b, and second selection are formed in a memory circuit region ER1. The gate structures 6a and 6b, the contact arrangement structures 10a, 11a, 10b, and 11b, and the planar layout of the selected gate electrode cutting portions 13, 14, 15, and 16, and the logic gates formed in the peripheral circuit region ER2 The planar layout of the polar structures 7a and 7b is shown as a center. Further, in FIG. 1, the side spacers formed on the respective side walls of the memory gate structures 4a and 4b and the contact-providing structures 10a, 11a, 10b, and 11b are omitted or formed in the first selection. The sidewalls of the gate structures 5a and 5b and the second selection gate structures 6a and 6b are formed in the memory well W1 and the element isolation layers of the logic wells W2 and W3.

本發明係於接點設置構造體10a、11a、10b、11b具有特徵性之構成，此處，首先，對形成有該等接點設置構造體10a、11a、10b、11b之半導體裝置1之整體構成進行說明，關於接點設置構造體10a、11a、10b、11b之具體之構成，於後段之「(1-2)半導體裝置之各部位 之剖面構成」詳細地進行說明。 The present invention has a characteristic configuration in the contact arrangement structures 10a, 11a, 10b, and 11b. Here, first, the entire semiconductor device 1 in which the structures 10a, 11a, 10b, and 11b are formed with the contacts is formed. The configuration of the contact arrangement structure 10a, 11a, 10b, and 11b is described in the following paragraphs. ((1-2) Each part of the semiconductor device The cross-sectional configuration will be described in detail.

於該情形時，半導體裝置1係於未圖示之半導體基板包含記憶體電路區域ER1與周邊電路區域ER2，例如於記憶體電路區域ER1形成有P型之記憶井W1，於周邊電路區域ER2形成有P型之邏輯井W2及N型之邏輯井W3。 In this case, the semiconductor device 1 includes a memory circuit region ER1 and a peripheral circuit region ER2, and a P-type memory well W1 is formed in the memory circuit region ER1, and is formed in the peripheral circuit region ER2. There are P-type logic well W2 and N-type logic well W3.

又，具有如下構成：於記憶體電路區域ER1，於閘極接觸‧切斷區域ER12、ER13間設置有記憶胞區域ER11，於該記憶胞區域ER11呈矩陣狀配置有複數個記憶胞3a、3b、3c、3d、3e、3f。再者，該等記憶胞3a、3b、3c、3d、3e、3f全部具有相同之構成，因此，此處，以下，主要著眼於配置於A-A'部分之記憶胞3a、3b進行說明。 Further, in the memory circuit region ER1, a memory cell region ER11 is provided between the gate contact and the cut regions ER12 and ER13, and a plurality of memory cells 3a and 3b are arranged in a matrix in the memory cell region ER11. , 3c, 3d, 3e, 3f. In addition, since all of the memory cells 3a, 3b, 3c, 3d, 3e, and 3f have the same configuration, the following description mainly focuses on the memory cells 3a and 3b disposed in the A-A' portion.

於該情形時，記憶胞3a具有於第1選擇閘極構造體5a與第2選擇閘極構造體6a間介隔側壁間隔件(未圖示)配置有記憶體閘極構造體4a的構成。於本實施形態之情形時，形成第1行之記憶胞3a、3c、3e之一記憶體閘極構造體4a與形成其他之第2行之記憶胞3b、3d、3f之另一記憶體閘極構造體4b係形成為直線狀，且以相互並行之方式配置。再者，於記憶體閘極構造體4a(4b)，豎立設置有連接於記憶體閘極線(未圖示)之接點C4a(C4b)，可自該記憶體閘極線經由接點C4a(C4b)對記憶體閘極電極G1a(G1b)施加特定之記憶體閘極電壓。 In this case, the memory cell 3a has a configuration in which the memory gate structure 4a is disposed between the first selective gate structure 5a and the second selective gate structure 6a via a sidewall spacer (not shown). In the case of the present embodiment, one of the memory gate structures 4a of the memory cells 3a, 3c, and 3e in the first row and the other memory gates of the memory cells 3b, 3d, and 3f forming the other second row are formed. The polar structures 4b are formed in a linear shape and arranged in parallel with each other. Further, in the memory gate structure 4a (4b), a contact C4a (C4b) connected to a memory gate line (not shown) is erected, and the memory gate line can be connected via the contact C4a. (C4b) A specific memory gate voltage is applied to the memory gate electrode G1a (G1b).

於記憶胞區域ER11，具備第1選擇閘極電極G2a(G2b)之第1選擇閘極構造體5a(5b)與具備第2選擇閘極電極G3a(G3b)之第2選擇閘極構造體6a(6b)形成為直線狀，該等第1選擇閘極構造體5a(5b)及第2選擇閘極構造體6a(6b)係以與記憶體閘極構造體4a(4b)並行之方式配置。第1選擇閘極電極G2a(G2b)及第2選擇閘極電極G3a(G3b)係沿著記憶體閘極電極G1a(G1b)之側壁之側壁間隔件形成為側壁狀，且配置於周繞記憶體閘極電極G1a(G1b)之同一周繞線上，並藉由未形成第1選擇閘極電極G2a(G2b)及第2選擇閘極電極G3a(G3b)之複數個選擇閘極電極 切斷部13、14(15、16)而電性分離。 In the memory cell region ER11, the first selection gate structure 5a (5b) including the first selection gate electrode G2a (G2b) and the second selection gate structure 6a including the second selection gate electrode G3a (G3b) (6b) is formed in a linear shape, and the first selection gate structure 5a (5b) and the second selection gate structure 6a (6b) are arranged in parallel with the memory gate structure 4a (4b). . The first selection gate electrode G2a (G2b) and the second selection gate electrode G3a (G3b) are formed in a sidewall shape along the sidewall spacers of the sidewalls of the memory gate electrode G1a (G1b), and are disposed in the peripheral winding memory. The same circumference of the body gate electrode G1a (G1b) is wound, and a plurality of selective gate electrodes are formed without forming the first selection gate electrode G2a (G2b) and the second selection gate electrode G3a (G3b) The cutting portions 13 and 14 (15, 16) are electrically separated.

又，於該記憶胞區域ER11中之記憶井W1之表面，2個源極區域D1、D3隔開特定間隔左右對稱地形成，於該等源極區域D1、D3間形成有複數個汲極區域D2。於該情形時，於記憶胞區域ER11，於一源極區域D1與汲極區域D2之間配置有第1行之記憶胞3a、3c、3e，於該汲極區域D2與另一源極區域D3之間配置有第2行之記憶胞3b、3d、3f，記憶胞3a、3c、3e與記憶胞3b、3d、3f以汲極區域D2為中心線左右對稱地形成。再者，於位於一源極區域D1與汲極區域D2之間之記憶胞3a、3c、3e，具有於第1選擇閘極構造體5a與第2選擇閘極構造體6a間配置有記憶體閘極構造體4a的構成，另一方面，於位於汲極區域D2與另一源極區域D3之間之記憶胞3b、3d、3f，具有於第2選擇閘極構造體6b與第1選擇閘極構造體5b間配置有記憶體閘極構造體4b的構成。 Further, on the surface of the memory well W1 in the memory cell region ER11, the two source regions D1 and D3 are formed symmetrically with respect to each other with a predetermined interval, and a plurality of drain regions are formed between the source regions D1 and D3. D2. In this case, in the memory cell region ER11, the memory cells 3a, 3c, and 3e of the first row are disposed between the source region D1 and the drain region D2, and the drain region D2 and the other source region are disposed. The memory cells 3b, 3d, and 3f of the second row are disposed between D3, and the memory cells 3a, 3c, and 3e and the memory cells 3b, 3d, and 3f are formed bilaterally symmetrically with the drain region D2 as a center line. Further, the memory cells 3a, 3c, and 3e located between the source region D1 and the drain region D2 have memory disposed between the first selection gate structure 5a and the second selection gate structure 6a. The gate structure 4a is configured on the other hand, and the memory cells 3b, 3d, and 3f located between the drain region D2 and the other source region D3 have the second selection gate structure 6b and the first selection. The memory gate structure 4b is disposed between the gate structures 5b.

實際上，形成於記憶井W1之表面之一源極區域D1係沿著一第1選擇閘極構造體5a形成，並且對準第1行之記憶胞3a、3c、3e之形成位置形成至與該第1選擇閘極構造體5a鄰接之區域為止，由排列成一行之複數個記憶胞3a、3c、3e所共有。於源極區域D1，豎立設置有連接於源極線(未圖示)之接點C1，可自該源極線經由接點C1施加特定之源極電壓。 Actually, one source region D1 formed on the surface of the memory well W1 is formed along a first selection gate structure 5a, and the formation positions of the memory cells 3a, 3c, and 3e aligned with the first row are formed to The first selected gate structure 5a is shared by a plurality of memory cells 3a, 3c, and 3e arranged in a line until the region adjacent to the gate structure 5a. In the source region D1, a contact C1 connected to a source line (not shown) is erected, and a specific source voltage can be applied from the source line via the contact C1.

又，第2選擇閘極構造體6a、6b間之形成於記憶井W1之表面之複數個汲極區域D2係對準相鄰之記憶胞3a、3b(3c、3d，3e、3f)之形成位置分別形成於與第2選擇閘極構造體6a、6b鄰接之區域，而可於相鄰之記憶胞3a、3b(3c、3d，3e、3f)共有1個汲極區域D2。於各汲極區域D2，豎立設置有連接於位元線(未圖示)之接點C2，可自該位元線經由接點C2施加特定之位元電壓。再者，未圖示之位元線係由圖1中沿列方向排列之每一組記憶胞3a、3b(3c、3d)(3e、3f)共有，可對各列 之記憶胞3a、3b(3c、3d)(3e、3f)以列為單位一律施加特定之位元電壓。 Further, a plurality of gate regions D2 formed on the surface of the memory well W1 between the second selection gate structures 6a and 6b are aligned with the formation of adjacent memory cells 3a and 3b (3c, 3d, 3e, 3f). The positions are respectively formed in regions adjacent to the second selected gate structures 6a and 6b, and one drain region D2 can be shared by the adjacent memory cells 3a and 3b (3c, 3d, 3e, and 3f). A contact C2 connected to a bit line (not shown) is erected in each of the drain regions D2, and a specific bit voltage can be applied from the bit line via the contact C2. Further, a bit line (not shown) is shared by each group of memory cells 3a, 3b (3c, 3d) (3e, 3f) arranged in the column direction in FIG. 1, and can be used for each column. The memory cells 3a, 3b (3c, 3d) (3e, 3f) uniformly apply a specific bit voltage in units of columns.

進而，形成於記憶井W1之表面之另一源極區域D3係與一源極區域D1左右對稱地形成，與一源極區域D1同樣地，形成至與另一第1選擇閘極構造體5b鄰接之區域為止，由第2行之記憶胞3b、3d、3f所共有。再者，於該源極區域D3，豎立設置有接點C3，與一源極區域D1相同之源極線連接於接點C3。如此一來，可對配置於記憶胞區域ER11之記憶胞3a、3b、3c、3d、3e、3f經由接點C1、C3一律施加相同之源極電壓。 Further, the other source region D3 formed on the surface of the memory well W1 is formed bilaterally symmetrically with respect to the one source region D1, and is formed to be connected to the other first selected gate structure 5b similarly to the source region D1. The adjacent cells are shared by the memory cells 3b, 3d, and 3f in the second row. Further, in the source region D3, a contact C3 is erected, and a source line identical to the source region D1 is connected to the contact C3. In this way, the same source voltage can be uniformly applied to the memory cells 3a, 3b, 3c, 3d, 3e, and 3f disposed in the memory cell region ER11 via the contacts C1 and C3.

於與記憶胞區域ER11鄰接之一閘極接觸‧切斷區域ER12、及同樣與記憶胞區域ER11鄰接之另一閘極接觸‧切斷區域ER13，於記憶胞區域ER11並行之2根記憶體閘極電極G1a、G1b原樣呈直線狀延伸並行，該記憶體閘極電極G1a、G1b之一端可配置於一閘極接觸‧切斷區域ER12，該記憶體閘極構造體4a、4b之另一端可配置於另一閘極接觸‧切斷區域ER13。 One gate adjacent to the memory cell region ER11, the severing region ER12, and the other gate adjacent to the memory cell region ER11, the severing region ER13, and the memory cell region ER11 in parallel with the two memory gates The electrode electrodes G1a and G1b extend linearly in parallel, and one end of the memory gate electrodes G1a and G1b can be disposed in a gate contact ‧ a cut-off region ER12, and the other ends of the memory gate structures 4a and 4b can be It is placed in another gate contact ‧ cut-off area ER13.

於本實施形態之情形時，構成第1行之記憶胞3a、3c、3e之第1選擇閘極電極G2a、記憶體閘極電極G1a、及第2選擇閘極電極G3a與構成第2行之記憶胞3b、3d、3f之第2選擇閘極電極G3b、記憶體閘極電極G1b、及第1選擇閘極電極G2b左右對稱地形成，因此，此處，以下，著眼於構成第1行之記憶胞3a、3c、3e之第1選擇閘極電極G2a、記憶體閘極電極G1a、及第2選擇閘極電極G3a對閘極接觸‧切斷區域ER12、ER13進行說明。 In the case of the present embodiment, the first selection gate electrode G2a, the memory gate electrode G1a, and the second selection gate electrode G3a constituting the memory cells 3a, 3c, and 3e of the first row and the second row are formed. The second selection gate electrode G3b, the memory gate electrode G1b, and the first selection gate electrode G2b of the memory cells 3b, 3d, and 3f are formed bilaterally symmetrically. Therefore, the following is focused on the first row. The first selection gate electrode G2a, the memory gate electrode G1a, and the second selection gate electrode G3a of the memory cells 3a, 3c, and 3e describe the gate contact/cut regions ER12 and ER13.

於該情形時，於一閘極接觸‧切斷區域ER12，設置有自記憶體閘極電極G1a分斷而與該記憶體閘極電極G1a絕緣之接點設置構造體10a。於本實施形態之情形時，接點設置構造體10a係形成為帶狀，且配置於與記憶體閘極電極G1a之長度方向為同一直線上。除此以外， 於一閘極接觸‧切斷區域ER12，自記憶胞區域ER11延伸之第1選擇閘極電極G2a形成為四邊狀，於由該第1選擇閘極電極G2a包圍之中心區域介隔側壁間隔件配置有接點設置構造體10a，第1選擇閘極電極G2a與接點設置構造體10a介隔側壁間隔件鄰接。 In this case, a contact-providing structure 10a is provided in the contact region ER12 in which the gate electrode erection is separated from the memory gate electrode G1a. In the case of the present embodiment, the contact-providing structure 10a is formed in a strip shape and arranged on the same straight line as the longitudinal direction of the memory gate electrode G1a. Other than that, In the first contact gate electrode ER12, the first selection gate electrode G2a extending from the memory cell region ER11 is formed in a quadrangular shape, and the sidewall spacer is disposed in a central region surrounded by the first selection gate electrode G2a. The contact arrangement structure 10a is provided, and the first selection gate electrode G2a and the contact arrangement structure 10a are adjacent to each other via the side wall spacer.

此處，於一閘極接觸‧切斷區域ER12，於自接點設置構造體10a上跨過側壁間隔件及第1選擇閘極電極G2a直至基板表面為止之區域豎立設置有接點C5a。藉此，可對第1選擇閘極電極G2a自第1選擇閘極線(未圖示)經由接點C5a施加特定之第1選擇閘極電壓。 Here, in a gate contact/cut region ER12, a contact C5a is erected in a region from the contact-arranged structure 10a across the sidewall spacer and the first selection gate electrode G2a to the surface of the substrate. Thereby, the first selection gate voltage can be applied to the first selection gate electrode G2a from the first selection gate line (not shown) via the contact C5a.

又，除此以外，於一閘極接觸‧切斷區域ER12，於形成為四邊狀之第1選擇閘極電極G2a之一部分與自記憶胞區域ER11延伸之直線狀之第2選擇閘極電極G3a之末端之間設置有選擇閘極電極切斷部13。選擇閘極電極切斷部13係使形成為四邊狀之第1選擇閘極電極G2a之一部分與第2選擇閘極電極G3a之末端隔開特定距離對向配置，而將第1選擇閘極電極G2a與第2選擇閘極電極G3a電性分離。藉此，於一閘極接觸‧切斷區域ER12，即便經由接點C5a對第1選擇閘極電極G2a施加第1選擇閘極電壓，亦可藉由選擇閘極電極切斷部13將自第1選擇閘極電極G2a對第2選擇閘極電極G3a之電壓施加遮斷。 Further, in addition to the gate contact ER12, a portion of the first selection gate electrode G2a formed in a quadrangular shape and a linear second selection gate electrode G3a extending from the memory cell region ER11. A selective gate electrode cutting portion 13 is provided between the ends. The gate electrode cutting portion 13 is configured such that one of the first selection gate electrodes G2a formed in a quadrangular shape is disposed opposite to the end of the second selection gate electrode G3a by a predetermined distance, and the first selection gate electrode is disposed. G2a is electrically separated from the second selection gate electrode G3a. Thereby, the first selection gate voltage is applied to the first selection gate electrode G2a via the contact C5a at the gate contact ‧ the cut region ER12, and the gate electrode cut portion 13 can be selected by the gate electrode cut portion 13 The gate electrode G2a is selected to block the voltage of the second selection gate electrode G3a.

另一方面，於另一閘極接觸‧切斷區域ER13，亦設置有自記憶體閘極電極G1a分斷而與該記憶體閘極電極G1a絕緣的接點設置構造體11a。於本實施形態之情形時，接點設置構造體11a亦與上述一接點設置構造體10a同樣地形成為帶狀，且配置於與記憶體閘極電極G1a之長度方向為同一直線上。 On the other hand, the other gate contact/cut region ER13 is also provided with a contact installation structure 11a that is separated from the memory gate electrode G1a and insulated from the memory gate electrode G1a. In the case of the present embodiment, the contact-arranged structure 11a is also formed in a strip shape in the same manner as the above-described contact-providing structure 10a, and is disposed on the same straight line as the longitudinal direction of the memory gate electrode G1a.

又，於另一閘極接觸‧切斷區域ER13，自記憶胞區域ER11延伸之第2選擇閘極電極G3a形成為四邊狀，於由該第2選擇閘極電極G3a包圍之中心區域介隔側壁間隔件形成有接點設置構造體11a，第2選擇閘極電極G3a與接點設置構造體11a介隔側壁間隔件鄰接。 Further, in the other gate contact/cut region ER13, the second selection gate electrode G3a extending from the memory cell region ER11 is formed in a quadrangular shape, and the sidewall is surrounded by the central region surrounded by the second selection gate electrode G3a. The spacer is formed with a contact arrangement structure 11a, and the second selection gate electrode G3a and the contact arrangement structure 11a are adjacent to each other via the side wall spacer.

此處，於另一閘極接觸‧切斷區域ER13，亦於自接點設置構造體11a跨過側壁間隔件及第2選擇閘極電極G3a直至基板表面為止之區域豎立設置有接點C6a。藉此，可對第2選擇閘極電極G3a自第2選擇閘極線(未圖示)經由接點C6a施加特定之第2選擇閘極電壓。 Here, in the other gate contact/cut region ER13, a contact C6a is erected in a region from the contact-arranged structure 11a across the sidewall spacer and the second selection gate electrode G3a to the substrate surface. Thereby, the second selection gate voltage can be applied to the second selection gate electrode G3a from the second selection gate line (not shown) via the contact C6a.

又，除此以外，於另一閘極接觸‧切斷區域ER13，亦於形成為四邊狀之第2選擇閘極電極G3a之一部分與自記憶胞區域ER11延伸之直線狀之第1選擇閘極電極G2a之末端之間設置有選擇閘極電極切斷部14。藉此，於另一閘極接觸‧切斷區域ER13，形成為四邊狀之第2選擇閘極電極G3a之一部分與第1選擇閘極電極G2a之末端亦藉由選擇閘極電極切斷部14分斷而電性分離。藉此，於另一閘極接觸‧切斷區域ER13，即便亦經由接點C6a對第2選擇閘極電極G3a施加第2選擇閘極電壓，亦可藉由選擇閘極電極切斷部14將自第2選擇閘極電極G3a對第1選擇閘極電極G2a之電壓施加遮斷。 Further, in addition to the other gate contact ‧ the cut region ER13, a portion of the second selection gate electrode G3a formed in a quadrangular shape and a linear first selection gate extending from the memory cell region ER11 A selective gate electrode cutting portion 14 is provided between the ends of the electrode G2a. Thereby, the other gate contact ‧ the cut region ER13, one end of the second selection gate electrode G3a formed in a quadrangular shape and the end of the first selection gate electrode G2a are also selected by the gate electrode cut portion 14 Split and electrically separated. Thereby, the other gate is in contact with the cut-off region ER13, and even if the second selection gate voltage is applied to the second selection gate electrode G3a via the contact C6a, the gate electrode cutting portion 14 can be selected. The voltage of the first selection gate electrode G2a is blocked by the second selection gate electrode G3a.

如此一來，於記憶體電路區域ER1，連接於一接點C5a之接點設置構造體10a及第1選擇閘極電極G2a與連接於另一接點C6a之接點設置構造體11a及第2選擇閘極電極G3a藉由選擇閘極電極切斷部13、14而電性分離，從而構成為可獨立地控制第1選擇閘極電極G2a及第2選擇閘極電極G3a。 In this way, in the memory circuit region ER1, the contact arrangement structure 10a and the first selection gate electrode G2a connected to one contact C5a and the contact arrangement structure 11a and the second connection connected to the other contact C6a are provided. The selection gate electrode G3a is electrically separated by selecting the gate electrode cutting portions 13 and 14, so that the first selection gate electrode G2a and the second selection gate electrode G3a can be independently controlled.

附帶而言，閘極接觸‧切斷區域ER12、ER13之第2行側之第2選擇閘極電極G3b、記憶體閘極電極G1b、及第1選擇閘極電極G2b係具有與上述之第1行側之第1選擇閘極電極G2a構造體5a、記憶體閘極電極G1a、及第2選擇閘極電極G3a相同之構成，與第1行同樣地設置有接點設置構造體10b、11b及選擇閘極電極切斷部15、16。 Incidentally, the gate contact ‧ the second selection gate electrode G3b on the second row side of the ER12 and ER13, the memory gate electrode G1b, and the first selection gate electrode G2b have the first The first selection gate electrode G2a structure 5a, the memory gate electrode G1a, and the second selection gate electrode G3a on the row side have the same configuration, and the contact arrangement structures 10b and 11b are provided in the same manner as the first row. The gate electrode cutting portions 15 and 16 are selected.

其中，於該記憶體電路區域ER1，以與第1行之第2選擇閘極電極G3a相鄰之方式配置有第2行之第2選擇閘極電極G3b，第1選擇閘極電極G2b及第2選擇閘極電極G3b左右顛倒地配置。 In the memory circuit region ER1, the second selection gate electrode G3b in the second row, the first selection gate electrode G2b, and the first row are disposed adjacent to the second selection gate electrode G3a in the first row. 2 Select the gate electrode G3b to be placed upside down.

因此，連接有對第2行之第2選擇閘極電極G3b施加電壓之接點C6b之接點設置構造體11b係配置於一閘極接觸‧切斷區域ER12，另一方面，連接有對第2行之第1選擇閘極電極G2b施加電壓之接點C5b之接點設置構造體10b係配置於另一閘極接觸‧切斷區域ER13。 Therefore, the contact installation structure 11b to which the contact C6b for applying a voltage to the second selection gate electrode G3b of the second row is connected is disposed in a gate contact/cut region ER12, and the pair is connected. The contact arrangement structure 10b of the contact C5b to which the first selection gate electrode G2b is applied in the second row is disposed in the other gate contact/cut region ER13.

又，於第2選擇閘極電極G3b、記憶體閘極電極G1b、及第1選擇閘極電極G2b，連接於一接點C5b之接點設置構造體10b及第1選擇閘極電極G2b與連接於另一接點C6b之接點設置構造體11b及第2選擇閘極電極G3b亦藉由選擇閘極電極切斷部15、16分斷而電性分離，從而構成為可獨立地控制第1選擇閘極電極G2b及第2選擇閘極電極G3b。 Further, the second selection gate electrode G3b, the memory gate electrode G1b, and the first selection gate electrode G2b are connected to the contact arrangement structure 10b and the first selection gate electrode G2b connected to one contact C5b. The contact arrangement structure 11b and the second selection gate electrode G3b at the other contact C6b are also electrically separated by the selection of the gate electrode cutting units 15 and 16, and are configured to independently control the first The gate electrode G2b and the second selection gate electrode G3b are selected.

其次，以下，對與以上述構成形成之記憶體電路區域ER1鄰接之周邊電路區域ER2進行說明。再者，於本實施形態之情形時，周邊電路區域ER2係配置於與記憶體電路區域ER1中之記憶胞區域ER11鄰接之位置，但本發明並不限定於此，亦可設置於與一閘極接觸‧切斷區域ER12鄰接之位置或與另一閘極接觸‧切斷區域ER13鄰接之位置或者與記憶胞區域ER11與閘極接觸‧切斷區域ER12間鄰接之位置等其他多種位置。 Next, a peripheral circuit region ER2 adjacent to the memory circuit region ER1 formed as described above will be described below. Furthermore, in the case of the present embodiment, the peripheral circuit region ER2 is disposed adjacent to the memory cell region ER11 in the memory circuit region ER1. However, the present invention is not limited thereto, and may be provided in a gate. The pole contact ‧ the cutting area ER12 is adjacent to the position or the other gate, the cutting area ER13 is adjacent to the position, or the memory cell area ER11 is in contact with the gate ‧ the cutting area ER12 is adjacent to the other positions.

實際上，於周邊電路區域ER2，形成有複數個周邊電路18、19。周邊電路18係例如具有形成於P型之邏輯井W2之N型之MOS(Metal-Oxide-Semiconductor，金屬氧半導體)電晶體構造。於該情形時，於邏輯井W2形成有邏輯閘極構造體7a，可經由接點C8對邏輯閘極構造體7a施加特定之邏輯閘極電壓。 Actually, a plurality of peripheral circuits 18 and 19 are formed in the peripheral circuit region ER2. The peripheral circuit 18 is, for example, an N-type MOS (Metal-Oxide-Semiconductor) transistor structure formed in a P-type logic well W2. In this case, a logic gate structure 7a is formed in the logic well W2, and a specific logic gate voltage can be applied to the logic gate structure 7a via the contact C8.

又，於該邏輯井W2，於以隔著邏輯閘極構造體7a之方式與該邏輯閘極構造體7a鄰接之區域形成有雜質擴散區域D4、D5，於一雜質擴散區域D4豎立設置有接點C9，並且於另一雜質擴散區域D5豎立設置有另一接點C10。 Further, in the logic well W2, impurity diffusion regions D4 and D5 are formed in a region adjacent to the logic gate structure 7a so as to sandwich the logic gate structure 7a, and an impurity diffusion region D4 is erected and connected. Point C9, and another contact C10 is erected in the other impurity diffusion region D5.

另一方面，另一周邊電路19係例如形成於N型之邏輯井W3且具 有P型之MOS電晶體構造。於該情形時，於邏輯井W3形成有邏輯閘極構造體7b，可經由接點C12對邏輯閘極構造體7b施加特定之邏輯閘極電壓。 On the other hand, another peripheral circuit 19 is formed, for example, on the N-type logic well W3 and has There is a P-type MOS transistor structure. In this case, a logic gate structure 7b is formed in the logic well W3, and a specific logic gate voltage can be applied to the logic gate structure 7b via the contact C12.

又，於該邏輯井W3，亦於以隔著邏輯閘極構造體7b之方式與該邏輯閘極構造體7b鄰接之區域形成有雜質擴散區域D6、D7，於一雜質擴散區域D6豎立設置有接點C13，並且於另一雜質擴散區域D7豎立設置有另一接點C14。 Further, in the logic well W3, impurity diffusion regions D6 and D7 are formed in a region adjacent to the logic gate structure 7b so as to sandwich the logic gate structure 7b, and an impurity diffusion region D6 is erected in an impurity diffusion region D6. The contact C13 is provided, and another contact C14 is erected in the other impurity diffusion region D7.

(1-2)半導體裝置之各部位之剖面構成 (1-2) Cross-sectional composition of each part of the semiconductor device

圖2係表示圖1之A-A'部分之側剖面構成且設置於記憶胞區域ER11之記憶胞3a、3b及設置於周邊電路區域ER2之周邊電路18、19之側剖面構成的剖視圖。於該情形時，於半導體裝置1設置有半導體基板S，於記憶體電路區域ER1之半導體基板S上形成有記憶井W1，於周邊電路區域ER2之半導體基板S上形成有邏輯井W2、W3。 2 is a cross-sectional view showing a side cross-sectional configuration of the memory cells 3a and 3b of the memory cell region ER11 and the peripheral circuits 18 and 19 provided in the peripheral circuit region ER2, which are formed in a side cross section of the AA' portion of FIG. In this case, the semiconductor device S is provided in the semiconductor device 1, the memory well W1 is formed on the semiconductor substrate S of the memory circuit region ER1, and the logic wells W2 and W3 are formed on the semiconductor substrate S in the peripheral circuit region ER2.

於本實施形態之情形時，於記憶井W1，於A-A'部分配置有2個記憶胞3a、3b，於該等記憶胞3a、3b間之基板表面形成有豎立設置有接點C2之汲極區域D2。再者，記憶胞3a、3b雖然左右對稱地形成，但具有相同之構成，因此，此處，以下，著眼於一記憶胞3a進行說明。 In the case of the present embodiment, two memory cells 3a and 3b are disposed in the A-A' portion of the memory well W1, and a contact C2 is formed on the surface of the substrate between the memory cells 3a and 3b. Bungee area D2. In addition, although the memory cells 3a and 3b are formed symmetrically in the left-right direction, they have the same configuration. Therefore, the following description focuses on one memory cell 3a.

記憶胞3a係於記憶井W1形成有例如形成N型之電晶體構造之記憶體閘極構造體4a、形成N型之MOS電晶體構造之第1選擇閘極構造體5a、及同樣形成N型之MOS電晶體構造之第2選擇閘極構造體6a。 The memory cell 3a is formed with, for example, a memory gate structure 4a in which an N-type transistor structure is formed, a first selected gate structure 5a in which an N-type MOS transistor structure is formed, and an N-type is formed in the memory well W1. The second selection gate structure 6a of the MOS transistor structure.

實際上，於記憶井W1之表面，隔開特定距離形成有源極區域D1與汲極區域D2，可將來自源極線之源極電壓經由接點C1(圖1)施加至源極區域D1，並且可將來自位元線之位元電壓經由接點C2施加至汲極區域D2。再者，於本實施形態之情形時，源極區域D1及汲極區域D2係將雜質濃度選定為1.0 E21/cm3以上，另一方面，記憶井W1中藉由製造過程中進行之雜質注入而形成通道層之表面區域(例如，距離 表面50[nm]為止之區域)之雜質濃度選定為1.0 E19/cm3以下，較佳為選定為3.0 E18/cm3以下。 Actually, the source region D1 and the drain region D2 are formed on the surface of the memory well W1 by a certain distance, and the source voltage from the source line can be applied to the source region D1 via the contact C1 (FIG. 1). And the bit voltage from the bit line can be applied to the drain region D2 via the contact C2. Further, in the case of the present embodiment, the source region D1 and the drain region D2 have an impurity concentration of 1.0 E21/cm 3 or more, and on the other hand, impurity implantation by the manufacturing process is performed in the memory well W1. The impurity concentration of the surface region where the channel layer is formed (for example, the region from the surface 50 [nm]) is selected to be 1.0 E19/cm 3 or less, preferably 3.0 E18/cm 3 or less.

記憶體閘極構造體4a係於源極區域D1與汲極區域D2間之記憶井W1上，介隔包含SiO2等之絕緣構件之下部閘極絕緣膜23a而包含由例如氮化矽(Si3N4)或氮氧化矽(SiON)、氧化鋁(Al2O3)等形成之電荷儲存層EC，進而，於該電荷儲存層EC上，介隔同樣由絕緣構件構成之上部閘極絕緣膜23b而包含記憶體閘極電極G1a。藉此，記憶體閘極構造體4a具有藉由下部閘極絕緣膜23a及上部閘極絕緣膜23b將電荷儲存層EC與記憶井W1及記憶體閘極電極G1a絕緣的構成。 The memory gate structure 4a is formed on the memory well W1 between the source region D1 and the drain region D2, and is interposed between the gate insulating film 23a including the insulating member including SiO 2 or the like and contains, for example, tantalum nitride (Si). 3 N 4 ) or a charge storage layer EC formed by cerium oxynitride (SiON), aluminum oxide (Al 2 O 3 ) or the like, and further, on the charge storage layer EC, the upper gate insulating layer is also formed by an insulating member. The film 23b includes a memory gate electrode G1a. Thereby, the memory gate structure 4a has a configuration in which the charge storage layer EC is insulated from the memory well W1 and the memory gate electrode G1a by the lower gate insulating film 23a and the upper gate insulating film 23b.

於記憶體閘極構造體4a，沿著側壁形成有由絕緣構件構成之側壁間隔件27a，介隔該側壁間隔件27a而鄰接第1選擇閘極構造體5a。如上所述之形成於記憶體閘極構造體4a與第1選擇閘極構造體5a之間之側壁間隔件27a係以特定之膜厚形成，而可將記憶體閘極構造體4a與第1選擇閘極構造體5a絕緣。 In the memory gate structure 4a, a sidewall spacer 27a made of an insulating member is formed along the side wall, and the first selection gate structure 5a is adjacent to the sidewall spacer 27a. The sidewall spacer 27a formed between the memory gate structure 4a and the first selective gate structure 5a as described above is formed with a specific film thickness, and the memory gate structure 4a and the first can be formed. The gate structure 5a is selected to be insulated.

又，第1選擇閘極構造體5a係於側壁間隔件27a與源極區域D1間之記憶井W1上形成有由絕緣構件構成且膜厚為9[nm]以下、較佳為3[nm]以下的閘極絕緣膜25a，於該閘極絕緣膜25a上形成有連接有第1選擇閘極線之第1選擇閘極電極G2a。 Further, the first selective gate structure 5a is formed of an insulating member formed on the memory well W1 between the sidewall spacer 27a and the source region D1, and has a film thickness of 9 [nm] or less, preferably 3 [nm]. In the gate insulating film 25a, a first selection gate electrode G2a to which a first selection gate line is connected is formed on the gate insulating film 25a.

另一方面，於記憶體閘極構造體4a之另一側壁，亦形成有由絕緣構件構成之側壁間隔件27a，介隔該側壁間隔件27a而鄰接第2選擇閘極構造體6a。如上所述之形成於記憶體閘極構造體4a與第2選擇閘極構造體6a之間之側壁間隔件27a亦以與記憶體閘極構造體4a與第1選擇閘極構造體5a間之側壁間隔件27a相同之膜厚形成，而可將記憶體閘極構造體4a與第2選擇閘極構造體6a絕緣。 On the other hand, a side wall spacer 27a made of an insulating member is formed on the other side wall of the memory gate structure 4a, and the second selection gate structure 6a is adjacent to the side wall spacer 27a. The sidewall spacer 27a formed between the memory gate structure 4a and the second selective gate structure 6a as described above is also interposed between the memory gate structure 4a and the first selection gate structure 5a. The side wall spacers 27a are formed to have the same film thickness, and the memory gate structure 4a and the second selection gate structure 6a can be insulated.

又，第2選擇閘極構造體6a係於側壁間隔件27a與汲極區域D2間之記憶井W1上形成有由絕緣構件構成且膜厚為9[nm]以下、較佳為 3[nm]以下的閘極絕緣膜25b，於該閘極絕緣膜25b上形成有連接有第2選擇閘極線之第2選擇閘極電極G3a。 Further, the second selective gate structure 6a is formed of an insulating member and has a film thickness of 9 [nm] or less, preferably in the memory well W1 between the sidewall spacer 27a and the drain region D2. The gate insulating film 25b of 3 [nm] or less has a second selection gate electrode G3a to which the second selection gate line is connected is formed on the gate insulating film 25b.

此處，介隔側壁間隔件27a沿著記憶體閘極電極G1a之側壁形成之第1選擇閘極電極G2a及第2選擇閘極電極G3a係藉由在下述之製造步驟中對導電層進行回蝕而形成，因此，分別形成為隨著遠離記憶體閘極電極G1a而頂部朝向記憶井W1逐漸下降般的側壁狀。 Here, the first selection gate electrode G2a and the second selection gate electrode G3a which are formed along the sidewall of the memory gate electrode G1a via the sidewall spacer 27a are returned to the conductive layer in the following manufacturing steps. Since the etch is formed, it is formed in a side wall shape which gradually falls toward the memory well W1 as it goes away from the memory gate electrode G1a.

於第1選擇閘極構造體5a之側壁與第2選擇閘極構造體6a之側壁，形成有由絕緣構件形成之側壁SW，於一側壁SW下部之記憶井W1表面形成有擴展區域D1a，亦於另一側壁SW下部之記憶井W1表面形成有擴展區域D2a。 A sidewall SW formed of an insulating member is formed on a sidewall of the first selective gate structure 5a and a sidewall of the second selective gate structure 6a, and an extended region D1a is formed on a surface of the memory well W1 at a lower portion of the sidewall SW. An extended region D2a is formed on the surface of the memory well W1 at the lower portion of the other side wall SW.

再者，於本實施形態之情形時，於針對第1選擇閘極電極G2a與第2選擇閘極電極G3a之間之記憶井W1將距離表面50[nm]為止之區域之雜質濃度設為1 E19/cm3以下的情形時，可藉由之後之製造步驟將閘極絕緣膜25a、25b之各膜厚形成為9[nm]以下。又，於針對第1選擇閘極電極G2a與第2選擇閘極電極G3a之間之記憶井W1將距離表面50[nm]為止之區域之雜質濃度設為3 E18/cm3以下的情形時，可藉由之後之製造步驟將閘極絕緣膜25a、25b之各膜厚形成為3[nm]以下。 Further, in the case of the present embodiment, the impurity concentration in the region from the surface 50 [nm] to the memory well W1 between the first selection gate electrode G2a and the second selection gate electrode G3a is set to 1 In the case of E19/cm 3 or less, the film thicknesses of the gate insulating films 25a and 25b can be made 9 [nm] or less by the subsequent manufacturing steps. When the memory well W1 between the first selection gate electrode G2a and the second selection gate electrode G3a has an impurity concentration in a region from the surface 50 [nm] of 3 E18/cm 3 or less, The thickness of each of the gate insulating films 25a and 25b can be made 3 [nm] or less by the subsequent manufacturing steps.

附帶而言，另一記憶胞3b亦具有與一記憶胞3a相同之構成，於另一源極區域D3與汲極區域D2間之記憶井W1上包含第1選擇閘極構造體5b及第2選擇閘極構造體6b，於該等第1選擇閘極構造體5b與第2選擇閘極構造體6b間介隔側壁間隔件27a形成有記憶體閘極構造體4b。又，於記憶胞3b，亦於第1選擇閘極構造體5b之對向之側壁分別形成有側壁SW，於該側壁SW下部之記憶井W1表面分別形成有擴展區域D3a、D2b。 Incidentally, the other memory cell 3b has the same configuration as that of the memory cell 3a, and the first selection gate structure 5b and the second are included in the memory well W1 between the other source region D3 and the drain region D2. The gate structure 6b is selected, and the memory gate structure 4b is formed between the first selection gate structure 5b and the second selection gate structure 6b via the sidewall spacers 27a. Further, in the memory cell 3b, sidewalls SW are formed on the opposite sidewalls of the first selection gate structure 5b, and extension regions D3a and D2b are formed on the surface of the memory well W1 at the lower portion of the sidewall SW, respectively.

形成於記憶體電路區域ER1之記憶井W1與形成於周邊電路區域ER2之一邏輯井W2係藉由一元件分離層20而電性分離，進而，形成 於周邊電路區域ER2之一邏輯井W2與另一邏輯井W3亦藉由另一元件分離層20而電性分離。此處，於本實施形態之情形時，於一邏輯井W2形成有具有N型之MOS電晶體構造之周邊電路18，於另一邏輯井W3形成有具有P型之MOS電晶體構造之周邊電路19。 The memory well W1 formed in the memory circuit region ER1 and the logic well W2 formed in the peripheral circuit region ER2 are electrically separated by an element separation layer 20, thereby forming One of the logic wells W2 and the other logic wells W3 in the peripheral circuit region ER2 are also electrically separated by another element separation layer 20. Here, in the case of the present embodiment, the peripheral circuit 18 having the N-type MOS transistor structure is formed in one logic well W2, and the peripheral circuit having the P-type MOS transistor structure is formed in the other logic well W3. 19.

實際上，於一邏輯井W2，於形成於基板表面之相對之雜質擴散區域D4、D5間，設置有介隔閘極絕緣膜29a形成有邏輯閘極電極G5之邏輯閘極構造體7a。再者，於邏輯閘極構造體7a之側壁形成有側壁SW，於各側壁SW下部之基板表面形成有擴展區域D4a、D5a。 Actually, in the logic well W2, a logic gate structure 7a in which the gate electrode G5 is formed via the gate insulating film 29a is provided between the opposite impurity diffusion regions D4 and D5 formed on the surface of the substrate. Further, sidewalls SW are formed on the sidewalls of the logic gate structure 7a, and extension regions D4a and D5a are formed on the surface of the substrate below the sidewalls SW.

又，導電型與一邏輯井W2不同之另一邏輯井W3亦具有與一邏輯井W2相同之構成，於形成於基板表面之相對之雜質擴散區域D6、D7間，設置有介隔閘極絕緣膜29b形成有邏輯閘極電極G6之邏輯閘極構造體7b。再者，於邏輯閘極構造體7b之側壁形成有側壁SW，於各側壁SW下部之基板表面形成有擴展區域D6a、D7a。 Further, the other logic well W3 having a conductivity type different from that of the logic well W2 has the same configuration as that of the logic well W2, and is provided with a barrier gate insulation between the opposite impurity diffusion regions D6 and D7 formed on the surface of the substrate. The film 29b is formed with a logic gate structure 7b of the logic gate electrode G6. Further, sidewalls SW are formed on the sidewalls of the logic gate structure 7b, and extension regions D6a and D7a are formed on the surface of the substrate below the sidewalls SW.

再者，半導體裝置1中，第1選擇閘極構造體5a、5b及記憶體閘極構造體4a、4b、第2選擇閘極構造體6a、6b、接點C2、邏輯閘極構造體7a、7b等由層間絕緣層21覆蓋，而各部位相互絕緣。又，例如源極區域D1、D3或汲極區域D2等其他多種各部位表面由矽化物SC覆蓋。 Further, in the semiconductor device 1, the first selection gate structures 5a and 5b and the memory gate structures 4a and 4b, the second selection gate structures 6a and 6b, the contacts C2, and the logic gate structures 7a 7b, etc. are covered by the interlayer insulating layer 21, and the respective portions are insulated from each other. Further, for example, the surfaces of the other various portions such as the source regions D1 and D3 or the drain region D2 are covered with the telluride SC.

此處，圖3係表示圖1之B-B'部分之側剖面構成且記憶體電路區域ER1之閘極接觸‧切斷區域ER12中選擇閘極電極切斷部13、15之側剖面構成的剖視圖。如圖3所示，選擇閘極電極切斷部13、15係形成於形成在記憶井W1之元件分離層20上。 Here, FIG. 3 shows a side cross-sectional configuration of the portion BB' of FIG. 1 and a gate cross-section of the memory circuit region ER1 and a side cross-section of the selected gate electrode cutting portions 13 and 15 in the cut region ER12. Cutaway view. As shown in FIG. 3, the selected gate electrode cutting portions 13, 15 are formed on the element isolation layer 20 formed in the memory well W1.

例如，於形成選擇閘極電極切斷部15之區域，於記憶體閘極構造體4b之一側壁介隔側壁間隔件27a形成有側壁狀之第2選擇閘極電極G3b，但是，於該記憶體閘極構造體4b之另一側壁，未形成第1選擇閘極電極G2b或第2選擇閘極電極G3b，而僅形成有側壁間隔件或由側壁構成之絕緣壁27b。 For example, in the region where the gate electrode cutting portion 15 is formed, the second selection gate electrode G3b having a sidewall shape is formed on the sidewall of the memory gate structure 4b via the sidewall spacer 27a. However, in the memory On the other side wall of the bulk gate structure 4b, the first selection gate electrode G2b or the second selection gate electrode G3b is not formed, and only the sidewall spacer or the insulating wall 27b composed of the side walls is formed.

又，於本實施形態之情形時，於一記憶體閘極構造體4a側之選擇閘極電極切斷部13，亦於記憶體閘極構造體4a之一側壁介隔側壁間隔件27a形成有側壁狀之第1選擇閘極電極G2a，但是，於該記憶體閘極構造體4a之另一側壁，未形成第1選擇閘極電極G2a或第2選擇閘極電極G3a，而僅形成有側壁間隔件或由側壁構成之絕緣壁27b。再者，於形成選擇閘極電極切斷部13、15之區域，藉由在製造過程中將基板表面削去一部分，而於元件分離層20之表面形成凹部30。 Further, in the case of the present embodiment, the selective gate electrode cutting portion 13 on the side of the memory gate structure 4a is also formed with the side wall spacer 27a on one side wall of the memory gate structure 4a. The first gate electrode G2a is selected in the form of a sidewall. However, the first selection gate electrode G2a or the second selection gate electrode G3a is not formed on the other sidewall of the memory gate structure 4a, and only sidewalls are formed. A spacer or an insulating wall 27b composed of a side wall. Further, in a region where the gate electrode cutting portions 13 and 15 are formed, the concave portion 30 is formed on the surface of the element separating layer 20 by cutting a part of the surface of the substrate during the manufacturing process.

其次，以下，對具有本發明之特徵性構成之接點設置構造體10a、11a、10b、11b進行說明，該等接點設置構造體10a、11a、10b、11b全部具有相同之構成，因此，此處，以下，著眼於接點設置構造體10a進行說明。圖4A係表示圖1之C-C'部分之側剖面構成且形成於記憶體電路區域ER1之閘極接觸‧切斷區域ER12之一接點設置構造體10a之側剖面構成的剖視圖。又，圖4B係表示圖1之與C-C'部分正交之D-D'部分之接點設置構造體10a之側剖面構成的剖視圖。 Next, the contact-providing structures 10a, 11a, 10b, and 11b having the characteristic configuration of the present invention will be described below. The contact-providing structures 10a, 11a, 10b, and 11b all have the same configuration. Here, the following description will be focused on the contact arrangement structure 10a. 4A is a cross-sectional view showing a side cross-sectional configuration of a contact arrangement structure 10a which is formed in a side cross-sectional configuration of a portion C-C' of FIG. 1 and which is formed in a gate contact/cut region ER12 of the memory circuit region ER1. 4B is a cross-sectional view showing a side cross-sectional configuration of the contact-arranged structure 10a of the D-D' portion orthogonal to the C-C' portion of FIG.

如圖4A及圖4B所示，接點設置構造體10a係形成於形成在記憶井W1之元件分離層20之基板表面上，具有依次積層有構成記憶體閘極構造體4a之電荷儲存層EC、上部閘極絕緣膜23b、及由與記憶體閘極電極G1a相同之層形成之記憶體閘極電極(分離記憶體閘極電極)G8a的構成。另一方面，接點設置構造體10a包含與記憶體閘極構造體4a相同之電荷儲存層EC、上部閘極絕緣膜23b、及記憶體閘極電極G8a，但不會於記憶體閘極電極G8a下部發生因較大之電壓差產生之量子穿隧效應，而電荷無法注入至電荷儲存層EC。 As shown in FIG. 4A and FIG. 4B, the contact arrangement structure 10a is formed on the surface of the substrate formed on the element isolation layer 20 of the memory well W1, and has a charge storage layer EC constituting the memory gate structure 4a in this order. The upper gate insulating film 23b and the memory gate electrode (separate memory gate electrode) G8a formed of the same layer as the memory gate electrode G1a. On the other hand, the contact arrangement structure 10a includes the same charge storage layer EC, upper gate insulating film 23b, and memory gate electrode G8a as the memory gate structure 4a, but does not exist in the memory gate electrode. A quantum tunneling effect due to a large voltage difference occurs in the lower portion of G8a, and charges cannot be injected into the charge storage layer EC.

再者，於本實施形態之情形時，構成接點設置構造體10a之電荷儲存層EC、上部閘極絕緣膜23b、及記憶體閘極電極G8a係由與構成記憶體閘極構造體4a之電荷儲存層EC、上部閘極絕緣膜23b、及記憶體閘極電極G1a相同之層形成，因此，各膜厚可形成為與記憶體閘極 構造體4a相同。 Further, in the case of the present embodiment, the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G8a constituting the contact-arranged structure 10a are formed by the memory gate structure 4a. The charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G1a are formed in the same layer. Therefore, each film thickness can be formed as a memory gate. The structure 4a is the same.

於該情形時，如圖4A所示，於接點設置構造體10a，沿著形成於側壁之側壁間隔件27c形成有側壁狀之第1選擇閘極電極G2a，於自記憶體閘極電極G8a之平坦之頂部之一部分跨過一側壁間隔件27c及第1選擇閘極電極G2a直至基板表面為止的區域豎立設置有接點C5a。於該情形時，接點C5a係於平坦之記憶體閘極電極G8a之頂部豎立設置一部分，並且亦於平坦之元件分離層20之基板表面豎立設置一部分，因此，可穩定地設置。 In this case, as shown in FIG. 4A, the structure 10a is provided at the contact, and the first selection gate electrode G2a having a sidewall shape is formed along the sidewall spacer 27c formed on the side wall, and the self-memory gate electrode G8a is formed. A portion C5a is erected in a portion of the flat top portion across a side wall spacer 27c and a first selection gate electrode G2a up to the surface of the substrate. In this case, the contact C5a is erected on the top of the flat memory gate electrode G8a, and is also erected on the substrate surface of the flat element separation layer 20, and therefore, can be stably disposed.

又，接點C5a係以於自接點設置構造體10a之記憶體閘極電極G8a至元件分離層20之間跨過第1選擇閘極電極G2a之方式形成，例如即便於利用光微影步驟形成接點C5a時相對於第1選擇閘極電極G2a產生對準偏移，亦可使接點C5a始終接觸於第1選擇閘極電極G2a之表面。如此一來，接點設置構造體10a係與第1選擇閘極電極G2a電性連接，其電阻可不受光微影步驟之影響而變得穩定。 Further, the contact C5a is formed so as to straddle the first selection gate electrode G2a between the memory gate electrode G8a of the contact-arranged structure 10a and the element isolation layer 20, for example, even in the photolithography step. When the contact C5a is formed, an alignment shift occurs with respect to the first selection gate electrode G2a, and the contact C5a may always be in contact with the surface of the first selection gate electrode G2a. In this manner, the contact arrangement structure 10a is electrically connected to the first selection gate electrode G2a, and its resistance can be stabilized without being affected by the photolithography step.

接點設置構造體10a未形成如先前般覆蓋至記憶體閘極電極之頂部之覆蓋部，而由與記憶體閘極構造體4a相同之電荷儲存層EC、上部閘極絕緣膜23b、及記憶體閘極電極G8a之層構成，因此，被限於與該記憶體閘極構造體4a大致相同之高度，進而，可藉由接點C5a使沿著記憶體閘極構造體4a之側壁之側壁間隔件27a形成之側壁狀之第1選擇閘極電極G2a與上層之配線層(未圖示)更確實地連接。 The contact setting structure 10a does not form a cover portion that covers the top of the memory gate electrode as before, but has the same charge storage layer EC, upper gate insulating film 23b, and memory as the memory gate structure 4a. Since the body gate electrode G8a has a layer structure, it is limited to substantially the same height as the memory gate structure 4a, and further, the sidewalls along the sidewall of the memory gate structure 4a can be spaced apart by the contact C5a. The first selection gate electrode G2a having the sidewall shape formed by the member 27a is more reliably connected to the wiring layer (not shown) of the upper layer.

如此一來，接點設置構造體10a能以記憶體閘極構造體4a之高度為基準選定基板表面至上層之配線層之距離，又，不包含如先前般覆蓋至記憶體閘極電極之頂部之覆蓋部，可相應地使層間絕緣層21之厚度較薄，而可防止自基板表面延伸至上層之配線層之接點之縱橫比變大。 In this way, the contact setting structure 10a can select the distance from the substrate surface to the wiring layer of the upper layer based on the height of the memory gate structure 4a, and does not include the top of the memory gate electrode as before. The cover portion can accordingly make the thickness of the interlayer insulating layer 21 thin, and can prevent the aspect ratio of the contact of the wiring layer extending from the substrate surface to the upper layer from becoming large.

再者，如圖4B所示，於沿著記憶體閘極電極G1a之末端之側壁形 成之側壁間隔件27a與沿著接點設置構造體10a之末端之側壁形成之側壁間隔件27c對向配置的區域GP1，亦無間隙地形成有第1選擇閘極電極G2a。藉此，關於第1選擇閘極電極G2a，可自接點設置構造體10a遍及記憶體閘極電極G1a連設第1選擇閘極電極G2a。 Furthermore, as shown in FIG. 4B, the sidewall shape along the end of the memory gate electrode G1a The first side gate electrode G2a is formed in the region GP1 where the side wall spacer 27a and the side wall spacer 27c formed along the side wall of the end of the contact mounting structure 10a are disposed without any gap. Thereby, regarding the first selection gate electrode G2a, the first selection gate electrode G2a can be connected to the memory gate electrode G1a from the contact arrangement structure 10a.

如此一來，於對自接點設置構造體10a跨及側壁間隔件27c及第1選擇閘極電極G2a之接點C5a施加第1選擇閘極電壓的情形時，可對介隔側壁間隔件27a與記憶體閘極電極G1a鄰接之側壁狀之第1選擇閘極電極G2a施加第1選擇閘極電壓。 In this manner, when the first selection gate voltage is applied to the contact C5a of the side wall spacer 27c and the first selection gate electrode G2a from the contact arrangement structure 10a, the sidewall spacer 27a can be interposed. The first selection gate voltage is applied to the first selection gate electrode G2a having a sidewall shape adjacent to the memory gate electrode G1a.

附帶而言，於本實施形態之情形時，於記憶體閘極電極G1a之側壁之側壁間隔件27a與接點設置構造體10a之側壁之側壁間隔件27c對向配置的區域GP1，藉由在製造過程中對導電層進行回蝕而形成有第1選擇閘極電極G2a，因此，於距離對向配置之各側壁間隔件27a、27c最遠之側壁間隔件27a、27c間之大致中央附近，第1選擇閘極電極G2a之膜厚可形成得最薄。 Incidentally, in the case of the present embodiment, the side wall spacer 27a on the side wall of the memory gate electrode G1a and the side wall spacer 27c on the side wall of the contact providing structure 10a are disposed opposite to each other, by In the manufacturing process, the conductive layer is etched back to form the first selective gate electrode G2a. Therefore, near the center of the sidewall spacers 27a and 27c which are the farthest from the side wall spacers 27a and 27c disposed opposite each other, The film thickness of the first selection gate electrode G2a can be formed to be the thinnest.

因此，於記憶體閘極電極G1a之側壁間隔件27a與接點設置構造體10a之側壁間隔件27c對向配置的區域GP1，隨著自該等側壁間隔件27a、27c朝向該側壁間隔件27a、27c間之中央附近，第1選擇閘極電極G2a之頂部表面逐漸朝向基板表面傾斜，而可凹陷形成為「ㄑ」字狀。再者，於記憶體閘極電極G1a或接點設置構造體10a、第1選擇閘極電極G2a等之各表面形成有矽化物SC。 Therefore, the side wall spacer 27a of the memory gate electrode G1a and the side wall spacer 27c of the contact arrangement structure 10a are disposed toward the side wall spacer 27a along with the side wall spacers 27a, 27c. In the vicinity of the center of 27c, the top surface of the first selection gate electrode G2a is gradually inclined toward the surface of the substrate, and may be recessed into a "ㄑ" shape. Further, a telluride SC is formed on each surface of the memory gate electrode G1a, the contact arrangement structure 10a, and the first selection gate electrode G2a.

此處，半導體裝置1係以如下方式形成有記憶體閘極電極G1a、G1b、接點設置構造體10a、11a、10b、11b、側壁間隔件27a、27c、第1選擇閘極電極G2a、G2b、及第2選擇閘極電極G3a、G3b，即，如圖1及圖4B所示，例如，將記憶體閘極電極G1a之側壁之側壁間隔件27a與接點設置構造體10a之側壁之側壁間隔件27c對應配置的區域GP1中記憶體閘極電極G1a之側壁與接點設置構造體10a之側壁之相隔距離 設為Dp，進而，如圖1及圖4A所示，將自形成於記憶體閘極電極G1a之側壁之側壁間隔件27c至側壁SW之選擇閘極電極G2a之厚度設為Dsw，將接點設置構造體10a之記憶體閘極電極G8a與第1選擇閘極電極G2a之間之側壁間隔件27c之厚度設為Dsp時，Dp<(2×Dsp)+(2×Dsw)之關係成立。 Here, the semiconductor device 1 is formed with the memory gate electrodes G1a and G1b, the contact arrangement structures 10a, 11a, 10b, and 11b, the sidewall spacers 27a and 27c, and the first selection gate electrodes G2a and G2b as follows. And the second selection gate electrodes G3a and G3b, that is, as shown in FIGS. 1 and 4B, for example, the side wall spacers 27a of the side walls of the memory gate electrode G1a and the side walls of the side walls of the contact arrangement structure 10a The distance between the side wall of the memory gate electrode G1a and the side wall of the contact arrangement structure 10a in the region GP1 corresponding to the spacer 27c As shown in FIG. 1 and FIG. 4A, the thickness of the selected gate electrode G2a from the side wall spacer 27c formed on the side wall of the memory gate electrode G1a to the side wall SW is Dsw, and the contact is made. When the thickness of the side wall spacer 27c between the memory gate electrode G8a of the structure 10a and the first selection gate electrode G2a is Dsp, the relationship of Dp<(2*Dsp)+(2*Dsw) is established.

於半導體裝置1，藉由滿足上述式，可於記憶體閘極電極G1a(G1b)之側壁之側壁間隔件27a和與該側壁間隔件27a對向配置之接點設置構造體10a、11a(10b、11b)之側壁之側壁間隔件27c之間之區域GP1無間隙地形成第1選擇閘極電極G2a(G2b)及第2選擇閘極電極G3a(G3b)。 In the semiconductor device 1, by satisfying the above formula, the side wall spacers 27a on the side walls of the memory gate electrode G1a (G1b) and the contacts disposed opposite to the side wall spacers 27a are provided with the structures 10a, 11a (10b). The first selection gate electrode G2a (G2b) and the second selection gate electrode G3a (G3b) are formed in the region GP1 between the sidewall spacers 27c of the side wall of the 11b) without a gap.

再者，於本實施形態之情形時，對使記憶體閘極電極G1a與接點設置構造體10a配置於同一直線上之情形進行了敍述，但本發明並不限定於此，只要能於記憶體閘極電極G1a之側壁之側壁間隔件27a和與該側壁間隔件27a對向配置之接點設置構造體10a之側壁之側壁間隔件27c之間之區域GP1無間隙地形成第1選擇閘極電極G1a，則亦可設為其他各種配置關係。 In the case of the present embodiment, the case where the memory gate electrode G1a and the contact arrangement structure 10a are arranged on the same straight line has been described. However, the present invention is not limited thereto, as long as it can be memorized. The first selection gate is formed without gaps between the sidewall spacer 27a of the sidewall of the bulk gate electrode G1a and the sidewall GP1 between the sidewall spacer 27c of the sidewall of the contact spacer 27a disposed opposite the sidewall spacer 27a. The electrode G1a can also be in various other arrangement relationships.

例如，亦可為儘管記憶體閘極電極G1a與接點設置構造體10a對向配置但記憶體閘極電極G1a之中心線與接點設置構造體10a之中心線產生偏移的構成、或記憶體閘極電極G1a與接點設置構造體10a不位於同一直線上之構成。 For example, the memory gate electrode G1a may be disposed opposite to the contact arrangement structure 10a, but the center line of the memory gate electrode G1a and the center line of the contact arrangement structure 10a may be shifted, or may be stored. The body gate electrode G1a and the contact arrangement structure 10a are not located on the same straight line.

又，將記憶體閘極電極G1a與接點設置構造體10a之寬度設為相同之寬度，但本發明並不限定於此，接點設置構造體10a之寬度亦可較記憶體閘極電極G1a之寬度小，又，亦可較記憶體閘極電極G1a之寬度大。又，關於接點設置構造體10a，於平面佈局上形成為棒狀，但本發明並不限定於此，亦可設為例如L字狀或J字狀等其他各種外廓形狀。 Further, the width of the memory gate electrode G1a and the contact-arranged structure 10a is set to be the same width. However, the present invention is not limited thereto, and the width of the contact-providing structure 10a may be larger than that of the memory gate electrode G1a. The width is small, and may be larger than the width of the memory gate electrode G1a. In addition, the contact-arranged structure 10a is formed in a rod shape on a planar layout. However, the present invention is not limited thereto, and may be other various outer shapes such as an L-shape or a J-shape.

(1-3)關於在寫入選擇記憶胞中使電荷注入至電荷儲存層之動作原理 (1-3) Principle of the action of injecting charge into the charge storage layer in the write selection memory cell

其次，以下，對在本發明之半導體裝置1中對例如記憶胞3a之電荷儲存層EC注入電荷而對該記憶胞3a寫入資料的情形簡單地進行說明。於該情形時，如圖2所示，使電荷注入至電荷儲存層EC之記憶胞(亦稱為寫入選擇記憶胞)3a可自記憶體閘極線(未圖示)經由接點C4a(圖1)對記憶體閘極構造體4a之記憶體閘極電極G1a施加12[V]之電荷儲存閘極電壓而沿著與該記憶體閘極電極G1a對向之記憶井W1之表面形成通道層(未圖示)。 Next, a case where the charge is injected into the charge storage layer EC of the memory cell 3a and the data is written to the memory cell 3a in the semiconductor device 1 of the present invention will be briefly described below. In this case, as shown in FIG. 2, the memory cell (also referred to as write select memory cell) 3a for injecting charge into the charge storage layer EC may be connected from the memory gate line (not shown) via the contact C4a ( 1) applying a charge storage gate voltage of 12 [V] to the memory gate electrode G1a of the memory gate structure 4a to form a channel along the surface of the memory well W1 opposed to the memory gate electrode G1a Layer (not shown).

此時，對於第1選擇閘極構造體5a，可自第1選擇閘極線(未圖示)經由接點C5a(圖1)對第1選擇閘極電極G2a施加0[V]之閘極斷開電壓，且可對源極區域D1施加0[V]之源極斷開電壓。藉此，第1選擇閘極構造體5a不會於與第1選擇閘極電極G2a對向之記憶井W1表面形成通道層，而可將源極區域D1與記憶體閘極構造體4a之通道層之電性連接遮斷而阻止自源極區域D1對記憶體閘極構造體4a之通道層施加電壓。 At this time, for the first selection gate structure 5a, a gate of 0 [V] can be applied to the first selection gate electrode G2a via the first selection gate line (not shown) via the contact C5a (FIG. 1). The voltage is turned off, and a source-off voltage of 0 [V] can be applied to the source region D1. Thereby, the first selection gate structure 5a does not form a channel layer on the surface of the memory well W1 facing the first selection gate electrode G2a, but can provide a channel between the source region D1 and the memory gate structure 4a. The electrical connection of the layers is blocked to prevent voltage from being applied to the channel layer of the memory gate structure 4a from the source region D1.

另一方面，對於第2選擇閘極構造體6a，可自第2選擇閘極線(未圖示)經由接點C6a(圖1)對第2選擇閘極電極G3a施加1.5[V]之第2選擇閘極電壓，且可對汲極區域D2施加0[V]之電荷儲存位元電壓。藉此，第2選擇閘極構造體6a係於與第2選擇閘極電極G2a對向之記憶井W1形成通道層而成為導通狀態，汲極區域D2與記憶體閘極構造體4a之通道層電性連接，從而可使記憶體閘極構造體4a之通道層為電荷儲存位元電壓即0[V]。再者，此時，可對記憶井W1施加與電荷儲存位元電壓相同之0[V]之基板電壓。 On the other hand, in the second selection gate structure 6a, the second selection gate electrode (not shown) can be applied to the second selection gate electrode G3a via the contact C6a (FIG. 1) by 1.5 [V]. 2 The gate voltage is selected, and a charge storage bit voltage of 0 [V] can be applied to the drain region D2. Thereby, the second selection gate structure 6a is formed in a channel state by forming a channel layer in the memory well W1 opposed to the second selection gate electrode G2a, and the channel layer of the drain region D2 and the memory gate structure 4a. The electrical connection is such that the channel layer of the memory gate structure 4a is the charge storage bit voltage, that is, 0 [V]. Further, at this time, a substrate voltage of 0 [V] which is the same as the charge storage bit voltage can be applied to the memory well W1.

如此一來，於記憶體閘極構造體4a，記憶體閘極電極G1a成為12[V]，通道層成為0[V]，因此，於記憶體閘極電極G1a與通道層間產 生12[V]之較大之電壓差，可利用由此產生之量子穿隧效應向電荷儲存層EC內注入電荷，而可成為寫入有資料之狀態。 As a result, in the memory gate structure 4a, the memory gate electrode G1a becomes 12 [V], and the channel layer becomes 0 [V], so that the memory gate electrode G1a and the channel layer are produced. A large voltage difference of 12 [V] can be used to inject a charge into the charge storage layer EC by the quantum tunneling effect generated thereby, and can be written in a state of data.

(1-4)關於在記憶體閘極電極被施加高電壓之電荷儲存閘極電壓之寫入非選擇記憶胞中不對電荷儲存層注入電荷的動作原理 (1-4) The principle of not injecting charge into the charge storage layer in the write non-selective memory cell in which the charge gate voltage of the memory gate electrode is applied with a high voltage

於利用本發明之製造方法製造之半導體裝置1，於例如不使電荷注入至記憶胞3a之電荷儲存層EC之情形時，將與資料之寫入時相同之高電壓之電荷儲存閘極電壓施加至記憶體閘極電極G1a，藉由第1選擇閘極構造體5a將源極區域D1與記憶體閘極構造體4a之通道層之電性連接遮斷，且藉由第2選擇閘極構造體6a將汲極區域D2與記憶體閘極構造體4a之通道層之電性連接遮斷，而可阻止向記憶體閘極構造體4a之電荷儲存層EC注入電荷。 The semiconductor device 1 manufactured by the manufacturing method of the present invention applies a high-voltage charge storage gate voltage which is the same as that at the time of writing the data, for example, when no charge is injected into the charge storage layer EC of the memory cell 3a. To the memory gate electrode G1a, the source region D1 and the channel layer of the memory gate structure 4a are electrically disconnected by the first selection gate structure 5a, and the second selection gate structure is used. The body 6a blocks the electrical connection between the drain region D2 and the channel layer of the memory gate structure 4a, and prevents charge injection into the charge storage layer EC of the memory gate structure 4a.

實際上，此時，於不使電荷注入至電荷儲存層EC之記憶胞(亦稱為寫入非選擇記憶胞)3a之記憶體閘極構造體4a，對記憶體閘極電極G1a施加12[V]之電荷儲存閘極電壓，因此，電荷儲存閘極電壓傳輸至記憶井W1，而可沿著與該記憶體閘極電極G1a對向之記憶井W1之表面形成通道層。 Actually, at this time, 12 is applied to the memory gate electrode G1a without injecting a charge into the memory gate structure 4a of the memory cell (also referred to as a non-selected memory cell) 3a of the charge storage layer EC. The charge of V] stores the gate voltage, and therefore, the charge storage gate voltage is transmitted to the memory well W1, and a channel layer can be formed along the surface of the memory well W1 opposed to the memory gate electrode G1a.

對於第1選擇閘極構造體5a，可自第1選擇閘極線(未圖示)經由接點C5a(圖1)對第1選擇閘極電極G2a施加0[V]之閘極斷開電壓，且可對源極區域D1施加0[V]之源極斷開電壓。藉此，記憶胞3a之第1選擇閘極構造體5a係於與第1選擇閘極電極G2a對向之記憶井W1成為非導通狀態，而可將源極區域D1與記憶體閘極構造體4a之通道層之電性連接遮斷。 In the first selection gate structure 5a, a gate-off voltage of 0 [V] can be applied to the first selection gate electrode G2a from the first selection gate line (not shown) via the contact C5a (FIG. 1). And a source disconnection voltage of 0 [V] can be applied to the source region D1. Thereby, the first selection gate structure 5a of the memory cell 3a is in a non-conduction state with respect to the memory well W1 opposed to the first selection gate electrode G2a, and the source region D1 and the memory gate structure can be formed. The electrical connection of the channel layer of 4a is interrupted.

又，除此以外，對於第2選擇閘極構造體6a，可自第2選擇閘極線(未圖示)經由接點C6a(圖1)對第2選擇閘極電極G3a施加1.5[V]之第2選擇閘極電壓，且可對汲極區域D2施加1.5[V]之斷開電壓。藉此，該第2選擇閘極構造體6a中與第2選擇閘極電極G3a對向之記憶井W1成為非 導通狀態，而可將汲極區域D2與記憶體閘極構造體4a之通道層之電性連接遮斷。 In addition, in the second selection gate structure 6a, 1.5 [V] can be applied to the second selection gate electrode G3a via the second selection gate line (not shown) via the contact C6a (FIG. 1). The second selection gate voltage is applied, and a drain voltage of 1.5 [V] can be applied to the drain region D2. Thereby, the memory well W1 facing the second selection gate electrode G3a in the second selection gate structure 6a becomes non- In the on state, the gate region D2 and the channel layer of the memory gate structure 4a can be electrically disconnected.

如此般，於記憶胞3a之記憶體閘極構造體4a，於兩側之第1選擇閘極構造體5a及第2選擇閘極構造體6a之下部記憶井W1成為非導通狀態，因此，藉由記憶體閘極電極G1a而形成於記憶井W1表面之通道層成為來自汲極區域D2及源極區域D1之電性連接被遮斷之狀態，而可於該通道層之周邊形成空乏層。 In the memory gate structure 4a of the memory cell 3a, the memory well W1 in the lower portion of the first selection gate structure 5a and the second selection gate structure 6a on both sides is in a non-conduction state. The channel layer formed on the surface of the memory well W1 by the memory gate electrode G1a is in a state in which the electrical connection from the drain region D2 and the source region D1 is blocked, and a depletion layer can be formed around the channel layer.

此處，於記憶體閘極構造體4a中，藉由上部閘極絕緣膜23b、電荷儲存層EC、及下部閘極絕緣膜23a之3層構成所獲得之電容(以下，稱為閘極絕緣膜電容)C2與形成於記憶井W1內且包圍通道層之空乏層之電容(以下，稱為空乏層電容)C1可視為串聯連接之構成，因此，若假設例如閘極絕緣膜電容C2為空乏層電容C1之3倍之電容，則通道層之通道電位Vch係根據下述式而成為9[V]。 Here, in the memory gate structure 4a, the capacitance obtained by the three layers of the upper gate insulating film 23b, the charge storage layer EC, and the lower gate insulating film 23a is formed (hereinafter, referred to as gate insulation). The film capacitance C2 and the capacitance (hereinafter, referred to as a depletion layer capacitance) C1 formed in the memory well W1 and surrounding the depletion layer of the channel layer can be regarded as a series connection. Therefore, for example, it is assumed that the gate insulating film capacitance C2 is deficient. When the capacitance of the layer capacitor C1 is three times, the channel potential Vch of the channel layer becomes 9 [V] according to the following formula.

藉此，於記憶體閘極構造體4a，即便對記憶體閘極電極G1a施加12[V]之電荷儲存閘極電壓，於記憶井W1由空乏層包圍之通道層之通道電位Vch亦成為9[V]，因此，記憶體閘極電極G1a與通道層間之電壓差為3[V]而變小，其結果，不會產生量子穿隧效應，而可阻止向電荷儲存層EC注入電荷。 As a result, even in the memory gate structure 4a, even if a charge storage gate voltage of 12 [V] is applied to the memory gate electrode G1a, the channel potential Vch of the channel layer surrounded by the depletion layer in the memory well W1 becomes 9 [V], therefore, the voltage difference between the memory gate electrode G1a and the channel layer is reduced to 3 [V], and as a result, quantum tunneling effect is not generated, and charge injection into the charge storage layer EC can be prevented.

除此以外，於該記憶胞3a，於記憶體閘極構造體4a與第1選擇閘極構造體5a之間之記憶井W1之區域或記憶體閘極構造體4a與第2選擇閘極構造體6a之間之記憶井W1之區域未形成雜質濃度較高之雜質擴散區域，因此，可於形成於記憶井W1表面周邊之通道層之周邊確實地形成空乏層，可藉由該空乏層阻止通道電位Vch自通道層到達至第 1選擇閘極構造體5a及第2選擇閘極構造體6a之各閘極絕緣膜25a、25b。 In addition, in the memory cell 3a, the memory well W1 region between the memory gate structure 4a and the first selective gate structure 5a, or the memory gate structure 4a and the second selective gate structure The impurity diffusion region having a high impurity concentration is not formed in the region of the memory well W1 between the bodies 6a. Therefore, the depletion layer can be surely formed around the channel layer formed around the surface of the memory well W1, and can be blocked by the depletion layer Channel potential Vch arrives from the channel layer to the first 1 The gate insulating films 25a and 25b of the gate structure 5a and the second selection gate structure 6a are selected.

藉此，於記憶胞3a，即便相應於汲極區域D2之低電壓之位元電壓或源極區域D1之低電壓之源極電壓而將第1選擇閘極構造體5a及第2選擇閘極構造體6a之閘極絕緣膜25a、25b之各膜厚形成得較薄，亦可藉由空乏層阻止通道層之通道電位Vch到達至閘極絕緣膜25a、25b，因此，可防止因通道電位Vch引起之閘極絕緣膜25a、25b之絕緣破壞。 Thereby, the first selection gate structure 5a and the second selection gate are connected to the memory cell 3a even with the source voltage of the low voltage corresponding to the drain region D2 or the source voltage of the low voltage of the source region D1. The film thicknesses of the gate insulating films 25a and 25b of the structure 6a are formed thin, and the channel potential Vch of the channel layer can be prevented from reaching the gate insulating films 25a and 25b by the depletion layer, thereby preventing the channel potential. The insulation breakdown of the gate insulating films 25a, 25b caused by Vch.

(2)半導體裝置之製造方法 (2) Manufacturing method of semiconductor device

具有如上所述之構成之半導體裝置1係藉由經過下述製造步驟，可經過較少之光罩步驟製造接點設置構造體10a、11a、10b、11b、以及可獨立地控制之第1選擇閘極電極G2a、G2b及第2選擇閘極電極G3a、G3b。圖5表示圖1之A-A'部分之側剖面構成。於該情形時，首先，如圖5A所示，準備半導體基板S，然後利用STI(Shallow Trench Isolation，淺溝槽隔離)法等於記憶體電路區域ER1與周邊電路區域ER2之邊界等其他特定部位形成包含絕緣構件之元件分離層20。 The semiconductor device 1 having the above configuration can produce the contact arrangement structures 10a, 11a, 10b, 11b and the first control which can be independently controlled by the following manufacturing steps by a small number of photomask steps. Gate electrodes G2a and G2b and second selection gate electrodes G3a and G3b. Fig. 5 is a side sectional view showing a portion AA' of Fig. 1. In this case, first, as shown in FIG. 5A, the semiconductor substrate S is prepared, and then STI (Shallow Trench Isolation) method is used to form other specific portions such as the boundary between the memory circuit region ER1 and the peripheral circuit region ER2. An element separation layer 20 including an insulating member.

其次，為了進行雜質注入而利用熱氧化法等於半導體基板S之表面形成犧牲氧化膜30a之後，於周邊電路區域ER2，利用例如離子注入法注入P型雜質或N型雜質，藉此形成P型之邏輯井W2及N型之邏輯井W3。 Next, in order to perform impurity implantation, a sacrificial oxide film 30a is formed on the surface of the semiconductor substrate S by thermal oxidation, and then a P-type impurity or an N-type impurity is implanted in the peripheral circuit region ER2 by, for example, ion implantation, thereby forming a P-type. Logical well W2 and N type logic well W3.

繼而，使用記憶體電路區域ER1之加工專用之第1光罩(未圖示)，利用光微影技術及蝕刻技術將抗蝕劑圖案化，如對與圖5A之對應部分標註相同符號加以表示之圖5B般，形成使記憶體電路區域ER1露出且覆蓋周邊電路區域ER2之抗蝕劑Rm1。 Then, the first photomask (not shown) dedicated to the processing of the memory circuit region ER1 is used to pattern the resist by photolithography and etching techniques, and the same reference numerals are given to the corresponding portions in FIG. 5A. Similarly to FIG. 5B, a resist Rm1 that exposes the memory circuit region ER1 and covers the peripheral circuit region ER2 is formed.

繼而，藉由經圖案化之抗蝕劑Rm1，僅對記憶體電路區域ER1注入P型雜質，而形成記憶井W1。進而，對記憶體電路區域ER1之表面 注入N型雜質，於與之後形成之記憶體閘極電極G1a、G1b及側壁間隔件27a(圖2)對向之基板表面形成通道形成層(未圖示)之後，原狀使用該抗蝕劑Rm1，藉由氫氟酸等將記憶體電路區域ER1之犧牲氧化膜30a去除(第1光罩加工步驟)。 Then, by the patterned resist Rm1, only the P-type impurity is implanted into the memory circuit region ER1 to form the memory well W1. Further, on the surface of the memory circuit region ER1 After the N-type impurity is implanted, a channel formation layer (not shown) is formed on the surface of the substrate opposite to the memory gate electrodes G1a and G1b and the sidewall spacer 27a (FIG. 2) formed later, and the resist Rm1 is used as it is. The sacrificial oxide film 30a of the memory circuit region ER1 is removed by hydrofluoric acid or the like (first mask processing step).

再者，於第1光罩加工步驟中，於使用P型基板作為半導體基板S之情形時，可省略將P型雜質注入至半導體基板S而形成記憶井W1之步驟。 In the case where the P-type substrate is used as the semiconductor substrate S in the first mask processing step, the step of implanting the P-type impurity into the semiconductor substrate S to form the memory well W1 can be omitted.

繼而，去除抗蝕劑Rm1之後，如對與圖5B之對應部分標註相同符號加以表示之圖5C般，於記憶體電路區域ER1及周邊電路區域ER2之整面分別形成使層狀之下部閘極絕緣膜23a、電荷儲存層EC、及上部閘極絕緣膜23b依次積層所得之ONO(Oxide-Nitride-Oxide，氧化物-氮化物-氧化物)膜之後，於上部閘極絕緣膜23b上形成之後成為記憶體閘極電極G1a、G1b之層狀之記憶體閘極電極用導電層35。繼而，利用熱氧化法或CVD(Chemical Vapor Deposition，化學氣相沈積)法等於記憶體閘極電極用導電層35上形成由絕緣構件構成之保護絕緣膜30b。 Then, after the resist Rm1 is removed, as shown in FIG. 5C, which is denoted by the same reference numeral as that of FIG. 5B, the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2 is formed so that the layered lower gate is formed. After the insulating film 23a, the charge storage layer EC, and the upper gate insulating film 23b are sequentially laminated, the obtained ONO (Oxide-Nitride-Oxide) film is formed on the upper gate insulating film 23b. The memory layer 35 for the memory gate electrode of the memory gate electrodes G1a and G1b is formed. Then, a protective insulating film 30b made of an insulating member is formed on the conductive layer 35 for the memory gate electrode by a thermal oxidation method or a CVD (Chemical Vapor Deposition) method.

繼而，使用記憶體電路區域ER1之加工專用之第2光罩(未圖示)，利用光微影技術及蝕刻技術將抗蝕劑圖案化，如對與圖5C之對應部分標註相同符號加以表示之圖6A般，僅於記憶體閘極構造體4a、4b之形成預定位置及接點設置構造體10a、11a、10b、11b之形成預定位置形成抗蝕劑Rm2，使用該抗蝕劑Rm2將記憶體閘極電極用導電層35圖案化，藉此形成記憶體閘極電極G1a、G1b、及與該記憶體閘極電極G1a、G1b分斷之小片之記憶體閘極電極G8a、G9a、G8b、G9b(第2光罩加工步驟)。 Then, using a second photomask (not shown) dedicated to the processing of the memory circuit region ER1, the resist is patterned by photolithography and etching techniques, and the same reference numerals are given to the corresponding portions in FIG. 5C. As shown in FIG. 6A, the resist Rm2 is formed only at the predetermined positions where the memory gate structures 4a and 4b are formed and the predetermined positions of the contact-providing structures 10a, 11a, 10b, and 11b are formed, and the resist Rm2 is used. The memory gate electrode is patterned by the conductive layer 35, thereby forming the memory gate electrodes G1a, G1b, and the memory gate electrodes G8a, G9a, G8b which are separated from the memory gate electrodes G1a, G1b. , G9b (2nd mask processing step).

於本實施形態之情形時，記憶體閘極電極用導電層35藉由抗蝕劑Rm2，能以記憶體閘極電極G1a(G1b)和與該記憶體閘極電極 G1a(G1b)分斷之小片之記憶體閘極電極G8a、G9a(G8b、G9b)可配置於同一直線上之方式圖案化。 In the case of the present embodiment, the memory gate electrode conductive layer 35 can be used as the memory gate electrode G1a (G1b) and the memory gate electrode by the resist Rm2. The memory gate electrodes G8a and G9a (G8b, G9b) of the G1a (G1b) divided small pieces can be patterned in such a manner as to be arranged on the same straight line.

又，如圖7所示，此時，可於使用抗蝕劑Rm2形成之記憶體閘極電極G1a(G1b)之側壁與小片之記憶體閘極電極G8a、G9a(G8b、G9b)之側壁之間形成隔開特定之距離對向配置之電極間區域GP2。 Further, as shown in FIG. 7, at this time, the side walls of the memory gate electrode G1a (G1b) formed using the resist Rm2 and the side walls of the memory gate electrodes G8a, G9a (G8b, G9b) of the small piece can be used. An inter-electrode region GP2 that is disposed opposite to a specific distance is formed.

繼而，將抗蝕劑Rm2去除之後，如對與圖6A之對應部分標註相同符號加以表示之圖6B般，將於記憶體閘極電極G1a、G1b及小片之記憶體閘極電極G8a、G9a、G8b、G9b之各形成位置以外之位置露出之上部閘極絕緣膜23b及電荷儲存層EC依次去除(將ON(Oxide-Nitride，氧化物-氮化物)膜去除)，形成對準經圖案化之記憶體閘極電極G1a、G1b與小片之記憶體閘極電極G8a、G9a、G8b、G9b殘存的上部閘極絕緣膜23b及電荷儲存層EC。 Then, after the resist Rm2 is removed, as shown in FIG. 6B, which is denoted by the same reference numeral as that of FIG. 6A, the memory gate electrodes G1a, G1b and the memory gate electrodes G8a, G9a of the small pieces, The upper gate insulating film 23b and the charge storage layer EC are sequentially removed at positions other than the respective formation positions of G8b and G9b (the ON (Oxide-Nitride) film is removed) to form an aligned patterned pattern. The upper gate insulating film 23b and the charge storage layer EC remaining in the memory gate electrodes G1a and G1b and the memory gate electrodes G8a, G9a, G8b, and G9b of the small pieces.

藉此，於記憶體電路區域ER1，可形成依次積層有下部閘極絕緣膜23a、電荷儲存層EC、上部閘極絕緣膜23b、及記憶體閘極電極G1a(G1b)之記憶體閘極構造體4a(4b)，另一方面，於閘極接觸‧切斷區域ER12、ER13，可於元件分離層20上形成依次積層有與記憶體閘極構造體4a(4b)相同之電荷儲存層EC、上部閘極絕緣膜23b、及記憶體閘極電極G1a(G1b)的接點設置構造體10a、11a(10b、11b)(接點構造體形成步驟)。 Thereby, in the memory circuit region ER1, a memory gate structure in which a lower gate insulating film 23a, a charge storage layer EC, an upper gate insulating film 23b, and a memory gate electrode G1a (G1b) are sequentially laminated can be formed On the other hand, the body 4a (4b) is formed on the element isolation layer 20 so as to have the same charge storage layer EC as the memory gate structure 4a (4b) in the gate contact layer ER12 and ER13. The structures of the upper gate insulating film 23b and the memory gate electrode G1a (G1b) are provided with structures 10a and 11a (10b, 11b) (contact structure forming step).

繼而，如對與圖6B之對應部分標註相同符號加以表示之圖6C般，於記憶體電路區域ER1及周邊電路區域ER2之整面形成保護絕緣膜30c。附帶而言，於本實施形態中，對整面地形成1層保護絕緣膜30c之情形進行敍述，但本發明並不限定於此，亦可整面地形成例如使氧化膜系之絕緣膜與氮化膜系之絕緣膜依次積層所得之雙層之保護絕緣膜。 Then, the protective insulating film 30c is formed on the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2 as shown in FIG. 6C, which is denoted by the same reference numeral as that of FIG. 6B. Incidentally, in the present embodiment, a case where one protective insulating film 30c is formed over the entire surface will be described. However, the present invention is not limited thereto, and an insulating film such as an oxide film may be formed over the entire surface. The insulating film of the nitride film is sequentially laminated to obtain the double-layered protective insulating film.

此處形成之保護絕緣膜30c成為之後形成於記憶體閘極構造體 4a(4b)及接點設置構造體10a、11a(10a、11b)之各側壁之側壁間隔件27a、27c，因此，成為相當於上述式Dp<(2×Dsp)+(2×Dsw)中表示接點設置構造體10a之記憶體閘極電極G8a與第1選擇閘極電極G2a之間之側壁間隔件27c之厚度的Dsp者。因此，保護絕緣膜30c能以上述式Dp<(2×Dsp)+(2×Dsw)成立之方式形成。 The protective insulating film 30c formed here is formed later in the memory gate structure 4a (4b) and the contact side wall spacers 27a and 27c of the respective side walls of the structures 10a and 11a (10a, 11b) are provided so as to correspond to the above formula Dp < (2 × Dsp) + (2 × Dsw). A Dsp indicating the thickness of the sidewall spacer 27c between the memory gate electrode G8a of the contact structure 10a and the first selection gate electrode G2a. Therefore, the protective insulating film 30c can be formed in such a manner that the above formula Dp < (2 × Dsp) + (2 × Dsw) holds.

繼而，藉由對保護絕緣膜30c進行回蝕，而如對與圖6C之對應部分標註相同符號加以表示之圖8A般，形成覆蓋記憶體閘極構造體4a、4b之周邊之側壁間隔件27a，並且形成未圖示之覆蓋接點設置構造體10a、11a、10b、11b之周邊之側壁間隔件27c(側壁間隔件形成步驟)。繼而，使用記憶體電路區域ER1之加工專用之第3光罩(未圖示)，利用光微影技術及蝕刻技術將抗蝕劑圖案化，如對與圖8A之對應部分標註相同符號加以表示之圖8B般，形成覆蓋周邊電路區域ER2之整面且使記憶體電路區域ER1露出的抗蝕劑Rm3。 Then, by etching back the protective insulating film 30c, the side spacers 27a covering the periphery of the memory gate structures 4a, 4b are formed as shown in Fig. 8A, which is denoted by the same reference numerals as those in Fig. 6C. And a side wall spacer 27c (side wall spacer forming step) covering the periphery of the contact providing structure 10a, 11a, 10b, 11b (not shown) is formed. Then, using a third photomask (not shown) dedicated to the processing of the memory circuit region ER1, the resist is patterned by photolithography and etching techniques, and the same reference numerals are given to the corresponding portions in FIG. 8A. Similarly to FIG. 8B, a resist Rm3 covering the entire surface of the peripheral circuit region ER2 and exposing the memory circuit region ER1 is formed.

繼而，使用該抗蝕劑Rm3，對成為第1選擇閘極構造體5a、5b(圖2)之形成預定位置及第2選擇閘極構造體6a、6b(圖2)之形成預定位置之記憶體電路區域ER1注入雜質，於與之後形成之第1選擇閘極電極G2a、G2b及第2選擇閘極電極G3a、G3b對向之基板表面形成通道形成層(未圖示)(第3光罩加工步驟)。 Then, using the resist Rm3, the predetermined position of the first selection gate structures 5a and 5b (Fig. 2) and the predetermined position of the second selection gate structures 6a and 6b (Fig. 2) are formed. The bulk circuit region ER1 implants impurities, and forms a channel formation layer (not shown) on the surface of the substrate opposite to the first selection gate electrodes G2a and G2b and the second selection gate electrodes G3a and G3b formed later (third photomask) Processing steps).

繼而，將抗蝕劑Rm3去除之後，藉由氫氟酸等將周邊電路區域ER2之犧牲氧化膜30a去除，如對與圖8B之對應部分標註相同符號加以表示之圖8C般，利用熱氧化法等，於記憶體電路區域ER1之第1選擇閘極電極G2a、G2b(圖1)及第2選擇閘極電極G3a、G3b(圖1)之形成預定位置形成閘極絕緣膜25a、25b，並且亦於周邊電路區域ER2之邏輯閘極電極G5、G6(圖1)之形成預定位置形成閘極絕緣膜29a、29b。 Then, after the resist Rm3 is removed, the sacrificial oxide film 30a of the peripheral circuit region ER2 is removed by hydrofluoric acid or the like, as shown in FIG. 8C, which is denoted by the same reference numeral as that of FIG. 8B, by thermal oxidation. And forming a gate insulating film 25a, 25b at a predetermined position where the first selection gate electrodes G2a, G2b (FIG. 1) and the second selection gate electrodes G3a, G3b (FIG. 1) of the memory circuit region ER1 are formed, and Gate insulating films 29a and 29b are also formed at predetermined positions of the logic gate electrodes G5 and G6 (FIG. 1) of the peripheral circuit region ER2.

繼而，如對與圖8C之對應部分標註相同符號加以表示之圖9A般，於記憶體電路區域ER1及周邊電路區域ER2呈層狀形成藉由之後 之加工而成為第1選擇閘極電極G2a、G2b、第2選擇閘極電極G3a、G3b、及一邏輯閘極電極G5的例如N型之導電層37，並且於周邊電路區域ER2呈層狀形成成為另一邏輯閘極電極G6之P型之逆導電層38。 Then, as shown in FIG. 9A, which is denoted by the same reference numeral as that of FIG. 8C, the memory circuit region ER1 and the peripheral circuit region ER2 are layered and formed. For example, the N-type conductive layer 37 is formed as the first selection gate electrodes G2a and G2b, the second selection gate electrodes G3a and G3b, and a logic gate electrode G5, and is formed in a layered manner in the peripheral circuit region ER2. It becomes the P-type reverse conductive layer 38 of the other logic gate electrode G6.

繼而，使用記憶體電路區域ER1之加工專用之第4光罩(未圖示)，利用光微影技術及蝕刻技術將抗蝕劑圖案化，並使用該抗蝕劑對記憶體電路區域ER1之導電層37進行加工(第4光罩加工步驟(選擇閘極電極形成用光罩加工步驟))。如對與圖9A之對應部分標註相同符號加以表示之圖9B般，藉由抗蝕劑Rm4，對覆蓋周邊電路區域ER2之整面且露出至記憶體電路區域ER1之導電層37(圖9A)進行回蝕。藉此，於周邊電路區域ER2，由抗蝕劑Rm4覆蓋之導電層37及逆導電層38原樣殘存。另一方面，於記憶體電路區域ER1，由於對露出之導電層37進行回蝕，故而沿著記憶體閘極構造體4a、4b之側壁之側壁間隔件27a與接點設置構造體10a、11a、10b、11b之側壁之側壁間隔件27c形成側壁狀之選擇閘極電極Ga、Gb。 Then, using a fourth photomask (not shown) dedicated to the processing of the memory circuit region ER1, the resist is patterned by photolithography and etching, and the resist is used for the memory circuit region ER1. The conductive layer 37 is processed (the fourth mask processing step (selecting the mask processing step for gate electrode formation)). The conductive layer 37 covering the entire surface of the peripheral circuit region ER2 and exposed to the memory circuit region ER1 is formed by the resist Rm4 as shown in FIG. 9B, which is denoted by the same reference numeral as that of FIG. 9A (FIG. 9A). Perform etch back. Thereby, in the peripheral circuit region ER2, the conductive layer 37 and the reverse conductive layer 38 covered by the resist Rm4 remain as they are. On the other hand, in the memory circuit region ER1, since the exposed conductive layer 37 is etched back, the sidewall spacers 27a and the contact-providing structures 10a, 11a along the sidewalls of the memory gate structures 4a, 4b are provided. The sidewall spacers 27c of the sidewalls of 10b, 11b form sidewall-shaped selective gate electrodes Ga, Gb.

再者，圖10係使沿著記憶體閘極構造體4a、4b及接點設置構造體10a、11a、10b、11b之各周邊形成之側壁狀之選擇閘極電極Ga、Gb相對於圖1所示之完成時之半導體裝置1中之記憶體電路區域ER1之平面佈局重合時的概略圖。 In addition, FIG. 10 is a side-gate selective gate electrode Ga, Gb formed along each of the memory gate structures 4a and 4b and the contact-arranged structures 10a, 11a, 10b, and 11b with respect to FIG. A schematic diagram when the plane layout of the memory circuit region ER1 in the semiconductor device 1 at the time of completion is overlapped.

如圖10所示，未分割狀態之選擇閘極電極Ga係一體地形成有周繞記憶體閘極電極G1a之周邊之區域、及周繞與記憶體閘極電極G1a電性分離之接點設置構造體10a、11a之周邊之區域，可無間隙地形成於記憶體閘極電極G1a之側壁之側壁間隔件27a與接點設置構造體10a、11a之側壁之側壁間隔件27c對向之區域GP1。 As shown in FIG. 10, the selective gate electrode Ga in the undivided state is integrally formed with a region around the periphery of the memory gate electrode G1a and a contact arrangement in which the peripheral winding is electrically separated from the memory gate electrode G1a. The region around the structures 10a and 11a can be formed on the side wall spacer 27a of the side wall of the memory gate electrode G1a and the side wall spacer 27c facing the side wall of the contact arrangement structures 10a and 11a without gaps. .

再者，於本實施形態之情形時，未分割狀態之選擇閘極電極Ga係由於記憶體閘極電極G1a形成為直線狀，故而具有下述形狀：以包圍分別沿一方向延伸之記憶體閘極電極G1a之周邊之方式周繞之長四 邊狀之區域與亦以包圍接點設置構造體10a、11a之各周邊之方式周繞之短四邊狀之各區域一體成形。 Further, in the case of the present embodiment, the selected gate electrode Ga in the undivided state is formed in a linear shape by the memory gate electrode G1a, and thus has a shape in which a memory gate extending in one direction is surrounded. The way around the pole electrode G1a The region of the ridge shape is integrally formed with each of the short quadrangular regions that are circumferentially wound so as to surround the respective periphery of the structures 10a and 11a.

此處，形成於記憶體電路區域ER1之導電層37或藉由對該導電層37進行回蝕而形成之選擇閘極電極Ga、Gb能以上述式Dp<(2×Dsp)+(2×Dsw)成立之方式，設定導電層37之膜厚或該導電層37之回蝕條件。 Here, the conductive layer 37 formed in the memory circuit region ER1 or the selective gate electrodes Ga, Gb formed by etching back the conductive layer 37 can have the above formula Dp < (2 × Dsp) + (2 × The manner in which Dsw is established is to set the film thickness of the conductive layer 37 or the etch back condition of the conductive layer 37.

藉由以上述式成立之方式設定各步驟中之製造條件，如表示圖10之D-D'部分之側剖面構成之圖11般，於記憶體閘極電極G1a之側壁之側壁間隔件27a與接點設置構造體10a之側壁之側壁間隔件27c對向配置之區域GP1，即便於導電層37之回蝕後，該導電層37亦無間隙地殘存，其結果，可自記憶體閘極電極G1a之側壁之側壁間隔件27a遍及接點設置構造體10a之側壁之側壁間隔件27c形成選擇閘極電極Ga。 By setting the manufacturing conditions in the respective steps in the above manner, as shown in FIG. 11 showing the side cross-sectional configuration of the D-D' portion of FIG. 10, the sidewall spacers 27a on the side walls of the memory gate electrode G1a are The conductive layer 37 remains without gaps even after the etch back of the conductive layer 37, and the self-memory gate electrode can be self-retained. The side wall spacer 27a of the side wall of the G1a forms the selection gate electrode Ga over the side wall spacer 27c of the side wall of the contact arrangement structure 10a.

再者，形成於記憶體閘極電極G1a之側壁之側壁間隔件27a與接點設置構造體10a之側壁之側壁間隔件27c之間的選擇閘極電極Ga係藉由對導電層37進行回蝕而形成，因此，於距離對向配置之各側壁間隔件27a、27c最遠之側壁間隔件27a、27c間之大致中央附近，膜厚形成得最薄，於側壁間隔件27a、27c間之中央附近，頂部表面朝向基板表面凹陷成「ㄑ」字狀。 Furthermore, the selective gate electrode Ga formed between the sidewall spacer 27a of the sidewall of the memory gate electrode G1a and the sidewall spacer 27c of the sidewall of the contact arrangement structure 10a is etched back by the conductive layer 37. Further, the film thickness is formed to be the thinnest in the vicinity of the center between the side wall spacers 27a and 27c which are the farthest from the side wall spacers 27a and 27c disposed opposite to each other, and is centered between the side wall spacers 27a and 27c. Nearby, the top surface is recessed into a "ㄑ" shape toward the surface of the substrate.

再者，此時，如圖9B所示，對未由抗蝕劑Rm4覆蓋之記憶體電路區域ER1利用離子注入法等注入低濃度之N型雜質，而於露出至外部之記憶井W1之表面形成擴展區域ETa，其後，可將抗蝕劑Rm4去除。 Further, at this time, as shown in FIG. 9B, a low-concentration N-type impurity is implanted into the memory circuit region ER1 not covered by the resist Rm4 by ion implantation or the like, and is exposed on the surface of the external memory well W1. The extended region ETa is formed, after which the resist Rm4 can be removed.

繼而，於本實施形態之情形時，使用光罩(未圖示)，利用光微影技術及蝕刻技術將抗蝕劑圖案化，並使用該抗蝕劑將周邊電路區域ER2之導電層37及逆導電層38圖案化，而於閘極絕緣膜29a、29b上形成邏輯閘極電極G5、G6，此時，可原狀利用形成邏輯閘極電極G5、 G6時使用之抗蝕劑而同時亦將記憶體電路區域ER1之選擇閘極電極Ga、Gb之一部分去除。 Then, in the case of the present embodiment, the resist is patterned by a photolithography technique and an etching technique using a photomask (not shown), and the conductive layer 37 of the peripheral circuit region ER2 is formed using the resist. The reverse conductive layer 38 is patterned, and the logic gate electrodes G5 and G6 are formed on the gate insulating films 29a and 29b. At this time, the logic gate electrode G5 can be formed as it is. The resist used in G6 is also partially removed from the selected gate electrodes Ga, Gb of the memory circuit region ER1.

於本實施形態之情形時，如對與圖9A之對應部分標註相同符號加以表示之圖12A般，可於周邊電路區域ER2於邏輯閘極構造體7a、7b之形成預定位置配置對照之後形成之該邏輯閘極構造體7a、7b之外廓形狀形成的抗蝕劑Rr1a。藉此，於周邊電路區域ER2，將露出至外部之導電層37及逆導電層38去除，而能夠僅使由抗蝕劑Rr1a覆蓋之導電層37及逆導電層38殘存。如此一來，可於周邊電路區域ER2形成與抗蝕劑Rr1a之外廓形狀一致之邏輯閘極電極G5、G6，而可形成在閘極絕緣膜29a、29b上積層有邏輯閘極電極G5、G6之邏輯閘極構造體7a、7b。 In the case of the present embodiment, as shown in FIG. 12A, which is denoted by the same reference numeral as that of FIG. 9A, it can be formed after the peripheral circuit region ER2 is placed at a predetermined position on the predetermined positions of the logic gate structures 7a and 7b. The logic gate structures 7a and 7b have a resist Rr1a formed in an outer shape. Thereby, the conductive layer 37 and the reverse conductive layer 38 exposed to the outside are removed in the peripheral circuit region ER2, and only the conductive layer 37 and the reverse conductive layer 38 covered by the resist Rr1a can remain. In this way, the logic gate electrodes G5 and G6 having the outer shape of the resist Rr1a can be formed in the peripheral circuit region ER2, and the logic gate electrode G5 can be formed on the gate insulating films 29a and 29b. Logic gate structure 7a, 7b of G6.

此時，於記憶體電路區域ER1，大致整面由抗蝕劑Rr1b覆蓋，但是，其中僅於選擇閘極電極切斷部13、14、15、16之形成預定位置，對照該選擇閘極電極切斷部13、14、15、16之外廓形狀而於抗蝕劑Rr1b形成有開口部。 At this time, in the memory circuit region ER1, substantially the entire surface is covered by the resist Rr1b, but only the selected gate electrode cutting portions 13, 14, 15, 16 are formed at predetermined positions, and the selected gate electrode is compared with the selected gate electrode. The cut portions 13 , 14 , 15 , and 16 have an outer shape and an opening is formed in the resist Rr1b.

此處，於圖10中表示將選擇閘極電極Ga、Gb之一部分去除而形成選擇閘極電極切斷部13、14、15、16之形成預定位置Pf1、Pf2、Pf3、Pf4。於配置於記憶體電路區域ER1之抗蝕劑Rr1b，僅於該等形成預定位置Pf1、Pf2、Pf3、Pf4形成開口部，藉由將自該抗蝕劑Rr1b之開口部露出之選擇閘極電極Ga、Gb之導電層去除，可對照該抗蝕劑Rr1b之開口部之外廓形狀形成將選擇閘極電極Ga、Gb分斷之選擇閘極電極切斷部13、14、15、16。 Here, FIG. 10 shows that the selected gate electrodes Ga and Gb are partially removed to form the formation target positions Pf1, Pf2, Pf3, and Pf4 of the selected gate electrode cutting portions 13, 14, 15, and 16. The resist Rr1b disposed in the memory circuit region ER1 forms an opening only at the predetermined positions Pf1, Pf2, Pf3, and Pf4, and the selected gate electrode is exposed from the opening of the resist Rr1b. The conductive layers of Ga and Gb are removed, and the selected gate electrode cutting portions 13, 14, 15, and 16 for dividing the selection gate electrodes Ga and Gb are formed in accordance with the outer shape of the opening of the resist Rr1b.

例如，圖12B表示於圖1之B-B'部分形成選擇閘極電極切斷部13、15時之側剖面構成。於抗蝕劑Rr1b之開口部H1、H3，將露出之選擇閘極電極Ga、Gb去除，如圖12B所示，可形成以該抗蝕劑Rr1b之開口部H1、H3之外廓形狀構成之選擇閘極電極切斷部13、15。 For example, FIG. 12B shows a side cross-sectional configuration in which the gate electrode cutting portions 13 and 15 are selectively formed in the portion BB' of FIG. The exposed gate electrodes Ga and Gb are removed from the openings H1 and H3 of the resist Rr1b, and as shown in FIG. 12B, the openings H1 and H3 of the resist Rr1b can be formed to have an outer shape. The gate electrode cutting portions 13 and 15 are selected.

再者，此時，於抗蝕劑Rr1b之開口部H1、H3，除選擇閘極電極Gb外，側壁間隔件27a或閘極絕緣膜29b亦露出。因此，此時，亦能將自抗蝕劑Rr1b之開口部H1、H3露出之側壁間隔件27a或閘極絕緣膜25a去除一部分。藉此，於自開口部H1、H3露出之區域，藉由去除側壁間隔件27a而於側壁間隔件27a之頂部附近形成缺損部40，並且不僅閘極絕緣膜25a，亦將元件分離層20之一部分表面去除，而可形成朝該元件分離層20凹陷之凹部30。 Further, at this time, in addition to the selection of the gate electrode Gb, the side wall spacers 27a or the gate insulating film 29b are exposed in the openings H1 and H3 of the resist Rr1b. Therefore, at this time, a part of the sidewall spacer 27a or the gate insulating film 25a exposed from the openings H1 and H3 of the resist Rr1b can be removed. Thereby, the defect portion 40 is formed in the vicinity of the top of the sidewall spacer 27a by removing the sidewall spacer 27a in the region where the opening portions H1, H3 are exposed, and not only the gate insulating film 25a but also the element isolation layer 20 A part of the surface is removed, and a recess 30 recessed toward the element separation layer 20 may be formed.

如此般，於記憶體電路區域ER1，於選擇閘極電極Ga(Gb)之複數個部位，藉由將該選擇閘極電極Ga(Gb)去除而將選擇閘極電極Ga(Gb)分斷。如此一來，可自一體之選擇閘極電極Ga(Gb)設置第1選擇閘極電極G2a(G2b)及第2選擇閘極電極G3a(G3b)，該第1選擇閘極電極G2a(G2b)包圍一接點設置構造體10a(10b)、且沿著記憶體閘極電極G1a(G1b)之一側壁之側壁間隔件27a形成為側壁狀，該第2選擇閘極電極G3a(G3b)包圍另一接點設置構造體11a(11b)、且沿著記憶體閘極電極G1a(G1b)之另一側壁之側壁間隔件27a形成為側壁狀。 In this manner, in the memory circuit region ER1, the selection gate electrode Ga (Gb) is divided by a plurality of portions of the gate electrode Ga (Gb), and the gate electrode Ga (Gb) is divided. In this way, the first selection gate electrode G2a (G2b) and the second selection gate electrode G3a (G3b) can be provided from the gate electrode Ga (Gb), and the first selection gate electrode G2a (G2b) can be provided. The side wall spacer 27a surrounding one side of the memory gate electrode G1a (G1b) is formed in a side wall shape, and the second selection gate electrode G3a (G3b) surrounds the other side. The side wall spacer 27a of the other side wall of the memory gate electrode G1a (G1b) is formed in a side wall shape by a contact point providing structure 11a (11b).

其後，藉由例如灰化等將抗蝕劑Rr1a、Rr1b去除之後，使用圖案化為N型用或P型用之抗蝕劑而對周邊電路區域ER2利用離子注入法等注入低濃度之N型雜質或P型雜質，如圖12A(再者，於圖12A中，原樣圖示出應於該步驟中去除之抗蝕劑Rr1a、Rr1b)所示，可於露出至外部之一邏輯井W2之基板表面形成N型之擴展區域ETa，並且可於同樣露出至外部之另一邏輯井W3之基板表面形成P型之擴展區域ETb。 After that, the resists Rr1a and Rr1b are removed by, for example, ashing, and then a low concentration N is implanted into the peripheral circuit region ER2 by ion implantation or the like using a resist patterned into an N-type or a P-type. The type of impurity or P type impurity, as shown in FIG. 12A (further, as shown in FIG. 12A, the resist Rr1a, Rr1b which should be removed in this step) can be exposed to one of the external logic wells W2. The surface of the substrate forms an N-type extension region ETa, and a P-type extension region ETb can be formed on the surface of the substrate of another logic well W3 which is also exposed to the outside.

繼而，將該抗蝕劑去除之後，經過形成側壁SW之步驟及其他的利用離子注入法等對必需部位注入高濃度之N型雜質或P型雜質而形成源極區域D1、D3及汲極區域D2之步驟、形成矽化物SC之步驟等之後，以覆蓋該等記憶胞3a、3b、3c、3d、3e、3f或接點設置構造體10a、11a、10b、11b、周邊電路18、19之方式形成層間絕緣層21。 Then, after the resist is removed, the source regions D1, D3, and the drain regions are formed by injecting a high concentration of N-type impurities or P-type impurities into the necessary portions by a step of forming the sidewalls SW and the like by ion implantation or the like. After the step of D2, the step of forming the telluride SC, and the like, the structures 10a, 11a, 10b, 11b, the peripheral circuits 18, 19 are disposed to cover the memory cells 3a, 3b, 3c, 3d, 3e, 3f or the contacts. The interlayer insulating layer 21 is formed in a manner.

繼而，自一接點設置構造體10a(10b)之頂部跨過第1選擇閘極電極G2a(G2b)遍及基板表面，於層間絕緣層21形成接觸孔。又，自另一接點設置構造體11a(11b)之頂部跨過第2選擇閘極電極G3a(G3b)遍及基板表面，於層間絕緣層21形成接觸孔。進而，此時，亦於其他必需之部位在層間絕緣層21形成接觸孔。 Then, a contact hole is formed in the interlayer insulating layer 21 from the top of the one-contact arrangement structure 10a (10b) across the first selection gate electrode G2a (G2b) over the substrate surface. Further, a contact hole is formed in the interlayer insulating layer 21 from the top of the other contact-arranged structure 11a (11b) across the second selection gate electrode G3a (G3b) over the substrate surface. Further, at this time, contact holes are formed in the interlayer insulating layer 21 at other necessary portions.

繼而，向各接觸孔注入導電構件而可於各接觸孔形成柱狀之接點C1、C2、C3、...等。此時，例如，若著眼於接點設置構造體10a、11a、11b、11b中之1個接點設置構造體10a，則可形成自接點設置構造體10a之平坦之頂部跨過第1選擇閘極電極G2a遍及基板表面豎立設置的剖面長方形狀之接點C5a。藉由依次進行如上所述之各步驟等，可製造具有如圖1、圖2、圖3及圖4所示之構成的半導體裝置1。 Then, a conductive member is injected into each contact hole, and columnar contacts C1, C2, C3, ..., etc. can be formed in each contact hole. In this case, for example, when one of the contact-providing structures 10a, 11a, 11b, and 11b is provided with the structure 10a, the flat top of the contact-arranged structure 10a can be formed across the first selection. The gate electrode G2a has a rectangular cross-section contact C5a which is erected on the surface of the substrate. The semiconductor device 1 having the configuration shown in FIGS. 1, 2, 3, and 4 can be manufactured by sequentially performing the above-described steps and the like.

(3)作用及效果 (3) Function and effect

於以上之構成中，於半導體裝置1設置如下接點設置構造體10a、11a(10b、11b)，即，該接點設置構造體10a、11a(10b、11b)具有依次積層有與記憶體閘極構造體4a(4b)相同之電荷儲存層EC、上部閘極絕緣膜23b、及記憶體閘極電極G8a、G9a(G8b、G9b)的構成，且自記憶體閘極構造體4a(4b)電性分離。又，於半導體裝置1設置自記憶體閘極構造體4a(4b)遍及一接點設置構造體10a、11a(10b、11b)連設之側壁狀之第1選擇閘極電極G2a(G2b)及第2選擇閘極電極G3a(G3b)。 In the above configuration, the semiconductor device 1 is provided with the following contact providing structures 10a, 11a (10b, 11b), that is, the contact providing structures 10a, 11a (10b, 11b) have the layers and the memory gates in this order. The charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrodes G8a, G9a (G8b, G9b) having the same polar structure 4a (4b), and the self-memory gate structure 4a (4b) Electrical separation. Further, the semiconductor device 1 is provided with a first gate electrode G2a (G2b) having a sidewall shape in which the memory gate structure 4a (4b) is connected to the contact structure 10a, 11a (10b, 11b). The second gate electrode G3a (G3b) is selected.

又，於半導體裝置1，設置遍及自一接點設置構造體10a(10b)之頂部跨過側壁間隔件27c及第1選擇閘極電極G2a(G2b)直至基板表面為止之區域豎立設置的一接點C5a(C5b)、及遍及自另一接點設置構造體11a(11b)之頂部跨過側壁間隔件27c及第2選擇閘極電極G3a(G3b)直至基板表面為止之區域豎立設置的另一接點C6a(C6b)，藉由一接點C5a(C5b)，將第1選擇閘極電極G2a(G2b)與上層之一配線層連接，藉由另一接點C6a(C6b)，將第2選擇閘極電極G3a(G3b)與上層之另一配 線層連接。 Further, in the semiconductor device 1, a connection is provided which is erected over the region from the top of the contact-providing structure 10a (10b) across the sidewall spacer 27c and the first selection gate electrode G2a (G2b) up to the surface of the substrate. Point C5a (C5b) and another erected region spanning from the top of the other contact arrangement structure 11a (11b) across the sidewall spacer 27c and the second selection gate electrode G3a (G3b) up to the surface of the substrate Contact C6a (C6b), the first selection gate electrode G2a (G2b) is connected to one of the upper wiring layers by a contact C5a (C5b), and the second connection is made by the other contact C6a (C6b). Select gate electrode G3a (G3b) and another one of the upper layer Line layer connection.

因此，於半導體裝置1，以自例如由與記憶體閘極構造體4a相同之電荷儲存層EC、上部閘極絕緣膜23b、及記憶體閘極電極G8a之層構成之接點設置構造體10a之平坦之頂部，跨至第1選擇閘極電極G2a的方式設置接點C5a，因此，不存在如先前般覆蓋至記憶體閘極構造體110之頂部之覆蓋部102b(圖13)，可相應地縮短至上層之配線層為止之距離而使接點C2等之縱橫比較小，如此一來，可防止接觸電阻值增大。又，於半導體裝置1，不存在如先前般覆蓋至記憶體閘極構造體110之頂部之覆蓋部102b，亦可相應地使接點設置構造體10a與上層之配線層遠離，因此，可防止與上層之配線層之接觸不良。 Therefore, in the semiconductor device 1, the structure 10a is provided by a contact formed of, for example, a layer of the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G8a which are the same as the memory gate structure 4a. The flat top portion is provided with the contact point C5a so as to straddle the first selection gate electrode G2a. Therefore, there is no cover portion 102b (FIG. 13) covering the top of the memory gate structure 110 as before, and correspondingly The distance to the wiring layer of the upper layer is shortened to make the contact C2 and the like relatively small, so that the contact resistance value can be prevented from increasing. Further, in the semiconductor device 1, there is no cover portion 102b covering the top of the memory gate structure 110 as before, and the contact arrangement structure 10a can be prevented from being separated from the wiring layer of the upper layer, thereby preventing Poor contact with the wiring layer of the upper layer.

又，於本發明之半導體裝置1之製造方法中，於記憶體電路區域ER1，將層狀之記憶體閘極電極用導電層35、層狀之上部閘極絕緣膜23b、及層狀之電荷儲存層EC依次圖案化，形成由記憶體閘極電極G1a、上部閘極絕緣膜23b、電荷儲存層EC、及下部閘極絕緣膜23a構成之記憶體閘極構造體4a、4b時，形成調用與該記憶體閘極構造體4a、4b相同之層而形成且與記憶體閘極構造體4a、4b電性分離的接點設置構造體10a、11a、10b、11b(圖6A及圖7)。 Further, in the method of manufacturing the semiconductor device 1 of the present invention, the layered memory gate electrode conductive layer 35, the layered upper gate insulating film 23b, and the layered charge are formed in the memory circuit region ER1. When the memory layer EC is sequentially patterned to form the memory gate structures 4a and 4b composed of the memory gate electrode G1a, the upper gate insulating film 23b, the charge storage layer EC, and the lower gate insulating film 23a, the call is formed. The structures 10a, 11a, 10b, and 11b are formed at the same points as the memory gate structures 4a and 4b and are electrically separated from the memory gate structures 4a and 4b (Figs. 6A and 7). .

又，於半導體裝置1之製造方法中，於形成有由側壁間隔件27a、27c覆蓋之記憶體閘極構造體4a、4b及接點設置構造體10a、11a、10b、11b之記憶體電路區域ER1(圖8A)以及周邊電路區域ER2形成閘極絕緣膜25a、25b、25c、29a、29b之後，於該閘極絕緣膜25a、25b、25c、29a、29b上形成導電層37及逆導電層38(圖9A)，其後，使周邊電路區域ER2之導電層37及逆導電層38原樣殘存，並且對記憶體電路區域ER1之導電層37進行回蝕。 Further, in the method of manufacturing the semiconductor device 1, the memory gate regions 4a and 4b covered by the sidewall spacers 27a and 27c and the memory circuit regions of the contact-providing structures 10a, 11a, 10b, and 11b are formed. After the ER1 (FIG. 8A) and the peripheral circuit region ER2 form the gate insulating films 25a, 25b, 25c, 29a, and 29b, the conductive layer 37 and the reverse conductive layer are formed on the gate insulating films 25a, 25b, 25c, 29a, and 29b. 38 (Fig. 9A), thereafter, the conductive layer 37 and the reverse conductive layer 38 of the peripheral circuit region ER2 remain as they are, and the conductive layer 37 of the memory circuit region ER1 is etched back.

藉此，於半導體裝置1之製造方法中，可形成遍及記憶體閘極構造體4a、4b與接點設置構造體10a、11a、10b、11b之周邊連設且沿著 側壁間隔件27a、27c形成為側壁狀的選擇閘極電極Ga、Gb(圖9B、圖10及圖11)。 Thereby, in the method of manufacturing the semiconductor device 1, the memory gate structures 4a and 4b and the contact arrangement structures 10a, 11a, 10b, and 11b can be formed and connected along the periphery. The side wall spacers 27a and 27c are formed as side wall-shaped selection gate electrodes Ga and Gb (FIGS. 9B, 10, and 11).

除此以外，於該半導體裝置1之製造方法中，使用藉由光罩而圖案化之抗蝕劑Rr1a將周邊電路區域ER2之導電層37及逆導電層38圖案化，藉此，於閘極絕緣膜29a、29b上形成邏輯閘極電極G5、G6，並原狀利用形成該邏輯閘極電極G5、G6時使用之抗蝕劑Rr1a、Rr1b，亦將記憶體電路區域ER1之選擇閘極電極Ga、Gb之一部分去除而將該選擇閘極電極Ga、Gb分斷。 In addition, in the method of manufacturing the semiconductor device 1, the conductive layer 37 and the reverse conductive layer 38 of the peripheral circuit region ER2 are patterned using the resist Rr1a patterned by the mask, thereby being gated. The logic gate electrodes G5 and G6 are formed on the insulating films 29a and 29b, and the resists Rr1a and Rr1b used when the logic gate electrodes G5 and G6 are formed are used as they are, and the gate electrode Ga of the memory circuit region ER1 is also selected. One of the Gb portions is removed to separate the selected gate electrodes Ga and Gb.

藉此，於半導體裝置1之製造方法中，可形成包圍一接點設置構造體10a(10b)之周邊之第1選擇閘極電極G2a(G2b)、及與該第1選擇閘極電極G2a(G2b)電性分離且包圍另一接點設置構造體11a(11b)之周邊之第2選擇閘極電極G3a(G3b)(圖12、圖13)。 Thereby, in the method of manufacturing the semiconductor device 1, the first selection gate electrode G2a (G2b) surrounding the periphery of the contact-providing structure 10a (10b) and the first selection gate electrode G2a can be formed ( G2b) electrically separates and surrounds the second selection gate electrode G3a (G3b) around the other contact providing structure 11a (11b) (FIG. 12, FIG. 13).

如此一來，於半導體裝置1之製造方法中，於形成周邊電路區域ER2之邏輯閘極電極G5、G6之光罩步驟時，同時亦將記憶體電路區域ER1之選擇閘極電極Ga、Gb分斷，藉此，可形成沿著記憶體閘極電極G1a、G1b對向配置且電性分離的第1選擇閘極電極G2a、G2b及第2選擇閘極電極G3a、G3b。 In this way, in the manufacturing method of the semiconductor device 1, when the photomask steps of the logic gate electrodes G5 and G6 of the peripheral circuit region ER2 are formed, the gate electrodes Ga and Gb of the memory circuit region ER1 are also divided. As a result, the first selection gate electrodes G2a and G2b and the second selection gate electrodes G3a and G3b which are disposed opposite to each other along the memory gate electrodes G1a and G1b and electrically separated can be formed.

又，於半導體裝置1之製造方法中，以覆蓋記憶胞3a、3b、3c、3d、3e、3f或接點設置構造體10a、11a、10b、11b等之方式形成層間絕緣層21之後，自接點設置構造體10a、11a、10b、11b之頂部跨過第1選擇閘極電極G2a、G2b或第2選擇閘極電極G3a、G3b中之任一者穿設接觸孔，並向該接觸孔填充導電構件。 Further, in the method of manufacturing the semiconductor device 1, after the interlayer insulating layer 21 is formed so as to cover the memory cells 3a, 3b, 3c, 3d, 3e, and 3f or the contact-providing structures 10a, 11a, 10b, and 11b, The top of the contact setting structures 10a, 11a, 10b, and 11b passes through the first selection gate electrodes G2a and G2b or the second selection gate electrodes G3a and G3b, and the contact holes are bored. Fill the conductive member.

藉此，於本發明中，可形成自接點設置構造體10a、11a、10b、11b之頂部跨過第1選擇閘極構造體5a、5b或第2選擇閘極構造體6a、6b中之任一者的接點C5a、C5b、C6a、C6b，藉由該接點C5a、C5b、C6a、C6b，可將位於記憶體閘極構造體4a、4b之上層之配線層與第1選 擇閘極電極G2a、G2b或第2選擇閘極電極G3a、G3b連接。 Therefore, in the present invention, the tops of the self-contacting-arranged structures 10a, 11a, 10b, and 11b can be formed to straddle the first selection gate structures 5a and 5b or the second selection gate structures 6a and 6b. Any of the contacts C5a, C5b, C6a, and C6b, by the contacts C5a, C5b, C6a, and C6b, the wiring layer located above the memory gate structures 4a, 4b and the first selection The gate electrodes G2a and G2b or the second gate electrodes G3a and G3b are connected.

(4)省略第3光罩加工步驟之其他實施形態之製造方法 (4) Manufacturing method of another embodiment in which the third mask processing step is omitted

於上述實施形態中，若著眼於利用專用於記憶體電路區域ER1之加工之專用之光罩將抗蝕劑圖案化之專用光罩步驟，則進行第1光罩加工步驟、第2光罩加工步驟、第3光罩加工步驟、及選擇閘極電極形成用之第4光罩加工步驟(選擇閘極電極形成用光罩加工步驟)之合計4個步驟，但本發明並不限定於此，亦可不進行第3光罩加工步驟中之雜質注入而設為第1光罩加工步驟、第2光罩加工步驟、及選擇閘極電極形成用光罩加工步驟(相當於上述第4光罩加工步驟)之合計3個步驟。 In the above embodiment, the first mask processing step and the second mask processing are performed by focusing on the dedicated mask step of patterning the resist using a dedicated photomask dedicated to the processing of the memory circuit region ER1. The total number of steps of the step, the third mask processing step, and the fourth mask processing step for forming the gate electrode (selecting the gate electrode forming mask processing step) are four steps, but the present invention is not limited thereto. The first mask processing step, the second mask processing step, and the selection of the gate electrode forming mask processing step (corresponding to the fourth mask processing described above) may be performed without performing impurity implantation in the third mask processing step. The total of steps) is 3 steps.

即，即便不進行第3光罩加工步驟中之雜質注入，最終形成之第1選擇閘極構造體5a、5b及第2選擇閘極構造體6a、6b之閾值電壓(Vth)亦成為所期望之值的情形時，無須進行第3光罩加工步驟，而可省略該第3光罩加工步驟。 In other words, even if the impurity implantation in the third mask processing step is not performed, the threshold voltage (Vth) of the first selected gate structures 5a and 5b and the second selected gate structures 6a and 6b which are finally formed becomes desired. In the case of the value, the third mask processing step is not required, and the third mask processing step can be omitted.

實際上，於此種省略第3光罩加工步驟之製造方法中，如圖8A所示，形成覆蓋記憶體閘極構造體4a、4b(圖6B)之周邊之側壁間隔件27a(側壁間隔件形成步驟)之後，藉由氫氟酸等將周邊電路區域ER2之犧牲氧化膜30a去除，而如圖8C所示，利用熱氧化法等，於記憶體電路區域ER1之第1選擇閘極電極G2a、G2b(圖1)及第2選擇閘極電極G3a、G3b(圖1)之形成預定位置形成閘極絕緣膜25a、25b，並且亦於周邊電路區域ER2之邏輯閘極電極G5、G6(圖1)之形成預定位置形成閘極絕緣膜29a、29b。其後，可與上述實施形態之製造方法同樣地經過圖9~圖12所示之製造步驟製造圖1所示之半導體裝置1。 Actually, in the manufacturing method in which the third mask processing step is omitted, as shown in FIG. 8A, sidewall spacers 27a (side spacers) covering the periphery of the memory gate structures 4a, 4b (FIG. 6B) are formed. After the formation step), the sacrificial oxide film 30a of the peripheral circuit region ER2 is removed by hydrofluoric acid or the like, and as shown in FIG. 8C, the first gate electrode G2a is selected in the memory circuit region ER1 by thermal oxidation or the like. G2b (FIG. 1) and second selection gate electrodes G3a, G3b (FIG. 1) are formed at predetermined positions to form gate insulating films 25a, 25b, and also in logic gate electrodes G5, G6 of peripheral circuit region ER2 (Fig. 1) The gate insulating film 29a, 29b is formed at a predetermined position. Thereafter, the semiconductor device 1 shown in Fig. 1 can be manufactured through the manufacturing steps shown in Figs. 9 to 12 in the same manner as the manufacturing method of the above embodiment.

於省略第3光罩加工步驟之本實施形態中，藉由對一般之周邊電路之製造製程追加相當於3塊光罩之製造製程，便可將以將記憶體閘極電極G1a、G1b夾入之方式配置有第1選擇閘極電極G2a、G2b及第2 選擇閘極電極G3a、G3b且可獨立控制第1選擇閘極電極G2a、G2b及第2選擇閘極電極G3a、G3b的記憶胞3a、3b、3c、3d、3e、3f裝入。因此，省略第3光罩加工步驟之製造方法與上述實施形態之製造方法相比，可減少光罩，從而可相應地謀求成本降低。 In the present embodiment in which the third mask processing step is omitted, the memory gate electrodes G1a and G1b can be sandwiched by adding a manufacturing process corresponding to three masks to the manufacturing process of the general peripheral circuit. The first selection gate electrodes G2a, G2b, and the second are disposed. The memory cells 3a, 3b, 3c, 3d, 3e, and 3f that can select the gate electrodes G3a and G3b and independently control the first selection gate electrodes G2a and G2b and the second selection gate electrodes G3a and G3b are mounted. Therefore, the manufacturing method of omitting the third mask processing step can reduce the mask as compared with the manufacturing method of the above-described embodiment, and the cost can be reduced accordingly.

(5)其他實施形態 (5) Other embodiments

再者，本發明並不限定於本實施形態，可於本發明之主旨之範圍內實施各種變化，例如，記憶胞3a、3b、3c、3d、3e、3f之數量或周邊電路18、19之數量、接點設置構造體10a、11a、10b、11b之數量、選擇閘極電極切斷部13、14、15、16之數量等亦可設為各種數量，又，記憶井W1或邏輯井W2、W3之導電型可為N型或P型中之任一種。進而，亦可設置3個以上之接點設置構造體10a、11a、...或者設置3個以上之選擇閘極電極切斷部。 Furthermore, the present invention is not limited to the embodiment, and various changes can be made within the scope of the gist of the invention, for example, the number of memory cells 3a, 3b, 3c, 3d, 3e, 3f or peripheral circuits 18, 19 The number, the number of contact arrangement structures 10a, 11a, 10b, and 11b, the number of selected gate electrode cutting portions 13, 14, 15, and 16 may be various numbers, and the memory well W1 or the logic well W2 The conductive type of W3 may be any of N type or P type. Further, three or more contact providing structures 10a, 11a, ... or three or more selected gate electrode cutting portions may be provided.

又，於上述實施形態中，對應用藉由選擇閘極電極切斷部13、14、15、16將未分割之選擇閘極電極Ga、Gb分斷而可獨立控制之第1選擇閘極電極G2a、G2b及第2選擇閘極電極G3a、G3b作為選擇閘極電極的情形進行了敍述。 Further, in the above-described embodiment, the first selection gate electrode which can be independently controlled by dividing the undivided selection gate electrodes Ga and Gb by the selection of the gate electrode cutting portions 13, 14, 15, and 16 is applied. G2a, G2b, and second selection gate electrodes G3a, G3b have been described as the selection of the gate electrode.

然而，本發明並不限定於此，亦可不將未分割而一體形成之選擇閘極電極Ga、Gb分斷，而原狀使用周繞記憶體閘極電極G1a、G1b之狀態之選擇閘極電極Ga、Gb作為側壁型閘極電極。於該情形時，於圖10中，例如亦可將2個接點設置構造體10a、11a中之1個接點設置構造體10a設置於選擇閘極電極Ga。於此種半導體裝置，以自接點設置構造體10a之頂部跨至側壁間隔件27a及選擇閘極電極Ga之方式豎立設置接點C5a，藉此，藉由自1個接點C5a對選擇閘極電極Ga施加電壓，可與記憶體閘極電極G1a分開地獨立控制選擇閘極電極Ga，可與上述實施形態同樣地獲得效果。 However, the present invention is not limited thereto, and the selection gate electrodes Ga and Gb which are integrally formed without being divided may not be divided, and the gate electrode Ga of the state around the memory gate electrodes G1a and G1b may be used as it is. Gb is used as a sidewall type gate electrode. In this case, in FIG. 10, for example, one of the two contact-arranged structures 10a and 11a may be provided on the selection gate electrode Ga. In such a semiconductor device, the contact C5a is erected so as to straddle the top of the contact-arranged structure 10a to the sidewall spacer 27a and the gate electrode Ga, whereby the gate is selected from one contact C5a. When the voltage is applied to the electrode electrode Ga, the gate electrode Ga can be independently controlled separately from the memory gate electrode G1a, and an effect can be obtained in the same manner as in the above embodiment.

進而，於上述實施形態中，對如下情形進行了敍述，即，作為 選擇閘極電極切斷部，將選擇閘極電極Ga之一部分去除而物理性地切斷，藉此，自選擇閘極電極Ga形成第1選擇閘極電極G2a及第2選擇閘極電極G3a，但本發明並不限定於此，例如，亦可設置包含導電型與選擇閘極電極Ga相反之逆導電型電極切斷層或本徵半導體層之選擇閘極電極切斷部，藉由選擇閘極電極切斷部，於選擇閘極電極形成PIN接合構造、NIN接合構造、PIP接合構造、NPN接合構造或PNP接合構造，將選擇閘極電極電性分離而形成第1選擇閘極電極G2a與第2選擇閘極電極G3a。 Further, in the above embodiment, the following case has been described, that is, as The gate electrode cutting portion is selected, and one of the selection gate electrodes Ga is removed and physically cut, whereby the first selection gate electrode G2a and the second selection gate electrode G3a are formed from the selection gate electrode Ga. However, the present invention is not limited thereto, and for example, a gate electrode cut portion including a reverse conductivity type electrode cut layer or an intrinsic semiconductor layer having a conductivity type opposite to that of the gate electrode Ga may be provided by selecting a gate electrode. The electrode cutting portion forms a PIN junction structure, a NIN bonding structure, a PIP bonding structure, an NPN bonding structure, or a PNP bonding structure in the selection gate electrode, and electrically separates the selection gate electrode to form the first selection gate electrode G2a and the first electrode. 2 Select the gate electrode G3a.

又，於上述實施形態中，對設置對與記憶體閘極電極G1a對向之基板表面之通道層選擇性地施加電壓之第1選擇閘極電極G2a與第2選擇閘極電極G3a作為選擇閘極電極的情形進行了敍述，但本發明並不限定於此，亦可相對於記憶體閘極電極G1a設置具有選擇該記憶體閘極電極G1a之功能之第1選擇閘極電極G2a或第2選擇閘極電極G3a中之任一者。 Further, in the above embodiment, the first selection gate electrode G2a and the second selection gate electrode G3a for selectively applying a voltage to the channel layer of the substrate surface facing the memory gate electrode G1a are used as the selection gates. Although the case of the pole electrode has been described, the present invention is not limited thereto, and the first selection gate electrode G2a or the second having the function of selecting the memory gate electrode G1a may be provided to the memory gate electrode G1a. Any one of the gate electrodes G3a is selected.

進而，於上述實施形態中，對首先形成有記憶體閘極構造體4a之半導體裝置1進行了敍述，但本發明並不限定於此，可應用於形成有閘極電極且於該閘極電極之側壁介隔側壁間隔件形成側壁型閘極電極之各種半導體裝置之全部。 Further, in the above-described embodiment, the semiconductor device 1 in which the memory gate structure 4a is first formed has been described. However, the present invention is not limited thereto, and can be applied to the gate electrode and the gate electrode. The sidewalls are all of the various semiconductor devices that form sidewall-type gate electrodes via the sidewall spacers.

例如，於記憶體閘極構造體4a設置電荷儲存層EC，但亦可為如下半導體裝置，即，該半導體裝置不設置電荷儲存層，而設為於基板上介隔閘極絕緣膜具有閘極電極之閘極構造體，設置有包含由與該閘極電極相同之層形成之分離閘極電極且自閘極構造體電性分離的接點設置構造體。於該情形時，半導體裝置成為如下構成：設置有自閘極構造體遍及接點設置構造體連設之側壁型閘極電極，且以自接點設置構造體之頂部跨至側壁間隔件及側壁型閘極電極之方式豎立設置有接點。 For example, the charge storage layer EC is provided in the memory gate structure 4a, but may be a semiconductor device in which the semiconductor device is not provided with a charge storage layer, and the gate insulating film has a gate on the substrate. The gate structure of the electrode is provided with a contact-arranged structure including a separate gate electrode formed of the same layer as the gate electrode and electrically separated from the gate structure. In this case, the semiconductor device is configured such that a sidewall-type gate electrode connected from the gate structure to the contact-arranged structure is provided, and the top portion of the self-contacting structure is spanned to the sidewall spacer and the sidewall The type of gate electrode is erected with contacts.

進而，作為其他實施形態，亦可於自閘極構造體遍及接點設置構造體連設之側壁型閘極電極與基板表面之間介隔閘極絕緣膜設置電荷儲存層。於該情形時，包含側壁型閘極電極之側壁型閘極構造體具有依次積層有下部閘極絕緣膜、電荷儲存層、上部閘極絕緣膜、及記憶體閘極電極的構成。另一方面，可成為如下構成：於側壁介隔側壁間隔件形成側壁型閘極構造體之閘極構造體係於基板上介隔閘極絕緣膜配置閘極電極，接點設置構造體包含與閘極電極相同之層之分離閘極電極。 Further, in another embodiment, a charge storage layer may be provided between the sidewall-type gate electrode connected to the contact-providing structure from the gate structure and the surface of the substrate via a gate insulating film. In this case, the sidewall type gate structure including the sidewall type gate electrode has a structure in which a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode are laminated in this order. On the other hand, a gate structure in which a sidewall type gate structure is formed by a side wall spacer sidewall spacer is disposed on the substrate, and a gate electrode is disposed on the substrate via a gate insulating film, and the contact arrangement structure includes a gate A separate gate electrode of the same layer as the pole electrode.

又，於上述實施形態中，接點設置構造體10a、11a或選擇閘極電極切斷部13、14等亦可形成於各種位置。 Further, in the above embodiment, the contact-providing structures 10a and 11a or the selective gate electrode cutting portions 13, 14 and the like may be formed at various positions.

附帶而言，於上述實施形態中，作為周邊電路18、19，除形成於與記憶胞3a、3b、3c、3d、3e、3f相同之區域之感測放大器或行解碼器、列解碼器等其他各種周邊電路(直接周邊電路)以外，亦可應用形成於與記憶胞3a、3b、3c、3d、3e、3f不同之區域之CPU(Central Processing Unit，中央處理單元)或ASIC(Application-Specific Integrated Circuit，特殊應用積體電路)、輸入輸出電路等其他各種周邊電路。 Incidentally, in the above-described embodiment, the peripheral circuits 18 and 19 are formed by sensing amplifiers, row decoders, column decoders, and the like formed in the same area as the memory cells 3a, 3b, 3c, 3d, 3e, and 3f. Other than various other peripheral circuits (direct peripheral circuits), a CPU (Central Processing Unit) or an ASIC (Application-Specific) formed in a region different from the memory cells 3a, 3b, 3c, 3d, 3e, and 3f may be applied. Integrated Circuit, special application integrated circuit), input and output circuits, and other various peripheral circuits.

10a‧‧‧接點設置構造體 10a‧‧‧Contact setting structure

20‧‧‧元件分離層(基板) 20‧‧‧Component separation layer (substrate)

21‧‧‧層間絕緣層 21‧‧‧Interlayer insulation

23b‧‧‧上部閘極絕緣膜 23b‧‧‧Upper gate insulating film

27a‧‧‧側壁間隔件 27a‧‧‧ sidewall spacers

27c‧‧‧側壁間隔件 27c‧‧‧ sidewall spacers

C5a‧‧‧接點 C5a‧‧‧Contact

Dsw‧‧‧厚度 Dsw‧‧‧ thickness

Dsp‧‧‧厚度 Dsp‧‧‧ thickness

Dp‧‧‧距離 Dp‧‧‧ distance

EC‧‧‧電荷儲存層 EC‧‧‧Charge storage layer

G1a‧‧‧記憶體閘極電極(閘極電極) G1a‧‧‧ memory gate electrode (gate electrode)

G2a‧‧‧第1選擇閘極電極(側壁型閘極電極) G2a‧‧‧1st selection gate electrode (sidewall type gate electrode)

G8a‧‧‧記憶體閘極電極(分離記憶體閘極電極) G8a‧‧‧ memory gate electrode (separate memory gate electrode)

GP1‧‧‧區域 GP1‧‧‧ area

S‧‧‧半導體基板 S‧‧‧Semiconductor substrate

SC‧‧‧矽化物 SC‧‧‧ Telluride

SW‧‧‧側壁 SW‧‧‧ side wall

W1‧‧‧記憶井(基板) W1‧‧‧ memory well (substrate)

Claims (8)

一種半導體裝置，其特徵在於包括：閘極構造體，其設置有閘極電極；接點設置構造體，其包含由與上述閘極電極相同之層形成之分離閘極電極，且自上述閘極構造體電性分離；側壁型閘極電極，其介隔側壁間隔件呈側壁狀形成於上述閘極構造體之側壁，並且亦介隔上述側壁間隔件呈側壁狀形成於上述接點設置構造體之側壁，且自上述閘極構造體遍及上述接點設置構造體連設；及接點，其以自上述接點設置構造體之頂部跨至上述側壁間隔件及上述側壁型閘極電極之方式豎立設置。 A semiconductor device comprising: a gate structure provided with a gate electrode; and a contact arrangement structure including a separation gate electrode formed of the same layer as the gate electrode, and from the gate The structure is electrically separated; the sidewall type gate electrode has a sidewall spacer formed on the sidewall of the gate structure in a sidewall shape, and is also formed in the contact arrangement body via the sidewall spacer. a side wall, wherein the gate structure is connected to the contact arrangement structure; and a contact is formed from the top of the contact arrangement structure to the sidewall spacer and the sidewall type gate electrode Set upright. 如請求項1之半導體裝置，其中於上述閘極電極之側壁之上述側壁間隔件、和與該側壁間隔件對向配置之上述分離閘極電極之側壁之上述側壁間隔件之間之區域，無間隙地形成有上述側壁型閘極電極。 The semiconductor device of claim 1, wherein the sidewall spacer between the sidewall spacer of the gate electrode and the sidewall spacer of the sidewall of the split gate electrode disposed opposite the sidewall spacer is absent The above-described sidewall type gate electrode is formed in a gap. 如請求項1之半導體裝置，其中將上述閘極電極之側壁與上述分離閘極電極之側壁之相隔距離設為Dp，將自上述閘極電極之側壁之上述側壁間隔件起之上述側壁型閘極電極之厚度設為Dsw，將上述閘極電極與上述側壁型閘極電極之間之上述側壁間隔件之厚度設為Dsp時，Dp<(2×Dsp)+(2×Dsw)之關係成立。 The semiconductor device of claim 1, wherein a distance between a sidewall of the gate electrode and a sidewall of the separation gate electrode is Dp, and the sidewall spacer is used for the sidewall spacer from a sidewall of the gate electrode The thickness of the pole electrode is Dsw, and when the thickness of the sidewall spacer between the gate electrode and the sidewall type gate electrode is Dsp, the relationship of Dp<(2×Dsp)+(2×Dsw) is established. . 如請求項1至3中任一項之半導體裝置，其中上述閘極電極為記憶體閘極電極，上述閘極構造體係依次積層有下部閘極絕緣膜、電荷儲存層、上部閘極絕緣膜、及上述記憶體閘極電極之記憶體閘極構造體， 上述接點設置構造體具有至少依次積層有上述電荷儲存層、上述上部閘極絕緣膜、及由與上述記憶體閘極電極相同之層形成之分離記憶體閘極電極的構成，且自上述記憶體閘極構造體電性分離，上述側壁型閘極電極係具有選擇上述記憶體閘極構造體之功能之選擇閘極電極。 The semiconductor device according to any one of claims 1 to 3, wherein the gate electrode is a memory gate electrode, and the gate structure system is sequentially laminated with a lower gate insulating film, a charge storage layer, an upper gate insulating film, And a memory gate structure of the memory gate electrode, The contact arrangement structure has a configuration in which at least the charge storage layer, the upper gate insulating film, and a separate memory gate electrode formed of the same layer as the memory gate electrode are sequentially stacked, and the memory is restored from the above The body gate structure is electrically separated, and the sidewall type gate electrode has a selection gate electrode that selects a function of the memory gate structure. 如請求項4之半導體裝置，其中上述選擇閘極電極包括沿著上述記憶體閘極電極之一側壁之上述側壁間隔件形成為側壁狀之第1選擇閘極電極、及呈側壁狀形成於上述記憶體閘極電極之另一側壁之上述側壁間隔件之第2選擇閘極電極，且上述第1選擇閘極電極與上述第2選擇閘極電極電性分離。 The semiconductor device according to claim 4, wherein the selection gate electrode includes a first selection gate electrode formed in a sidewall shape along the sidewall spacer of one side wall of the memory gate electrode, and is formed in a sidewall shape a second selected gate electrode of the sidewall spacer of the other sidewall of the memory gate electrode, and the first selected gate electrode is electrically separated from the second selected gate electrode. 一種半導體裝置之製造方法，其特徵在於包括如下步驟：接點設置構造體形成步驟，其形成具備閘極電極之閘極構造體、及至少包含由與上述閘極電極相同之層形成之分離閘極電極且自上述閘極構造體電性分離的接點設置構造體；側壁間隔件形成步驟，其沿著上述閘極構造體及上述接點設置構造體之各側壁形成側壁間隔件；側壁型閘極電極形成步驟，其以覆蓋側壁由上述側壁間隔件覆蓋之上述閘極構造體及上述接點設置構造體之方式形成導電層之後，對該導電層進行回蝕，藉此，形成自上述閘極構造體介隔上述側壁間隔件呈側壁狀連設至上述接點設置構造體之各側壁的側壁型閘極電極；及接點形成步驟，其形成以自上述接點設置構造體之頂部跨至上述側壁型閘極電極之方式豎立設置之接點。 A method of manufacturing a semiconductor device, comprising the steps of: forming a contact structure forming step, forming a gate structure having a gate electrode; and separating gates including at least a layer formed by the same layer as the gate electrode a contact electrode provided with a pole electrode and electrically separated from the gate structure; a sidewall spacer forming step of forming a sidewall spacer along each sidewall of the gate structure and the contact arrangement structure; a gate electrode forming step of forming a conductive layer so as to cover the gate structure covered by the sidewall spacer and the contact arrangement structure, and then etching back the conductive layer, thereby forming the above a gate-type gate electrode in which the gate structure is connected to each side wall of the contact-providing structure via a sidewall spacer; and a contact forming step of forming a top of the structure from the contact A joint that is erected across the sidewall type gate electrode. 一種半導體裝置之製造方法，其特徵在於包括如下步驟：接點設置構造體形成步驟，其於使下部閘極絕緣膜、電荷儲 存層、上部閘極絕緣膜、及記憶體閘極電極依次分別呈層狀積層於基板上之後進行圖案化，藉此，形成依次積層有上述下部閘極絕緣膜、上述電荷儲存層、上述上部閘極絕緣膜、及上述記憶體閘極電極之記憶體閘極構造體，並且形成至少依次積層有上述電荷儲存層、上述上部閘極絕緣膜、及由與上述記憶體閘極電極相同之層形成之分離記憶體閘極電極且自上述記憶體閘極構造體電性分離的接點設置構造體；側壁間隔件形成步驟，其沿著上述記憶體閘極構造體及上述接點設置構造體之各側壁形成側壁間隔件；選擇閘極電極形成步驟，其以覆蓋側壁由上述側壁間隔件覆蓋之上述記憶體閘極構造體及上述接點設置構造體之方式形成導電層之後，對該導電層進行回蝕，藉此，形成自上述記憶體閘極構造體介隔上述側壁間隔件連設至上述接點設置構造體之各側壁的側壁狀之選擇閘極電極；及接點形成步驟，其形成以自上述接點設置構造體之頂部跨至上述選擇閘極電極之方式豎立設置的接點。 A method of manufacturing a semiconductor device, comprising the steps of: a contact setting structure forming step for causing a lower gate insulating film and a charge storage The memory layer, the upper gate insulating film, and the memory gate electrode are sequentially layered on the substrate, and then patterned, thereby forming the lower gate insulating film, the charge storage layer, and the upper portion in this order. a gate insulating film and a memory gate structure of the memory gate electrode, and forming at least the charge storage layer, the upper gate insulating film, and the same layer as the memory gate electrode a formed contact body for separating the memory gate electrode and electrically separated from the memory gate structure; a sidewall spacer forming step of arranging the structure along the memory gate structure and the contact Forming a sidewall spacer on each of the sidewalls; and selecting a gate electrode forming step of forming the conductive layer so as to cover the memory gate structure and the contact arrangement structure covered by the sidewall spacer; The layer is etched back, whereby each of the memory gate structure is connected to the contact arrangement structure via the sidewall spacer The choice of wall-shaped side wall gate electrode; and a contact forming step of forming the contact to the contact point from the top of the structure is provided to extend over the gate electrode of the selection erected manner. 如請求項7之半導體裝置之製造方法，其中於上述接點設置構造體形成步驟中，形成2個以上之上述接點設置構造體，於上述選擇閘極電極形成步驟中，作為上述選擇閘極電極，形成介隔上述側壁間隔件連設於一上述接點設置構造體及上述記憶體閘極構造體之側壁狀之第1選擇閘極電極、及介隔上述側壁間隔件連設於另一上述接點設置構造體及上述記憶體閘極構造體且與上述第1選擇閘極電極電性分離的側壁狀之第2選擇閘極電極，於上述接點形成步驟中，形成以自一上述接點設置構造體之 頂部跨至上述第1選擇閘極電極之方式豎立設置之一上述接點、及以自另一上述接點設置構造體之頂部跨至上述第2選擇閘極電極之方式豎立設置之另一上述接點。 The method of manufacturing a semiconductor device according to claim 7, wherein in the contact-providing structure forming step, two or more contact-providing structures are formed, and in the selective gate electrode forming step, the selective gate is used The electrode is formed with a first selection gate electrode that is connected to the side wall spacer in a side wall shape of the contact arrangement structure and the memory gate structure, and the sidewall spacer is connected to the other via the sidewall spacer The second selection gate electrode having a sidewall shape electrically separated from the first selection gate electrode and the memory gate structure is formed in the contact forming step Contact setting structure One of the above-mentioned contacts is erected so as to straddle the top of the first selection gate electrode, and the other is erected so as to straddle from the top of the other contact-providing structure to the second selection gate electrode. contact.
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