KR101824376B1 - Semiconductor device, and production method therefor - Google Patents

Abstract

Since the contact C5a is provided so as to extend from the top of the contact mounting structure 10a having the same structure as that of the memory gate structure 4a to the first selection gate electrode G2a in the semiconductor device 1, The aspect ratio can be reduced by shortening the distance to the wiring layer of the upper layer as much as there is no raised portion 102b climbing up to the top of the memory gate structure 110 as shown in FIG. It is possible to prevent the contact mounting structure 10a and the wiring layer of the upper layer from being separated from each other because there is no raised portion 102b that rises up to the top of the memory gate structure 110 as in the prior art Therefore, a semiconductor device and a manufacturing method thereof which can prevent a contact failure with an upper wiring layer are proposed.

Description

Technical Field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof,

The present invention relates to a semiconductor device and a method of manufacturing the same.

Conventionally, in a semiconductor device, when a gate electrode provided on a substrate and a wiring layer disposed on an upper layer of the gate electrode are connected to each other, a columnar contact is provided and the gate electrode and the wiring layer are electrically connected using the contact (See, for example, Non-Patent Document 1). As a semiconductor device provided with a plurality of contacts, for example, a memory gate structure in which a lower gate insulating film, a charge accumulation layer, an upper gate insulating film, and a memory gate electrode are stacked in order, A configuration in which the select gate structure is provided on the active region (on the surface of the substrate), and the contact is provided in each portion is considered.

For example, in such a semiconductor device, a predetermined voltage is applied to a gate electrode through a contact from various wiring layers, a selection gate electrode of a selection gate structure, and the like, so that the surface of the substrate and the memory gate electrode G100 So that charge can be injected into the charge storage layer EC by a quantum tunnel effect generated by a voltage difference.

In this case, the select gate structure provided on the sidewall of the memory gate structure through the sidewall spacers may be formed by applying a predetermined voltage to the select gate electrode from the contact mounting portion separately from the memory gate electrode, Are independently controllable.

13, in this type of semiconductor device 100, a contact (not shown) formed integrally with a select gate electrode (not shown) is formed on an element isolation layer 101 adjacent to an active region The mounting portion 102 can be installed. In this case, in the semiconductor device 100, the charge storage layer EC of the memory gate structure, the upper gate insulating film 23b, and the memory gate electrode G100 are extended to the element isolation layer 101, The contact mounting portion 102 may be formed on the sidewall of the charge accumulation layer EC, the upper gate insulating film 23b, and the memory gate electrode G100 through the sidewall spacer 105. [ Each part of the memory gate electrode G100 and the contact mounting part 102 is covered with the interlayer insulating layer 120 and is electrically connected to another interlayer insulating layer 121 in the upper layer of the interlayer insulating layer 120 An upper wiring layer 112 is provided.

The contact mounting portion 102 is provided with a contact C100 on a flat contact mounting face 102c and is electrically connected to the wiring layer 112 of the upper layer by the contact C100. Thereby, the contact mounting portion 102 can apply a voltage applied from the wiring layer 112 in the upper layer to the selection gate electrode formed in the active region.

In such a semiconductor device 100, not only the contact mounting portion 102 and one wiring layer 112 in the upper layer are electrically connected by the contact C100, but also in an active region (not shown), for example, An impurity diffusion region (not shown) formed on the region and another wiring layer 113 in the upper layer are electrically connected to each other by the other contact C101.

Another semiconductor device 100 is provided with another interlayer insulating layer 123 on the upper layer of the interlayer insulating layer 121 provided with the wiring layers 112 and 113 and the other interlayer insulating layer 123 is provided with another The wiring layer 114 can be disposed. In this case, in the semiconductor device 100, the wiring layers 113 and 114 are electrically connected by the contact C102. For example, a voltage applied to the wiring layer 114 of the uppermost layer is electrically connected to the contacts C102, The interconnection layer 113, and the contact C101 in this order to the impurity diffusion layer on the substrate surface.

"Until the formation of semiconductors," Renesas Electronics, "[online], October 08, 2014 search, Internet (URL: http://japan.renesas.com/company_info/fab/line/line.html)

When manufacturing the selection gate electrode (not shown) adjacent to the memory gate electrode G100 through the sidewall spacer 105 and the contact installation portion 102 formed integrally with the selection gate electrode, first, the sidewall spacer The upper gate insulating film 23b and the memory gate electrode G100 covered with the sidewall spacers 105 are formed in the element isolation layer 101 when the memory gate structure covered with the gate insulating film 105 is formed on the active region. .

Subsequently, a layered conductive layer is formed on the entire surface of these active regions or device isolation layers 101. [ Subsequently, a resist is formed in a region of the element isolation layer 101, which is a position where the contact mounting portion 102 is to be formed, and then the conductive layer is etched back. Then, along the sidewall spacer 105, Is formed on the active region and the conductive layer is left as it is in the resist forming region to form the contact mounting portion 102 continuously provided with the selection gate electrode in the device isolation layer 101. [

The contact mounting portion 102 thus formed is provided with a base portion 102a having a flat contact mounting face 102c on which the contact C100 can be set up and installed and the base portion 102a is formed from the base portion 102a, The raised portion 102b climbing up to the top of the frame G100 is formed. As a result, in the semiconductor device 100, the memory gate electrode G100 and the contact mounting portion 102 are arranged such that the raised portion 102b protruding upward from the top of the memory gate electrode G100 is formed It is necessary to increase the film thickness of the interlayer insulating layer 120.

Thus, in the conventional semiconductor device 100, since the thickness of the interlayer insulating layer 120 is increased, the height of the contact surface C101 connecting the substrate surface of the memory well to the wiring layer 113 of the upper layer is also increased, The aspect ratio (contact height / contact diameter) of the contact C101 becomes large. As a result, there is a problem that the contact resistance value increases.

On the other hand, if the thickness of the interlayer insulating layer 120 is made thinner in order to reduce the aspect ratio in order to prevent an increase in the contact resistance value of the contact C101, the top portion of the contact mounting portion 102, There is a possibility that contact failure may occur between the contact mounting portion 102 to which different voltages are applied and the wiring layer 113 of the upper layer.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and it is an object of the present invention to propose a semiconductor device capable of preventing an increase in contact resistance value and also preventing a contact failure with a wiring layer and a manufacturing method thereof.

In order to solve such a problem, a semiconductor device of the present invention comprises a memory gate structure in which a lower gate insulating film, a charge accumulation layer, an upper gate insulating film, and a memory gate electrode are stacked in order, at least the charge accumulation layer, And a separate memory gate electrode formed of the same layer as the memory gate electrode are stacked in this order on a side wall of the memory gate structure and electrically isolated from the memory gate structure; Side select gate electrode formed continuously from the memory gate structure to the contact mounting structure and formed in a side wall shape through the side wall spacer on the side wall of the contact mounting structure, Characterized from the top of the contact to the mounting structure comprising the side wall spacer and the contact erected to span the side-by wolhyeong selection gate electrode.

The semiconductor device according to the present invention is the semiconductor device as described above, wherein the sidewall-shaped select gate electrode includes: a first select gate electrode formed in a sidewall shape along the sidewall spacer on one sidewall of the memory gate electrode; And a second select gate electrode formed in a sidewall shape in the sidewall spacer of the other sidewall of the memory gate electrode, wherein the first select gate electrode and the second select gate electrode are electrically separated from each other, Wherein the contact mounting structure includes a first contact mounting structure disposed at one end side in the longitudinal direction of the memory gate structure and a second contact contact structure disposed at the other end side in the longitudinal direction of the memory gate structure, Wherein the first contact is formed by a mounting structure, A first contact provided so as to extend from the top of the tact installation structure to the sidewall spacer and the first select gate electrode, and a second contact provided so as to extend from the top of the second contact mounting structure to the sidewall spacer and the second select gate electrode And a second contact.

The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device comprising depositing a lower gate insulating film, a charge accumulating layer, an upper gate insulating film, and a memory gate electrode in this order on a substrate, The upper gate insulating film, and the memory gate electrode are stacked in this order, and at least the charge accumulation layer, the upper gate insulating film, and the isolation formed of the same layer as the memory gate electrode Forming a contact mounting structure in which memory gate electrodes are stacked in order and electrically disconnected from the memory gate structure; and forming a contact hole in the contact gate structure to form a sidewall spacer along each side wall of the memory gate structure and the contact mounting structure Sidewall spacer And forming a conductive layer on the memory gate structure to cover the side wall of the memory gate structure and the contact mounting structure by the sidewall spacers and then etching back the conductive layer, A selective gate electrode formation step of forming a sidewall-shaped selective gate electrode continuously provided through the sidewall spacers on the gate insulating film, a contact forming step of forming a contact so as to extend from the top of the contact mounting structure to the selective gate electrode, And FIG.

According to the present invention, since the contact is provided so as to extend from the top of the contact mounting structure having the same structure as that of the memory gate structure to the select gate electrode, there is no contact with the top of the memory gate structure , The distance to the wiring layer in the upper layer can be shortened and the aspect ratio can be reduced. Thus, the increase in the contact resistance value can be prevented. In addition, since the contact mounting structure and the wiring layer in the upper layer can be separated from each other, the contact failure with the wiring layer can be prevented.

1 is a schematic view showing a planar layout of a semiconductor device manufactured by a manufacturing method according to the present invention.
2 is a cross-sectional view showing a side cross-sectional configuration at a portion AA 'in Fig.
3 is a cross-sectional view showing a side cross-sectional configuration at a portion BB 'in Fig.
4 (a) is a cross-sectional view showing a side cross-sectional configuration at CC 'in Fig. 1, and Fig. 4 (b) is a cross- to be.
5A is a schematic view showing the manufacturing process 1 of the semiconductor device, FIG. 5B is a schematic view showing the manufacturing process 2 of the semiconductor device, and FIG. 5C is a cross- (3) of a semiconductor device.
6 (a) is a schematic view showing a manufacturing process (4) of a semiconductor device, FIG. 6 (b) is a schematic view showing a semiconductor device manufacturing process (5) (6) of a semiconductor device.
7 is a cross-sectional view showing a side cross-sectional configuration in the DD 'portion of FIG. 1 in the semiconductor device manufacturing process (4).
8A is a schematic view showing a semiconductor device manufacturing process 7, FIG. 8B is a schematic view showing a semiconductor device manufacturing process 8, and FIG. 8C is a cross- (9) of a semiconductor device.
FIG. 9A is a schematic view showing a semiconductor device manufacturing process 10, and FIG. 9B is a schematic view showing a semiconductor device manufacturing process 11. FIG.
10 is a schematic view showing a plan layout of FIG. 1 in which a selection gate electrode is overlapped and a formation position of a selection gate electrode cut portion is to be formed.
11 is a cross-sectional view showing a side cross-sectional configuration in DD 'of FIG.
FIG. 12A is a cross-sectional view showing a side cross-sectional configuration at a portion AA 'in FIG. 1 in the semiconductor device manufacturing process 12, and FIG. 12B is a cross- 12 is a cross-sectional view showing a side cross-sectional configuration taken along the line BB 'in FIG.
13 is a cross-sectional view showing a side sectional configuration of a conventional semiconductor device having a contact mounting portion.

Hereinafter, embodiments for carrying out the present invention will be described. The description will be made in the order described below.

1. Configuration of the semiconductor device according to the present invention

  1-1. Flat layout of semiconductor devices

  1-2. Sectional configuration of each portion of the semiconductor device

  1-3. As to the operation principle of injecting charge into the charge storage layer in the write select memory cell

  1-4. In a write unselected memory cell in which a charge accumulation gate voltage of a high voltage is applied to the memory gate electrode,

2. Manufacturing Method of Semiconductor Device

3. Action and effect

4. Manufacturing method according to another embodiment in which the third photomask processing step is omitted

5. Other Embodiments

(1) Configuration of the semiconductor device according to the present invention

(1-1) Flat layout of semiconductor device

1 is a schematic view showing a plan layout of a semiconductor device 1 according to the present invention and includes memory gate structures 4a and 4b formed in a memory circuit region ER1, first select gate structures 5a and 5b, The planar layout of the select gate structures 6a and 6b and the contact mounting structures 10a and 11a and 10b and 11b and the select gate electrode cutouts 13 and 14 and 15 and 16 and the logic formed in the peripheral circuit region ER2 Are centered on the plane layout of the gate structures 7a and 7b. 1, a side wall spacer formed on each side wall of the memory gate structures 4a and 4b and the contact mounting structures 10a and 11a, 10b and 11b and the first select gate structures 5a and 5b, And the sidewall formed in the second select gate structures 6a and 6b, the memory well W1, and the element isolation layer formed in the logic well W2 and W3 are omitted.

The present invention is characterized in that the contact mounting structures 10a, 11a, 10b, and 11b have characteristic features. First, the contact mounting structures 10a, 11a, 10b, The detailed configuration of the contact mounting structures 10a, 11a, 10b, and 11b will be described in detail later in "(1-2) Sectional Configuration at Each Part of the Semiconductor Device".

In this case, the semiconductor device 1 has a memory circuit region ER1 and a peripheral circuit region ER2 on a semiconductor substrate (not shown). For example, the P-type memory well W1 is connected to the memory circuit region ER1 , And a P-type logic well W2 and an N-type logic well W3 are formed in the peripheral circuit region ER2.

A memory cell region ER11 is provided between the gate contact and trimming regions ER12 and ER13 in the memory circuit region ER1 and a plurality of memory cells 3a, 3b, 3c, 3d, 3e, and 3f are arranged in a matrix form. Since these memory cells 3a, 3b, 3c, 3d, 3e and 3f all have the same configuration, the memory cells 3a and 3b arranged mainly in the A-A 'portion will be described here.

In this case, the memory cell 3a has a structure in which the memory gate structure 4a is arranged between the first select gate structure 5a and the second select gate structure 6a through a sidewall spacer (not shown). In this embodiment, one memory gate structure 4a forming the first memory cell 3a, 3c and 3e and the other memory gate 3b forming the second memory cell 3b, 3d and 3f The structures 4b are formed in a straight line and are arranged so as to be in parallel with each other. A contact C4a (C4b) connected to a memory gate line (not shown) is provided in the memory gate structure 4a (4b), and the memory gate electrode G1a (G1b) A predetermined memory gate voltage may be applied via the contact C4a (C4b).

The memory cell region ER11 is provided with a first select gate structure 5a (5b) having the first select gate electrode G2a (G2b) and a second select gate electrode G3a (G3b) The first select gate structure 5a (5b) and the second select gate structure 6a (6b) are formed in the memory gate structure 4a (4b )]. The first select gate electrode G2a (G2b) and the second select gate electrode G3a (G3b) are formed in a sidewall shape along the sidewall spacer of the sidewall of the memory gate electrode G1a (G1b) The first selection gate electrode G2a (G2b) and the second selection gate electrode G3a (G3b) are arranged on the same main line circulating the gate electrode G1a (G1b) And are electrically separated by the electrode cutouts 13 and 14 (15 and 16).

Two source regions D1 and D3 are formed symmetrically on the surface of the memory well W1 in the memory cell region ER11 with a predetermined gap therebetween. A plurality of drain regions D2 are formed. In this case, in the memory cell region ER11, the memory cells 3a, 3c, and 3e in the first column are disposed between one source region D1 and the drain region D2, The memory cells 3a to 3d and the memory cells 3b and 3d are arranged with the drain region D2 as a center line between the source regions D3 and D3. , 3d and 3f are symmetrically formed. In the memory cells 3a, 3c and 3e between one source region D1 and the drain region D2 between the first select gate structure 5a and the second select gate structure 6a, In the memory cells 3b, 3d, and 3f disposed between the drain region D2 and the other source region D3, the second select gate structure 6b and the third select gate structure And the memory gate structure 4b is disposed between the first select gate structures 5b.

In practice, one source region D1 formed on the surface of the memory well W1 is formed along one first select gate structure 5a, and the formation of the memory cells 3a, 3c, and 3e in the first column 3c and 3e arranged in a line in the region adjacent to the first select gate structure 5a in accordance with the position of the first select gate structure 5a. In the source region D1, a contact C1 connected to a source line (not shown) is provided, and a predetermined source voltage can be applied from the source line through the contact C1.

A plurality of drain regions D2 formed on the surface of the memory well W1 between the second select gate structures 6a and 6b are connected to the drain regions D2 of the adjacent memory cells 3a and 3b (3c, 3d, 3e and 3f) 3b, 3c, 3d, 3e, and 3f) are formed in regions adjacent to the second select gate structures 6a, 6b, respectively, in accordance with the formation positions of the memory cells 3a, 3b ). In each drain region D2, a contact C2 connected to a bit line (not shown) is provided, and a predetermined bit voltage can be applied from the bit line through the contact C2. The bit lines (not shown) are shared by the memory cells 3a, 3b (3c, 3d) 3e, 3f arranged in the row direction in FIG. 1 and the memory cells 3a, 3b 3c, 3d) (3e, 3f)], a predetermined bit voltage can be uniformly applied in units of rows.

The other source region D3 formed on the surface of the memory well W1 is formed symmetrically with respect to one source region D1 and in the same way as one source region D1, (5b) and shared by the memory cells 3b, 3d, and 3f in the second column. In this source region D3, a contact C3 is provided upright, and the same source line as that of one source region D1 is connected to the contact C3. In this way, the same source voltage can be uniformly applied to the memory cells 3a, 3b, 3c, 3d, 3e, and 3f disposed in the memory cell area ER11 through the contacts C1 and C3.

One gate contact / trimming region ER12 adjacent to the memory cell region ER11 and another gate contact / trimming region ER13 adjacent to the memory cell region ER11 are formed in the memory cell region ER11 The two memory gate electrodes G1a and G1b are arranged in a straight line and are arranged in one line. One end of the memory gate electrodes G1a and G1b is disposed in one gate contact / cut region ER12, The other end of the memory gate structures 4a and 4b may be disposed in the other gate contact / trimming region ER13.

In this embodiment, the first select gate electrode G2a, the memory gate electrode G1a, and the second select gate electrode G3a constituting the memory cell 3a, 3c, and 3e in the first column, Since the second selection gate electrode G3b, the memory gate electrode G1b and the first selection gate electrode G2b constituting the memory cells 3b, 3d and 3f of the memory cell array 3b are symmetrically formed, Attention is focused on the first select gate electrode G2a, the memory gate electrode G1a, and the second select gate electrode G3a constituting the tenth memory cell 3a, 3c, 3e and the gate contact / , ER13 will be described.

In this case, one gate contact / cut region ER12 is provided with a contact mounting structure 10a which is separated from the memory gate electrode G1a and is insulated from the memory gate electrode G1a. In the case of this embodiment, the contact mounting structure 10a is formed in a strip shape and arranged on the same straight line as the longitudinal direction of the memory gate electrode G1a. In addition, a first select gate electrode G2a extending from the memory cell region ER11 is formed in a quadrangular shape in one gate contact / cut region ER12, and the first select gate electrode G2a The contact mounting structure 10a is disposed through the sidewall spacer in the central region surrounded by the first selection gate electrode G2a and the contact mounting structure 10a via the sidewall spacer.

Here, in one gate contact / cutoff region ER12, a contact C5a is set up in a region from the top of the contact mounting structure 10a to the surface of the substrate via the sidewall spacer and the first select gate electrode G2a . Thereby, a predetermined first select gate voltage can be applied to the first select gate electrode G2a from the first select gate line (not shown) through the contact C5a.

In addition, in one gate contact / cut-off region ER12, a part of the first select gate electrode G2a formed in a quadrangular form and a part of the second select gate electrode GL2a extending from the memory cell region ER11 A selective gate electrode cut-off portion 13 is provided between the ends of the gate electrodes G1a and G3a. The selective gate electrode cutout portion 13 is disposed such that a part of the first select gate electrode G2a formed in a quadrangular shape and the end of the second select gate electrode G3a face each other with a predetermined distance therebetween, (G2a) and the second selection gate electrode (G3a). Thereby, even if the first select gate voltage is applied to the first select gate electrode G2a through the contact C5a in one gate contact cut region ER12, the select gate electrode cut- The voltage application from the gate electrode G2a to the second selection gate electrode G3a can be blocked.

On the other hand, the other gate contact / trimming region ER13 is also provided with a contact mounting structure 11a which is separated from the memory gate electrode G1a and is insulated from the memory gate electrode G1a. In the case of this embodiment, the contact mounting structure 11a is also formed in the shape of a band like the one contact mounting structure 10a described above, and arranged on the same straight line as the longitudinal direction of the memory gate electrode G1a have.

A second select gate electrode G3a extending from the memory cell region ER11 is formed in a quadrangular shape in the other gate contact / cutout region ER13. A center region surrounded by the second select gate electrode G3a, And the second selection gate electrode G3a and the contact mounting structure 11a are adjacent to each other through the sidewall spacers.

Here, in another gate contact / trimming region ER13, a contact C6a is provided in a region from the contact mounting structure 11a to the surface of the substrate through the sidewall spacer and the second selection gate electrode G3a. As a result, a predetermined second select gate voltage can be applied to the second select gate electrode G3a from the second select gate line (not shown) through the contact C6a.

In addition, in the other gate contact / trimming region ER13, a part of the second selection gate electrode G3a formed in a quadrangular form and a part of the linear first selection gate electrode G2a extending from the memory cell region ER11 A selective gate electrode cut-off portion 14 is provided between the end of the selective gate electrode cut- As a result, even in the other gate contact / trimming region ER13, a part of the second select gate electrode G3a formed in a quadrangle and the end of the first select gate electrode G2a are electrically connected to each other by the select gate electrode cut- It is divided and electrically separated. Thus, even if the second select gate voltage is applied to the second select gate electrode G3a through the contact C6a in the other gate contact / cutout region ER13, the select gate electrode cut- The voltage application to the first selection gate electrode G2a from the electrode G3a can be cut off.

In this manner, in the memory circuit region ER1, the contact mounting structure 10a and the first selection gate electrode G2a connected to one contact C5a and the contact mounting structure 11a And the second select gate electrode G3a are electrically separated by the select gate electrode cutouts 13 and 14 so that the first select gate electrode G2a and the second select gate electrode G3a can be independently controlled .

In addition, the second select gate electrode G3b, the memory gate electrode G1b, and the first select gate electrode G2b on the second row side of the gate contact / cutout regions ER12 and ER13 are formed on the above- The memory cell has the same structure as the first select gate electrode G2a structure 5a, the memory gate electrode G1a and the second select gate electrode G3a. In the same way as in the first column, the contact cell array structure 10b, 11b, Gate electrode cut portions 15 and 16 are provided.

In this memory circuit region ER1, the second selection gate electrode G3b is arranged so as to be adjacent to the first selection gate electrode G3a, and the second selection gate electrode G2b and And the second selection gate electrode G3b is arranged in the opposite direction to the left and right.

The contact mounting structure 11b to which the contact C6b for applying the voltage to the second selection gate electrode G3b of the second row is connected is disposed in one gate contact cutting region ER12, The contact mounting structure 10b to which the contact C5b for applying the voltage to the tenth first select gate electrode G2b is connected is disposed in the other gate contact trench region ER13.

Also in the second selection gate electrode G3b, the memory gate electrode G1b and the first selection gate electrode G2b, the contact mounting structure 10b connected to one contact C5b and the first selection gate electrode G2b, The contact mounting structure 11b and the second selection gate electrode G3b connected to the other contact C6b are separated by the selective gate electrode cutout portions 15 and 16 to be electrically isolated, The first select gate electrode G2b and the second select gate electrode G3b are independently controllable.

Next, the peripheral circuit region ER2 adjacent to the memory circuit region ER1 having such a configuration will be described below. In the case of this embodiment, the peripheral circuit region ER2 is disposed at a position adjacent to the memory cell region ER11 in the memory circuit region ER1, but the present invention is not limited to this, The position adjacent to the contact / cutting region ER12, the position adjacent to the other gate contact / cutting region ER13, or the position adjacent to the memory cell region ER11 and between the gate contact / cutting region ER12, It may be installed at various positions outside.

In practice, a plurality of peripheral circuits 18 and 19 are formed in the peripheral circuit region ER2. The peripheral circuit 18 has an N-type MOS (Metal-Oxide-Semiconductor) transistor structure formed in, for example, a P-type logic well W2. In this case, a logic gate structure 7a is formed in the logic well W2, and a predetermined logic gate voltage can be applied to the logic gate structure 7a via the contact C8.

The logic well W2 is provided with impurity diffusion regions D4 and D5 in the region adjacent to the logic gate structure 7a with the logic gate structure 7a sandwiched therebetween. A contact C9 is provided upright in the diffusion region D4 and another contact C10 is set up in another impurity diffusion region D5.

On the other hand, the other peripheral circuit 19 has, for example, a P-type MOS transistor structure formed in the N-type logic well W3. In this case, a logic gate structure 7b is formed in the logic well W3, and a predetermined logic gate voltage can be applied to the logic gate structure 7b via the contact C12.

The logic well W3 is also provided with impurity diffusion regions D6 and D7 in the region adjacent to the logic gate structure 7b with the logic gate structure 7b sandwiched therebetween. A contact C13 is provided upright on the contact region D6 and another contact C14 is provided on the other impurity diffusion region D7.

(1-2) Cross-sectional configuration at each portion of the semiconductor device

Fig. 2 is a side cross-sectional view of the portion AA 'in Fig. 1, showing the memory cells 3a and 3b provided in the memory cell region ER11 and the side of the peripheral circuits 18 and 19 provided in the peripheral circuit region ER2 Sectional structure showing a cross-sectional configuration. In this case, the semiconductor device 1 is provided with the semiconductor substrate S, the memory well W1 is formed on the semiconductor substrate S of the memory circuit region ER1, the semiconductor well S of the peripheral circuit region ER2 is formed, Logic wells W2 and W3 are formed on the substrate S.

In this embodiment, two memory cells 3a and 3b are disposed in a portion AA 'of the memory well W1, and a contact C2 is formed on the surface of the substrate between the memory cells 3a and 3b A drain region D2 is formed. Although the memory cells 3a and 3b are formed symmetrically to the left and right, they have the same configuration, so that one memory cell 3a will be described here.

The memory cell 3a includes, for example, a memory gate structure 4a for forming an N-type transistor structure, a first select gate structure 5a for forming an N-type MOS transistor structure, A second select gate structure 6a forming a MOS transistor structure is formed in the memory well W1.

Actually, a source region D1 and a drain region D2 are formed at a predetermined distance on the surface of the memory well W1, and a source voltage from the source line is supplied through the contact C1 (FIG. 1) Is applied to the region D1 and a bit voltage from the bit line can be applied to the drain region D2 through the contact C2. In this embodiment, the impurity concentration of the source region D1 and the drain region D2 is selected to be 1.0E21 / cm3 or more, while the memory well W1 is doped with impurity ions The impurity concentration of the surface region (for example, a region from the surface to 50 [nm]) where the channel layer is formed is selected to be 1.0E19 / cm3 or less, preferably 3.0E18 / cm3 or less.

Through a memory gate structure (4a) comprises a source region (D1) and the drain region (D2) a lower gate insulating film (23a) made of an insulating member of SiO _2, etc. on the memory-well (W1) between, for example, silicon nitride ( Si ₃ N ₄ ), silicon oxynitride (SiON), alumina (Al ₂ O ₃ ), and the like. Further, on this charge storage layer EC, And the memory gate electrode G1a through the upper gate insulating film 23b. The memory gate structure 4a is structured such that the charge accumulation layer EC is insulated from the memory well W1 and the memory gate electrode G1a by the lower gate insulating film 23a and the upper gate insulating film 23b .

In the memory gate structure 4a, a sidewall spacer 27a made of an insulating material is formed along the sidewall, and the first select gate structure 5a is adjacent to the sidewall spacer 27a. The sidewall spacer 27a formed between the memory gate structure 4a and the first select gate structure 5a is formed to have a predetermined film thickness and includes a memory gate structure 4a, So that the structure 5a can be insulated.

The first select gate structure 5a is formed of an insulating member on the memory well W1 between the sidewall spacer 27a and the source region D1 and has a film thickness of 9 [ And a first selection gate electrode G2a to which a first selection gate line is connected is formed on the gate insulation film 25a.

On the other hand, on the other side wall of the memory gate structure 4a, a sidewall spacer 27a made of an insulating member is formed, and the second select gate structure 6a is adjacent through the sidewall spacer 27a. Such a memory gate structure 4a and a sidewall spacer 27a formed between the second select gate structure 6a are also formed on the sidewall spacer 27a between the memory gate structure 4a and the first select gate structure 5a, And is configured to insulate the memory gate structure 4a and the second select gate structure 6a from each other.

The second select gate structure 6a is formed on the memory well W1 between the sidewall spacer 27a and the drain region D2 by an insulating member and has a film thickness of 9 [ And the second selection gate electrode G3a to which the second selection gate line is connected is formed on the gate insulation film 25b.

Here, the first select gate electrode G2a and the second select gate electrode G3a formed along the sidewall of the memory gate electrode G1a through the sidewall spacer 27a are formed by etching back the conductive layer in the manufacturing process described later The top portion is formed in the shape of a sidewall that descends toward the memory well W1 as being separated from the memory gate electrode G1a.

A sidewall SW formed by an insulating member is formed on the sidewall of the first select gate structure 5a and the sidewall of the second select gate structure 6a, An extension region D1a is formed on the surface of the memory cell W1 and an extension region D2a is formed on the surface of the memory well W1 under another side wall SW.

In this embodiment, the memory well W1 between the first select gate electrode G2a and the second select gate electrode G3a is set to be 1E19 / cm < 3 > in the region from the surface to 50 [ Cm 3 or less, the film thicknesses of the gate insulating films 25a and 25b can be formed to 9 [nm] or less by a later manufacturing process. When the impurity concentration in the memory well W1 between the first select gate electrode G2a and the second select gate electrode G3a in the region from the surface to 50 [nm] is 3E18 / cm3 or less , The film thicknesses of the gate insulating films 25a and 25b can be set to 3 [nm] or less by a later manufacturing process.

In addition, the other memory cell 3b has the same configuration as that of one memory cell 3a, and the first select gate structure (the second memory cell 3b) is formed on the memory well W1 between the other source region D3 and the drain region D2 5b and a second select gate structure 6b and a memory gate structure 4b is formed between the first select gate structure 5b and the second select gate structure 6b through a sidewall spacer 27a . In the memory cell 3b as well, sidewalls SW are formed on the opposing sidewalls of the first select gate structure 5b, and on the surface of the memory well W1 under the sidewall SW, (D3a, D2b) are formed.

The memory well W1 formed in the memory circuit region ER1 and one logic well W2 formed in the peripheral circuit region ER2 are electrically separated by one device isolation layer 20, One logic well W2 formed in the circuit region ER2 and the other logic well W3 are electrically separated by the other device isolation layer 20. [ Here, in this embodiment, the peripheral circuit 18 having the N-type MOS transistor structure is formed in one logic well W2, and the other logic well W3 has the P-type MOS transistor structure A peripheral circuit 19 is formed.

A logic gate structure 7a in which a logic gate electrode G5 is formed through a gate insulating film 29a is provided between a pair of impurity diffusion regions D4 and D5 formed on the substrate surface, Respectively. Sidewalls SW are formed on the side walls of the logic gate structure 7a and extension regions D4a and D5a are formed on the surface of the substrate below each sidewall SW.

The other logic well W3 having a conductivity type different from that of the logic well W2 also has a configuration similar to that of the logic well W2 and has a pair of impurity diffusion regions D6, A logic gate structure 7b in which a logic gate electrode G6 is formed through a gate insulating film 29b is provided. Sidewalls SW are formed on the side walls of the logic gate structure 7b and extension regions D6a and D7a are formed on the surface of the substrate under each side wall SW.

The semiconductor device 1 also includes first select gate structures 5a and 5b, memory gate structures 4a and 4b, second select gate structures 6a and 6b, a contact C2, a logic gate structure 7a and 7b are covered by the interlayer insulating layer 21, and the respective portions are insulated from each other. In addition, for example, various other sub-surfaces such as the source regions D1 and D3 and the drain region D2 are covered with the silicide SC.

Here, FIG. 3 is a side cross-sectional view of the portion BB 'of FIG. 1 and shows a side sectional configuration of the selective gate electrode cutout portions 13 and 15 in the gate contact / cutout region ER12 of the memory circuit region ER1 Fig. As shown in Fig. 3, the selective gate electrode cutout portions 13 and 15 are formed on the element isolation layer 20 formed in the memory well W1.

For example, in a region where the selective gate electrode cutout 15 is formed, a sidewall-shaped second select gate electrode G3b is formed on one sidewall of the memory gate structure 4b through a sidewall spacer 27a However, the first select gate electrode G2b and the second select gate electrode G3b are not formed on the other side wall of the memory gate structure 4b, but only the insulating wall 27b formed of the sidewall spacer and the sidewall is formed .

In the case of this embodiment as well, the select gate electrode cut-off portion 13 on one memory gate structure 4a side is provided with a sidewall spacer 23a on one sidewall of the memory gate structure 4a through a sidewall spacer 27a. The first select gate electrode G2a and the second select gate electrode G3a are not formed on the other side walls of the memory gate structure 4a and the side wall spacers Only an insulating wall 27b made of sidewalls is formed. In the region where the selective gate electrode cutout portions 13 and 15 are formed, the surface of the substrate is partially cut in the manufacturing process, so that the recess 30 is formed on the surface of the device isolation layer 20. [

Next, the contact mounting structures 10a, 11a, 10b, and 11b having the characteristic constructions of the present invention will be described below. However, since these contact mounting structures 10a, 11a, 10b, and 11b all have the same configuration, Here, the contact mounting structure 10a will be described below. Fig. 4A is a side cross-sectional view of the CC 'portion of Fig. 1 and shows a side sectional configuration of one contact mounting structure 10a formed in the gate contact / cutting region ER12 of the memory circuit region ER1 Fig. 4 (b) is a cross-sectional view showing a side cross-sectional structure of the contact mounting structure 10a at a portion D-D 'orthogonal to the portion C-C' in Fig.

4A and 4B, the contact mounting structure 10a is formed on the surface of the substrate of the element isolation layer 20 formed in the memory well W1, The charge accumulation layer EC constituting the structure 4a, the upper gate insulating film 23b and the memory gate electrode (separate memory gate electrode) G8a formed of the same layer as the memory gate electrode G1a are sequentially stacked Lt; / RTI > On the other hand, the contact mounting structure 10a has the same charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G8a as the memory gate structure 4a, The quantum tunnel effect generated by the large voltage difference does not occur and the charge can not be injected into the charge storage layer EC.

In this embodiment, the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G8a constituting the contact mounting structure 10a are electrically connected to each other by the charge Since the storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G1a are formed of the same layer, each film thickness can be formed like the memory gate structure 4a.

In this case, as shown in Fig. 4A, a first selective gate electrode G2a having a sidewall shape is formed on the contact mounting structure 10a along the sidewall spacer 27c formed on the sidewall, A contact C5a is provided upright in a region from a part of the flat top of the memory gate electrode G8a to the surface of the substrate across one sidewall spacer 27c and the first select gate electrode G2a. In this case, since the contact C5a is partly erected on the top of the flat memory gate electrode G8a and is partially mounted on the substrate surface of the flat element isolation layer 20, .

The contact C5a is formed so as to extend over the first select gate electrode G2a between the memory gate electrode G8a of the contact mounting structure 10a and the element isolation layer 20, The contact C5a is always brought into contact with the surface of the first select gate electrode G2a even when alignment displacement occurs with respect to the first select gate electrode G2a when the contact C5a is formed by the photolithography process, . In this way, the contact mounting structure 10a is electrically connected to the first select gate electrode G2a, and its electrical resistance can be stabilized without being influenced by the photolithography process.

The contact mounting structure 10a is formed with the charge accumulation layer EC, the upper gate insulating film 23b, and the upper gate insulating film 23 which are the same as the memory gate structure 4a, The memory gate structure 4a is formed with a layer of the memory gate electrode G8a so that the memory gate structure 4a has substantially the same height as that of the memory gate structure 4a and further has a sidewall spacer shape formed along the sidewall spacer 27a of the sidewall of the memory gate structure 4a The first selection gate electrode G2a and the upper wiring layer (not shown) can be reliably connected by the contact C5a.

In this way, the distance between the surface of the substrate and the wiring layer of the upper layer can be selected based on the height of the memory gate structure 4a, and the contact mounting structure 10a can be mounted on the top of the memory gate electrode It is possible to reduce the thickness of the interlayer insulating layer 21 and to prevent the aspect ratio of the contact extending from the substrate surface to the upper wiring layer from becoming large.

4 (b), a side wall spacer 27a formed along the side wall of the end of the memory gate electrode G1a and a side wall spacer 27a formed along the side wall of the end of the contact mounting structure 10a The first selection gate electrode G2a is formed without a gap in the region GP1 in which the first selection gate electrode 27a and the second selection gate electrode 27c are disposed opposite to each other. As a result, the first select gate electrode G2a can be provided with the first select gate electrode G2a continuously from the contact mounting structure 10a to the memory gate electrode G1a.

Thus, when the first select gate voltage is applied from the contact mounting structure 10a to the contact C5a extending from the side wall spacer 27c and the first select gate electrode G2a, the memory gate electrode G1a, The first select gate voltage may be applied to the adjacent first sidewall-shaped first select gate electrode G2a through the spacer 27a.

In this embodiment, in the region GP1 in which the sidewall spacer 27a of the sidewall of the memory gate electrode G1a is opposed to the sidewall spacer 27c of the sidewall of the contact mounting structure 10a, The first selection gate electrode G2a is formed by etch-back of the conductive layer in the vicinity of the center of the sidewall spacers 27a and 27c that are most distant from the opposed sidewall spacers 27a and 27c , The thickness of the first select gate electrode G2a may be the thinnest.

Therefore, in the region GP1 in which the sidewall spacers 27a of the memory gate electrode G1a and the sidewall spacers 27c of the contact mounting structure 10a are opposed to each other, the sidewall spacers 27a, The top surface of the first select gate electrode G2a is gradually inclined toward the substrate surface and can be formed concave in a " " -shaped shape as it approaches the center between the first and second gate electrodes 27a and 27c. In addition, silicide SC is formed on each surface of the memory gate electrode G1a, the contact mounting structure 10a, the first select gate electrode G2a, and the like.

Here, as shown in Figs. 1 and 4 (b), the semiconductor device 1 has a structure in which the sidewall spacer 27a on the side wall of the memory gate electrode G1a and the side wall spacer 27a of the contact mounting structure 10a The distance Dp between the side wall of the memory gate electrode G1a and the side wall of the contact mounting structure 10a in the region GP1 in which the side wall spacer 27c of the side wall is correspondingly arranged is Dp, The thickness of the select gate electrode G2a from the sidewall spacer 27c formed on the sidewall of the memory gate electrode G1a to the sidewall SW is denoted by Dsw as shown in Fig. The relationship of Dp < (2 x Dsp) + (2 x Dsw), where Dsp represents the thickness of the sidewall spacer 27c between the memory gate electrode G8a and the first select gate electrode G2a of the structure 10a, The memory gate electrodes G1a and G1b, the contact mounting structures 10a, 11a, 10b and 11b, the side wall spacers 27a and 27c, This byte electrode (G2a, G2b), and a second selection gate electrode (G3a, G3b) are formed.

In the semiconductor device 1, by satisfying this formula, the side wall spacers 27a on the side walls of the memory gate electrode G1a (G1b) and the contact mounting structures 10a, 11a The first select gate electrode G2a (G2b) and the second select gate electrode G3a (G3b) are formed in the region GP1 between the side wall spacers 27c of the sidewalls of the gate electrodes 10a and 10b .

In this embodiment, the case where the memory gate electrode G1a and the contact mounting structure 10a are arranged on the same straight line has been described. However, the present invention is not limited to this, and the memory gate electrode G1a In the region GP1 between the side wall spacer 27a on the sidewall of the contact mounting structure 10a and the sidewall spacer 27c on the side wall of the contact mounting structure 10a opposed to the sidewall spacer 27a, May be arranged in various other arrangements as long as they can be formed without gaps.

For example, the memory gate electrode G1a and the contact mounting structure 10a are opposed to each other, but the center line of the memory gate electrode G1a is shifted from the center line of the contact mounting structure 10a, (G1a) and the contact mounting structure 10a are not in the same straight line.

Although the width of the memory gate electrode G1a and the width of the contact mounting structure 10a are the same, the present invention is not limited to this, and the width of the contact mounting structure 10a may be different from the width of the memory gate electrode G1a And may be larger. Further, the contact mounting structure 10a is formed in a rod shape in a planar layout, but the present invention is not limited to this. For example, even if the contact mounting structure 10a is formed in various other outer shapes such as an L shape or a J shape do.

(1-3) On the operation principle of injecting charge into the charge storage layer in the write-selected memory cell

Next, in the semiconductor device 1 of the present invention, for example, when charge is injected into the charge storage layer EC of the memory cell 3a and data is written in the memory cell 3a, I will explain briefly. In this case, as shown in Fig. 2, a memory cell (called a 'write-selected memory cell') 3a for injecting a charge into the charge storage layer EC is connected to a contact C4a A charge accumulation gate voltage of 12 [V] is applied to the memory gate electrode G1a of the memory gate structure 4a through the gate electrode G1a (FIG. 1) A channel layer (not shown) may be formed along the surface.

At this time, a gate-off voltage of 0 [V] is applied to the first select gate electrode 5a from the first select gate line (not shown) through the contact C5a (Fig. 1) to the first select gate electrode G2a And a source-off voltage of 0 [V] can be applied to the source region D1. The first select gate structure 5a is formed such that the channel layer is not formed on the surface of the memory well W1 opposite to the first select gate electrode G2a and the source region D1 and the memory gate structure 4a are formed, It is possible to prevent electrical connection with the channel layer of the memory gate structure 4a from the source region D1 and prevent voltage application to the channel layer of the memory gate structure 4a from the source region D1.

On the other hand, the second select gate structure 6a is provided with a second select gate (not shown) of 1.5 [V] from the second select gate line (not shown) to the second select gate electrode G3a through the contact C6a A voltage is applied, and a charge accumulation bit voltage of 0 [V] can be applied to the drain region D2. As a result, the second select gate structure 6a has a channel layer formed in the memory well W1 opposed to the second select gate electrode G2a to be in a conductive state, and the drain region D2 and the memory gate structure 4a are electrically connected to each other so that the channel layer of the memory gate structure 4a can be 0 [V], which is the charge accumulation bit voltage. At this time, a substrate voltage of 0 [V] equal to the charge accumulation bit voltage can be applied to the memory well W1.

Thus, in the memory gate structure 4a, 12 [V] is applied to the memory gate electrode G1a and the channel layer because the memory gate electrode G1a is 12 [V] and the channel layer becomes 0 [V] And a charge can be injected into the charge storage layer EC due to the quantum tunnel effect generated thereby, so that the data can be written.

(1-4) In a write unselected memory cell in which a charge accumulation gate voltage of a high voltage is applied to a memory gate electrode, an operation principle in which no charge is injected into the charge accumulation layer

In the semiconductor device 1 manufactured by the manufacturing method of the present invention, for example, when charge is not injected into the charge storage layer EC of the memory cell 3a, A voltage is applied to the memory gate electrode G1a to block the electrical connection between the source region D1 and the channel layer of the memory gate structure 4a by the first select gate structure 5a, The electrical connection between the drain region D2 and the channel layer of the memory gate structure 4a is cut off by the gate structure 6a to prevent the charge injection to the charge storage layer EC of the memory gate structure 4a .

Actually, the memory gate structure 4a of the memory cell (also referred to as a "write non-selected memory cell") 3a in which charge is not injected into the charge storage layer EC is provided with 12 The charge accumulation gate voltage is applied to the memory well W1 and the channel layer is formed along the surface of the memory well W1 facing the memory gate electrode G1a .

A gate-off voltage of 0 [V] is applied from the first select gate line (not shown) to the first select gate electrode G2a through the contact C5a (FIG. 1) in the first select gate structure 5a , A source-off voltage of 0 [V] may be applied to the source region D1. This causes the first select gate structure 5a of the memory cell 3a to become non-conductive in the memory well W1 opposed to the first select gate electrode G2a, The electrical connection with the channel layer of the structure 4a can be blocked.

In addition, in the second select gate structure 6a, a first select gate electrode (not shown) is formed in the second select gate structure 6a through a contact C6a (FIG. 1) A second select gate voltage may be applied, and a turn-off voltage of 1.5 [V] may be applied to the drain region D2. As a result, the second select gate structure 6a is formed such that the memory well W1 opposed to the second select gate electrode G3a is in a non-conductive state to form the drain region D2 and the memory gate structure 4a, It is possible to cut off the electrical connection with the channel layer.

As described above, in the memory gate structure 4a of the memory cell 3a, the memory well W1 is made to be in a non-conductive state under the first select gate structure 5a and the second select gate structure 6a on both sides The channel layer formed on the surface of the memory well W1 by the memory gate electrode G1a is in a state in which the electrical connection from the drain region D2 and the source region D1 is cut off, A depletion layer may be formed.

Hereinafter, the memory gate structure 4a will be referred to as a capacitor having a three-layer structure of the upper gate insulating film 23b, the charge storage layer EC and the lower gate insulating film 23a ) C2 and a capacitance of a depletion layer formed in the memory well W1 and surrounding the channel layer (hereinafter, referred to as a depletion layer capacitance) C1 can be regarded as a series-connected configuration , For example, assuming that the gate insulating film capacitance C2 is three times the capacitance of the depletion layer capacitance C1, the channel potential Vch of the channel layer becomes 9 [V] from the following expression.

&Quot; (1) &quot;

Thus, even if a charge accumulation gate voltage of 12 [V] is applied to the memory gate electrode G1a in the memory gate structure 4a, the channel potential Vch of the channel layer surrounded by the depletion layer in the memory well W1 becomes 9 [V], the voltage difference between the memory gate electrode G1a and the channel layer becomes 3 [V]. As a result, the quantum tunnel effect does not occur and the charge injection to the charge storage layer EC . &Lt; / RTI &gt;

In addition to this, in this memory cell 3a, the memory well W1 between the memory gate structure 4a and the first select gate structure 5a, the memory gate W1 between the memory gate structure 4a and the second select gate structure 5a, A depletion layer having a high impurity concentration is not formed in the region of the memory well W1 between the memory well W1 and the memory well W1. Therefore, a depletion layer can be reliably formed around the channel layer formed around the surface of the memory well W1 The depletion layer can prevent the channel potential Vch from reaching the gate insulating films 25a and 25b of the first select gate structure 5a and the second select gate structure 6a from the channel layer .

Thereby, in the memory cell 3a, the first select gate structure 5a and the second select gate structure (second select gate structure) are formed in accordance with the bit voltage of the low voltage of the drain region D2 or the source voltage of the low voltage of the source region D1 The depletion layer can prevent the channel potential Vch of the channel layer from reaching the gate insulating films 25a and 25b even if the respective thicknesses of the gate insulating films 25a and 25b of the channel layers 6a and 6a are made thin. Insulation breakdown of the gate insulating films 25a and 25b due to the channel potential Vch can be prevented.

(2) Method of manufacturing semiconductor device

The semiconductor device 1 having the above-described structure can be manufactured by forming the contact mounting structures 10a, 11a, 10b, and 11b, the first select gate electrodes G2a and G2b independently controllable, The second select gate electrodes G3a and G3b can be manufactured by using a small photomask process. Fig. 5 shows a side cross-sectional configuration taken along the line A-A 'in Fig. 5 (a), after the semiconductor substrate S is prepared, the element isolation layer 20 made of an insulating member is formed by a STI (Shallow Trench Isolation) method or the like, Is formed at a predetermined position such as a boundary between the circuit region ER1 and the peripheral circuit region ER2.

Subsequently, a sacrificial oxide film 30a is formed on the surface of the semiconductor substrate S by thermal oxidation or the like in order to implant the impurity, and then the peripheral circuit region ER2 is doped with a P-type impurity Or N-type impurity is implanted to form P-type logic well W2 and N-type logic well W3.

Subsequently, a resist is patterned by using a photolithography technique and an etching technique using a first photomask (not shown) dedicated to fabrication of the memory circuit region ER1, and the resist is patterned in the same manner as in FIG. 5 (a) The resist Rm1 is formed by exposing the memory circuit region ER1 and covering the peripheral circuit region ER2, as shown in Fig. 5 (b).

Subsequently, the P-type impurity is implanted only into the memory circuit region ER1 by the patterned resist Rm1 to form the memory well W1. N-type impurity is implanted into the surface of the memory circuit region ER1 and a channel forming layer (not shown) is formed on the surface of the substrate facing the memory gate electrodes G1a and G1b and the sidewall spacers 27a (Fig. 2) The sacrifice oxide film 30a of the memory circuit region ER1 is removed by hydrofluoric acid or the like using the resist Rm1 as it is (first photomask processing step).

When the P-type substrate is used as the semiconductor substrate S in the first photomask processing step, the step of implanting the P-type impurity into the semiconductor substrate S to form the memory well W1 is omitted can do.

After removing the resist Rm1, the resistances Rm1 and Rm2 of the memory circuit region ER1 and the peripheral circuit region ER2 are removed as shown in Fig. 5 (c) An ONO film in which a layered bottom gate insulating film 23a, a charge storage layer EC and an upper gate insulating film 23b are stacked in this order is formed on the entire surface, and then an ONO film is formed on the memory gate electrodes G1a and G1b Is formed on the upper gate insulating film 23b. Subsequently, a protective insulating film 30b made of an insulating material is formed on the conductive layer 35 for a memory gate electrode by a thermal oxidation method, a CVD (Chemical Vapor Deposition) method or the like.

Subsequently, a second photomask (not shown) dedicated to fabrication of the memory circuit region ER1 is used, and the resist is patterned by using a photolithography technique and an etching technique, and the resist is patterned in the same manner as in FIG. 5C The resist Rm2 is formed only at a position where the memory gate structures 4a and 4b are to be formed and at a position where the contact mounting structures 10a, 11a, 10b and 11b are to be formed, as shown in Fig. And the conductive layer 35 for the memory gate electrode is patterned by using the resist Rm2 to form the memory gate electrodes G1a and G1b and the memory gate electrodes G1a and G1b, Thereby forming the electrodes G8a, G9a, G8b, and G9b (second photomask processing step).

In the case of this embodiment, the conductive layer 35 for the memory gate electrode is formed by the resist Rm2 on the side of the memory gate electrode G1a (G1b) and the memory gate electrode G1a (G1b) The memory gate electrodes G8a and G9a (G8b and G9b) may be patterned so as to be arranged on the same straight line.

7, the side walls of the memory gate electrodes G1a (G1b) formed using the resist Rm2 and the side walls of the memory gate electrodes G8a, G9a (G8b, G9b) An interelectrode region GP2 disposed opposite to each other with a predetermined distance therebetween can be formed.

Subsequently, after the resist Rm2 is removed, the memory gate electrodes G1a and G1b and the memory gates G1a and G1b as shown in Fig. 6B, which are denoted by the same reference numerals as those in Fig. 6A, The upper gate insulating film 23b and the charge storage layer EC exposed in the positions other than the forming positions of the electrodes G8a, G9a, G8b and G9b are sequentially removed (ON film is removed), and the patterned memory gate electrode The upper gate insulating film 23b and the charge storage layer EC are formed so as to be aligned with the memory gate electrodes G8a, G9a, G8b and G9b of the small pieces.

Thereby, a memory gate structure is formed in the memory circuit region ER1 in the order of the lower gate insulating film 23a, the charge storage layer EC, the upper gate insulating film 23b, and the memory gate electrode G1a (G1b) The charge accumulation layer EC such as the memory gate structure 4a (4b) is formed on the device isolation layer 20 in the gate contact / cut regions ER12 and ER13. , The upper gate insulating film 23b and the memory gate electrode G1a (G1b) are stacked in this order (contact structure forming step).

Subsequently, a protective insulating film 30c is formed on the entire surface of the memory circuit region ER1 and the peripheral circuit region ER2, as shown in Fig. 6C, which is the same as the portion corresponding to Fig. 6B, . In this embodiment, a case is described in which one protective insulating film 30c is formed on the entire surface. However, the present invention is not limited to this. For example, an insulating film of an oxide film system, Layer protective insulating film may be formed on the entire surface in this order.

The protective insulating film 30c formed here becomes the sidewall spacers 27a and 27c formed later on the side walls of the memory gate structure 4a (4b) and the contact mounting structures 10a and 11a (10a and 11b) Of the side wall spacer 27c between the memory gate electrode G8a of the contact mounting structure 10a and the first selection gate electrode G2a in the above-described equation, Dp <(2 × Dsp) + (2 × Dsw) Corresponds to Dsp representing the thickness. Therefore, the protective insulating film 30c can be formed so as to satisfy the above-described formula, Dp < (2 x Dsp) + (2 x Dsw).

Subsequently, the protective insulating film 30c is etched back so as to cover the periphery of the memory gate structures 4a and 4b as shown in Fig. 8 (a), in which parts corresponding to those in Fig. 6 (c) The side wall spacers 27a are formed and side wall spacers 27c covering the periphery of the contact mounting structures 10a, 11a, 10b, and 11b (not shown) are formed. Subsequently, a third photomask (not shown) dedicated to fabrication of the memory circuit region ER1 is used, and the resist is patterned by using the photolithography technique and the etching technique. The resist is patterned in the same manner as in FIG. 8A The resist Rm3 is formed so as to cover the entire surface of the peripheral circuit region ER2 and to expose the memory circuit region ER1, as shown in Fig. 8 (b).

Subsequently, by using the resist Rm3, a predetermined formation position of the first select gate structures 5a and 5b (FIG. 2) and a predetermined formation position of the second select gate structures 6a and 6b (FIG. 2) The channel formation layer (not shown) is formed on the surface of the substrate opposite to the first select gate electrodes G2a and G2b and the second select gate electrodes G3a and G3b to be formed later (Third photomask processing step).

Subsequently, after the resist Rm3 is removed, the sacrificial oxide film 30a of the peripheral circuit region ER2 is removed by hydrofluoric acid or the like. the first select gate electrodes G2a and G2b (Fig. 1) and the second select gate electrodes G3a and G3b (Fig. 1) of the memory circuit region ER1 are to be formed The gate insulating films 25a and 25b are formed and the gate insulating films 29a and 29b are formed in the positions where the logic gate electrodes G5 and G6 (FIG. 1) of the peripheral circuit region ER2 are to be formed .

Subsequently, the memory circuit region ER1 and the peripheral circuit region ER2 are subjected to a first selection (hereinafter referred to as &quot; first selection &quot;) by later processing, as shown in Fig. 9A, For example, an N-type conductive layer 37 made of the gate electrodes G2a and G2b, the second selection gate electrodes G3a and G3b and the one logic gate electrode G5 is formed into a layer shape, A P-type reverse-conduction layer 38 which becomes a different logic gate electrode G6 in the peripheral circuit region ER2 is formed in a layer shape.

Subsequently, a fourth photomask (not shown) dedicated to fabrication of the memory circuit region ER1 is used, the resist is patterned by photolithography and etching, and the resist is used to form the memory circuit region ER1, (The fourth photomask processing step (photomask processing step for forming the selective gate electrode)). The memory circuit region ER1 is formed so as to cover the entire surface of the peripheral circuit region ER2 with the resist Rm4 as shown in Figure 9B with the same reference numerals attached to the portions corresponding to Figure 9 (a) The conductive layer 37 (FIG. 9 (a)) is exposed. As a result, in the peripheral circuit region ER2, the conductive layer 37 and the reverse conductive layer 38 covered with the resist Rm4 remain intact. On the other hand, in the memory circuit region ER1, since the exposed conductive layer 37 is etched back, the side wall spacers 27a of the side walls of the memory gate structures 4a and 4b and the contact mounting structures 10a, 11a, Side gate-shaped select gate electrodes Ga and Gb are formed along the sidewall spacers 27c of the sidewalls of the gate electrodes 10a and 10b and 11b.

10 is a plan view of the memory gate structure 4a and 4b and the contact mounting structures 10a, 11a, and 11b for the plan layout of the memory circuit area ER1 in the semiconductor device 1 at completion, 10b, and 11b are overlapped with the sidewall-shaped select gate electrodes Ga and Gb formed along the periphery of the gate electrodes Ga and Gb.

10, the select gate electrode Ga in the non-division state is divided into a region around the memory gate electrode G1a and a contact assembly structure 10a The side wall spacers 27a on the side walls of the memory gate electrode G1a and the side wall spacers 27c on the side walls of the contact mounting structures 10a and 11a are integrally formed, Can be formed in the opposed region GP1 without gaps.

In this embodiment, since the memory gate electrode G1a is formed in a linear shape, the select gate electrode Ga in the non-division state surrounds the periphery of the memory gate electrode G1a extending in one direction And a short quadrangular area surrounding the periphery of the contact mounting structures 10a and 11a so as to surround the periphery of the contact mounting structures 10a and 11a.

Here, the conductive layer 37 formed in the memory circuit region ER1 and the selection gate electrodes Ga and Gb formed by etching back the conductive layer 37 satisfy the above-described formula, Dp < (2 x Dsp ) + (2 x Dsw), the thickness of the conductive layer 37 and the etch-back condition of the conductive layer 37 can be set.

10, which shows the side cross-sectional configuration of the portion DD 'in FIG. 10, the side wall spacer 27a on the side wall of the memory gate electrode G1a and the side wall spacer 27a on the side wall of the memory gate electrode G1a, The conductive layer 37 remains in the area GP1 where the sidewall spacer 27c of the sidewall of the structure 10a is opposed to the conductive layer 37 even after etch-back of the conductive layer 37. As a result, The selective gate electrode Ga can be formed from the side wall spacers 27a of the side walls of the contact mounting structure 10a to the side wall spacers 27c of the side walls of the contact mounting structure 10a.

The selection gate electrode Ga formed between the sidewall spacer 27a on the sidewall of the memory gate electrode G1a and the sidewall spacer 27c on the sidewall of the contact mounting structure 10a is electrically connected to the conductive layer 37, The film thickness is formed to be the thinnest near the center between the sidewall spacers 27a and 27c that are most distant from the opposing sidewall spacers 27a and 27c and the sidewall spacers 27a and 27c Quot; &quot; -shaped shape in the vicinity of the center between the upper surface of the substrate and the upper surface of the substrate.

At this time, as shown in FIG. 9 (b), the N-type impurity at a low concentration is implanted into the memory circuit region ER1 not covered with the resist Rm4 by the ion implantation method or the like, An extension region ETa is formed on the surface of the memory well W1, and then the resist Rm4 can be removed.

Subsequently, in the case of this embodiment, the resist is patterned using a photolithography technique and an etching technique by using a photomask (not shown), and the conductive layer 37 of the peripheral circuit region ER2 is formed by using the resist, And the reverse conductive layer 38 are patterned to form the logic gate electrodes G5 and G6 on the gate insulating films 29a and 29b. At this time, the resist used for forming the logic gate electrodes G5 and G6 is directly used , And at the same time, part of the select gate electrodes (Ga, Gb) of the memory circuit region (ER1) can also be removed.

In this embodiment, the logic gate structures 7a and 7b are to be formed in the peripheral circuit region ER2 as shown in Fig. 12 (a) with the same reference numerals attached to the corresponding portions in Fig. 9 The resist Rr1a formed in conformity with the outer shape of the logic gate structures 7a and 7b to be formed later can be disposed. As a result, in the peripheral circuit region ER2, the conductive layer 37 and the reverse conductive layer 38 exposed to the outside are removed, and only the conductive layer 37 and the reverse conductive layer 38 covered with the resist Rr1a Can remain. In this way, the logic gate electrodes G5 and G6 are formed in the peripheral circuit region ER2 in conformity with the outer shape of the resist Rr1a and the logic gate electrodes G5 and G6 are formed on the gate insulating films 29a and 29b, The logic gate structures 7a and 7b may be formed.

At this time, in the memory circuit region ER1, almost the entire surface is covered with the resist Rr1b, but only the selective gate electrode cut portion 13, 14, 15, 16 13, 14, 15, and 16, an opening is formed in the resist Rr1b.

10 shows the to-be-formed positions Pf1, Pf2, Pf3, and Pf4 where the select gate electrodes Ga and Gb are partially removed to form the select gate electrode cutouts 13, 14, 15 and 16 have. Pf3 and Pf4 are formed in the resist Rr1b disposed in the memory circuit region ER1 and the select gate electrodes Ga and Srb exposed from the openings of the resist Rr1b are formed in the predetermined positions Pf1, The selection gate electrode cutout portions 13, 14, 15, 16 for dividing the selection gate electrodes Ga, Gb can be formed in conformity with the outer shape of the opening of the resist Rr1b by removing the conductive layer of the resist Rr1b.

For example, FIG. 12 (b) shows a side cross-sectional configuration when the selection gate electrode cutout portions 13 and 15 are formed in the portion B-B 'in FIG. The exposed select gate electrodes Ga and Gb are removed at the openings H1 and H3 of the resist Rr1b and the openings H1 and H3 of the resist Rr1b are removed as shown in Fig. The selection gate electrode cutout portions 13 and 15 can be formed.

At this time, in addition to the selection gate electrode Gb, the sidewall spacers 27a and the gate insulating film 29b are also exposed to the openings H1 and H3 of the resist Rr1b. Therefore, at this time, the sidewall spacers 27a and the gate insulating film 25a, which are exposed from the openings H1 and H3 of the resist Rr1b, can be partially removed. This eliminates the sidewall spacers 27a in the regions exposed from the openings H1 and H3 so that the defective portions 40 are formed in the vicinity of the top of the sidewall spacers 27a and that not only the gate insulating film 25a, A part of the surface of the element isolation layer 20 is also removed, so that the recess 30 can be formed in the element isolation layer 20.

In this manner, in the memory circuit region ER1, the selected gate electrode Ga (Gb) is divided by removing the selected gate electrode Ga (Gb) at a plurality of portions of the selected gate electrode Ga (Gb) . In this way, one sidewall sidewall spacer 27a of the memory gate electrode G1a (G1b), which surrounds one contact mounting structure 10a (10b) from the integral select gate electrode Ga (Gb) G2a (G2b)] formed in the shape of a sidewall and other contact mounting structures 11a (11b), and the sidewall spacers 27a (G1a) of the other side walls of the memory gate electrode G1a The second selection gate electrode G3a (G3b) formed in a sidewall shape can be provided.

Thereafter, the resist (Rr1a, Rr1b) is removed by, for example, ashing or the like, and a resist pattern patterned for N-type or P-type is used to implant a low-concentration N-type impurity or P 12 (a) (the resist (Rr1a, Rr1b) to be removed in this step is shown as it is in Figure 12 (a)), An N-type extension region ETa is formed on the substrate surface of one logic well W2 and a P-type extension region ETb is formed on the substrate surface of another logic well W3 which is also exposed to the outside May be formed.

Subsequently, after the resist is removed, a step of forming the sidewall SW, or a step of implanting N-type impurity or P-type impurity at a high concentration into a necessary portion by ion implantation or the like to form source regions D1 and D3 and 3b, 3c, 3d, 3e, and 3f and the contact mounting structures 10a, 11a, 10b, and 10c after the step of forming the drain region D2, the step of forming the silicide SC, 11b, and the peripheral circuits 18, 19 are formed.

Subsequently, the first select gate electrode G2a (G2b) extends from the top of one contact mounting structure 10a (10b) to the substrate surface, and a contact hole is formed in the interlayer insulating layer 21. [ In addition, contact holes are formed in the interlayer insulating layer 21 from the top of the other contact mounting structure 11a (11b) to the substrate surface across the second select gate electrode G3a (G3b). At this time, contact holes are also formed in the interlayer insulating layer 21 at other necessary positions.

Subsequently, conductive members are injected into the respective contact holes to form columnar contacts (C1, C2, C3, ...) in the respective contact holes. At this time, when one of the contact installation structures 10a, 11a, 11b, and 11b is considered, for example, the contact installation structure 10a contacts the first select gate electrode G2a from the flat top portion A contact C5a having a rectangular cross section provided standing up from the surface of the substrate can be formed. The semiconductor device 1 having the structure shown in Figs. 1, 2, 3, and 4 can be manufactured by sequentially performing each of these processes.

(3) Action and effect

In the semiconductor device 1, the same charge storage layer EC, upper gate insulating film 23b, and memory gate electrodes G8a and G9a (G8b and G9b) as the memory gate structure 4a (4b) (10a, 11a (10b, 11b)) which are stacked in this order and are electrically separated from the memory gate structure 4a (4b). In the semiconductor device 1, the first select gate electrode G2a (10b, 11b), which is continuously provided from the memory gate structure 4a (4b) to one contact mounting structure 10a G2b) and the second selection gate electrode G3a (G3b).

In the semiconductor device 1, the portion from the top of one contact mounting structure 10a (10b) to the surface of the substrate across the sidewall spacer 27c and the first select gate electrode G2a (G2b) The area from the top of one contact [C5a (C5b)] provided and the other contact mounting structure 11a (11b) to the surface of the substrate across the sidewall spacer 27c and the second select gate electrode G3a (G3b) (C5a) connected to the first selection gate electrode G2a (G2b) and one wiring layer of the upper layer, and the other contact C5a (C5b) And the second selection gate electrode G3a (G3b) is connected to another wiring layer in the upper layer by another contact [C6a (C6b)].

Therefore, in the semiconductor device 1, for example, a contact mounting structure 10a made of a layer of the same charge accumulation layer EC, the upper gate insulating film 23b and the memory gate electrode G8a as the memory gate structure 4a, Since the contact C5a is provided so as to extend from the flat top of the memory gate structure G1 to the first select gate electrode G2a and thus the portion 102b which rises up to the top of the memory gate structure 110 is not present 13), the distance to the wiring layer in the upper layer can be shortened, and the aspect ratio of the contacts C2 and the like can be reduced. Thus, it is possible to prevent the increase of the contact resistance value. In the semiconductor device 1, the contact mounting structure 10a and the wiring layer in the upper layer may be separated from each other because there is no raised portion 102b that rises up to the top of the memory gate structure 110, , It is possible to prevent defective contact with the upper wiring layer.

In the method of manufacturing the semiconductor device 1 according to the present invention, in the memory circuit region ER1, the layered memory gate electrode conductive layer 35, the layered upper gate insulating film 23b, The charge storage layer EC in the shape of a memory gate structure G is composed of a memory gate electrode G1a, an upper gate insulating film 23b, a charge storage layer EC, and a lower gate insulating film 23a. 4a and 4b and the contact mounting structures 10a, 11a, and 11b electrically connected to the memory gate structures 4a and 4b are formed by using the same layer as the memory gate structures 4a and 4b, 10b and 11b are formed (Fig. 6 (a) and Fig. 7).

In the manufacturing method of the semiconductor device 1, the memory circuit regions ER1 (ER1) and ER2 (2) in which the memory gate structures 4a and 4b covered with the side wall spacers 27a and 27c and the contact mounting structures 10a and 11a, The gate insulating films 25a, 25b, 25c, 29a, and 29b are formed after the gate insulating films 25a, 25b, 25c, 29a, 29b are formed in the peripheral circuit region ER2 The conductive layer 37 and the reversed conductive layer 38 of the peripheral circuit region ER2 are left intact as they are as shown in Fig. And the conductive layer 37 of the memory circuit region ER1 is etched back.

Thus, in the method of manufacturing the semiconductor device 1, the memory gate structures 4a and 4b and the contact mounting structures 10a, 11a, 10b, and 11b are continuously provided to reach the periphery and the side wall spacers 27a and 27c The select gate electrodes Ga and Gb formed in the sidewall shape can be formed (Fig. 9 (b), Fig. 10 and Fig. 11).

In addition to this, in the manufacturing method of the semiconductor device 1, the conductive layer 37 and the reverse conductive layer 38 of the peripheral circuit region ER2 are patterned by using the resist Rr1a patterned by the photomask The logic gate electrodes G5 and G6 are formed on the gate insulating films 29a and 29b and the resist Rr1a and Rr1b used to form the logic gate electrodes G5 and G6 are used as they are to form the memory circuit region A part of the select gate electrodes Ga and Gb of the select gate electrodes Ga and Gb is also removed and the select gate electrodes Ga and Gb are divided.

Thereby, in the manufacturing method of the semiconductor device 1, the first selection gate electrode G2a (G2b) surrounding the periphery of one contact installation structure 10a (10b) and the first selection gate electrode G2a The second selection gate electrode G3a (G3b) which is electrically separated from the other contact mounting structure 11a (11b) and which surrounds the other contact mounting structure 11a (11b) can be formed (Figs. 12 and 13).

In this way, in the manufacturing method of the semiconductor device 1, at the time of the photomask process for forming the logic gate electrodes G5 and G6 of the peripheral circuit region ER2, the selection gate electrode Ga of the memory circuit region ER1 And Gb are also divided so as to form the first select gate electrodes G2a and G2b and the second select gate electrodes G3a and G3b which are disposed to face each other along the memory gate electrodes G1a and G1b .

In the manufacturing method of the semiconductor device 1, the interlayer insulating layer 21 is formed so as to cover the memory cells 3a, 3b, 3c, 3d, 3e, 3f, the contact mounting structures 10a, 11a, 10b, The contact holes are drilled through the first select gate electrodes G2a and G2b or the second select gate electrodes G3a and G3b from the top of the contact mounting structures 10a, 11a, 10b and 11b And the conductive member is filled in the contact hole.

As a result, in the present invention, the contacts extending from the tops of the contact mounting structures 10a, 11a, 10b, and 11b through either the first select gate structures 5a and 5b or the second select gate structures 6a and 6b The wiring layers in the upper layers of the memory gate structures 4a and 4b and the wiring layers in the upper portion of the memory gate structures 4a and 4b and the first selection gate electrodes (C5a, C5b, C6a, and C6b) can be formed by the contacts C5a, G2a, and G2b, or the second select gate electrodes G3a and G3b.

(4) Manufacturing method according to another embodiment in which the third photomask processing step is omitted

In the embodiment described above, when a dedicated photomask process for patterning a resist with a dedicated photomask used exclusively for processing the memory circuit region ER1 is taken into consideration, the first photomask processing step, the second photomask processing step, The third photomask processing step, and the fourth photomask processing step for forming the selective gate electrode (the photomask processing step for forming the selective gate electrode). However, the present invention is not limited to this, A total of three photomask processing steps corresponding to the first photomask processing step, the second photomask processing step, and the selective gate electrode forming photomask processing step (corresponding to the fourth photomask processing step) are performed without impurity implantation in the photomask processing step Process.

That is, the threshold voltage Vth of the first select gate structures 5a and 5b and the second select gate structures 6a and 6b, which are finally formed, Value, it is not necessary to perform the third photomask processing step, and the third photomask processing step can be omitted.

Actually, in the manufacturing method in which such a third photomask processing step is omitted, as shown in FIG. 8A, the peripheral portions of the memory gate structures 4a and 4b (FIG. 6B) The sacrificial oxide film 30a of the peripheral circuit region ER2 is removed by hydrofluoric acid or the like after forming the sidewall spacer 27a (the sidewall spacer forming step) The gate insulating films 25a and 25b (see FIG. 1) are formed at the positions where the first select gate electrodes G2a and G2b (FIG. 1) and the second select gate electrodes G3a and G3b And the gate insulating films 29a and 29b are also formed at the positions where the logic gate electrodes G5 and G6 (FIG. 1) of the peripheral circuit region ER2 are to be formed. Thereafter, the semiconductor integrated circuit device 1 shown in Fig. 1 can be manufactured through the manufacturing steps shown in Figs. 9 to 12 similarly to the manufacturing method of the above-described embodiment.

In this embodiment, in which the third photomask processing step is omitted, the memory gate electrodes G1a and G1b are sandwiched by simply adding three photomask manufacturing processes to a general peripheral circuit manufacturing process The first select gate electrodes G2a and G2b and the second select gate electrodes G3a and G3b are arranged so that the first select gate electrodes G2a and G2b and the second select gate electrodes G3a and G3b are independent The memory cells 3a, 3b, 3c, 3d, 3e and 3f which can be controlled can be incorporated. Therefore, in the manufacturing method in which the third photomask processing step is omitted, the cost can be reduced by reducing the photomask as compared with the manufacturing method according to the above-described embodiment.

(5) Another embodiment

The present invention is not limited to the present embodiment, but various modifications can be made within the scope of the present invention. For example, the number of memory cells 3a, 3b, 3c, 3d, 3e, The numbers of the peripheral circuits 18 and 19, the number of the contact mounting structures 10a, 11a, 10b and 11b and the number of the selective gate electrode cutouts 13, 14, 15 and 16 may be various numbers, The conduction type of the well W1 or the logic well W2 or W3 may be either N-type or P-type. Further, three or more contact mounting structures 10a, 11a, ... may be provided, or three or more selection gate electrode cut portions may be provided.

In the above-described embodiment, the non-divisional selection gate electrodes Ga and Gb are divided by the selection gate electrode division portions 13, 14, 15 and 16 as the selection gate electrodes, The first selection gate electrodes G2a and G2b and the second selection gate electrodes G3a and G3b are applied.

However, the present invention is not limited to this. The selection gate electrodes Ga and Gb formed around the memory gate electrodes G1a and G1b without dividing the select gate electrodes Ga and Gb, May be used as the side wall type gate electrode as it is. In this case, for example, of the two contact installation structures 10a and 11a, one contact installation structure 10a may be provided on the select gate electrode Ga in Fig. In such a semiconductor device, a contact C5a is provided so as to extend from the top of the contact mounting structure 10a to the sidewall spacer 27a and the select gate electrode Ga, The selective gate electrode Ga can be independently controlled separately from the memory gate electrode G1a by applying a voltage to the gate electrodes G1 and Ga so that the same effect as in the above-described embodiment can be obtained.

In the above-described embodiment, as the selective gate electrode cutting portion, a part of the select gate electrode Ga is physically cut off so that the first select gate electrode G2a and the second select gate electrode G2b are electrically disconnected from the select gate electrode Ga. The present invention is not limited to this. For example, the selection gate electrode Ga may be formed with a gate electrode G3a, A PIN junction structure, an NIN junction structure, a PIP junction structure, an NPN junction structure, or a PNP junction structure is formed on the selective gate electrode by the selective gate electrode cutoff portion, The selection gate electrode G2a and the second selection gate electrode G3a may be formed.

In the above-described embodiment, the first select gate electrode G2a and the second select gate electrode G2a, which selectively apply a voltage to the channel layer of the substrate surface facing the memory gate electrode G1a, The present invention is not limited to this. The first select gate electrode (G1a) having a function of selecting the memory gate electrode G1a may be formed on the memory gate electrode G1a G2a or the second selection gate electrode G3a may be provided.

Although the semiconductor device 1 in which the memory gate structure 4a is first formed has been described in the above embodiment, the present invention is not limited to this. The gate electrode and the gate electrode may be formed on the side wall And is applicable to various semiconductor devices in which sidewall gate electrodes are formed through sidewall spacers.

For example, although the charge storage layer EC is provided in the memory gate structure 4a, it is possible to use a gate structure having no charge accumulation layer and a gate electrode on the substrate through a gate insulating film, The semiconductor device may be a semiconductor device having a contact gate structure formed of the same layer and provided with a contact mounting structure electrically separated from the gate structure. In this case, the semiconductor device has a structure in which a gate electrode in the form of a sidewall is continuously provided from the gate structure to the contact installation structure, contacts are formed so as to extend from the top of the contact installation structure to the sidewall spacer and the sidewall- .

In another embodiment, the charge accumulation layer may be provided between the gate-type gate electrode continuously extending from the gate structure to the contact mounting structure and the substrate surface through the gate insulating film. In this case, the sidewall gate structure having a sidewall gate electrode has a structure in which a bottom gate insulation film, a charge storage layer, a top gate insulation film, and a memory gate electrode are stacked in this order. On the other hand, the gate structure in which the sidewall gate structure is formed through the sidewall spacer on the sidewall is a structure in which the gate electrode is disposed on the substrate through the gate insulation film, and the contact installation structure has the structure having the isolation gate electrode in the same layer as the gate electrode .

In the above-described embodiment, the contact installation structures 10a and 11a, the selection gate electrode cutouts 13 and 14, and the like may be formed at various positions.

The peripheral circuits 18 and 19 may be a sense amplifier, a column decoder, a row decoder or the like formed in the same area as the memory cells 3a, 3b, 3c, 3d, 3e and 3f, A central processing unit (CPU), an application-specific integrated circuit (ASIC), and a flash memory, which are formed in different areas from the memory cells 3a, 3b, 3c, 3d, 3e, And various other peripheral circuits such as an input / output circuit may be applied.

1: Semiconductor device
3a, 3b, 3c, 3d, 3e, 3f:
4a, 4b: memory gate structure (gate structure)
5a, 5b: a first select gate structure
6a, 6b: a second select gate structure
10a, 11a, 10b, 11b: contact mounting structure
Ga, Gb: selection gate electrode (sidewall gate electrode)
G1a, G1b: memory gate electrode (gate electrode)
G2a, G2b: a first select gate electrode (sidewall gate electrode)
G3a, G3b: a second selection gate electrode (sidewall gate electrode)
G8a, G8b, G9a, G9b: memory gate electrode (isolation memory gate electrode)
EC: charge accumulation layer
20: Device isolation layer (substrate)
23a: the lower gate insulating film
23b: upper gate insulating film
Rr1a and Rr1b:
W1: Memory well (substrate)
W2, W3: Logic well (substrate)

Claims (8)

A memory gate structure in which a lower gate insulating film, a charge storage layer, an upper gate insulating film, and a memory gate electrode are stacked in this order,
A contact mounting structure electrically separated from the memory gate structure and having a structure in which at least the charge storage layer, the upper gate insulating film, and a separate memory gate electrode made of the same layer as the memory gate electrode are stacked in this order,
Wherein the memory gate structure is formed in a sidewall shape through a sidewall spacer on a sidewall of the memory gate structure and is formed in a sidewall shape through sidewall spacers on sidewalls of the contact mounting structure, And a gate electrode formed on the gate insulating film,
A plurality of contacts provided so as to extend from the top of the contact mounting structure to the sidewall spacers and the sidewall-
The semiconductor device comprising: a semiconductor substrate; The method according to claim 1,
The sidewall-shaped select gate electrode is formed in a region between the sidewall spacer on the sidewall of the memory gate electrode and the sidewall spacer on the sidewall of the separated memory gate electrode arranged opposite to the sidewall spacer, . The method according to claim 1,
The distance between the sidewall of the memory gate electrode and the sidewall of the isolation memory gate electrode is Dp and the thickness of the sidewall select gate electrode from the sidewall spacer of the sidewall of the memory gate electrode is Dsw, Dp < (2 x Dsp) + (2 x Dsw) holds when the thickness of the sidewall spacer between the memory gate electrode and the sidewall select gate electrode is Dsp. 4. The method according to any one of claims 1 to 3,
The sidewall-shaped select gate electrode comprises a first select gate electrode formed in a sidewall shape along the sidewall spacers on one sidewall of the memory gate electrode and a second select gate electrode formed in a sidewall spacing on the sidewall spacers on the other sidewall of the memory gate electrode The first selection gate electrode and the second selection gate electrode are electrically separated from each other, and the first selection gate electrode and the second selection gate electrode are electrically separated from each other. 5. The method of claim 4,
Wherein the memory gate structure is formed in a straight line,
The contact mounting structure is composed of a first contact mounting structure disposed at one end side in the longitudinal direction of the memory gate structure and a second contact mounting structure disposed at the other end side in the longitudinal direction of the memory gate structure,
Wherein the contact includes a first contact provided upright from the top of the first contact mounting structure to extend from the top of the second contact mounting structure to the sidewall spacer and the first select gate electrode, And a second contact provided upright to extend to the gate electrode
And the semiconductor device. 6. The method of claim 5,
Wherein each of the first contact mounting structure and the second contact mounting structure is formed in a strip shape and is arranged on the same straight line as the longitudinal direction of the memory gate structure. The charge accumulation layer, the upper gate insulating film, and the memory gate electrode are stacked in this order on the substrate in the order of the lower gate insulating film, the charge accumulating layer, the upper gate insulating film, and the memory gate electrode, Electrodes are stacked in this order and at least the charge storage layer, the upper gate insulating film, and a separate memory gate electrode composed of the same layer as the memory gate electrode are stacked in this order, A contact mounting structure forming step of forming a contact mounting structure electrically separated from the structure,
A sidewall spacer forming step of forming a sidewall spacer along each side wall of the memory gate structure and the contact mounting structure;
Forming a conductive layer over the memory gate structure and sidewall spacers covered with the sidewall spacers so as to cover the contact mounting structure and then etching back the conductive layer to form sidewall spacers on the sidewalls of the contact mounting structure from the memory gate structure, A selective gate electrode forming step of forming a sidewall-shaped selective gate electrode continuously provided through the gate insulating film,
A contact forming step of forming a contact so as to extend from the top of the contact mounting structure to the selective gate electrode
Wherein the semiconductor device is a semiconductor device. 8. The method of claim 7,
In the step of forming the contact mounting structure, two or more of the contact mounting structures are formed,
In the selective gate electrode forming step, as the selective gate electrode,
A first select gate electrode in the form of a sidewall continuously provided through the sidewall spacer to one of the contact installation structure and the memory gate structure and the other contact formation structure and the memory gate structure through the sidewall spacer And a second select gate electrode of a sidewall shape electrically separated from the first select gate electrode is formed,
The contact forming step may include one contact which is erected to extend from the top of one of the contact mounting structures to the first select gate electrode and a second contact which extends from the top of the other contact mounting structure to the second select gate electrode, So as to form another contact
Wherein the semiconductor device is a semiconductor device.

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