TW201621509A - Bandgap reference circuit - Google Patents

Abstract

The present invention relates to a bandgap reference circuit, which having an output operation circuit configured to generate an output voltage for any low voltage level and provide a variety of reference voltages required by an integrated circuit. Moreover, the voltage level of the power required by the bandgap reference circuit of the present invention is low. Therefore, it is applicable to a low-voltage semiconductor manufacturing process. In addition, the bandgap reference circuit of the present invention can be digitalized and does not need a high-gain operational amplifier.

Description

Bandgap reference circuit 【0001】

The present invention relates to a bandgap reference circuit, and more particularly to a bandgap reference circuit that can generate a low voltage level.

【0002】

The Bandgap reference circuit has good stability and is insensitive to changes in the system's working environment (such as operating voltage, ambient temperature and output load), so the gap reference circuit can provide accurate accuracy for other circuits. The reference voltage, therefore, the gap reference circuit is an important sub-circuit in analog-like integrated circuits and many mixed-signal integrated circuits. The reference voltage generated by the bandgap reference circuit can be supplied to the data converter and the bias circuit. Generally, the output voltage generated by the conventional bandgap reference circuit must be 1.25V, and the power required for the conventional bandgap reference circuit must be at least 1.5V. However, today's latest CMOS processes have reduced the voltage below 1V. Therefore, the conventional bandgap reference circuit is not suitable for use in the latest CMOS process.

[0003]

Please refer to FIG. 1 , which is a circuit diagram of a conventional energy gap reference circuit, which includes two diodes D1 and D2 , a plurality of resistors R1 , R2 and R3 , and an operational amplifier 10 , and the connection relationship between the components is as shown in FIG. Show, so no longer detailed here. The voltage V+ at the positive input terminal of the operational amplifier 10 is V _D1 , and V _D1 is the voltage of the diode D1. The negative input terminal of the operational amplifier 10 to be forced equal to the voltage V- at the positive input of the operational amplifier 10 to voltage V + and V _D1. The voltage drop ΔV across resistor R3 can be expressed as follows:
ΔV = V _D1 - V _D2
Where V _D2 is the voltage of the diode D2. The current I flowing through the resistor R3 can be expressed as follows:
I = ΔV / R3
The voltage drop V _R2 across resistor R2 can be expressed as follows:
V _R2 = I × R2
=(ΔV / R3)× R2
The output voltage V _{O of the} operational amplifier 10 can be expressed as follows:
V _O = V _D1 + V _R2
= V _D1 +(R2/R3)× ΔV
Wherein, V _D1 is a voltage having a negative temperature coefficient, and ΔV is proportional to the threshold voltage V _T , and is a voltage having a positive temperature coefficient, so that the output voltage can be controlled by appropriately adjusting the ratio of the resistance values of R 2 and R 3 . V _{O is} not affected by temperature and is maintained at a fixed voltage as a reference voltage. This produced the conventional bandgap reference circuit output voltage V _O would fall near 1.25V. One of the power supplies V _DD received by the operational amplifier 10 must be 1.5V or more.

[0004]

As mentioned above, in the current low voltage requirements of the latest CMOS process, many of the circuits inside the integrated circuit require a reference voltage below 1V. However, the conventional bandgap reference circuit shown in Figure 1 does not produce a low voltage reference voltage, and it requires a higher voltage level power supply V _DD , so this conventional bandgap reference circuit is not suitable for a new CMOS process. Although there are many types of bandgap reference circuits, most of them cannot produce a low voltage reference voltage, and both require a higher voltage level power supply. At present, although other types of reference voltage generating circuits can generate reference voltages below 1V, which use a resistor shunt to generate a reference voltage, such a type of circuit has a problem of large nonlinear temperature and requires compensation.

[0005]

Accordingly, the present invention is directed to the above problem to provide a bandgap reference circuit that can generate a low voltage level reference voltage and does not require a higher voltage level power supply, but is suitable for low voltage semiconductor processes. In this way, the problem of the above conventional circuit is solved.

[0006]

It is an object of the present invention to provide a bandgap reference circuit that can generate an output voltage of a low voltage level for supply to other circuits as a reference voltage.

【0007】

It is an object of the present invention to provide a bandgap reference circuit having a voltage level of a required power supply at a low voltage level, and thus is suitable for a low voltage semiconductor process.

[0008]

It is an object of the present invention to provide a bandgap reference circuit that can generate output voltages of various voltage levels by an output operation circuit.

【0009】

It is an object of the present invention to provide a bandgap reference circuit having a circuit architecture that is a digital architecture without the need for a high gain operational amplifier for use in new semiconductor processes.

[0010]

The present invention discloses a bandgap reference circuit including a current generating circuit, a first bipolar junction component, a first impedance component, a second bipolar junction component, a second impedance component, and a control circuit. And an output operation circuit. The current generating circuit generates a first current, a second current and a third current; the first bipolar junction element is coupled between the current generating circuit and a ground, and is coupled to the first current, the first bipolar The connection end of the junction element and the current generating circuit has a first voltage; the first end of the first impedance element is coupled to the current generating circuit and coupled to the second current, and the first end of the first impedance element has a first end a second voltage; a second bipolar junction element is coupled between the second end of the first impedance element and the ground; the first end of the second impedance element is coupled to the first bipolar junction element and the current is generated a second end of the second impedance element coupled to the third current and having a third voltage; the control circuit controls the current generating circuit; the output computing circuit receives the first voltage and the third voltage, and operates the first voltage With the third voltage, an output voltage is generated. This output voltage is supplied to other circuits of the integrated circuit as a reference voltage.

10, 40‧‧‧Operational Amplifier
30‧‧‧Output arithmetic circuit
310‧‧‧First operational amplifier
313, 315, 317, 323, 325, 327‧ ‧ switches
320‧‧‧Second operational amplifier
45, 47‧‧‧ comparator
50‧‧‧Digital Circuit
61‧‧‧First digital analog converter
62‧‧‧Second digital analog converter
63‧‧‧ third digit analog converter
71‧‧‧First switch
73‧‧‧Second switch
75‧‧‧third switch
77‧‧‧fourth switch
79‧‧‧Detection operation circuit
AN1‧‧‧first analog signal
AN2‧‧‧Second analog signal
AN3‧‧‧ third analog signal
C1, C2, C3, C4‧‧‧ capacitors
D1, D2‧‧‧ diode
D11‧‧‧First bipolar junction element
D22‧‧‧Second bipolar junction element
DI1‧‧‧ first digit signal
DI2‧‧‧ second digit signal
DI3‧‧‧ third digit signal
I‧‧‧current
I ₁ ‧‧‧First current
I ₂ ‧‧‧second current
I ₃ ‧‧‧third current
I _R ‧‧‧reference current
M1‧‧‧ first current source
M2‧‧‧second current source
M3‧‧‧ reference current source
M4, M5‧‧‧ transistor
M6‧‧‧ third current source
R1, R2, R3‧‧‧ resistance
R11‧‧‧First impedance element
R22‧‧‧second impedance element
RS1‧‧‧first detection unit
RS2‧‧‧Second detection unit
RS3‧‧‧ third detection unit
SW1, SW11‧‧‧ first switching signal
SW2, SW22‧‧‧ second switching signal
SW3, SW33‧‧‧ third switching signal
SW4, SW44‧‧‧ fourth switching signal
SW5‧‧‧ fifth switching signal
SW6‧‧‧ sixth switching signal
V+, V-, V ₄ , V _D1 , V _D11 , V _D2 , V _D22 ‧‧‧ voltage
V ₁ ‧‧‧First voltage
V ₂ ‧‧‧second voltage
V ₃ ‧‧‧ third voltage
V _COM ‧‧‧ comparison signal
V _COM1 ‧‧‧ first comparison signal
V _COM2 ‧‧‧Second comparison signal
V _CON ‧‧‧ control signal
V _DD ‧‧‧ power supply
V _O ‧‧‧Output voltage
V _OUT ‧‧‧ output voltage
V _S1 ‧‧‧First detection signal
V _S2 ‧‧‧second detection signal
V _S3 ‧‧‧ third detection signal

[0011]

Figure 1 is a circuit diagram of a conventional energy gap reference circuit;
2 is a circuit diagram of an embodiment of a bandgap reference circuit of the present invention;
3A and 3B are circuit diagrams showing an embodiment of an output operation circuit of the bandgap reference circuit of the present invention;
4 is a circuit diagram of another embodiment of a bandgap reference circuit of the present invention; and FIG. 5 is a circuit diagram of still another embodiment of a bandgap reference circuit of the present invention.

[0012]

In order to provide a better understanding and understanding of the features and the efficacies of the present invention, the preferred embodiment and the detailed description are as follows:

[0013]

Please refer to FIG. 2, which is a circuit diagram of an embodiment of a bandgap reference circuit of the present invention. As shown, the bandgap reference circuit of the present embodiment includes a current generating circuit, a plurality of impedance elements R11 and R22, a plurality of bipolar junction elements D11 and D22, an output operation circuit 30, and a control circuit. In this embodiment, the current generating circuit is coupled to a power source V _DD for generating a first current I ₁ , a second current I _{2 ,} and a third current I ₃ . The current generating circuit includes a first current source M1, a second current source M2 and a third current source. The third current source includes a reference current source M3 and a current mirror, and the current mirror includes two transistors M4 and M5.

[0014]

A first current source M1, M2 and the second current source M3 are the reference current source coupled to the power V _DD, respectively providing a first current I _1, I ₂ and a second current reference current I _R. The current mirror transistor M5 is coupled to the reference current source M3, and receives the reference current I _R , the current mirror transistor M4 is coupled to the transistor M5, and the current mirror mirrors the reference current I _R to generate the third current I _{3 .} Crystal M4. The transistors M4 and M5 of the current mirror are more coupled to the ground. In an embodiment of the invention, the first current source M1, the second current source M2, and the reference current source M3 are implemented by a transistor. In one embodiment of the invention, the ratio of the currents of the currents I ₁ , I ₂ , I _R and I ₃ is 2:1:1:1.

[0015]

The first end of the first bipolar junction element D11 is coupled to the first current source M1 of the current generating circuit, and coupled to the first current I ₁ . The second end of one of the first bipolar junction elements D11 is coupled to the ground. Thus, the connection end of the first bipolar junction element D11 connected to the first current source M1 has a first voltage V ₁ .

[0016]

The first end of the first impedance element R11 is coupled to the second current source M2 and coupled to the second current I ₂ . The first end of the second bipolar junction element D22 is coupled to the second end of the first impedance element R11, and the second end of the second bipolar junction element D22 is coupled to the ground end. In addition, the first end of the first impedance element R11 has a second voltage V ₂ . In this embodiment, the first bipolar junction element D11 and the second bipolar junction element D22 are a diode. However, the first bipolar junction element D11 and the second bipolar junction element D22 may also be a Bipolar Junction Transistor (BJT). The ratio of the area of the first bipolar junction element D11 to the second bipolar junction element D22 is N:1, and N is greater than one.

[0017]

The first end of the second impedance element R22 is coupled to the connection end of the first bipolar junction element D11 and the first current source M1, and the second end of the second impedance element R22 is coupled to the transistor of the third current source M4 is coupled to the third current I ₃ , and the second end of the second impedance element R22 has a third voltage V ₃ . In an embodiment of the invention, the first impedance element R11 and the second impedance element R22 are resistors.

[0018]

In the embodiment, an operational amplifier 40 is used as a control circuit for controlling the current generating circuit to control the amount of current of the first current I ₁ , the second current I ₂ and the third current I ₃ . The negative input terminal of the operational amplifier 40 is coupled to the connection end of the first bipolar junction element D11 and the first current source M1 to receive the first voltage V ₁ . One positive input terminal of the operational amplifier 40 is coupled to the first end of the first impedance element R11 and receives the second voltage V ₂ . The operational amplifier 40 compares the first voltage V ₁ and the second voltage V ₂ to generate a control signal V _CON to control the first current source M1, the second current source M2 and the reference current source M3 of the third current source to control The amount of current of the first current I ₁ , the second current I ₂ , the reference current I _R and the third current I ₃ . The output operation circuit 30 is coupled to the connection end of the first bipolar junction element D11 and the first current source M1 and the second end of the second impedance element R22 to receive the first voltage V ₁ and the third voltage V ₃ and operate The first voltage V ₁ and the third voltage V ₃ generate an output voltage V _OUT .

[0019]

In the circuit architecture of this embodiment, the operational amplifier 40 adjusts the first current source M1 and the second current source M2 to force the second voltage V _{2 to} be equal to the first voltage V ₁ . The first voltage V ₁ is the voltage V _D11 of the first bipolar junction element _D11 . In this embodiment, the first bipolar junction element D11 is a diode, so the first voltage V ₁ is the voltage V _{D11 of the} diode, and the first voltage V ₁ has a negative temperature coefficient, which means the first The voltage V ₁ drops as the temperature rises. If the first bipolar junction element D11 is a bipolar junction transistor, the first voltage V ₁ is the base-emitter voltage V _BE of the bipolar junction transistor.

[0020]

Since the second voltage V ₂ is equal to the first voltage V ₁ , the voltage drop ΔVd across the first impedance element R11 can be expressed as follows:
ΔVd = V ₂ - V _D22
= V _D11 - V _D22
Wherein, V _D22 is the voltage of the second bipolar junction element D22. In this embodiment, it is a diode voltage. If the second bipolar junction element D22 is a bipolar junction transistor, V _D22 is the base-emitter voltage V _BE of the bipolar junction transistor. ΔVd and threshold voltage V _T will be proportional to the threshold voltage V _T has a positive temperature coefficient, which means that the voltage across the first impedance element R11 of ΔVd drop will increase with increasing temperature.

[0021]

The second current I ₂ flowing through the first impedance element R11 can be expressed as follows:
I ₂ = ΔVd / R11
Since the reference current I _R is equal to the second current I ₂ and the third current I ₃ is equal to the reference current I _R , the third current I ₃ can be expressed as follows:
I ₃ = I _R = I ₂ = ΔVd / R11

[0022]

The voltage drop V _R22 across the second impedance element _R22 can be expressed as follows:
V _R22 = I ₃ × R22
=(ΔVd / R11)× R22
= ΔVd × (R22/ R11)

[0023]

Since ΔVd has a positive temperature coefficient, the voltage drop V _R22 across the second impedance element R22 has a positive temperature coefficient. Thus, the voltage drop V _R22 having a positive temperature coefficient can be used to compensate the first voltage V ₁ having a negative temperature coefficient, so the first voltage V ₁ and the voltage drop V _R22 across the second impedance element _R22 can be used to generate The output voltage V _{OUT of the} temperature change, this output voltage V _OUT can be supplied to other circuits as a reference voltage. The output voltage V _OUT can be expressed as follows:
V _OUT = V ₁ + V _R22
= V ₁ + ΔVd × (R22/ R11)
It can be seen from the above equation that the ratio of the resistance value of the second impedance element R22 to the resistance value of the first impedance element R11 is used as the compensation ratio, so the first impedance element R11 and the second impedance element R22 are used as the adjustment temperature compensation coefficient. . As can be seen from the above equation, the resistance value of the second impedance element R22 is greater than the resistance value of the first impedance element R11.

[0024]

As shown in FIG. 2, the voltage drop V _R22 across the two ends of the second impedance element R22 is the voltage difference between the first voltage V ₁ and the third voltage V ₃ . Therefore, the output voltage V _OUT can be expressed as follows:
V _OUT = V ₁ + V _R22
= V ₁ +(V ₁ - V ₃ )
= 2V ₁ - V ₃
Generates an output voltage V _OUT based on the above equation, the arithmetic circuit 30 outputs a first voltage V ₁ is operational and the third voltage V _3. In an embodiment of the invention, the first voltage V ₁ is about 0.7V, and the output voltage V _OUT (2V ₁ - V ₃ ) shown in the above equation is about 1.25V, which is only one embodiment of the present invention. The invention is not limited thereto. In addition, the output operation circuit 30 can generate output voltages V _{OUT of} various voltage levels based on the above equation and a scaling factor K. The output voltage V _OUT can be further expressed as follows:
V _OUT = (V ₁ + (V ₁ - V ₃ )) / K
=(2V ₁ - V ₃ )/ K
Wherein, the scale factor K is a positive number greater than zero. As can be seen from the above equation, the output voltage V _{OUT of the} present invention has a total composite ratio of the voltage drop (V ₁ - V ₃ ) across the second impedance element R22 and the first voltage V ₁ . As such, the bandgap reference circuit of the present invention can produce an output voltage below 1V.

[0025]

It can be seen from the above that the bandgap reference circuit of the present invention can generate an output voltage V _OUT with a voltage level lower than 1V, and can also generate output voltages V _{OUT of} various voltage levels by designing an arithmetic expression of the output operation circuit 30. . Moreover, since the voltage level of the first voltage V ₁ and the second voltage V ₂ is about 0.7 V, the bandgap reference circuit of the present invention requires only a power supply V _{DD of} about 0.9V. In summary, the bandgap reference circuit of the present invention is suitable for low voltage semiconductor processes.

[0026]

Please refer to FIGS. 3A and 3B, which are circuit diagrams of an embodiment of the output operation circuit 30 of the bandgap reference circuit of the present invention. The output arithmetic circuit 30 of this embodiment is a switched capacitor arithmetic circuit. As shown in the figure, the output operation circuit 30 of the present embodiment includes two switching capacitor operation units. This embodiment is described by taking the following equation as an example.
V _OUT = (2V ₁ - V ₃ ) / 2
= V ₁ -(V ₃ / 2)

[0027]

The first switching capacitor operation unit includes a first operational amplifier 310, a plurality of capacitors C1 and C2, and a plurality of switches 313, 315 and 317. The first end of the switch 313 is coupled to the first end of the capacitor C1, and the second end of the switch 313 is coupled to the second end of the second impedance element R22 (shown in FIG. 2) and coupled to the third voltage. V ₃ , a third end of the switch 313 is coupled to the ground end, and the switch 313 is controlled by a first switching signal SW1 . The first end of the switch 315 is coupled to one of the second ends of the capacitor C1. The second end of the switch 315 is coupled to one of the negative inputs of the first operational amplifier 310. The third end of the switch 315 is coupled to the ground. The switch 315 is controlled by a second switching signal SW2. One of the first operational amplifiers 310 has a positive input coupled to the ground. The capacitor C2 is coupled between the negative input terminal of the first operational amplifier 310 and one of the output terminals of the first operational amplifier 310. The two ends of the switch 317 are coupled to the two ends of the capacitor C2, and the switch 317 is controlled by a third switching signal SW3. In this embodiment, the capacitance of the capacitor C2 is twice the capacitance of the capacitor C1.

[0028]

The second switched capacitor operation unit includes a second operational amplifier 320, a plurality of capacitors C3 and C4, and a plurality of switches 323, 325, and 327. The first end of the switch 323 is coupled to one of the first ends of the capacitor C3, and the second end of the switch 323 is coupled to the first end of the first bipolar junction element D11 (as shown in FIG. 2), and coupled The first voltage V ₁ , the third end of the switch 323 is coupled to the output end of the first operational amplifier 310 and the capacitor C2 , and the switch 323 is controlled by a fourth switching signal SW4 . The first end of the switch 325 is coupled to one of the second ends of the capacitor C3. The second end of the switch 325 is coupled to one of the negative inputs of the second operational amplifier 320. The third end of the switch 325 is coupled to the ground. The switch 325 is controlled by a fifth switching signal SW5. One positive input terminal of the second operational amplifier 320 is coupled to the ground.

[0029]

The capacitor C4 is coupled between the negative input terminal of the second operational amplifier 320 and the output terminal of the second operational amplifier 320. The two ends of the switch 327 are coupled to the two ends of the capacitor C4, and the switch 327 is controlled by a sixth switching signal SW6. In this embodiment, the capacitance of the capacitor C4 is equal to the capacitance of the capacitor C3. In an embodiment of the present invention, the switching signals SW1 SW SW6 are generated by the digital circuit 50 (as shown in FIG. 4 ) or generated by any circuit of the integrated circuit, which is the field of the present invention. Known techniques are therefore not described in detail herein.

[0030]

As shown in FIG. 3A, the switch 313 is controlled by the first switching signal SW1, and is connected between the second end of the second impedance element R22 (as shown in FIG. 2) and the first end of the capacitor C1 for transmission. The third voltage V _{3 is} to the capacitor C1. The switch 315 is controlled by the second switching signal SW2 and is connected between the second end of the capacitor C1 and the ground. Thus, the third voltage V ₃ charges the capacitor C1, that is, the third voltage V ₃ is sampled at the capacitor C1. In addition, the switch 317 is turned on by the third switching signal SW3 to drive the capacitor C2 to discharge and reset the capacitor C2. As described above, the switch 323 is controlled by the fourth switching signal SW4, and is connected between the first end of the first bipolar junction element D11 (as shown in FIG. 2) and the first end of the capacitor C3 to transmit the first A voltage V ₁ to capacitor C3. The switch 325 is controlled by the fifth switching signal SW5 and is connected between the second end of the capacitor C3 and the ground. As such, the first voltage V ₁ is sampled at the capacitor C3. In addition, the switch 327 is turned on by the sixth switching signal SW6 to drive the capacitor C4 to discharge and reset the capacitor C4.

[0031]

Next, as shown in FIG. 3B, the switch 313 is switched to be turned on between the ground terminal and the first end of the capacitor C1. Switch 315 is switched to conduct between a second end of capacitor C1 and a negative input of first operational amplifier 310. The switch 317 is turned off by the third switching signal SW3. Thus, the charge stored in the capacitor C1 is transferred to the capacitor C2, that is, the third voltage V ₃ sampled is integrated. In the present embodiment, since the capacitance value of twice the capacitance value of capacitor C2 of the capacitor C1, the third voltage of the integrator is sampled voltage of ₃ V obtained from the half value of the third voltage V ₃ (V _3/2) .

[0032]

Referring to FIG. 3B, the switch 323 is switched to be turned on between the output of the first operational amplifier 310 and the first end of the capacitor C3. Switch 325 is switched to conduct between a second end of capacitor C3 and a negative input of second operational amplifier 320. The switch 327 is turned off by the sixth switching signal SW6. Thus, the voltage difference (V ₁ -(V ₃ / 2)) between the output voltage (V ₃ /2) of the first operational amplifier 310 and the first voltage V ₁ (sampled to the capacitor C3) is integrated. In this embodiment, since the capacitance value of the capacitor C4 is equal to the capacitance value of the capacitor C3, the output voltage V _OUT of the second operational amplifier 320 is the output voltage (V ₃ /2) of the first operational amplifier 310 and the first voltage. The voltage difference between V ₁ .

[0033]

Please refer to FIG. 4, which is a circuit diagram of another embodiment of the bandgap reference circuit of the present invention. The difference between this embodiment and the previous embodiment (as shown in FIG. 2) is that the control circuit of the present embodiment includes a comparator 45, a digital circuit 50, and a digital analog conversion circuit without the need for the operational amplifier 40. The digital analog conversion circuit of this embodiment includes a plurality of digital analog converters (DACs) 61, 62 and 63. The architecture of the bandgap reference circuit of this embodiment is a digital architecture that does not require a high gain operational amplifier and is therefore suitable for new semiconductor processes. In addition, the embodiment further includes a third current source M6, and does not require the reference current source M3 and the current mirror (the transistors M4 and M5) shown in FIG. The third current source M6 is coupled between the second end of the second impedance element R22 and the ground, and provides a third current I ₃ . In an embodiment of the invention, the third current source M6 is implemented by a transistor.

[0034]

As shown in FIG. 4, one of the negative input terminals of the comparator 45 is coupled to the connection end of the first bipolar junction element D11 and the first current source M1 to receive the first voltage V ₁ . The positive input terminal of one of the comparators 45 is coupled to the first end of the first impedance element R11 and receives the second voltage V ₂ . The comparator 45 compares the first voltage V ₁ with the second voltage V ₂ to generate a comparison signal V _COM . The digital circuit 50 is coupled to one of the outputs of the comparator 45 to receive the comparison signal V _COM . The digital circuit 50 generates a plurality of digital signals DI1, DI2, and DI3 according to the comparison signal V _COM . The first digital analog converter 61, the second digital analog converter 62 and the third digital analog converter 63 are coupled to the digital circuit 50, and convert the digital signals DI1, DI2 and DI3 into analog signals AN1, AN2 and AN3.

[0035]

The digital analog converters 61, 62 and 63 are respectively coupled to the first current source M1, the second current source M2 and the third current source M6, respectively, by the first analog signal AN1, the second analog signal AN2 and the third AN3 analog signal respectively controlling the plurality of current source M1, M2 and M6, and the plurality of the control current I _1, I ₂ and I ₃ of the current. In one embodiment of the invention, the digital circuit 50 can be a microprocessor, but the digital circuit 50 is not limited to a microprocessor. The remaining circuits of this embodiment are the same as those of the previous embodiment, so they will not be described in detail here, and the ratio of the current quantities of the currents I ₁ , I ₂ , and I ₃ is also maintained at 2:1:1.

[0036]

Please refer to FIG. 5, which is a circuit diagram of still another embodiment of the bandgap reference circuit of the present invention. The control circuit of the present embodiment further includes a detection circuit coupled to the current sources M1, M2, and M6 of the current generating circuit to detect the currents I ₁ , I _{2 ,} and I ₃ , and according to the The currents I ₁ , I ₂ and I ₃ generate a first detection signal V _S1 , a second detection signal V _S2 and a third detection signal V _S3 . The detection signals V _S1 , V _S2 and V _{S3 are} supplied to a comparison circuit. In the present embodiment, the comparison circuit includes a comparator 47. The comparator 47 compares the first detection signal V _S1 with the second detection signal V _S2 to generate a first comparison signal V _COM1 . In addition, the comparator 47 compares the second detection signal V _S2 with the third detection signal V _S3 to generate a second comparison signal V _COM2 . The digital circuit 50 receives the first comparison signal V _COM1 and the second comparison signal V _COM2 , and generates a plurality of digital signals DI1 , DI2 and DI3 according to the first comparison signal V _COM1 and the second comparison signal V _COM2 . The plurality of digital to analog converters 61, 62 and 63 convert the plurality of digital signals DI1, DI2 and DI3 of analog signals AN1, AN2 and AN3, to control the current sources M1, M2 and M6, and then control the plurality of current I _1, The amount of current of I ₂ and I ₃ .

[0037]

The detecting circuit of the embodiment includes a first detecting unit RS1, a second detecting unit RS2, a third detecting unit RS3, a first switch 71, a second switch 73, and a third switch 75. A detection operation circuit 79. In an embodiment of the invention, the detecting units RS1, RS2 and RS3 are resistors. The first end of the first switch 71 is coupled to the first current source M1, and the second end of the first switch 71 is coupled to one of the first ends of the first detecting unit RS1, and one of the first detecting units RS1 The second end of the first switch 71 is coupled to the first end of the first bipolar junction element D11. The first switch 71 is controlled by a first switching signal SW11, SW11 when the first switching signal controls the first switch 71 is turned between the first current source and the first detecting unit M1 RS1, first current I ₁ flowing through The first switch 71 and the first detecting unit RS1, such that the first detecting unit RS1 generates the first detecting signal V _S1 according to the first current I ₁ .

[0038]

The first end of the second switch 73 is coupled to the second current source M2, and the second end of the second switch 73 is coupled to one of the first ends of the second detecting unit RS2, and one of the second detecting units RS2 The second end of the second switch 73 is coupled to the first end of the first impedance element R11. The second switch 73 is controlled by a second switching signal SW22. When the second switching signal SW22 controls the second switch 73 to be turned on between the second current source M2 and the second detecting unit RS2, the second current I ₂ flows through. The second switch 73 and the second detecting unit RS2, such that the second detecting unit RS2 generates the second detecting signal V _S2 according to the second current I ₂ .

[0039]

The first end of the third switch 75 is coupled to the third current source M6, and the second end of the third switch 75 is coupled to one of the second ends of the third detecting unit RS3, and one of the third detecting units RS3 The first end is coupled to the power source V _DD , the power source V _{DD is} used to provide a voltage to the third detecting unit RS3 , and the third end of the third switch 75 is coupled to the second end of the second impedance element R22 . The third switch 75 is controlled by a third switching signal SW33, SW33 when the third switching signal to control the third switch 75 is turned between the third current source and the third detecting unit M6 RS3, a third current I ₃ flowing through The third detecting unit RS3, such that the third detecting unit RS3 generates the third detecting signal V _S3 according to the third current I ₃ . The third detection signal V _S3 is the voltage drop across the third detection unit RS3, so the third detection signal V _S3 can be expressed as follows:
V _S3 = (V _DD - V ₄ )
Wherein V ₄ is the voltage of the second end of the third detecting unit RS3. The detection operation circuit 79 receives the power source V _DD and the voltage V ₄ , and outputs the third detection signal V _{S3 by} calculating the power source V _DD and the voltage V ₄ according to the above equation. The detailed circuit of the detection arithmetic circuit 79 is similar to the output operation circuit 30 of FIG. 3A.

[0040]

One of the positive input terminal of comparator 47 is coupled to a first end of the second detecting unit RS2, the received second detection signal V _S2. One of the negative ends of the comparator 47 is coupled to a first end of the fourth switch 77, and the second end of the fourth switch 77 is coupled to the first end of the first detecting unit RS1 to receive the first detecting signal. V _S1, the fourth switch 77, one end of one of the third output terminal 79 coupled to the detection operation circuit receiving the third detection signal V _S3. The fourth switch 77 is controlled by a fourth switching signal SW44. In an embodiment of the present invention, the switching signals SW11, SW22, SW33, and SW44 are generated by the digital circuit 50, or are generated by any circuit of the integrated circuit, which is a well-known technology in the field to which the present invention pertains. It will not be detailed here.

[0041]

The manner in which the bandgap reference circuit of the present embodiment adjusts the current quantities of the currents I ₁ , I ₂ and I ₃ is as follows. The ratio of the currents of the currents I ₁ , I ₂ and I ₃ is 2:1. :1. The resistance ratios of the detecting units RS1, RS2 and RS3 in this embodiment are 1:2:2. A first switching signal 71 controls the first switch SW11 is turned between the first current source and the first detecting unit M1 RS1, to generate a first detecting signal V _S1. The second switching signal SW22 controls the second switch 73 to be turned on between the second current source M2 and the second detecting unit RS2 to generate the second detecting signal V _S2 . The fourth switching signal SW44 controls the fourth switch 77 to be turned on between the negative input terminal of the comparator 47 and the first end of the first detecting unit RS1.

[0042]

The comparator 47 receives the first detection signal V _S1 and the second detection signal V _S2 and compares them to generate a first comparison signal V _COM1 . The digital circuit 50 samples the first comparison signal V _COM1 and generates the first digital signal DI1 and the second digital signal DI2 according to the first comparison signal V _COM1 . The digital analog converters 61 and 62 respectively convert the first digital signal DI1 and the second digital signal DI2 into a first analog signal AN1 and a second analog signal AN2 to control the first current source M1 and the second current source M2, and adjust the current. I ₁ and I ₂ . The digital circuit 50 continuously adjusts the currents I ₁ and I ₂ until the first detection signal V _S1 is equal to the second detection signal V _S2 , which means that the ratio of the currents of the currents I ₁ and I ₂ is 2:1.

[0043]

In the continuation, the third switching signal SW33 controls the third switch 75 to be turned on between the third current source M6 and the third detecting unit RS3. The detection operation circuit 79 calculates the voltage of the power source V _DD and the voltage V ₄ to output a third detection signal V _S3 . In addition, the fourth switching signal SW44 controls the fourth switch 77 to be turned on between the negative input terminal of the comparator 47 and the output terminal of the detecting operation unit 79 to receive the third detecting signal V _S3 . The comparator 47 receives the third detection signal V _S3 and the second detection signal V _S2 and compares it to generate a second comparison signal V _COM2 . The digital circuit 50 samples the second comparison signal V _COM2 to generate the second digital signal DI2 and the third digital signal DI3. The digital analog converters 62 and 63 respectively convert the second digital signal DI2 and the third digital signal DI3 into a second analog signal AN2 and a third analog signal AN3 to control the second current source M2 and the third current source M6 to adjust the current. I ₂ and I ₃ . Digital circuit 50 continuously adjusts the current I ₂ and I ₃ until the second detection signal V _S2 equal to the third detection signal V _S3, so it means that the current I and the current I ₂ ratio of ₃ to 1: 1.

[0044]

As can be seen from the above, the digital circuit 50 first adjusts the currents I ₁ and I ₂ and then adjusts the currents I ₂ and I ₃ . Since the current I ₂ may be adjusted again, the ratio of the currents I ₁ to I ₂ may not be 2:1. Therefore, the detection circuit will re-detect the currents I ₁ and I ₂ , and the digital circuit 50 will re-adjust the currents I ₁ and I ₂ and then adjust the currents I ₂ and I ₃ . The digital circuit 50 of this embodiment will continue to perform the adjustment operation repeatedly, and slowly converge the currents I ₁ , I ₂ and I ₃ until the ratio of the currents I ₁ , I ₂ and I ₃ is 2:1:1. . After the digital circuit 50 finishes adjusting the currents I ₁ , I ₂ and I ₃ , the first switch 71 is switched to be turned on between the first current source M1 and the first bipolar junction element D11 , and the second switch 73 is switched. The third switch 75 is switched between the second current source M2 and the first impedance element R11 to be turned on between the third current source M3 and the second impedance element R22 to generate an output voltage V _OUT .

[0045]

In another embodiment of the present invention, the comparison circuit includes two comparators (not shown), and the first comparator receives the first detection signal V _S1 and the second detection signal V _S2 and compares A comparison signal V _COM1 . The second comparator receives the second detection signal V _S2 and the third detection signal V _S3 and compares it to generate a second comparison signal V _COM2 . Thus, the fourth switch 77 is not required. The detection circuit and the adjustment method are only one embodiment of the present invention, and the present invention is not limited to the adjustment of the currents I ₁ , I ₂ and I _{3 by} using the detection circuit and the adjustment method described above.

[0046]

In summary, the energy gap reference circuit of the present invention can use an output operation circuit to generate an output voltage of any voltage level, especially an output voltage of a low voltage level, for example, the voltage level is 1V or less. Moreover, the voltage level of the power supply required by the bandgap reference circuit of the present invention is low, so the bandgap reference circuit of the present invention is suitable for use in a low voltage semiconductor process. In addition, the bandgap reference circuit of the present invention can be digitized without the need for a high gain operational amplifier, but is suitable for use in new semiconductor processes.

[0047]

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the claims of the present invention. All should be included in the scope of the patent application of the present invention.

[0048]

The invention is a novelty, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, and the invention patent application is filed according to law, and the prayer bureau will grant the patent as soon as possible. prayer.

30‧‧‧Output arithmetic circuit

40‧‧‧Operational Amplifier

D11‧‧‧First bipolar junction element

D22‧‧‧Second bipolar junction element

I ₁ ‧‧‧First current

I ₂ ‧‧‧second current

I ₃ ‧‧‧third current

I _R ‧‧‧reference current

M1‧‧‧ first current source

M2‧‧‧second current source

M3‧‧‧ reference current source

M4‧‧‧O crystal

M5‧‧‧O crystal

R11‧‧‧First impedance element

R22‧‧‧second impedance element

V ₁ ‧‧‧First voltage

V ₂ ‧‧‧second voltage

V ₃ ‧‧‧ third voltage

V _CON ‧‧‧ control signal

V _D11 ‧‧‧ voltage

V _D22 ‧‧‧ voltage

V _DD ‧‧‧ power supply

V _OUT ‧‧‧ output voltage

Claims (14)

[Item 1] A bandgap reference circuit comprising:
a current generating circuit for generating a first current, a second current and a third current;
a first bipolar junction element coupled between the current generating circuit and a ground, coupled to the first current, the first bipolar junction element and the current generating circuit connected to one end Having a first voltage;
a first impedance component having a first end coupled to the current generating circuit and coupled to the second current, the first end of the first impedance component having a second voltage;
a second bipolar junction element coupled between the second end of the first impedance element and the ground end;
a second impedance element having a first end coupled to the first bipolar junction element and the connection end of the current generating circuit, and a second end of the second impedance element coupled to the third current and having a Third voltage
a control circuit that controls the current generating circuit; and an output computing circuit that receives the first voltage and the third voltage and calculates the first voltage and the third voltage to generate an output voltage. [Item 2] The bandgap reference circuit of claim 1, wherein the current generating circuit comprises:
a first current source providing the first current;
a second current source is provided to provide the second current; and a third current source is coupled between the second end of the second impedance element and the ground, and provides the third current. [Item 3] The gap reference circuit of claim 2, wherein the third current source comprises:
a reference current source, providing a reference current; and a current mirror coupled to the reference current source, the second end of the second impedance element and the ground, and providing the third current according to the reference current. [Item 4] The energy gap reference circuit of claim 1, wherein the control circuit comprises:
An operational amplifier compares the first voltage with the second voltage to generate a control signal to control the current generating circuit to control the current of the first current, the second current, and the third current. [Item 5] The energy gap reference circuit of claim 1, wherein the control circuit comprises:
a comparator, generating a comparison signal according to the first voltage and the second voltage;
a digital circuit coupled to the comparator and generating a plurality of digital signals according to the comparison signal; and a digital analog conversion circuit coupled to the digital circuit and the current generating circuit, and converting the digital signals into a plurality of analog signals The analog signals control the current generating circuit to control the amount of current of the first current, the second current, and the third current. [Item 6] The energy gap reference circuit of claim 5, wherein the digital signals comprise a first digital signal, a second digital signal and a third digital signal, wherein the analog signals comprise a first analog signal, a second analog signal and a third analog signal, the digital analog conversion circuit comprising:
a first digital analog converter coupled to the digital circuit and converting the first digital signal to the first analog signal;
a second digital analog converter coupled to the digital circuit and converting the second digital signal to the second analog signal;
a third digital analog converter coupled to the digital circuit and converting the third digital signal to the third analog signal;
The current generating circuit comprises:
a first current source providing the first current and controlled by the first analog signal;
a second current source is provided to be controlled by the second analog signal; and a third current source is coupled between the second end of the second impedance element and the ground end, and The third current is provided and controlled by the third analog signal. [Item 7] The energy gap reference circuit of claim 1, wherein the control circuit comprises:
a detecting circuit coupled to the current generating circuit to detect the first current, the second current, and the third current, and generating a first according to the first current, the second current, and the third current a detection signal, a second detection signal and a third detection signal;
Comparing the first detection signal and the second detection signal to generate a first comparison signal, and comparing the second detection signal with the third detection signal to generate a second comparison signal ;
a digital circuit coupled to the comparison circuit and generating a plurality of digital signals according to the first comparison signal and the second comparison signal; and a digital analog conversion circuit coupled to the digital circuit and the current generation circuit, and converting the The digital signals are a plurality of analog signals, and the analog signals control the current generating circuit to control the currents of the first current, the second current and the third current. [Item 8] The energy gap reference circuit of claim 7, wherein the detection circuit comprises:
a first detecting unit is coupled between the current generating circuit and the ground, and generates the first detecting signal according to the first current;
a first switch coupled between the current generating circuit and the first detecting unit, and coupled between the current generating circuit and the first bipolar junction element, when the first switch is turned on When the current generating circuit is between the first detecting unit, the first current flows through the first switch and the first detecting unit;
a second detecting unit is coupled between the current generating circuit and the ground, and generates the second detecting signal according to the second current;
a second switch coupled between the current generating circuit and the second detecting unit, and coupled between the current generating circuit and the first end of the first impedance element, when the second switch is turned on When the current generating circuit is between the second detecting unit, the second current flows through the second switch and the second detecting unit;
a third detecting unit is coupled between a voltage and the current generating circuit, and generates the third detecting signal according to the third current; and a third switch coupled to the current generating circuit and the first Between the three detecting units, and coupled between the current generating circuit and the second end of the second impedance element, when the third switch is turned on between the current generating circuit and the third detecting unit The third current flows through the third detecting unit. [Item 9] The energy gap reference circuit of claim 8, wherein the detecting circuit further comprises:
A detecting operation circuit calculates two voltages at both ends of the third detecting unit to output the third detecting signal. [Item 10] The gap reference circuit of claim 1, wherein the ratio between the first current, the second current, and the third current is 2:1:1. [Item 11] The gap reference circuit of claim 1, wherein the output voltage and a voltage drop across the two ends of the second impedance element and a total composite ratio of the first voltage. [Item 12] The gap reference circuit of claim 11, wherein the first voltage has a negative temperature coefficient, and the voltage drop across the second impedance element has a positive temperature coefficient. [Item 13] The gap reference circuit of claim 1, wherein the first bipolar junction element and the second bipolar junction element are a bipolar junction transistor or a diode. [Item 14] The gap reference circuit of claim 1, wherein the resistance value of the second impedance element is greater than the resistance value of the first impedance element.