TW201621327A - Remote differential voltage sensing - Google Patents

Abstract

A remote differential voltage sensing circuit having a voltage input (Vin) and a voltage output (Vout), comprises a dual differential input stage including a common-source or common-collector differential input stage in parallel with a common-gate or common-base differential input stage. The common-source or collector differential input stage has differential inputs, one coupled to the voltage input (Vin) and the other coupled to the voltage output (Vout). The common-gate or common-base differential input stage has differential inputs, one coupled to a local ground (Agnd) and the other coupled to a remote ground (Rgnd). An output stage is driven by an output of the dual differential input stage and produces an output voltage at the voltage output (Vout). A compensation network is coupled between the voltage output (Vout) and the output of the dual differential input stage.

Description

Remote differential voltage sensing

Embodiments of the present invention are generally related to a remote differential voltage sensing circuit, a system including a remote differential voltage sensing circuit, and for generating an output voltage (Vout) equal to an input voltage (Vin) Add or subtract a difference between a remote ground (Rgnd) and a local ground (Agnd).

Priority claim

The present application is a priority of U.S. Provisional Patent Application No. 62/042,104, filed on Aug. 26, 2014, which is incorporated herein by reference.

An electrical system (also referred to as an electrical device) typically includes both a grounding and a distal grounding. The grounding (which may also be referred to as a local ground, an analog ground, or Agnd) is a ground associated with a die or wafer. The ground of the distal end (also referred to as Rgnd, a return ground, or Rrtn) is the ground associated with a printed circuit board (PCB) to which the die or wafer is attached.

To improve the correctness of such systems, remote differential voltage sensing circuits (sometimes referred to as differential remote voltage sensing circuits) are often utilized. 1 is a diagram of a conventional remote differential voltage sensing circuit 102 that includes two amplifiers AMP1 and AMP2, and two A resistor divider is used to achieve remote sensing. One of the resistor dividers includes resistors R0 and R1, and the other of the resistor dividers includes resistors R2 and R3. The two inputs of the differential voltage sensing circuit 102 at the far end in FIG. 1 are Vin and Rgnd, and the output of the remote differential voltage sensing circuit 102 is Vout, where Vout=Vin+Rgnd-Agnd . The conventional remote differential voltage sensing circuit 102 of FIG. 1 essentially functions as an analog computing circuit.

A disadvantage associated with the conventional remote differential voltage sensing circuit 102 of Figure 1 is that it occupies more area than desired, which consumes more power than desired (because it contains two amplifiers And it has a greater than the desired voltage offset (VOS) error. More specifically, VOS=VOS1+2*VOS2, where VOS1 is the voltage offset error associated with the first amplifier (AMP1) and VOS2 is the voltage offset error associated with the second amplifier (AMP2), And the VOS is the total voltage offset error caused by the differential voltage sensing circuit 102 at the far end of FIG.

In order to reduce power consumption, reduce the area of the turns, and reduce the voltage offset error, a parallel transconductance (Gm) stage can be utilized to differentially sense a far-end signal. An example of such a topology is depicted in Figure 2. More specifically, FIG. 2 depicts a remote differential voltage sensing circuit 202 in which the three inputs of the remote differential voltage sensing circuit 202 are Vin, Rgnd, and Agrnd, and the distal end The output of the differential voltage sensing circuit 202 is Vout, where Vout = Vin + Rgnd - Agnd. A disadvantage associated with the remote differential voltage sensing circuit 202 of FIG. 2 is that it requires a very good match between the two input pairs, since grounding as an input would have a common mode range limitation, which still consumes More power than is expected, and it still has a greater than the desired voltage offset (VOS) error.

Embodiments of the present invention are differential voltage sensing circuits, packages that are generally related to the far end A system comprising a remote differential voltage sensing circuit, and for generating an output voltage (Vout) equal to an input voltage (Vin) plus or minus a ground (Rgnd) at a remote end and a local A method of difference between ground (Agnd). In accordance with some embodiments, a differential voltage sensing circuit having a voltage input (Vin) and a voltage output (Vout) distal end includes a dual differential input stage that includes or is common to a common gate a differential input stage in which the differential input stages of the base are connected in parallel or a differential input stage of the common collector, wherein the differential input stage of the common source or the common collector has a differential input, wherein a differential input An input is coupled to the voltage input (Vin), and another differential input is coupled to the voltage output (Vout), and wherein the common gate or common base differential input stage There is a differential input, one of which is coupled to a local ground (Agnd), and the other of which is coupled to a remote ground (Rgnd). Additionally, the remote differential voltage sensing circuit can include an output stage that is driven by an output of the dual differential input stage and produces an output at the voltage output (Vout) Voltage. Furthermore, the remote differential voltage sensing circuit can include a compensation network coupled between the voltage output (Vout) and the output of the dual differential input stage. The compensation network can include a capacitor and a resistor connected in series between the voltage output (Vout) and the output of the dual differential input stage. The remote differential voltage sensing circuit can also include a first current source biasing the dual differential input stage and a second current source biasing the output stage. In some embodiments, the differential input of the common or common base differential input stage is coupled to the local ground (Agnd) and the remote ground (Rgnd) So that Vout = Vin + Rgnd - Agnd. In other embodiments, the differential input of the common gate or common differential input stage is coupled to the local ground (Agnd) and the remote ground (Rgnd), Let Vout = Vin-Rgnd + Agnd.

102‧‧‧ Remote differential voltage sensing circuit

202‧‧‧ Remote differential voltage sensing circuit

302a, 302b‧‧‧ remote differential voltage sensing circuit

304a, 304b‧‧‧Dual differential input stage

306a‧‧‧ Common source differential input stage

306b‧‧‧Common emitter differential input stage

308a‧‧‧Common differential input stage

308b‧‧‧ Common base differential input stage

310a, 310b‧‧‧ output stage

312a, 312b‧‧‧ Compensation Network

402a, 402b‧‧‧ remote differential voltage sensing circuit

404a, 404b‧‧‧ double differential input stage

406a‧‧‧ Common source differential input stage

406b‧‧‧Common emitter differential input stage

408a‧‧‧Common differential input stage

408b‧‧‧ Common base differential input stage

410a, 410b‧‧‧ output stage

412a, 412b‧‧‧ compensation network

502a, 502b‧‧‧ remote differential voltage sensing circuit

504a, 504b‧‧‧ double differential input stage

506a‧‧‧ Common source differential input stage

506b‧‧‧Common emitter differential input stage

508a‧‧‧Common differential input stage

508b‧‧‧Basic differential input stage

510a, 510b‧‧‧ output stage

512a, 512b‧‧‧ compensation network

602a, 602b‧‧‧ remote differential voltage sensing circuit

604a, 604b‧‧‧Dual differential input stage

606a‧‧‧Common source differential input stage

606b‧‧‧Common emitter differential input stage

608a‧‧‧Common differential input stage

608b‧‧‧ Common base differential input stage

610a, 610b‧‧‧ output stage

612a, 612b‧‧‧ compensation network

706‧‧‧Voltage regulator

802, 804, 806, 808‧‧‧ method steps

1 is a diagram of a conventional remote differential voltage sensing circuit.

2 is an alternate embodiment depicting a remote differential voltage sensing circuit.

3A is a diagram of a differential voltage sensing circuit at the distal end, in accordance with an embodiment of the present invention.

3B is a diagram of a differential voltage sensing circuit at the far end, in accordance with another embodiment of the present invention.

4A is a diagram of a differential voltage sensing circuit at the distal end, in accordance with an embodiment of the present invention.

4B is a diagram of a differential voltage sensing circuit at the distal end, in accordance with another embodiment of the present invention.

5A is a diagram of a differential voltage sensing circuit at the distal end, in accordance with another embodiment of the present invention.

5B is a diagram of a differential voltage sensing circuit at the distal end, in accordance with yet another embodiment of the present invention.

6A is a diagram of a differential voltage sensing circuit at the far end, in accordance with another embodiment of the present invention.

6B is a diagram depicting a remote differential voltage sensing circuit in accordance with yet another embodiment of the present invention.

7A is a diagram depicting a system including a voltage regulator having an input terminal that receives the difference in the distal end described above with reference to FIGS. 3A, 3B, 6A, and 6B, in accordance with an embodiment of the present invention. The output voltage of one of the dynamic voltage sensing circuits.

7B is a diagram depicting a system including a voltage regulator having a voltage feedback in a feedback path as described above with reference to FIGS. 4A, 4B, 5A, and 5B, in accordance with an embodiment of the present invention. One of the remote differential voltage sensing circuits.

Figure 8 is a high level flow diagram for summarizing methods in accordance with various embodiments of the present invention.

The accompanying drawings, which are incorporated in the claims It will be appreciated that other embodiments may be utilized and that mechanical and electrical changes may be made. Therefore, the following detailed description is not intended to be taken in a limiting sense. In the following description, the same component symbols or reference indicators will be used to indicate similar components or components throughout. Further, the first digit of a component symbol is a map indicating that the component symbol first appears therein.

FIG. 3A depicts a remote differential voltage sensing circuit 302a in accordance with an embodiment of the present invention. As can be appreciated from Figure 3A, the embodiment shown therein can be implemented using only five metal oxide semiconductor field effect transistors (MOSFETs) Mp0, Mp1, Mn2, Mn3, and Mn5, and a capacitor C0. Advantageously, the small geometry device (i.e., the MOSFET) is easily biased in its sub-threshold region and has a mutual conductance similar to a bipolar junction transistor. (Gm). As shown in FIG. 3A, the sub-critical design is in the differential input stage by matching the mutual conductance (Gm) between the PMOS pair Mp0 and Mp1 and the NMOS pair Mn3 and Mn2. Implement it.

In the embodiment of FIG. 3A, the NMOS transistor Mn5 is an output stage 310a that functions as a differential voltage sensing circuit 302a for the remote end. Current sources I1 and I2 shown therein are differential voltage sensing circuits 302a that are used to bias the far end. The resistor R0 and the capacitor C0 are provided with a compensation network 312a to stabilize the differential voltage sense of the distal end. The amplifiers of the two stages of circuit 302a are measured. In one embodiment, the resistor R0 can be implemented by a MOSFET device that acts as a resistor. The resistor R0 (or equivalent) is the effect of reducing the feed-forward through the compensation capacitor C0, which improves the small signal stability of the circuit. The resistor R0 cooperates with the capacitors C0 and 1/Gm5 to move the right half plane (RHP) zero to the left half plane (LHP) zero. It is also feasible to eliminate the resistor R0 from the compensation network 312a. In other words, the resistor R0 is optional.

In the embodiment of FIG. 3A, the transistors Mp0, Mp1, Mn3, and Mn2 form a dual differential input stage 304a that includes a common source differential input in parallel with a common gate differential input stage 308a. Stage 306a. The common source differential input stage 306a has a differential input, one of the differential inputs is coupled to the voltage input (Vin), and another differential input is coupled to the voltage Output (Vout). The common gate differential input stage 308a has a differential input, one of the differential inputs is coupled to a local ground (Agnd), and the other differential input is coupled to a remote end Ground (Rgnd). An output of the dual differential input stage 304a is generated or provided at the junction of the transistors Mp0 and Mn3 connected together. In the embodiment of FIG. 3A, the transistor Mn5 is provided with an output stage 310a that is driven by an output of the dual differential input stage 304a and that is produced at the voltage output (Vout) An output voltage. The compensation network 312a is coupled between the voltage output (Vout) and the output of the dual differential input stage 304a.

In the embodiment of FIG. 3A, Vout = Vin + (Gm2 / Gm0) * (Rgnd - Agnd), where Gm2 is the mutual conductance of the transistor Mn2, and Gm0 is the mutual conductance of the transistor Mp0. If Gm2 = Gm0 (this can be achieved by appropriate adjustments in device size), then the equation becomes Vout = Vin + Rgnd - Agnd. Furthermore, what is noted is the reality described here. In each of the embodiments, if Vout is being measured in relation to Agnd, Agnd can be assumed to be zero, and the above equation becomes Vout=Vin+Rgnd. In the embodiment of Figure 3A, the transistors Mp0 and Mn2 both operate in their subcritical regions. The NMOS and PMOS transistors preferably have the same bias current (ID). Further, Gm = ID / (n * VT), where Gm0 = Gm2. VT is a thermal voltage that is, for example, for a two-carrier junction transistor, approximately 26 mV at 27 degrees Celsius, and Gm = IC/VT, where IC is the collector current. For a critical MOSFET, if ID = IC, then its Gm is less than the Gm of a two-carrier junction transistor, so the thermal voltage of a MOSFET is defined as n * VT, where n is greater than 1 and is related to W/L ratio, where W is the width of the MOSFET channel and L is the channel length. In FIG. 3A, since the PMOS transistors Mp1 and Mp0 are biased with the same bias current, and the PMOS transistors Mp1 and Mp0 are designed to have the same mutual conductance (ie, the same) Gm), the source-to-drain current through the PMOS transistors Mp1 and Mp0 will be the same. If Rgnd and Agnd are the same, the drain-to-source current through the NMOS transistors Mn2 and Mn3 will be the same, and Vout will be equal to Vin. However, if Rgnd and Agnd are different (almost always), the drain-to-source current through the NMOS transistors Mn2 and Mn3 will be different, which will have Vout=Vin+Rgnd- Agnd, or simply the effect of Vout=Vin+Rgnd (if Agnd is assumed to be zero).

In an alternate embodiment, as shown in FIG. 3B, bi-carrier junction transistors (BJT) Qp0, Qp1, Qn2, Qn3, and Qn5 can be utilized to replace the MOSFET transistors Mp0, Mp1, Mn2, respectively. , Mn3 and Mn5. In the embodiment of FIG. 3B, the transistors Qp0, Qp1, Qn3, and Qn2 form a dual differential input stage 304b that includes a common emitter differential input in parallel with a common base differential input stage 308b. Stage 306b. Differential input stage of the common emitter 306b is a differential input, one of the differential inputs being coupled to the voltage input (Vin), and wherein the other differential input is coupled to the voltage output (Vout). The common base differential input stage 308a has a differential input, one of the differential inputs is coupled to a local ground (Agnd), and the other differential input is coupled to a remote end Ground (Rgnd). An output of the dual differential input stage 304b is generated or provided at the junction of the transistors Qp0 and Qn3 connected together. In the embodiment of FIG. 3B, the transistor Qn5 is provided with an output stage 310b that is driven by an output of the dual differential input stage 304b and that is generated at the voltage output (Vout) An output voltage. A compensation network 312b is coupled between the voltage output (Vout) and the output of the dual differential input stage 304b. As in the example of Figure 3A, the resistor R0 of the compensation network 312b is optional and can therefore be removed. If Rgnd and Agnd are the same, the collector-to-emitter current through the NPN transistors Qn2 and Qn3 will be the same and Vout will be equal to Vin. However, if Rgnd and Agnd are different (almost always), the collector-to-emitter current through the NPN transistors Qn2 and Qn3 will be different, which will have Vout=Vin+(Gm2/ The effect of Gm0)*(Rgnd-Agnd), where Gm2 is the mutual conductance of the transistor Qn2, and Gm0 is the mutual conductance of the transistor Qp0. If Gm2 = Gm0 (this can be achieved by appropriate adjustments in device size), then the equation becomes Vout = Vin + Rgnd - Agnd. Furthermore, if Vout is measured by the associated Agnd, Agnd can be assumed to be zero, and the equation becomes Vout=Vin+Rgnd.

It is also within the scope of embodiments of the present invention to exchange the source connections of the NMOS transistors Mn2 and Mn3 in Figure 3A. More specifically, referring to FIG. 4A, by connecting the source of the transistor Mn2 to Agnd and connecting the source of the transistor Mn3 to Rgnd, Vout=Vin-(Gm2/Gm0)*(Rgnd- Agnd), wherein Gm2 is a mutual conductance of the transistor Mn2, and And Gm0 is a mutual conductance of the transistor Mp0. If Gm2 = Gm0, the equation becomes Vout = Vin - Rgnd + Agnd. Furthermore, if Vout is measured by the associated Agnd, Agnd can be assumed to be zero, and the equation becomes Vout=Vin-Rgnd. In FIG. 4A, the transistors Mp0, Mp1, Mn3, and Mn2 form a dual differential input stage 404a that includes a common source differential input stage 406a in parallel with a common gate differential input stage 408a. In FIG. 4A, the transistor Mn5 provides an output stage 410a, and a compensation network 412a is an amplifier that stabilizes the two stages of the remote differential voltage sensing circuit 402a.

It is also within the scope of an embodiment of the present invention to exchange the emitter connections of the NPN transistors Qn2 and Qn3 in Figure 3B. More specifically, referring to FIG. 4B, by connecting the emitter of the transistor Qn2 to Agnd and connecting the emitter of the transistor Qn3 to Rgnd, Vout=Vin-(Gm2/Gm0)*(Rgnd- Agnd), wherein Gm2 is the mutual conductance of the transistor Qn2, and Gm0 is the mutual conductance of the transistor Qp0. If Gm2 = Gm0, the equation becomes Vout = Vin - Rgnd + Agnd. Furthermore, if Vout is measured by the associated Agnd, Agnd can be assumed to be zero, and the equation becomes Vout=Vin-Rgnd. In FIG. 4B, the transistors Qp0, Qp1, Qn3, and Qn2 form a dual differential input stage 404b that includes a common emitter differential input stage 406b in parallel with a common base differential input stage 408b. In FIG. 4B, the transistor Qn5 is provided with an output stage 410b, and a compensation network 412b is an amplifier of two stages of the differential voltage sensing circuit 402b that stabilizes the far end.

The remote differential voltage sensing circuits 302a and 302b of FIGS. 3A and 3B operate as a voltage adder circuit and may therefore also be referred to as a voltage adder circuit. The remote differential voltage sensing circuits 402a and 402b of Figures 4A and 4B operate as a voltage subtractor circuit and may therefore also be referred to as a voltage subtractor circuit.

In the above embodiment, a remote differential sensing circuit accepts input from a remote ground (Rgnd) and local ground (Agnd) and determines the difference in potential between the two grounds. A difference between Rgnd and Agnd is an operation that compensates for the differential input stage. If Rgnd is larger, the current is adjusted between the left and right branches of the circuit, and the overall feedback is forcing the current in the pair to track this adjustment. For example, in FIG. 3A, when the circuit is operated, a first stage DC current output (which is the current through the source to the drain path of the transistor Mn5) will be due to the feedback relationship. Zero (ie, balanced). The current output from the first stage is Gmp. The AC current generated by Mp1 and Mp0 is (Vin-Vout)*Gmp. The current output applied to the first stage is an AC current generated by Mn2 and Mn3, which is (Rgnd-Agnd)*Gmn. The two AC currents are added together to be equal to zero. By designing Gmp = Gmn, a desired result is achieved, wherein the two Gm levels are fed into each other. In other words, two parallel Gm stages are forced and balanced with each other. Preferably, the Gm of the top and bottom stages should be substantially equal. Since these transistors share the same current, and because they operate in their subcritical operating regions, the Gm is primarily dependent on the current, so it is fairly easy to make the Gms substantially equal. When operating in its secondary critical operating region, the Gm of each transistor is substantially equal to the current divided by a certain fixed voltage (which is the same fixed voltage for each of the transistors). This enables the various Gm to be balanced. This configuration makes the matching of the various Gms more readily available than would otherwise be possible. Usually in order to match two Gm, there is usually a need to match the size ratio of the two devices and the current of the two devices. By definition, the current through the P-type device and the N-type device is matched. The electron mobility in this configuration is a second order, which is advantageous. The selection of the width and length of the transistor is selected to enable operation of the transistor In the next critical section.

FIG. 5A is a depiction of a remote differential voltage sensing circuit 502a in accordance with another embodiment of the present invention. In the embodiment of FIG. 5A, the MOSFET transistors Mp0, Mp1, Mn3, and Mn2 form a dual differential input stage 504a that includes a common source differential in parallel with a common gate differential input stage 508a. Input stage 506a. The common source differential input stage 506a has a differential input, one of the differential inputs is coupled to the voltage input (Vin), and another differential input is coupled to the voltage Output (Vout). The common gate differential input stage 508a has a differential input, one of the differential inputs is coupled to a local ground (Agnd), and the other differential input is coupled to a remote end Ground (Rgnd). In the embodiment of Figure 5A, the transistor Mn3 also functions as an output stage 510a for the remote differential voltage sensing circuit 502a. In Fig. 5A, it is assumed that Gm0 = Gm2, and Vout = Vin-Rgnd + Agnd. If Vout is measured by the associated Agnd, Agnd can be assumed to be zero, and the equation becomes Vout=Vin-Rgnd.

FIG. 5B is a depiction of a remote differential voltage sensing circuit 502b in accordance with another embodiment of the present invention. In the embodiment of FIG. 5B, the BJT transistors Qp0, Qp1, Qn3, and Qn2 form a dual differential input stage 504b that includes a common emitter differential in parallel with a common base differential input stage 508b. Input stage 506b. The common emitter differential input stage 506b has a differential input, one of the differential inputs is coupled to the voltage input (Vin), and another differential input is coupled to the voltage Output (Vout). The common base differential input stage 508b has a differential input, one of the differential inputs is coupled to a local ground (Agnd), and the other differential input is coupled to a remote end Ground (Rgnd). In the embodiment of FIG. 5B, the transistor Qn3 also functions as an output stage of the differential voltage sensing circuit 502b for the remote end. 510b. In FIG. 5B, it is assumed that Gm0=Gm2, and Vout=Vin-Rgnd+Agnd. If Vout is measured by the associated Agnd, Agnd can be assumed to be zero, and the equation becomes Vout=Vin-Rgnd.

It is also within the scope of embodiments of the present invention to exchange the source connections of the NMOS transistors Mn2 and Mn3 in Figure 5A. More specifically, referring to FIG. 6A, by connecting the source of the transistor Mn2 to Agnd and connecting the source of the transistor Mn3 to Rgnd, assuming Gm0 = Gm2, Vout = Vin + Rgnd - Agnd. If Vout is measured by the associated Agnd, Agnd can be assumed to be zero, and the equation becomes Vout = Vin + Rgnd. In the embodiment of FIG. 6A, the MOSFET transistors Mp0, Mp1, Mn3, and Mn2 form a dual differential input stage 604a that includes a common source differential in parallel with a common gate differential input stage 608a. Input stage 606a. The common source differential input stage 606a has a differential input, one of the differential inputs is coupled to the voltage input (Vin), and another differential input is coupled to the voltage Output (Vout). The common gate differential input stage 608a has a differential input, one of the differential inputs is coupled to a local ground (Agnd), and the other differential input is coupled to a remote end Ground (Rgnd). In the embodiment of Figure 6A, the transistor Mn3 also functions as an output stage 610a for the remote differential voltage sensing circuit 602a.

It is also within the scope of an embodiment of the present invention to exchange the emitter connections of the NPN transistors Qn2 and Qn3 in Figure 5B. More specifically, referring to FIG. 6B, by connecting the emitter of the transistor Qn2 to Agnd and connecting the emitter of the transistor Qn3 to Rgnd, assuming Gm0 = Gm2, Vout = Vin + Rgnd - Agnd. If Vout is measured by the associated Agnd, Agnd can be assumed to be zero, and the equation becomes Vout = Vin + Rgnd. In the embodiment of FIG. 6B, the BJT transistors Qp0, Qp1, Qn3, and Qn2 constitute a double differential input. Stage 604b includes a common emitter differential input stage 606b in parallel with a common base differential input stage 608b. The common emitter differential input stage 606b has a differential input, one of the differential inputs is coupled to the voltage input (Vin), and another differential input is coupled to the voltage Output (Vout). The common base differential input stage 608b has a differential input, one of the differential inputs is coupled to a local ground (Agnd), and the other differential input is coupled to a remote end Ground (Rgnd). In the embodiment of Figure 6B, the transistor Qn3 also functions as an output stage 610b for the remote differential voltage sensing circuit 602b.

As used herein, the term "Vin" can be utilized to represent both the input node of a remote differential voltage sensing circuit and the voltage at the input node, depending on the context. In other words, Vin is used to indicate both the input terminal of a circuit and the voltage at the input terminal. Similarly, depending on the context, the term "Vout" can be utilized to represent both the output node of a remote differential voltage sensing circuit and the voltage at the output node. In other words, Vout is used to indicate both the output terminal of a circuit and the voltage at the output terminal. Furthermore, Agnd can be utilized to represent the local ground node and the voltage at the node, and Rgnd can be utilized to represent the ground voltage of the far end and the voltage at the node. Furthermore, I1 represents both a current source and the current generated by the current source; and I2 represents both a current source and the current generated by the current source. From the context in which such terms are used, it will be apparent how such terms are used.

The differential voltage sensing circuit of FIGS. 4A, 4B, 5A, and 5B that generates the distal end of Vout=Vin-Rgnd+Agnd can be utilized in the case where Vin is a voltage relative to the outside of the wafer, and in the wafer There is a requirement for copying Vin. The differential voltage sensing circuit of FIGS. 3A, 3B, 6A, and 6B that generates the far end of Vout=Vin+Rgnd-Agnd can be utilized in Vin. In the case of a voltage relative to the interior of the wafer, and outside the wafer there is a requirement for replicating Vin.

The remote differential voltage sensing circuit described herein senses three inputs, namely Vin, Rgnd and Agnd, and produces a value equal to Vin+Rgnd-Agnd or Vin- depending on the embodiment. The output of Rgnd+Agnd is Vout. The Rgnd and Agnd inputs will typically have a low impedance and are within tens of mV of each other. In the embodiment described herein, a common gate (or common base) differential input stage (eg, 308a, 308b, 408a, 408b, 508a, 508b, 608a, or 608b) is sensed at Rgnd and Agnd. A difference between and produces a compensation current indicative of the difference. The compensation current generated by the differential input stage of the common gate (or common base) is a differential input stage (eg, 306a, 306b, used as a common source (or common emitter), a load of 406a, 406b, 506a, 506b, 606a or 606b), the differential input stage of the common source (or common emitter) sensing the input voltage Vin (higher than ground) and monitoring the Output voltage Vout (also higher than ground). By constructing the differential input stage of the common gate (or common base) to become a feedback amplifier, a difference between the ground potentials Rgnd and Agnd is automatically from the common source ( Or the input of the differential input stage (eg, 306a, 306b, 406a, 406b, 506a, 506b, 606a, or 606b) of the common emitter) is subtracted. Thus, the same current is used to sense the ground potentials Rgnd and Agnd and monitor the feedback, which provides current savings. The entire arithmetic operation Vin+Rgnd-Agnd or Vin-Rgnd+Agnd is four transistors in a double differential input stage (eg, 304a, 304b, 404a, 404b, 504a, 504b, 604a or 604b) That is, Mp0, Mp1, Mn2, and Mn3; or a loop of Qp0, Qp1, Qn2, and Qn3) is achieved, which provides the maximum speed for a given current level.

In another way, the remote differential voltage sensing circuit described herein is Sensing a voltage difference between a remote ground point (Rgnd) and a local ground (Agnd) and applying the voltage difference to a differential input stage of a common gate (or common base) (eg Between the source (or emitter) terminals of 308a, 308b, 408a, 408b, 508a, 508b, 608a or 608b) to facilitate a current imbalance therein. This current imbalance is a differential input stage (eg, 306a, 306b, 406a, 406b, 506a, 506b, 606a, or 606b) applied to a common source (or common emitter) to facilitate interference with the common source The symmetry of the differential input stage (eg, 306a, 306b, 406a, 406b, 506a, 506b, 606a, or 606b) of the pole (or common emitter), and thereby at the common source (or comrade) A voltage offset is generated between the inputs of the differential input stage (eg, the gates of Mp0 and Mp1, or the bases of Qp0 and Qp1).

According to some embodiments, a resistor may be coupled between Rgnd and Agnd to limit the application between the source junctions on the transistors Mn2 and Mn3 (or the emitter junctions on the transistors Qn2 and Qn3). The amount of electrostatic discharge (ESD) stress between the faces. According to other embodiments, a series resistor may be coupled between Rgnd and the source of transistor Mn2 (either between Rgnd and the emitter of transistor Qn2), and another series resistor may be coupled to Agnd Between the source of the transistor Mn3 (or between the emitter of Agnd and the transistor Qn3). Alternatively, any other conventional or non-practical ESD protection techniques can be utilized. According to some embodiments, the body of the transistor M2 is tied to its source, and the body of the transistor M3 is connected to its source.

Certain embodiments of the invention may be utilized to provide an input voltage to an input terminal of a voltage regulator. For example, FIG. 7A depicts a system including a voltage regulator 706 having an input terminal (which may also be referred to as a reference input terminal, or simply referred to as a reference terminal), The input terminal is one of the differential voltage sensing circuits 302a, 302b, 602a or 602b receiving the far end described above with reference to Figures 3A, 3B, 6A and 6B. Output voltage (Vout). The voltage regulator 706 can be, for example, a DC-DC buck converter, but is not limited thereto.

Certain embodiments of the invention may be embodied in a feedback path of a voltage regulator. For example, FIG. 7B depicts a system including a voltage regulator 706 that is fed back to a voltage output (Vout) terminal of the voltage regulator 706 and the voltage regulator 706. The feedback path between the terminals (FB) has one of the remote differential voltage sensing circuits 402a, 402b, 502a or 502b described above with reference to Figures 4A, 4B, 5A and 5B.

Embodiments of the present invention are also directed to generating an output voltage (Vout) equal to an input voltage (Vin) plus or minus a ground (Rgnd) at a far end and a local ground (Agnd) A difference method. This method is summarized in the high-level flow chart of Figure 8. In other words, Figure 8 is a high level flow diagram that is used to summarize the methods in accordance with various embodiments of the present invention. Referring to Figure 8, step 802 is a differential input stage (e.g., 306a, 306b, 406a, 406b, 506a, 506b, 606a, or 606b) that involves applying an input voltage (Vin) to a common source or a common emitter. One of a pair of inputs. Step 804 involves a differential input stage (eg, 308a, 308b, 408a, 408b, 508a, 508b, 608a, or 608b) that utilizes a common gate or a common base to sense grounding at a remote end (Rgnd). A voltage difference from a local ground (Agnd) to facilitate a current imbalance therein. Step 806 is directed to applying a differential input stage (eg, 306a, 306b, 406a, 406b, 506a, 506b, 606a, or 606b) that applies the current imbalance to the common source or common emitter to facilitate interference. The symmetry of the differential input stage of the common source or the common emitter, and thereby generating a voltage offset between the inputs of the pair of differential input stages of the common source or common emitter . Step 808 is directed to using a differential input stage (eg, 306a, 306b, 406a, 406b, 506a, 506b, 606a, or 606b) that utilizes the common source or common emitter as one configured as a single The bit gain voltage is followed by an input stage of the feedback follower of the voltage follower to generate an output voltage (Vout). The circuit of the voltage follower that acts as a unity gain is depicted in Figures 3A, 3B, 4A, 4B, 5A, 5B, 6A, and 6B. In other words, the remote differential voltage sensing circuit described herein can operate as a unity-gain voltage follower.

Although various embodiments of the invention have been described above, it is to be understood that It will be apparent to those skilled in the art that various changes in form and detail can be made therein without departing from the spirit and scope of the invention.

The breadth and scope of the present invention should not be limited to any of the above-described exemplary embodiments, but should be defined only by the scope of the following claims and their equivalents.

302a‧‧‧ Remote differential voltage sensing circuit

304a‧‧‧Dual differential input stage

306a‧‧‧ Common source differential input stage

308a‧‧‧Common differential input stage

310a‧‧‧Output

312a‧‧‧Compensation Network

Claims (21)

A differential voltage sensing circuit comprising a voltage input (Vin) and a voltage output (Vout), comprising: a dual differential input stage comprising a differential with a common gate or a common base The input source is connected in parallel with a common source or a common collector differential input stage; wherein the common source or the common collector differential input stage has a differential input, and one of the differential inputs is coupled to The voltage input (Vin), and another differential input thereof is coupled to the voltage output (Vout); and wherein the differential input stage of the common gate or common base is differential input One of the differential inputs is coupled to a local ground (Agnd), and the other differential input is coupled to a remote ground (Rgnd). The remote differential voltage sensing circuit of claim 1, further comprising: an output stage driven by an output of the dual differential input stage and outputting at the voltage ( An output voltage is generated at Vout). A remote differential voltage sensing circuit as claimed in claim 2, further comprising: a compensation network coupled to said voltage output (Vout) and said output of said dual differential input stage between. A remote differential voltage sensing circuit as claimed in claim 3, wherein the compensation network comprises a series connection of the voltage output (Vout) and the output of the dual differential input stage Capacitors and resistors. A remote differential voltage sensing circuit as claimed in claim 2, further comprising: a first current source biasing said dual differential input stage; A second current source that biases the output stage. The remote differential voltage sensing circuit of any one of claims 1-5, wherein the differential input of the common or common differential input stage is coupled to The local ground (Agnd) and the ground of the far end (Rgnd) are such that Vout = Vin + Rgnd - Agnd. The remote differential voltage sensing circuit of any one of claims 1-5, wherein the differential input of the common or common differential input stage is coupled to The local ground (Agnd) and the ground of the far end (Rgnd) are such that Vout = Vin-Rgnd + Agnd. A differential voltage sensing circuit including a voltage input (Vin) and a voltage output (Vout), comprising: a first transistor (Mp0 or Qp0) having a control terminal (gate or base) And a current path including a first current path terminal (drain or collector) and a second current path terminal (source or emitter), said first transistor (Mp0 or Qp0) a control terminal (gate or base) coupled to the voltage input (Vin); a second transistor (Mp1 or Qp1) having a control terminal (gate or base) and a first a current path terminal (drain or collector) and a current path of a second current path terminal (source or emitter), said control terminal (gate or base) of said second transistor (Mp1 or Qp1) Is coupled to the voltage output (Vout), and the second current path terminal (source or emitter) of the second transistor (Mp1 or Qp1) is coupled to the first transistor a second current path terminal (source or emitter) of (Mp0 or Qp0); a third transistor (Mn3 or Qn3) having a control terminal (gate or base) and a a current path of a first current path terminal (drain or collector) and a second current path terminal (source or emitter), said first current path terminal of said third transistor (Mn3 or Qn3) (bungee or a collector) is the first current path terminal (drain or collector) coupled to the first transistor (Mp0 or Qp0), and the first of the third transistor (Mn3 or Qn3) The two current path terminals (source or emitter) are coupled to a local ground (Agnd); a fourth transistor (Mn2 or Qn2) having a control terminal (gate or base) and a a current path of a first current path terminal (drain or collector) and a second current path terminal (source or emitter), said control terminal of said fourth transistor (Mn2 or Qn2) (gate or a base and a first current path terminal (drain or collector) are coupled to the first current path terminal of the second transistor (Mp1 or Qp1) (drain or Collector), and the second current path terminal (source or emitter) of the fourth transistor (Mn2 or Qn2) is coupled to a remote ground (Rgnd), the fourth transistor The control terminal (gate or base) of (Mn2 or Qn2) is also coupled to the control terminal (gate or base) of the third transistor (Mn3 or Qn3); a fifth transistor (Mn5 or Qn5), which has one a terminal (gate or base) and a current path including a first current path terminal (drain or collector) and a second current path terminal (source or emitter), said fifth transistor ( The control terminal (gate or base) of Mn5 or Qn5) is coupled to the first transistor (Mp0 or Qp0) and the third transistor (Mn3 or Qn3) a first current path terminal (drain or collector), the first current path terminal (drain or collector) of the fifth transistor (Mn5 or Qn5) being coupled to the voltage output (Vout And the second current path terminal (source or emitter) of the fifth transistor (Mn5 or Qn5) is coupled to the local ground (Agnd); and a compensation network coupled Connected between the voltage output (Vout) and the control terminal (gate or base) of the fifth transistor (Mn5 or Qn5); The first and second transistors ((Mp0 or Qp0) and (Mp1 or Qp1)) are PMOS transistors, and the third, fourth, and fifth transistors ((Mn3 or Qn3), (Mn2 or Qn2) and (Mn5 or Qn5)) are NMOS transistors; or the first and second transistors ((Mp0 or Qp0) and (Mp1 or Qp1)) are PNP transistors, and the third, The fourth and fifth transistors ((Mn3 or Qn3), (Mn2 or Qn2), and (Mn5 or Qn5)) are NPN transistors. A remote differential voltage sensing circuit as in claim 8 wherein Vout = Vin + (Gm2 / Gm0) * (Rgnd - Agnd), wherein Gm0 is the first transistor (Mp0 or Qp0) A mutual conductance, and Gm2 is a mutual conductance including the fourth transistor (Mn2 or Qn2). The remote differential voltage sensing circuit of claim 8 or 9, further comprising: a first current source (I1) coupled to a high voltage rail (AVDD) and the first power a crystal (Mp0 or Qp0) and the second current path terminal (source or emitter) coupled together of the second transistor (Mp1 or Qp1); and a second current source (I2), It is coupled between the high voltage rail (AVDD) and the voltage output (Vout). A remote differential voltage sensing circuit as claimed in claim 8 or 9, wherein the compensation network is coupled to the voltage output (Vout) and the fifth transistor (Mn5 or Qn5) Between the control terminals (gate or base), the compensation network includes a control terminal (gate) coupled to the voltage output (Vout) and the fifth transistor (Mn5 or Qn5) Capacitor (C0) between pole or base). A remote differential voltage sensing circuit as claimed in claim 11 wherein said compensation a network is coupled between the voltage output (Vout) and the control terminal (gate or base) of the fifth transistor (Mn5 or Qn5), the compensation network including one and the A capacitor (C0) is coupled in series to a resistor (R0) between the voltage output (Vout) and the control terminal (gate or base) of the fifth transistor (Mn5 or Qn5). A differential voltage sensing circuit including a voltage input (Vin) and a voltage output (Vout), comprising: a first transistor (Mp0 or Qp0) having a control terminal (gate or base) And a current path including a first current path terminal (drain or collector) and a second current path terminal (source or emitter), said first transistor (Mp0 or Qp0) a control terminal (gate or base) coupled to the voltage input (Vin); a second transistor (Mp1 or Qp1) having a control terminal (gate or base) and a first a current path terminal (drain or collector) and a current path of a second current path terminal (source or emitter), said control terminal (gate or base) of said second transistor (Mp1 or Qp1) Is coupled to the voltage output (Vout), and the second current path terminal (source or emitter) of the second transistor (Mp1 or Qp1) is coupled to the first transistor a second current path terminal (source or emitter) of (Mp0 or Qp0); a third transistor (Mn3 or Qn3) having a control terminal (gate or base) and a a current path of a first current path terminal (drain or collector) and a second current path terminal (source or emitter), said first current path terminal of said third transistor (Mn3 or Qn3) (drain or collector) is the first current path terminal (drain or collector) coupled to the first transistor (Mp0 or Qp0), and the third transistor (Mn3 or Qn3) The second current path terminal (source or emitter) is coupled to a remote ground (Rgnd); a fourth transistor (Mn2 or Qn2) having a control terminal (gate or base) and a terminal including a first current path (drain or collector) and a second current path terminal (source or a current path of the emitter, the control terminal (gate or base) of the fourth transistor (Mn2 or Qn2) and the first current path terminal (drain or collector) are coupled together And coupled to the first current path terminal (drain or collector) of the second transistor (Mp1 or Qp1), and the second current path of the fourth transistor (Mn2 or Qn2) The terminal (source or emitter) is coupled to a local ground (Rgnd), and the control terminal (gate or base) of the fourth transistor (Mn2 or Qn2) is also coupled to the a control terminal (gate or base) of a tri-crystal (Mn3 or Qn3); a fifth transistor (Mn5 or Qn5) having a control terminal (gate or base) and a first a current path terminal (drain or collector) and a current path of a second current path terminal (source or emitter), said control terminal (gate or base) of said fifth transistor (Mn5 or Qn5) Is coupled a first current path terminal (drain or collector) coupled to the first transistor (Mp0 or Qp0) and the third transistor (Mn3 or Qn3), the fifth The first current path terminal (drain or collector) of the crystal (Mn5 or Qn5) is coupled to the voltage output (Vout), and the second of the fifth transistor (Mn5 or Qn5) a current path terminal (source or emitter) coupled to the local ground (Agnd); and a compensation network coupled between the voltage output (Vout) and the fifth transistor (Mn5 or Between the control terminals (gate or base) of Qn5); wherein the first and second transistors ((Mp0 or Qp0) and (Mp1 or Qp1)) are PMOS transistors, and the third , fourth and fifth transistors ((Mn3 or Qn3), (Mn2 or Qn2) and (Mn5 or Qn5)) are NMOS transistors; or The first and second transistors ((Mp0 or Qp0) and (Mp1 or Qp1)) are PNP transistors, and the third, fourth, and fifth transistors ((Mn3 or Qn3), (Mn2 or Qn2) and (Mn5 or Qn5)) are NPN transistors. A remote differential voltage sensing circuit as claimed in claim 13 wherein Vout = Vin - (Gm2 / Gm0) * (Rgnd - Agnd), wherein Gm0 comprises the first transistor (Mp0 or Qp0) A mutual conductance, and Gm2 includes a mutual conductance of the fourth transistor (Mn2 or Qn2). The remote differential voltage sensing circuit of claim 13 or 14, further comprising: a first current source (I1) coupled to a high voltage rail (AVDD) and the first power a crystal (Mp0 or Qp0) and the second current path terminal (source or emitter) coupled to the second transistor (Mp1 or Qp1); and a second current source (I2) Connected between the high voltage rail (AVDD) and the voltage output (Vout). A remote differential voltage sensing circuit as claimed in claim 15 wherein said compensation network is coupled to said voltage output (Vout) and said fifth transistor (Mn5 or Qn5) The control network (gate or base) includes a control terminal (gate or Capacitor (C0) between the bases. A remote differential voltage sensing circuit as claimed in claim 16 wherein said compensation network is coupled to said voltage output (Vout) and said fifth transistor (Mn5 or Qn5) Between the control terminals (gate or base), the compensation network includes a capacitor (C0) coupled in series with the voltage output (Vout) and the fifth transistor (Mn5 or Qn5) The control terminal Or the base () between the resistors (R0). A system includes: a voltage regulator comprising a reference terminal, an output terminal, a feedback terminal, a local ground terminal coupled to a local ground (Agnd), and a coupling to a remote end a remote ground terminal of the ground (Rgnd); a remote differential voltage sensing circuit that alternatively provides a voltage to the reference terminal of the voltage regulator, or is connected to an interface a feedback path between the output terminal of the voltage regulator and the feedback terminal; wherein the remote differential voltage sensing circuit includes a dual differential input stage including a common gate Or a common source or a common collector differential input stage in parallel with the differential input stage of the common base; wherein the differential input stage of the common source or the common collector has a differential input, wherein A differential input is a voltage input coupled to the remote differential voltage sensing circuit, and wherein the other differential input is a voltage coupled to the remote differential voltage sensing circuit Output; and wherein the common gate or common base differential transmission Having a differential input stage, a differential input of which is coupled to the local ground (AGND), and further wherein the differential input is coupled to the distal end of the ground (Rgnd). The system of claim 18, wherein the remote differential voltage sensing circuit includes an output stage that is driven by an output of the dual differential input stage. The system of claim 19, further comprising: a compensation network coupled to the voltage output of the differential voltage sensing circuit at the distal end Between the output of the dual differential input stage. A method for generating an output voltage (Vout) equal to an input voltage (Vin) plus or minus a difference between a remote ground (Rgnd) and a local ground (Agnd), The method includes: (a) applying the input voltage (Vin) to an input of a pair of inputs of a common source or a common emitter differential input stage; (b) utilizing a common gate or a total a differential input stage of the base to sense a voltage difference between the ground (Rgnd) of the distal end and the local ground (Agnd) to facilitate generating a current imbalance therein; (c) applying The current is unbalanced to a differential input stage of the common source or common emitter to facilitate interference with a symmetry of the differential input stage of the common source or common emitter, and thereby Generating a voltage offset between the inputs of the pair of differential input stages of the common source or common emitter; and (d) by using the differential input stage of the common source or common emitter as An input stage of a feedback amplifier configured as a unity gain voltage follower to generate the output voltage (Vout).