TW201616928A - Manufacturing method of embedded component package structure - Google Patents

Abstract

A manufacturing method of embedded component package structure including the following steps is provided. A carrier having two opposite surfaces is provided. The carrier has at least two positioning pillars located on one of the surfaces. A stacked component module is disposed on the surface having the at least two positioning pillars, wherein the stacked component module is located between the at least two positioning pillars. A circuit substrate is provided. The circuit substrate includes a first dielectric layer. The first dielectric layer has at least two positioning holes, a through opening and at least one conductive through-via. Each of the at least two positioning pillars is aligned to the corresponding positioning hole and the circuit substrate is disposed on the carrier, so that each of the at least two positioning pillars is embedded into the corresponding positioning hole and the stacked component module is embedded in the through opening.

Description

Buried component packaging structure manufacturing method

The present invention relates to a method of fabricating a package structure, and more particularly to a method of fabricating a buried component package structure.

In general, the circuit substrate is mainly composed of a plurality of patterned patterned circuit layers and a dielectric layer alternately stacked. Wherein, the patterned circuit layer is formed by a copper foil layer through a lithography and etching process, and a dielectric layer is disposed between the patterned circuit layers for isolating the patterned circuit layer. In addition, the stacked patterned circuit layers are electrically connected to each other through a through hole (PTH) or a conductive via that penetrates the dielectric layer. Finally, various electronic components (for example, active components or passive components) are disposed on the surface of the circuit substrate, and electronic signal propagation is achieved by circuit design of the internal circuit.

However, as the market needs to be light, short, and portable for electronic products, in the current electronic products, the original soldering is to the circuit substrate. The upper electronic component is designed as a buried component that can be buried inside the circuit substrate, so that the layout area of the substrate surface can be increased to achieve the purpose of thinning the electronic product. In the fabrication process of the conventional buried component package structure, a through hole or a blind via is usually formed in the dielectric layer, and a single component is buried in the through hole or the blind via. Therefore, when a plurality of components are buried in the same dielectric layer or different dielectric layers, steps of forming vias or blind vias in the dielectric layer and embedding the components in the vias or blind vias are repeated. Not only the production process is complicated, but also the cost of materials. In addition, there is still a gap between the embedded component and the inner sidewall of the through hole or the blind hole. The gap not only affects the bonding between the substrate and the embedded component during pressing, but also affects the alignment of the embedded component and the contact when pressing. Time accuracy.

The invention provides a manufacturing method of a buried component packaging structure, which has a simple manufacturing process, can reduce the manufacturing cost and improve the production yield.

The invention provides a method for fabricating a buried component package structure, which comprises the following steps. First, a carrier plate having opposite surfaces is provided. The carrier has at least two alignment posts on one of the surfaces. The stacked component module is disposed on a surface having the foregoing at least two pairs of pillars, wherein the stacked component module is located between the at least two pairs of the pillars. Next, a circuit substrate is provided. The circuit substrate includes a first dielectric layer, wherein the first dielectric layer has opposite first and second surfaces, at least two alignment holes on the second surface, and through openings through the first surface and the second surface and at least a through hole. Afterwards, align the alignment posts to the corresponding alignment holes and route the base The plate is disposed on the carrier plate such that the respective alignment posts are embedded in the corresponding alignment holes, and the stacked component modules are embedded in the through openings.

In an embodiment of the invention, the method for fabricating the stacked component described above includes the following steps. a. Providing a core board comprising a core dielectric layer and a core metal layer on the core dielectric layer. b. Patterning the core metal layer to form a core circuit layer and forming a plurality of vias in the core dielectric layer. c. forming a glue layer on the core dielectric layer, wherein the glue layer and the core circuit layer are located on opposite sides of the core dielectric layer, and the glue layer covers the through holes. A plurality of components are respectively disposed in the through holes and fixed by the adhesive layer. e. Forming a build-up structure on the core dielectric layer and covering the core circuit layer, the vias, and the components. Next, the above steps a. to e. are repeated to form the first package and the second package, respectively. Thereafter, a plurality of stacked elements are formed using the first package and the second package.

In an embodiment of the invention, the method for fabricating the first package and the second package to form a plurality of stacked components includes the following steps. First, the first package is singulated to form a plurality of first package units. Next, the second package is singulated to form a plurality of second package units. Then, the second package units are turned over so that the glue layers of the respective second loading units face the glue layers of the corresponding first loading units. Afterwards, the glue layers of the second package units are removed, and the first package units are stacked on the corresponding second package unit, wherein the glue layers of the first package units are connected to the core of the corresponding second package unit. Electrical layer.

In an embodiment of the present invention, the e. forming a build-up structure on the core dielectric layer, covering the core circuit layer, the through holes, and the manufacturing method of the components Includes the following steps. First, a build-up dielectric layer and a build-up metal layer are provided, wherein the build-up metal layer is on the surface of the build-up dielectric layer. Next, the build-up dielectric is laminated to the core dielectric layer such that the build-up dielectric layer covers the core circuit layer, the vias, and the components. Thereafter, the metallization layer is patterned to form a build-up wiring layer, and a plurality of conductive vias are formed in the build-up dielectric layer, wherein each of the conductive vias is electrically connected to the build-up wiring layer and the corresponding component.

In an embodiment of the invention, the method for fabricating the above carrier board comprises the following steps. First, a second dielectric layer is provided, wherein the first metal layer and the second metal layer are respectively disposed on opposite surfaces of the second dielectric layer. Thereafter, the first metal layer is patterned to form the aforementioned at least two pairs of pillars.

In an embodiment of the invention, the thickness of the first metal layer is greater than the thickness of the second metal layer.

In an embodiment of the invention, the method for fabricating the above circuit substrate includes the following steps. First, a first dielectric layer, a third metal layer on a first surface of the first dielectric layer, and a fourth metal layer on a second surface of the first dielectric layer are provided. Next, the third metal layer and the fourth metal layer are patterned to form a third wiring layer and a fourth wiring layer, respectively. Then, the at least one via hole penetrating the first surface and the second surface is formed to electrically connect the third circuit layer and the fourth circuit layer. Thereafter, the at least two alignment holes on the second surface are formed, and a through opening penetrating the first surface and the second surface is formed.

In an embodiment of the invention, after the stacked component disposed on the carrier is embedded in the recess, the following steps are further included. First, a third dielectric layer is formed And a fifth metal layer on the first surface of the first dielectric layer, wherein the third dielectric layer covers the first surface of the first dielectric layer, the third circuit layer, the at least one via hole, the through opening and the stacked component Module. Then, the fifth metal layer is patterned to form a fifth circuit layer, and at least one first conductive via hole is formed on the third dielectric layer to electrically connect the fifth circuit layer and the third circuit layer. Thereafter, the second metal layer is patterned to form a second circuit layer, and at least one second conductive via is formed on the second dielectric layer to electrically connect the second circuit layer and the fourth circuit layer.

In an embodiment of the invention, the method for fabricating the embedded component package structure further includes the following steps. First, a fourth dielectric layer and a sixth circuit layer are formed on the second dielectric layer, wherein the fourth dielectric layer has at least one third conductive via hole to electrically connect the sixth circuit layer and the second circuit layer. Next, a fifth dielectric layer and a seventh circuit layer are formed on the third dielectric layer, wherein the fifth dielectric layer has at least one fourth conductive via hole to electrically connect the seventh circuit layer and the fifth circuit layer. Thereafter, a first solder mask layer is formed on the fourth dielectric layer and the sixth circuit layer, and the at least one third conductive via hole is exposed. Forming a second solder mask layer on the fifth dielectric layer and the seventh circuit layer, and exposing the at least one fourth conductive via hole.

In an embodiment of the invention, the number of the alignment holes is set corresponding to the alignment pillar.

Based on the above, the method for fabricating the embedded component package structure of the present invention is a step of stacking components to be buried in the circuit substrate, wherein the number of components in the stacked component module can be adjusted according to design requirements, It can improve the flexibility of the process and the integrity of the package. Next, the stacked components are placed in A carrier plate with a counter column, wherein the alignment column can be used as a registration reference point for subsequent packaging. On the other hand, the circuit substrate has a through opening for accommodating the stacked component module and a matching hole disposed on the side of the groove and corresponding to the alignment post, thereby burying the stacked component module disposed on the carrier In the through-opening of the circuit substrate, the alignment pillar may be aligned with the alignment hole and the circuit substrate is disposed on the carrier board, so that the alignment pillar is embedded in the alignment hole, and the stacked component module is buried in the groove. In order to improve the accuracy of the package alignment. In general, the method for fabricating the embedded component package structure of the present invention not only has a relatively simple manufacturing process, but also improves production yield, efficiency, and production cost.

The above described features and advantages of the invention will be apparent from the following description.

1‧‧‧Internal component package structure

10‧‧‧ core board

11, 11'‧‧‧ core dielectric layer

11a‧‧‧ upper surface

12‧‧‧ core metal layer

12a‧‧‧core circuit layer

13, 13’‧‧‧Tongkong

14, 14'‧‧‧ glue layer

15, 15' ‧ ‧ components

15a‧‧‧ pads

16‧‧‧Additional structure

17‧‧‧Additional dielectric layer

17a, 31a, 31b‧‧‧ surface

17b, 17c‧‧‧ vias

18‧‧‧Additional metal layer

18a‧‧‧Additional circuit layer

19a‧‧‧First package

19b‧‧‧Second package

19c‧‧‧First package unit

19d‧‧‧Second package unit

20‧‧‧Stacking component module

30‧‧‧ Carrier Board

31‧‧‧Second dielectric layer

32‧‧‧First metal layer

32a‧‧‧ alignment column

33‧‧‧Second metal layer

33a‧‧‧Second circuit layer

34‧‧‧Second conductive blind hole

40‧‧‧Line substrate

41‧‧‧First dielectric layer

41a‧‧‧ first surface

41b‧‧‧ first surface

42‧‧‧ Third metal layer

42a‧‧‧ third circuit layer

43‧‧‧Fourth metal layer

43a‧‧‧4th circuit layer

44‧‧‧through holes

45‧‧‧ alignment hole

46‧‧‧through opening

51‧‧‧ Third dielectric layer

52‧‧‧ fifth metal layer

52a‧‧‧ fifth circuit layer

53‧‧‧First conductive blind hole

55a‧‧‧4th dielectric layer

55b‧‧‧ sixth circuit layer

55c‧‧‧3rd conductive blind hole

56a‧‧‧ fifth dielectric layer

56b‧‧‧ seventh circuit layer

56c‧‧‧4th conductive blind hole

57‧‧‧First welding cap

58‧‧‧Second welding cap

1A to 1H are schematic diagrams showing a manufacturing process of a stacked component according to an embodiment of the present invention.

2A to 2B are schematic views showing a manufacturing process of a carrier board according to an embodiment of the present invention.

3A to FIG. 3G are schematic diagrams showing the manufacturing process of the stacked component of FIG. 1H after being disposed on the carrier of FIG. 2B and buried in the circuit substrate.

1A to 1H are diagrams showing a manufacturing process of a stacked component according to an embodiment of the present invention. schematic diagram. First, referring to FIG. 1A, a core board 10 is provided that includes a core dielectric layer 11 and a core metal layer 12 on the core dielectric layer 11. The material of the core dielectric layer 11 may be epoxy resin, glass fiber or glass epoxy resin, and the core metal layer 12 may be made of copper, but the invention is not limited thereto.

Next, referring to FIG. 1B, the core metal layer 12 is patterned to form the core wiring layer 12a, and a plurality of through holes 13 are formed in the core dielectric layer 11. The manner of patterning the core metal layer 12 may include a photolithography process. The manner in which the through holes 11b are formed may include laser drilling or mechanical drilling. Next, a glue layer 14 is formed on the core dielectric layer 11, wherein the glue layer 14 can be a polyimide film (or film), a vinyl tape (or film) or a cellophane tape (or film), but the invention Not limited to this. In detail, the glue layer 14 and the core circuit layer 12a are located on opposite sides of the core dielectric layer 11, and the glue layer 14 covers the through holes 13. That is, the through holes 13 expose only the opening adjacent to the side where the core wiring layer 12a is located for use in subsequent processes.

Next, referring to FIG. 1C, a plurality of components 15, such as passive components or active components, are disposed in the through holes 13, respectively. At this time, the component 15 can be bonded to the adhesive layer 14 and adhered to the through hole 13 through the adhesive layer 14, thereby preventing the component 15 from being displaced in the subsequent process. On the other hand, the pads 15a of the component 15 are substantially coplanar with the upper surface 11a of the core dielectric layer 11. Next, referring to FIG. 1D and FIG. 1E, a build-up structure 16 is formed on the core dielectric layer 11 and covers the core circuit layer 12a, the via 13 and the component 15. Specifically, the build-up structure 16 is formed by first providing a build-up dielectric layer 17 and a build-up metal layer 18, wherein the build-up metal layer 18 is on the surface 17a of the build-up dielectric layer 17. Next, the build-up dielectric layer 17 is pressed to the core dielectric layer 11, The build-up dielectric layer 17 covers the core circuit layer 12a, the through holes 13, and the elements 15. Generally, the material of the build-up dielectric layer 17 may be a polyimide, a polydimethylsiloxane or an ABF film, and an ABF film is preferred, so that the build-up dielectric layer 17 is pressed to the core. The electric layer 11 can be filled into the through hole 13 and cover the element 15 in the through hole 13 to firmly embed the element 15 in the core dielectric layer 11. Thereafter, the build-up metal layer 18 is patterned to form the build-up wiring layer 18a, and a plurality of conductive vias 17b are formed in the build-up dielectric layer 17, wherein each of the conductive vias 17b is electrically connected to the layer of the build-up line 18a and the corresponding layer Element 15. Next, the fabrication steps of FIGS. 1A to 1E are repeated to form a first package 19a and a second package 19b (shown in FIG. 1G), respectively.

Thereafter, the first package body 19a and the second package body 19b are used to form a plurality of stacked component modules 20, and the manufacturing steps thereof are as shown in FIGS. 1F to 1H. First, the first package 19a is singulated to form a plurality of first package units 19c, and the second package 19b is singulated to form a plurality of second package units 19d. In general, the singulation process can be accomplished by laser cutting, and between the center axis of one of the two adjacent through holes 13 (not shown) and the predetermined cutting line (not shown). The distance and the distance between the other central axis (not shown) of any two adjacent through holes 13 and the predetermined cutting line (not shown) are substantially equal. On the other hand, the first package unit 19c can be connected to each other through the adhesive layer 14, and the second package unit 19d can be connected to each other through the adhesive layer 14'. Next, the second package units 19d are turned over so that the glue layer 14' faces the glue layer 14. Thereafter, the adhesive layer 14' is removed and the respective first package units 19c are stacked on the corresponding second package unit 19d, wherein the glue layer 14 is connected to the core dielectric layer 11' of the corresponding second package unit 19d. Having the first package unit 19c and the corresponding second package unit 19d glued to fix. At this time, the elements 15 of the respective first package units 19c are juxtaposed with the elements 15' of the corresponding second package unit 19d, and the central axis (not shown) of the through holes 13 of the core dielectric layer 11 and the core dielectric The central axis (not shown) of the through hole 13' of the layer 11' is coaxial. Moreover, the glue layer 14 connecting the first package units 19c can be separated into a plurality of segments after being applied, and is bonded between the first package unit 19c and the corresponding second package unit 19d. So far, a plurality of stacked component modules 20 (one of which is schematically illustrated in FIG. 1H) stacked by the respective first package units 19c and the corresponding second package units 19d have been substantially completed.

It should be noted that the present invention is not limited to the manufacturing steps of forming the plurality of stacked component modules 20 by using the first package 19a and the second package 19b as shown in FIG. 1F to FIG. 1H. In the embodiment, the second package 19b may be flipped before the first package 19a and the second package 19b are singulated, so that the glue layer 14' of the second package 19b faces the first package. The glue layer 14 of the body 19a. Next, the adhesive layer 14' is removed, and the first package 19a is stacked on the second package 19b, wherein the adhesive layer 14 is bonded to the core dielectric layer 11' of the second package 19b. Thereafter, a singulation process is performed to cut the stacked first package body 19a and the second package body 19b along a predetermined cutting line (not shown), thereby dividing the plurality of stacked element modules 20.

2A to 2B are schematic views showing a manufacturing process of a carrier board according to an embodiment of the present invention. Referring to FIG. 2A to FIG. 2B, first, a second dielectric layer 31 is provided, wherein the first metal layer 32 and the second metal layer 33 are respectively disposed on the opposite surfaces 31a, 31b of the second dielectric layer 31, and The thickness of a metal layer 32 is, for example, greater than the thickness of the second metal layer 33. Thereafter, the first metal layer 32 is patterned to form at least two pairs of pillars 32a (two are schematically depicted in Figure 2B) and expose portions of surface 31a. So far, the production of the carrier 30 has been substantially completed.

3A to FIG. 3G are schematic diagrams showing the fabrication process of the stacked substrate of FIG. 1H after being disposed on the carrier of FIG. 2B and embedded in the circuit substrate, wherein FIGS. 3A to 3C illustrate the steps of fabricating the circuit substrate 40. Referring to FIG. 3A to FIG. 3C, first, a first dielectric layer 41 is provided, wherein the first dielectric layer 41 has opposite first and second surfaces 41a, 41b, and the first surface 41a and the second surface 41b. A third metal layer 42 and a fourth metal layer 43 are formed, respectively. Next, the third metal layer 42 and the fourth metal layer 43 are patterned to form a third wiring layer 42a and a fourth wiring layer 43a, respectively. Next, at least one via hole 44 (two are schematically shown in FIG. 3C) penetrating through the first surface 41a and the second surface 41b is formed to electrically connect the third wiring layer 42a and the fourth wiring layer 43a. Thereafter, at least two alignment holes 45 (two are schematically illustrated in FIG. 3C) on the second surface 41b are formed, and a through opening 46 penetrating the first surface 41a and the second surface 41b is formed. So far, the fabrication of the circuit substrate 40 has been substantially completed.

Generally, the via hole 44, the alignment hole 45 and the through hole 46 may be formed by laser drilling or mechanical drilling, wherein the via hole 44 is formed after the through hole is formed in the first dielectric layer 41. And then made by electroplating copper or other conductive material (for example, conductive paste) filled in the through hole.

Next, referring to FIG. 3D, the stacked component module 20 is disposed on the surface 31a of the carrier 30 having the alignment pillar 32, wherein the stacked component module 20 is located, for example, between the two alignment pillars 32a. Here, the number of the alignment holes 45 is set corresponding to the alignment pillars 32a, and the depth of each of the alignment holes 45 is substantially equal to the corresponding alignment pillar 32a. the height of. On the other hand, each of the alignment posts 32a is aligned with the corresponding alignment holes 45, and the circuit substrate 40 is disposed on the carrier 30 so that the respective alignment posts 32a are embedded in the corresponding alignment holes 45, and the stacked components are stacked. The module 20 is embedded in the through opening 46. At this time, the fourth wiring layer 43a is connected to the surface 31a of the second dielectric layer 31. In short, in the above manufacturing step, the alignment of the alignment pillar 32a and the alignment hole 45 can be transmitted to improve the accuracy of the package alignment.

Next, referring to FIG. 3E, a third dielectric layer 51 and a fifth metal layer 52 are formed on the first surface 41a of the first dielectric layer 41, wherein the third dielectric layer 51 covers the first surface 41a and the third surface. The wiring layer 42a, the via hole 44, the through opening 46, and the stacked component module 20. Generally, the material of the third dielectric layer 51 may be a polyimide, a polydimethyl siloxane or an ABF film, and an ABF film is preferred, so when the third dielectric layer 51 is pressed to the first The first surface 41a of the dielectric layer 41 can be filled into the via hole 44 and the through opening 46, and covers the stacked component module 20 in the through opening 46, thereby firmly burying the stacked component module 20 in the first Dielectric layer 41.

Next, referring to FIG. 3F, the fifth metal layer 52 is patterned to form a fifth wiring layer 52a, and at least one first conductive blind via 53 (a plurality of FIG. 3F is illustrated) is electrically formed on the third dielectric layer 51. The fifth wiring layer 52a and the third wiring layer 42a and the conductive via 17b are connected. On the other hand, the second metal layer 33 is patterned to form the second wiring layer 33a, and at least one second conductive blind via 34 (shown in FIG. 3F) is electrically connected to the second dielectric layer 31. The second wiring layer 33a and the fourth wiring layer 43a and the conductive via 17c.

Finally, referring to FIG. 3G, a fourth dielectric layer 55a and a sixth circuit layer are formed. 55b is on the second dielectric layer 31, wherein the fourth dielectric layer 55a has at least one third conductive blind via 55c (shown in FIG. 3G) to electrically connect the sixth circuit layer 55b and the second circuit layer. 33a and a second conductive via 34. On the other hand, the fifth dielectric layer 56a and the seventh wiring layer 56b are formed on the third dielectric layer 51, wherein the five dielectric layers 56a have at least one fourth conductive blind via 56c (a plurality of FIG. 3G is illustrated) The seventh circuit layer 56b and the fifth circuit layer 52a and the first conductive blind via 53 are electrically connected. In general, to prevent the occurrence of line mis-welding, the first solder mask layer 57 may be formed on the fourth dielectric layer 55a and the sixth wiring layer 55b, and only the third conductive blind via 55c may be exposed. Similarly, a second solder mask layer 58 is formed on the fifth dielectric layer 56a and the seventh wiring layer 56b, and only the fourth conductive via hole 56c is exposed. So far, the fabrication of the buried component package structure 1 has been substantially completed.

In summary, the method for fabricating the embedded component package structure of the present invention is a step of stacking components to be buried in a circuit substrate, wherein the number of components in the stacked component module can be adjusted according to design requirements. Therefore, the flexibility of the process and the integrity of the package can be improved. Next, the stacked components are disposed on the carrier having the alignment pillars, wherein the alignment pillars can serve as alignment reference points for subsequent packaging. On the other hand, the circuit substrate has a through opening for accommodating the stacked component and a registration hole disposed on the side of the through opening and corresponding to the alignment post, thereby embedding the stacked component module disposed on the carrier on the line When the substrate is penetrated through the opening, the alignment pillar can be aligned with the alignment pillar hole and the circuit substrate is disposed on the carrier plate, so that the alignment pillar is embedded in the alignment pillar hole, and the stacked component module is buried in the substrate. In the groove, to improve the accuracy of the package alignment. In general, the embedded component package of the present invention The method of fabricating the structure not only has a relatively simple production process, but also improves the production yield, efficiency, and production cost.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

1‧‧‧Internal component package structure

20‧‧‧Stacking component module

30‧‧‧ Carrier Board

31‧‧‧Second dielectric layer

32a‧‧‧ alignment column

33a‧‧‧Second circuit layer

34‧‧‧Second conductive blind hole

40‧‧‧Line substrate

41‧‧‧First dielectric layer

42a‧‧‧ third circuit layer

43a‧‧‧4th circuit layer

44‧‧‧through holes

45‧‧‧ alignment hole

46‧‧‧through opening

51‧‧‧ Third dielectric layer

52a‧‧‧ fifth circuit layer

53‧‧‧First conductive blind hole

55a‧‧‧4th dielectric layer

55b‧‧‧ sixth circuit layer

55c‧‧‧3rd conductive blind hole

56a‧‧‧ fifth dielectric layer

56b‧‧‧ seventh circuit layer

56c‧‧‧4th conductive blind hole

57‧‧‧First welding cap

58‧‧‧Second welding cap

Claims (10)

A method of fabricating a buried component package structure includes: providing a carrier having opposite surfaces, the carrier having at least two alignment posts on one of the two surfaces; and setting a stacked component module On the surface having the at least two pairs of pillars, wherein the stacked component module is located between the at least two pairs of pillars; providing a circuit substrate comprising a first dielectric layer, wherein the first dielectric layer Having a first surface and a second surface, at least two pairs of holes on the second surface, and a through opening and at least one through hole extending through the first surface and the second surface; Positioning the column on the corresponding alignment hole, and arranging the circuit substrate on the carrier, so that each of the alignment posts is embedded in the corresponding alignment hole, and the stacked component module is embedded in the through opening Inside. The manufacturing method of the embedded component package structure according to claim 1, wherein the method for fabricating the stacked component module comprises: a. providing a core board, including a core dielectric layer and a dielectric layer located at the core a core metal layer on the layer; b. patterning the core metal layer to form a core circuit layer, and forming a plurality of through holes in the core dielectric layer; c. forming a glue layer on the core dielectric layer, Wherein the adhesive layer and the core circuit layer are located on opposite sides of the core dielectric layer, and the adhesive layer covers the through holes; d. a plurality of components are respectively disposed in the through holes, and the adhesive layer is Fixed e. forming a build-up structure on the core dielectric layer, and covering the core circuit layer, the through holes and the components; repeating the steps a. to e. to form a first package and a a second package; and forming a plurality of the stacked component modules by using the first package and the second package. The manufacturing method of the embedded component package structure according to the second aspect of the invention, wherein the method for manufacturing the plurality of the stacked component modules by using the first package and the second package comprises: singulation The first package body is formed to form a plurality of first package units; the second package body is singulated to form a plurality of second package units; and the second package units are turned over to make the glue layer of each of the second package units And facing the corresponding layer of the first loading unit; and removing the glue layer of each of the second loading units, and stacking the first packaging units on the corresponding second packaging unit, wherein each of the layers The glue layer of the first package unit is connected to the corresponding core dielectric layer of the second package unit. The method for fabricating a buried component package structure according to claim 2, wherein e. forming the buildup structure on the core dielectric layer, covering the core circuit layer, the through holes, and the The method of manufacturing the device includes: providing a build-up dielectric layer and a build-up metal layer, wherein the build-up metal layer is on a surface of the build-up dielectric layer; and the build-up dielectric is laminated to the core a dielectric layer to cover the build-up dielectric layer Covering the core circuit layer, the through holes and the components; and patterning the build-up metal layer to form a build-up wiring layer, and forming a plurality of conductive vias in the build-up dielectric layer, wherein each of the conductive vias The holes are electrically connected to the build-up wiring layer and the corresponding component. The method of fabricating a buried component package structure according to claim 1, wherein the method of fabricating the carrier comprises: providing a second dielectric layer, wherein the opposite surfaces of the second dielectric layer are respectively A first metal layer and a second metal layer are disposed; and the first metal layer is patterned to form the at least two pairs of pillars. The method of fabricating a buried component package structure according to claim 5, wherein the thickness of the first metal layer is greater than the thickness of the second metal layer. The method of fabricating a buried component package structure according to claim 5, wherein the method of fabricating the circuit substrate comprises: providing the first dielectric layer on the first surface of the first dielectric layer a third metal layer and a fourth metal layer on the second surface of the first dielectric layer; patterning the third metal layer and the fourth metal layer to form a third circuit layer and a fourth circuit layer; the at least one via hole penetrating the first surface and the second surface to electrically connect the third circuit layer and the fourth circuit layer; and forming the at least the second surface Two alignment holes and forming the through opening through the first surface and the second surface. The method of manufacturing the embedded component package structure according to claim 7, wherein after the stacked component module disposed on the carrier is embedded in the through opening, the method further comprises: forming a third a dielectric layer and a fifth metal layer on the first surface of the first dielectric layer, wherein the third dielectric layer covers the first surface of the first dielectric layer, the third circuit layer, At least one via hole, the through opening and the stacked component; patterning the fifth metal layer to form a fifth circuit layer, and forming at least one first conductive blind via to electrically connect the third dielectric layer a fifth wiring layer and the third wiring layer; and patterning the second metal layer to form a second wiring layer, and forming at least one second conductive blind via to the second dielectric layer to electrically connect the second wiring a layer and the fourth circuit layer. The method for fabricating a buried component package structure according to claim 8 , further comprising: forming a fourth dielectric layer and a sixth circuit layer on the second dielectric layer, wherein the fourth dielectric layer The electrical layer has at least one third conductive via hole electrically connected to the sixth circuit layer and the second circuit layer; forming a fifth dielectric layer and a seventh circuit layer on the third dielectric layer, wherein The fifth dielectric layer has at least one fourth conductive via hole electrically connected to the seventh circuit layer and the fifth circuit layer; and a first solder mask layer is formed on the fourth dielectric layer and the sixth Forming, on the circuit layer, the at least one third conductive via hole to form a second solder mask layer on the fifth dielectric layer And the seventh circuit layer and exposing the at least one fourth conductive blind hole. The method of fabricating a buried component package structure according to claim 1, wherein the number of the alignment holes is set corresponding to the alignment pillars.