TW201616622A - Non-sticking testing method and substrate used by the method - Google Patents

Abstract

A packaging substrate includes: a substrate body having a packaging region and a testing region; a non-sticking part disposed on the testing region and having a plurality of conductive traces; and an interconnection circuit extending from the packaging region to the testing region and connected to the non-sticking part. The non-sticking part, since having the conductive traces, has its position that is not restricted. Therefore, the circuit layout design has an improved elasticity. The present invention further provides a non-sticking testing method.

Description

No need to detect the test method and the substrate used

The present invention relates to the detection of a packaging process, and more particularly to a non-Sticking test method and a substrate for use therewith.

As electronic products move toward versatility and mobility, semiconductor packaging technology has evolved to a high-density chip scale package (CSP). In the development of this packaging technology, the ball grid array package has become the most important packaging method at present, and the ball grid array package with Multi-Chip Module (MCM) is more important. During the packaging process, a so-called non-Sticking test is usually performed to know whether the electrical connection between the wafer and the substrate is good.

Figure 1A is a top plan view of a conventional multi-chip package substrate. As shown in FIG. 1A, the package substrate 1 defines at least one package area 11 (within a dotted line) and at least one detection area 12 (outside of a broken line). The package area 11 is provided with a plurality of wafer holders 111, 112, 113, 114 and a plurality of interconnection lines 111a, 112a, 113a, 114a. The detecting area 12 is provided with a plurality of metal pieces 121, 122, 123, 124, and each of the metal pieces 121, 122, 123, 124 is respectively The interconnection lines 111a, 112a, 113a, 114a are electrically connected to the wafer holders 111, 112, 113, 114.

After the wafers (not shown) are respectively disposed on the wafer holders 111, 112, 113, 114, a wire bonding process (or a flip chip process) is performed, and the wafers are electrically connected to the interconnection lines 111a, 112a, 113a around the wafer pads 111, 112, 113, 114, 114a. In order to know whether the electrical connection between the wafer and the package substrate 1 is off-line or off-ball (that is, the yield of electrical bonding), it is necessary to perform the detection test.

It is not known that the test system separately applies current to the wafer, and then indirectly determines whether the current can be separately measured in the test points (ie, the metal sheets 121, 122, 123, 124) to indirectly determine the wafer and the bonding wire (or solder balls). The advantages and disadvantages of the electrical connection.

Specifically, as shown in FIGS. 1B and 1C, current is applied to each of the wafers, and the elastic piece 10 of the hot platen 10 sequentially contacts the metal pieces 121, 122, 123, 124 with the contact rods 1011 to determine whether the metal pieces 121, 122, 123, 124 are respectively A current is generated to determine the yield of the electrical contact between each wafer and the package substrate 1.

However, it is not known to detect the test method, the functional circuits of various electronic products have packages of different sizes or different wiring designs, so that the positions of the metal pieces 121, 122, 123, 124 need to be changed with different packages, so that The positions of the metal sheets 121, 122, 123, and 124 on the package substrate 1 are limited, causing troubles in the layout design of the package substrate 1.

Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

The present invention provides a substrate for packaging, comprising: a substrate body having a package area and a detection area; at least one detection portion is disposed on the detection area, and the The detecting portion is formed by a plurality of conductive traces; and at least one interconnecting line is formed on the substrate body and extends from the package region to the detecting region to connect the detecting portion.

The present invention provides a packaging process that does not detect the test method, comprising: disposing at least one electronic component on the package area of the foregoing package substrate, and the electronic component is electrically connected to the interconnection line; The contact contacts the conductive traces; and energizes the electronic component, and the detecting device measures whether the current passes through the conductive traces to determine whether the electrical connection between the electronic component and the interconnect is good.

In the foregoing test method, a single contact portion simultaneously contacts at least two of the conductive traces.

In the aforementioned test method, the contact portion is a sheet.

In the aforementioned test method and the substrate used therewith, the detection zone surrounds the package area.

In the aforementioned test method and the substrate used therewith, the conductive traces are parallel to each other.

The foregoing test method and the substrate used therein include a plurality of metal sheets disposed on the detection area, and the non-detection portion is located between the two metal sheets. For example, the conductive traces contact the metal sheet.

As can be seen from the above, the present invention does not detect the test method and the basis used therein. The board is formed by a plurality of conductive traces without a detecting portion, so that the position of the substrate body without the detecting portion can be unrestricted, thereby improving the flexibility of the line layout design and improving the accuracy of the detection. .

1‧‧‧Package substrate

10,3‧‧‧Hot platen

101, 30‧‧ ‧ shrapnel

1011‧‧‧Contact rod

11‧‧‧Package area

111,112,113,114‧‧‧ wafer holder

111a, 112a, 113a, 114a‧‧‧ interconnection

12‧‧‧Detection area

121,122,123,124‧‧‧metal pieces

2‧‧‧Substrate

20‧‧‧Substrate body

200,200’‧‧· solder pads

201‧‧‧Package area

2011‧‧‧Settings

202‧‧‧Detection area

21‧‧‧Interconnection lines

22,22’‧‧‧Without the inspection department

220‧‧‧conductive traces

23‧‧‧metal pieces

300‧‧‧Contacts

4,4’‧‧‧Electronic components

1A is a top view of a conventional multi-chip package substrate; FIG. 1B is a schematic diagram of a conventional test method; FIG. 1C is a partial top view of FIG. 1B; and FIG. 2 is a package for the present invention. The top view of the substrate is omitted; the 3A is a perspective view of the test method without the detection method; and the 3B is a partial side view of the 3A.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper" and "one" as used in the specification are merely for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship is changed or adjusted. real The scope of the quality change technology is also considered to be within the scope of the invention.

As shown in Fig. 2, the package substrate 2 of the present invention comprises a substrate body 20, a plurality of interconnection lines 21, 21', a plurality of detection portions 22, 22', and a plurality of metal sheets 23.

The substrate body 20 has a package area 201 (dashed line in the figure)---"inner" and a detection area 202 (dashed line in the figure)---"outside", and the detection area 202 surrounds the package area. 201.

The interconnection lines 21, 21' are formed on the substrate body 20 and extend from the package area 201 to the detection area 202 to connect the detection portions 22, 22'.

The non-detection portions 22, 22' are disposed on the detection region 202, and the single non-detection portion 22 is composed of a plurality of conductive traces 220, as shown in the figure.

The metal piece 23 is disposed on the detecting area 202, and the detecting portion 22, 22' is located between the two metal sheets 23. In various aspects, the conductive traces 220 may contact the metal sheet 23 or the non-detection portion 22' may not contact the metal sheet 23.

In this embodiment, the substrate 2 can be a ball grid array package substrate, but not limited thereto, and the package region 201 can include a plurality of crystal places 2011 (dotted line in the figure)---"divided" The seeding portions 2011 are arranged in an array, and the substrate body 20 is formed with various functional circuits such as pads 200, 200'.

Moreover, the interconnecting lines 21, 21' are disposed at the crystallizing portion 2011 to electrically connect the pads 200, 200', and the interconnecting lines 21 can be independently connected. The detecting portion 22 is not provided; or, the plurality of interconnecting lines 21, 21' can be connected to the detecting portion 22' in common.

Moreover, the conductive traces 220 are disposed in the detection region 202 in parallel with each other.

In addition, the metal piece 23 is located at the position of the mold gate of the packaging process.

Therefore, the conductive traces 220 constitute the non-detection portions 22, 22', so that the positions of the non-detection portions 22, 22' are not restricted by the position of the wafer, so the wiring on the substrate body 20 Flexible design for different chip package needs.

When the test method is not performed, an electronic component 4 is first disposed on the seeding portion 2011 of the package region 201, and the electronic component 4 and the pads 200 are electrically connected by a wire bonding process, thereby electrically conducting. The electronic component 4 and the interconnecting line 21; a plurality of electronic components 4' may be disposed on the crystallizing portion 2011, and the electronic components 4' and the interconnecting lines 21 are electrically connected by a flip chip process. In this embodiment, the electronic components 4, 4' are active components such as semiconductor wafers or passive components such as resistors, capacitors, and inductors. Furthermore, the pads 200' are arranged for single wafer flipping; if used for a plurality of wafers, the extents of the pads 200' are reduced and divided into four regions (there are still nine pads in each region) 200'), can be used for flip chip of four wafers in the figure.

Next, the hot plate 3 of a detecting device is disposed on the substrate body 20, and the contact portion 300 of the elastic piece 30 on the hot plate 3 contacts the conductive traces 220, as shown in FIGS. 3A and 3B. (Electronic component 4 after the wire bonding process is omitted). In this embodiment, the single contact portion 300 is connected at the same time. At least two of the conductive traces 220 are touched, and the contact portion 300 is a sheet body. Therefore, the contact portion 300 can contact the plurality of conductive traces 220 by the design of the plurality of conductive traces 220 and the contact portion 300. Easy to positional contact to improve the accuracy of the test.

After the current is introduced into the electronic component 4, the detecting device measures whether the current passes through the conductive traces 220 to directly determine whether the electrical connection between the bonding pad 200 and the interconnection 21 is good. In fact, it is indirectly determined whether the electrical connection between the electronic component 4 and the pad 200 is good. In short, it is determined whether the electrical connection between the electronic component 4 and the interconnection 21 is good. However, when the current is not turned on by the detecting portion 22, it means that there is no electrical connection abnormality such as off-line (or off-ball) between the electronic component 4 and the pad 200, and vice versa.

In summary, the present invention does not detect the test method and the substrate used therein, and the main conductive traces are not formed by the plurality of conductive traces, so that the position of the substrate without the detection portion can be unrestricted. Therefore, the flexibility of the layout design can be improved, and the accuracy of the detection can be improved.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧Substrate

20‧‧‧Substrate body

200,200’‧‧· solder pads

201‧‧‧Package area

2011‧‧‧Settings

202‧‧‧Detection area

21‧‧‧Interconnection lines

22,22’‧‧‧Without the inspection department

220‧‧‧conductive traces

23‧‧‧metal pieces

4,4’‧‧‧Electronic components

Claims (12)

A package substrate includes: a substrate body defining a package area and a detection area; at least one detection portion is disposed on the detection area, and the detection portion is composed of a plurality of conductive traces And the at least one interconnection line is formed on the substrate body and extends from the package area to the detection area to connect the detection portion. The package substrate according to claim 1, wherein the detection area surrounds the package area. The package substrate according to claim 1, wherein the conductive traces are parallel to each other. The package substrate according to claim 1, further comprising a plurality of metal sheets disposed on the detection area, and the non-detection portion is located between the two metal sheets. The package substrate of claim 4, wherein the conductive traces contact the metal sheet. A method for detecting a package without a detection method, comprising: disposing at least one electronic component on a package area of a package substrate as described in claim 1 of the patent application, and electrically connecting the electronic component to the interconnection; Contacting the conductive traces with the contact portion of the detecting device; and energizing the electronic component, and measuring whether the current passes through the conductive traces by the detecting device to determine whether the electronic component and the interconnecting line are electrically connected connection. The test method is not detected as described in claim 6 of the scope of the patent application, wherein the detection zone surrounds the package area. The test method is not detected as described in claim 6 of the patent application, wherein the conductive traces are parallel to each other. If the test method is not detected as described in claim 6 of the patent application, the plurality of metal sheets are disposed on the detection area, and the non-detection portion is located between the two metal sheets. The test method is not detected as described in claim 9 of the patent application, wherein the conductive traces contact the metal sheet. The test method is not detected as described in claim 6 wherein a single contact portion simultaneously contacts at least two of the conductive traces. The test method is not detected as described in claim 6 of the patent application, wherein the contact portion is a sheet.