TW201616497A - Non-volatile static random access memory circuits - Google Patents

Abstract

A non-volatile static random access memory (nvSRAM) circuit is provided. The nvSRAM circuit includes first and second switches and a latch circuit. The first switch has a first terminal coupled to a first bit line. The second switch has a first terminal coupled to a second bit line. The latch circuit is coupled to second terminals of the first and second switches. The latch circuit has a first non-volatile memory element. When the nvSRAM circuit is at a writing mode, first input data on the first bit line is written into in the latch circuit, and the first non-volatile memory element has a first state corresponding to the first data. When the nvSRAM circuit is at a reading mode, first readout data is generated according to the first state of the first non-volatile memory element is generated and provided to the first bit line.

Description

Non-volatile static random access memory circuit

The present invention relates to a non-volatile static random access memory circuit, and more particularly to a non-volatile static random access memory circuit that does not have an access mode and a recall mode.

Semiconductor memory devices are widely used in computers or other electronic products to store digital information. A typical semiconductor memory device has a large number of memory elements, such as memory cells, which are capable of storing a single digital bit or data bit. In various semiconductor memory devices, the non-volatile static random access memory has a higher access speed. In addition, when the power supply of the non-volatile SRAM is turned off, the pre-stored data is not lost. Therefore, in the power-off state or the standby mode, the power supply of the non-volatile SRAM can be completely cut off without worrying about data storage, thereby reducing power consumption.

In general, a non-volatile SRAM must operate in a storage mode to store data from a latch to a non-volatile memory before the conventional non-volatile SRAM enters the power-off state or standby mode. element. After the power supply to the non-volatile SRAM is turned on, the non-volatile SRAM must operate in the recall mode to recall data from the non-volatile memory element to the latch. However, the above storage mode and call The occurrence of the back mode results in additional timing.

Therefore, it is desirable to provide a non-volatile static random access memory that does not need to operate in a storage mode or a recall mode when it is in a power off state or a standby mode.

The present invention provides a non-volatile static random access memory circuit including a first switch, a second switch, and a latch circuit. The first switch has a first end coupled to the first bit line and further has a second end. The second switch has a first end coupled to the second bit line and further has a second end. The latch circuit is coupled to the second end of the first switch and the second end of the second switch and has a first non-volatile memory element. When the non-volatile SRAM circuit is in the write mode, the first data on the first bit line is written to the latch circuit, and the first non-volatile memory unit has the first state corresponding to the first data. When the non-volatile SRAM circuit is in the read mode, the first read data is generated according to the first state of the first non-volatile memory cell and provided to the first bit line.

In the write mode, the first switch and the second switch are turned on. In the read mode, the first switch and the second switch are turned on. In another embodiment, between the write mode and the read mode, no supply voltage is applied to the non-volatile SRAM circuit, or the non-volatile SRAM circuit is in the standby mode.

The non-volatile static random access memory circuit further includes a write control circuit. The write control circuit is coupled to the latch circuit and receives a write select signal to control the latch circuit. In the write mode, the write select signal is at a first voltage level to control the latch circuit to change the first non-volatile memory element to be in the first status. In the read mode, the write select signal is at a second voltage level to control the latch circuit to generate a first read signal in accordance with the first state.

In one embodiment, the latch circuit of the non-volatile static random access memory circuit includes a first first type transistor, a first second type transistor, a second second type transistor, and a second first type a crystal, a third second type transistor, and a fourth second transistor. The first first type transistor has a control end coupled to the first node, an output end, and an output end coupled to the second node. The first second type transistor has a control end coupled to the third node, an input coupled to the second node, and an output coupled to the ground. The second second type transistor has a control end, an input coupled to the first node, and an output coupled to the second node. The second first type transistor has a control end coupled to the first node, an input end, and an output end coupled to the third node. The third second type transistor has a control end coupled to the second node, an input coupled to the third node, and an output coupled to the ground. The fourth second transistor has a control end, an input coupled to the fourth node, and an output coupled to the third node. The first non-volatile memory element is coupled between the second node and the fourth node. The second end of the first switch is coupled to the third node, and the second end of the second switch is coupled to the second node. In the write mode, the second second type transistor and the fourth second type of transistor are turned on. In the read mode, the second second type transistor and the fourth second type transistor are turned off, and the input end of the first first type transistor and the input end of the second first type transistor receive a non-volatile static random Access the supply voltage of the memory circuit.

The non-volatile static random access memory circuit further includes a third first type of transistor. The third first type transistor has a control end, an input end coupled to the supply voltage of the non-volatile static random access memory circuit, and an input end coupled to the first first type transistor and the second first type transistor An output of the input end. The control terminal of the second second type transistor and the control terminal of the fourth second type transistor receive the write selection signal. In the write mode, the third first type of transistor is turned off, and the write select signal is at a first voltage level to turn on the second second type of transistor and the fourth second type of transistor. In the read mode, the third first type of transistor is turned on, and the write select signal is at the second voltage level to turn off the second second type of transistor and the fourth second type of transistor.

In an embodiment, the control terminal of the third first type transistor receives the write selection signal. In the write mode, the write select signal is at a first voltage level to turn off the third first type of transistor. In the read mode, the write select signal is at a second voltage level to turn on the third first type of transistor.

In another embodiment, the control terminal of the third first type transistor receives the power supply limiting signal. In the write mode, the power supply limit is at the third voltage level to turn off the third first type of transistor. In the read mode, the power limit signal is at a fourth voltage level to turn on the third first type of transistor. When the non-volatile SRAM circuit is in the standby mode, the power limiting signal is at the third voltage level to turn off the third first type of transistor.

In another embodiment, the latch circuit of the non-volatile static random access memory circuit includes a first first type transistor, a first second type transistor, a second second type transistor, and a second first type. A transistor, a third second type transistor, and a fourth second type transistor. The first first type transistor has a control end coupled to the first node, an input end, and an output end coupled to the second node. The first second type transistor has a control end coupled to the first node, an input coupled to the third node, and an output coupled to the ground. The second second type transistor has a control end, an input coupled to the second node, and an output coupled to the first node. Second first type The crystal has a control end coupled to the first node, an input end, and an output coupled to the fourth node. The third second type transistor has a control end coupled to the third node, an input coupled to the first node, and an output coupled to the ground. The fourth second type transistor has a control end, an output coupled to the fourth node, and an output coupled to the third node. The first non-volatile memory unit is coupled between the first node and the fourth node. The second end of the first switch is coupled to the first node, and the second end of the second switch is coupled to the third node. In the write mode, the second second type transistor and the fourth second type of transistor are turned on. In the read mode, the second second type transistor and the fourth second type transistor are turned off, and the input end of the first first type transistor and the input end of the second first type transistor receive a non-volatile static random Access the supply voltage of the memory circuit.

The non-volatile static random access memory circuit further includes a third first type of transistor. The third first type transistor has a control end, an input end coupled to the supply voltage of the non-volatile static random access memory circuit, and an input end coupled to the first first type transistor and the second first type transistor The output of this input. The control terminal of the second second type transistor and the control terminal of the fourth second type transistor receive the write selection signal. In the write mode, the third first type of transistor is turned off, and the write select signal is at a first voltage level to turn on the second second type of transistor and the fourth second type of transistor. In the read mode, the third first type of transistor is turned on, and the write select signal is at the second voltage level to turn off the second second type of transistor and the fourth second type of transistor.

In an embodiment, the control terminal of the third first type transistor receives the write selection signal. In the write mode, the write select signal is at a first voltage level to turn off the third first type of transistor. Write selection in read mode The signal is at a second voltage level to turn on the third first type of transistor.

In another embodiment, the control terminal of the third first type transistor receives the power supply limiting signal. In the write mode, the power supply limit is at a third voltage level to turn off the third first type of transistor. In the read mode, the power limit signal is at a fourth voltage level to turn on the third first type of transistor. When the non-volatile SRAM circuit is in the standby mode, the power limiting signal is at the third voltage level to turn off the third first type of transistor.

In yet another embodiment, the latch circuit further includes a second non-volatile memory component. When the non-volatile SRAM circuit is in the write mode, the second data on the second bit line is written to the latch circuit, and the second non-volatile memory unit has the second state corresponding to the second data. When the non-volatile SRAM circuit is in the read mode, the second read data is generated according to the second state of the second non-volatile memory unit and provided to the second bit line.

1‧‧‧Nonvolatile Static Random Access Memory Circuit

10‧‧‧Control circuit

11‧‧‧Latch circuit

12, 13‧‧‧ switch

100‧‧‧ PMOS transistor

200, 201‧‧‧ PMOS transistor

202, 203, 204, 205‧‧‧ NMOS transistors

206, 207‧‧‧ Non-volatile memory components

208, 209‧‧‧ NMOS transistor

500, 501‧‧‧ PMOS transistor

502, 503, 504, 505‧‧‧ NMOS transistors

506, 507‧‧‧ Non-volatile memory components

508, 509‧‧‧ NMOS transistor

BL, BLB‧‧‧ bit line

GND‧‧‧ Grounding

HRS‧‧‧high impedance state

LRS‧‧‧Low impedance state

N10, N11, N12‧‧‧ nodes

N20, N21‧‧‧ nodes

N50, N51‧‧‧ nodes

OFF‧‧‧Close

ON‧‧‧Training

PG‧‧‧Power limit signal

VS‧‧‧ voltage source

WL‧‧‧ character line

1 shows a non-volatile static random access memory circuit in accordance with an embodiment of the present invention.

Fig. 2 shows a non-volatile static random access memory circuit in accordance with another embodiment of the present invention.

Figure 3A shows the operation of the non-volatile SRAM circuit of Figure 2 in the write mode, in accordance with an embodiment of the present invention.

Figure 3B shows the operation of the non-volatile SRAM circuit of Figure 2 in the read mode, in accordance with an embodiment of the present invention.

Figure 4A shows the non-volatile static of Figure 2, in accordance with another embodiment of the present invention. The operation of the random access memory circuit in write mode.

Fig. 4B is a view showing the operation of the nonvolatile volatile random access memory circuit of Fig. 2 in the read mode according to another embodiment of the present invention.

Figure 5 is a diagram showing a non-volatile static random access memory circuit in accordance with still another embodiment of the present invention.

Figure 6A shows the operation of the non-volatile SRAM circuit of Figure 5 in the write mode, in accordance with an embodiment of the present invention.

Figure 6B is a diagram showing the operation of the non-volatile SRAM circuit of Figure 5 in the read mode, in accordance with an embodiment of the present invention.

Figure 7A shows the operation of the non-volatile SRAM circuit of Figure 5 in the write mode, in accordance with another embodiment of the present invention.

Fig. 7B is a view showing the operation of the nonvolatile volatile random access memory circuit of Fig. 5 in the read mode according to another embodiment of the present invention.

Figure 8 shows a non-volatile static random access memory circuit in accordance with an embodiment of the present invention.

Figure 9 shows a non-volatile static random access memory circuit in accordance with another embodiment of the present invention.

The following description is an embodiment of the present invention. The intent is to exemplify the general principles of the invention and should not be construed as limiting the scope of the invention, which is defined by the scope of the claims.

It is noted that the following disclosure may provide embodiments or examples for practicing various features of the present invention. The specific component examples and arrangements described below are only used to briefly illustrate the spirit of the present invention, and are not intended to To limit the scope of the invention. In addition, the following description may reuse the same component symbols or characters in various examples. However, the re-use is for the purpose of providing a simplified and clear description, and is not intended to limit the relationship between the various embodiments and/or configurations discussed below. In addition, the description of one of the features described in the following description is connected to, coupled to, and/or formed on another feature, etc., and may include a plurality of different embodiments, including direct contact of the features, or other additional Features are formed between the features and the like such that the features are not in direct contact.

Figure 1 is a diagram showing a non-volatile static random access memory circuit in accordance with an embodiment of the present invention. In FIG. 1, the nonvolatile bulk random access memory circuit 1 includes a write control circuit 10, a latch circuit 11, and switches 12 and 13. As shown in FIG. 1, one end of the switch 12 is coupled to the bit line BL, and the other end thereof is coupled to the latch circuit 11 at the node N10. One end of the switch 13 is coupled to the bit line BLB, and the other end of the switch 13 is coupled to the latch circuit 11 at the node N11. The control terminals of switches 12 and 13 are coupled to word line WL. The write control circuit 10 is coupled to the latch circuit 11 to control the operation when the nonvolatile volatile random access memory circuit 1 operates in the write mode or the read mode. The data stored from the bit lines BL and BLB is stored in the latch circuit 11 by the control of the write control circuit 10. Therefore, the non-volatile SRAM circuit 1 does not have to operate in the conventional storage mode until the non-volatile SRAM circuit 1 enters the power-off state or the standby mode. In addition, after the power of the non-volatile SRAM circuit 1 is turned on, the non-volatile SRAM circuit 1 does not need to operate in the conventional recall mode. The detailed circuit architecture and operation of the non-volatile static random access memory circuit will be described below.

Referring to FIG. 2, in one embodiment, write control circuit 10 includes a P-type MOS transistor 100. The control terminal (gate) of the PMOS transistor 100 receives the write selection signal WS, and its input terminal (source) is coupled to the voltage source VS of the non-volatile SRAM circuit 1 and its output terminal (drain) The latch circuit 11 is coupled to the node N12. The latch circuit 11 includes PMOS transistors 200 and 201, N-type gold oxide half (NMOS) transistors 202-205, and non-volatile memory elements 206 and 207. In this embodiment, switches 12 and 13 are implemented with NMOS transistors 208 and 209. The gate of the PMOS transistor 200 is coupled to the node N20, the input end of which is coupled to the node N12, and the output end of which is coupled to the node N11. The control terminal (gate) of the NMOS transistor 202 is coupled to the node N10, the input terminal (drain) is coupled to the node N11, and the output terminal thereof is coupled to the ground GND. The control terminal of the NMOS transistor 204 receives the write selection signal WS, the input end of which is coupled to the node N20, and the output end of which is coupled to the node N11. The non-volatile memory component 206 is coupled between the nodes N20 and N10.

The control terminal 201 of the PMOS transistor is coupled to the node N21, the input end of which is coupled to the node N12, and the output end of which is coupled to the node N10. The control terminal of the NMOS transistor 203 is coupled to the node N11, the input end of which is coupled to the node N10, and the output end of which is coupled to the ground GND. The control terminal of the transistor 205 receives the write selection signal WS, the input end of which is coupled to the node N21, and the output end of which is coupled to the node N10. The non-volatile memory element 207 is coupled between the nodes N21 and N11.

As shown in FIG. 3A, when the supply voltage VD is supplied to the non-volatile SRAM circuit 1 through the voltage source VS and the non-volatile SRAM circuit 1 is operated in the write mode, the write selection is performed. Signal WS is at a high level of supply voltage VDD (SW = VDD) and word line WL has a high level. Assume that the data of logic "0" is on bit line BL (BL = 0), and the data bit of logic "1" On the bit line BLB (BLB = 1). The NMOS transistors 204 and 205 are turned "ON" due to the high level of the write select signal WS. Due to the high level of the word line WL, the NMOS transistors 208 and 209 are turned on. At this time, in response to the data of logic "0" on the bit line BL, the node N10 has a low level to turn off the NMOS transistor 202. Due to the low level of the node N10 and the conduction state of the NMOS transistor 205, the node N21 has a low level. Further, in response to the data of logic "1" on the bit line BLB, the node N11 has a high level to turn on the NMOS transistor 203. Due to the high level of the node N11 and the conduction state of the NMOS transistor 204, the node N20 has a high level.

As described above, the non-volatile memory element 206 is coupled between the nodes N20 and N10, and the non-volatile memory element 207 is coupled between the nodes N21 and N11. Since node N20 has a high level and node N10 has a low level, a forward bias is applied to non-volatile memory element 206, and non-volatile memory element 206 has a low impedance state (LRS) to record logic on bit line BL. 0" information. Conversely, since node N21 has a low level and node N11 has a high level, so that a reverse bias is applied to non-volatile memory element 207, and non-volatile memory element 206 has a high impedance state (HRS) to record bit line BLB. Information on the logic "1".

According to this embodiment, the data on the bit lines BL and BLB is recorded in the latch circuit 11 by the travel of the impedance states of the non-volatile memory elements 206 and 207. Therefore, before the non-volatile SRAM circuit 1 enters the power-off state or the standby mode (ie, no supply voltage VDD is supplied), the conventional mode is no longer needed, thereby saving the non-volatile static random access memory. The timing of circuit 1.

As shown in FIG. 3B, when the supply voltage VDD is supplied through the voltage source VS to supply power to the non-volatile SRAM circuit 1 and the non-volatile SRAM circuit 1 operates in the read mode, the write selection is performed. Signal WS is at a low level of 0V (WS = 0) and word line WL also has a high level. Due to the low level write select signal WS, the PMOS transistor 100 is turned on and the NMOS transistors 204 and 205 are turned off. The node N12 has a high level of the supply voltage VDD through the turned-on PMOS transistor 100. Due to the high level of the word line WL, the NMOS transistors 208 and 209 are turned on. At this time, since the non-volatile memory element 206 has a low impedance state, the node N20 is at a low level to turn on the PMOS transistor 200. Through the turned-on PMOS transistor 200, the node N11 is at a high level (N11 = "H") in response to the high level of the node N12. In addition, since the non-volatile memory element 207 has a high impedance state, the node N21 is at a high level to turn off the PMOS transistor 201. The NMOS transistor 203 is turned on in response to the high level of the node N11. Therefore, the node N10 is at a low level (N10 = "L"). The NMOS transistor 202 is turned off in response to the low level of the node 10.

As described above, node N11 is at a high level and node N10 is at a low level. Through the turned-on NMOS transistor 208, the bit line BL has a low level, that is, the bit line BL reads the data of the logic "0" from the latch circuit 11. Through the turned-on NMOS transistor 209, the bit line BLB has a high level, that is, the bit line BLB reads the data of the logic "1" from the latch circuit 11. Further, since the PMOS transistor 201 and the NMOS transistor 202 are both turned off, the bit line BL stably reads the data of the logic "0", and the bit line BLB stably reads the data of the logic "1". Therefore, after the supply voltage VDD of the non-volatile SRAM circuit 1 is supplied, the non-volatile SRAM circuit 1 does not need to operate in a conventional call. Back mode, which saves timing.

4A and 4B are diagrams showing the operation of the nonvolatile volatile random access memory circuit 1 according to another embodiment of the present invention. In this embodiment, as shown in FIG. 4A, when the non-volatile SRAM circuit 1 operates in the write mode, the data of the logic "1" is located on the bit line BL, and the data of the logic "0" is present. Located on the bit line BLB. When the non-volatile SRAM circuit 1 operates in the read mode, the bit line BL stably reads the data of the logic "1", and the bit line BLB stably reads the data of the logic "0", The operation of the nonvolatile volatile random access memory circuit 1 in Figs. 4A and 4B is similar to the operations of Figs. 3A and 3B. Therefore, the operations of the embodiments regarding the 4A and 4B diagrams are omitted here.

Figure 5 is a diagram showing a non-volatile static random access memory circuit 1 according to another embodiment of the present invention. Referring to Figures 2 and 5, the difference between the embodiment of Figure 2 and the embodiment of Figure 5 is the architecture of the latch circuit 11. As shown in FIG. 5, the latch circuit 11 includes PMOS transistors 500 and 501, NMOS transistors 502-505, and non-volatile memory elements 506 and 507. In this embodiment, switches 12 and 13 are implemented as NMOS transistors 508 and 509, respectively. The control terminal of the PMOS transistor 500 is coupled to the node N10, the input end of which is coupled to the node N12, and the output end of which is coupled to the node N50. The control terminal of the NMOS transistor 502 is coupled to the node N10, the input end of which is coupled to the node N11, and the output end of the NMOS transistor 502 is coupled to the GND. The control terminal of the NMOS transistor 504 receives the write selection signal WS, the input end of which is coupled to the node N50, and the output end of which is coupled to the node N10. The non-volatile memory element 506 is coupled between the nodes N50 and N11.

The control terminal of the PMOS transistor 501 is coupled to the node N11, the input end of which is coupled to the node N12, and the output end of which is coupled to the node N51. NMOS transistor 503 The control end is coupled to the node N11, the input end of which is coupled to the node N10, and the output end of which is coupled to the GND. The control terminal of the NMOS transistor 505 receives the write selection signal WS, the input end of which is coupled to the node N51, and the output end of which is coupled to the node N11. The non-volatile memory unit 507 is coupled between the nodes N51 and N10.

As shown in FIG. 6A, when the supply voltage VD is supplied to the non-volatile SRAM circuit 1 through the voltage source VS and the non-volatile SRAM circuit 1 is operated in the write mode, the write selection is performed. Signal WS is at a high level of supply voltage VDD (SW = VDD) and word line WL has a high level. It is assumed that the data of the logic "0" is located on the bit line BL (BL = 0), and the data of the logic "1" is located on the bit line BLB (BLB = 1). Due to the high level of write select signal WS, the PMOS transistor is turned "OFF" and NMOS transistors 504 and 505 are turned "ON". Due to the high level of the word line WL, the NMOS transistors 508 and 509 are turned on. At this time, in response to the data of logic "0" on the bit line BL, the node N10 has a low level to turn off the NMOS transistor 502. Due to the low level of node N10 and the conduction state of NMOS transistor 504, node N50 has a low level. Further, in response to the data of logic "1" on the bit line BLB, the node N11 has a high level to turn on the NMOS transistor 503. Due to the high level of the node N11 and the conduction state of the NMOS transistor 505, the node N51 has a high level.

As described above, the non-volatile memory element 506 is coupled between the nodes N50 and N11, and the non-volatile memory 507 is coupled between the nodes N51 and N10. Since node N50 has a low level and node N11 has a high level, a reverse bias is applied to non-volatile memory element 506, and non-volatile memory element 506 is defined to have a low impedance state (LRS) to record logic on bit line BL. "0" information. Conversely, since node N51 has a low level and node N10 has a high level, A forward bias is applied to the non-volatile memory element 507, and the non-volatile memory element 507 is defined as having a high impedance state (HRS) to record data of a logic "1" on the bit line BLB.

According to this embodiment, the data on the bit lines BL and BLB is recorded in the latch circuit 11 by the stroke of the impedance states of the non-volatile memory elements 506 and 507. Therefore, before the non-volatile SRAM circuit 1 enters the power-off state or the standby mode (ie, no supply voltage VDD is supplied), the conventional mode is no longer needed, thereby saving the non-volatile static random access memory. The timing of circuit 1.

As shown in FIG. 6B, when the supply voltage VDD is supplied to the non-volatile SRAM circuit 1 through the voltage source VS and the non-volatile SRAM circuit 1 operates in the read mode, the write selection is performed. Signal WS is at a low level of 0V (WS = 0) and word line WL also has a high level. Due to the low level write select signal WS, the PMOS transistor 100 is turned on and the NMOS transistors 504 and 505 are turned off. Through the turned-on PMOS transistor 100, the node N12 has a high level of the supply voltage VDD. Due to the high level of the word line WL, the NMOS transistors 508 and 509 are turned on. At this time, since the non-volatile memory element 507 has a high impedance state, the current flowing through the non-volatile memory element 507 is less, and the node N10 is at a low level (N10 = "L") to turn on the PMOS transistor 500 and turn off the NMOS. Transistor 502. In addition, since the non-volatile memory unit 506 has a low-level anti-state, the current flowing through the non-volatile memory element 506 is more, and the node N11 is at a high level (N11=“H”). The PMOS transistor 501 is turned off and the NMOS transistor is turned on. 503.

As described above, node N11 is at a high level and node N10 is at a low level. Through the turned-on switch 12, the bit line BL has a low level, that is, a bit line The BL self-latching circuit 11 reads the data of the logic "0". Through the turned-on switch 13, the bit line BLB has a high level, that is, the bit line BLB reads the data of the logic "1" from the latch circuit 11. Further, since the PMOS transistor 501 and the NMOS transistor 502 are both turned off, the bit line BL stably reads the data of the logic "0", and the bit line BLB stably reads the data of the logic "1".

7A and 7B are diagrams showing the operation of the nonvolatile volatile random access memory circuit 1 according to another embodiment of the present invention. In this embodiment, as shown in FIG. 7A, when the non-volatile SRAM circuit 1 operates in the write mode, the data of the logic "1" is located in the bit line BL, and the data of the logic "0" is present. Located on the bit line BLB. When the non-volatile SRAM circuit 1 operates in the read mode, the bit line BL stably reads the data of the logic "1", and the bit line BLB stably reads the data of the logic "0", The operation of the nonvolatile volatile random access memory circuit 1 in Figs. 7A and 7B is similar to the operations of Figs. 6A and 6B. Therefore, the operations of the embodiments regarding the 7A and 7B diagrams are omitted here.

Figure 8 is a diagram showing a non-volatile static random access memory circuit 1 according to another embodiment of the present invention. The difference between the embodiment of Fig. 2 and the embodiment of Fig. 8 lies in the architecture of the write control circuit 10. In the write control circuit 10, the control terminal of the PMOS transistor 100 receives the power supply limit signal PG, which replaces the write select signal WS. When the nonvolatile bulk random access memory circuit 1 operates in the standby mode or operates in the write mode, the power supply limit signal PG has a high level to turn off the PMOS transistor 100. When the nonvolatile bulk random access memory circuit 1 operates in the read mode, the power supply limit signal PG has a low level to turn on the PMOS transistor 100. The operation of the other elements of the non-volatile SRAM circuit 1 in the embodiment of Fig. 8 is similar to the operation of the pictures 2, 3A, 3B, 4A, 4B, This omits the related description. In this embodiment, the write select signal WS has a low level in the standby mode.

Figure 9 is a diagram showing a non-volatile static random access memory circuit 1 according to another embodiment of the present invention. The difference between the embodiment of Fig. 5 and the embodiment of Fig. 9 lies in the architecture of the write control circuit 10. In the write control circuit 10, the control terminal of the PMOS transistor 100 receives the power supply limit signal PG, which replaces the write select signal WS. When the nonvolatile bulk random access memory circuit 1 operates in the standby mode or operates in the write mode, the power supply limit signal PG has a high level to turn off the PMOS transistor 100. When the nonvolatile bulk random access memory circuit 1 operates in the read mode, the power supply limit signal PG has a low level to turn on the PMOS transistor 100. The other elements of the nonvolatile volatile random access memory circuit 1 in the embodiment of Fig. 8 are similar to the operations of Figs. 5, 6A, 6B, 7A, and 7B, and thus the related description will be omitted. In this embodiment, the write select signal WS has a low level in the standby mode.

The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

1‧‧‧Nonvolatile Static Random Access Memory Circuit

10‧‧‧Control circuit

11‧‧‧Latch circuit

12, 13‧‧‧ switch

BL, BLB‧‧‧ bit line

GND‧‧‧ Grounding

N10, N11, N12‧‧‧ nodes

VS‧‧‧ voltage source

WL‧‧‧ character line

Claims (15)

A non-volatile static random access memory circuit includes: a first switch having a first end coupled to a first bit line and further having a second end; and a second switch having a coupling a first end of the two-bit line and a second end; a latching circuit coupled to the second end of the first switch and the second end of the second switch, and having a first non- Volatile memory element; wherein, when the non-volatile SRAM circuit is in a write mode, a first data on the first bit line is written to the latch circuit, and the first non-volatile memory The unit has a first state corresponding to the first data; and wherein, when the non-volatile SRAM circuit is in a read mode, the first read data is based on the first non-volatile memory unit A state is generated and provided to the first bit line. The non-volatile SRAM circuit of claim 1, wherein the first switch and the second switch are turned on in the write and read modes. The non-volatile SRAM circuit of claim 1, wherein between the write mode and the read mode, no supply voltage is supplied to the non-volatile SRAM circuit, or the non- The volatile static random access memory circuit is in a standby mode. The non-volatile static random access memory circuit of claim 1, further comprising: a write control circuit coupled to the latch circuit and receiving a write select signal to control the latch circuit; wherein, in the write mode, the write select signal is at a first voltage level to Controlling the latch circuit to change the first non-volatile memory element to be in the first state; and wherein, in the read mode, the write select signal is at a second voltage level to control the latch The circuit generates the first readout signal based on the first state. The non-volatile static random access memory circuit of claim 1, wherein the latch circuit comprises: a first first type transistor having a control end coupled to the first node, An output terminal and an output coupled to a second node; a first second type transistor having a control end coupled to a third node, an input coupled to the second node, and coupled a second ground type transistor having a control terminal, an input coupled to the first node, and an output coupled to the second node; a second first type a transistor having a control terminal coupled to the first node, an input terminal, and an output coupled to the third node; a third second type transistor having a control coupled to the second node An input end coupled to the third node, and an output coupled to the ground; and a fourth second transistor having a control end, an input coupled to a fourth node, and a coupling Connected to an output of the third node; The first non-volatile memory element is coupled between the second node and the fourth node; and wherein the second end of the first switch is coupled to the third node, and the second switch The second end is coupled to the second node. The non-volatile SRAM circuit of claim 5, wherein in the write mode, the second second type transistor and the fourth second type of transistor are turned on. The non-volatile SRAM circuit of claim 5, wherein in the read mode, the second second type transistor and the fourth second type transistor are turned off, and the The input end of the first first type transistor and the input end of the second first type transistor receive a supply voltage of the non-volatile SRAM circuit. The non-volatile static random access memory circuit of claim 5, further comprising: a third first type transistor having a control end coupled to the non-volatile static random access memory circuit An input end of the supply voltage, and an output end coupled to the input end of the first first type transistor and the input end of the second first type transistor; wherein, the second second type transistor The control terminal and the control terminal of the fourth second type transistor receive the write selection signal; wherein, in the write mode, the third first type transistor is turned off, and the write select signal is in a a first voltage level to conduct the second second type transistor and the fourth second type of transistor; Wherein, in the read mode, the third first type transistor is turned on, and the write selection signal is at a second voltage level to turn off the second second type transistor and the fourth second type of electricity Crystal. The non-volatile SRAM circuit of claim 8, wherein the control terminal of the third first type transistor receives the write selection signal; wherein, in the write mode, The write select signal is at the first voltage level to turn off the third first type transistor; and wherein, in the read mode, the write select signal is at the second voltage level to turn on the third The first type of transistor. The non-volatile static random access memory circuit of claim 1, wherein the latch circuit comprises: a first first type transistor, having a control end coupled to a first node, and a An input end and an output coupled to a second node; a first second type transistor having a control end coupled to the first node, an input coupled to a third node, and coupled a second ground type transistor having a control terminal, an input coupled to the second node, and an output coupled to the first node; a second first type a transistor having a control terminal coupled to the first node, an input terminal, and an output coupled to a fourth node; a third second type transistor having a control coupled to the third node An input coupled to the first node and an output coupled to the ground; a fourth type of transistor having a control terminal, an output coupled to the fourth node, and an output coupled to the third node; wherein the first non-volatile memory unit is coupled to the Between the first node and the fourth node; and wherein the second end of the first switch is coupled to the first node, and the second end of the second switch is coupled to the third node. The non-volatile SRAM circuit of claim 10, wherein in the write mode, the second second type transistor and the fourth second type of transistor are turned on. The non-volatile SRAM circuit of claim 10, wherein in the read mode, the second second type transistor and the fourth second type transistor are turned off, and the The input end of the first first type transistor and the input end of the second first type transistor receive a supply voltage of the non-volatile SRAM circuit. The non-volatile static random access memory circuit of claim 10, further comprising: a third first type transistor having a control end coupled to the non-volatile static random access memory circuit An input end of the supply voltage, and an output end coupled to the input end of the first first type transistor and the input end of the second first type transistor; wherein, the second second type transistor The control terminal and the control terminal of the fourth second type transistor receive the write selection signal; In the write mode, the third first type transistor is turned off, and the write selection signal is at a first voltage level to turn on the second second type transistor and the fourth second type of electricity. a crystal; and wherein, in the read mode, the third first type transistor is turned on, and the write select signal is at a second voltage level to turn off the second second type transistor and the fourth Type II transistor. The non-volatile SRAM circuit of claim 13, wherein the control terminal of the third first type transistor receives the write selection signal; wherein, in the write mode, The write select signal is at the first voltage level to turn off the third first type transistor; and wherein, in the read mode, the write select signal is at the second voltage level to turn on the third The first type of transistor. The non-volatile SRAM circuit of claim 1, wherein the latch circuit further comprises a second non-volatile memory element; wherein, when the non-volatile SRAM circuit is in the In the write mode, a second data on the second bit line is written to the latch circuit, and the second non-volatile memory unit has a second state corresponding to the second material; and wherein, when When the volatile static random access memory circuit is in the read mode, a second read data is generated according to the second state of the second non-volatile memory unit and provided to the second bit line.