TW201611358A - Semiconductor light emitting device and lead frame - Google Patents

Abstract

According to one embodiment, a semiconductor light emitting device includes a lead frame; a chip mounted on the lead frame, the chip including a substrate and a light emitting element provided on the substrate; a wall section including an inner wall facing to a side portion of the chip, and an outer wall on an opposite side to the inner wall; and a phosphor layer provided on at least the chip. A distance between the side portion of the chip and the inner wall of the wall section is smaller than a thickness of the chip. An angle between an upper surface of the lead frame and the inner wall is smaller than an angle between the upper surface of the lead frame and the outer wall.

Description

Semiconductor light emitting device and lead frame [Related application]

This application claims priority from Japanese Patent Application No. 2014-187089 (filing date: September 12, 2014) as a basic application. This application contains the entire contents of the basic application by reference to the basic application.

Embodiments relate to a semiconductor light emitting device and a lead frame.

Although the surface mount type light-emitting device using a germanium substrate is expected to greatly reduce the cost, the light absorption of the germanium substrate is a concern.

Embodiments of the present invention provide a semiconductor light-emitting device and a lead frame capable of improving light extraction efficiency.

According to an embodiment, a semiconductor light emitting device includes a lead frame, a wafer, a wall portion, and a phosphor layer. The wafer is mounted on the lead frame and has a substrate and a light-emitting element provided on the substrate. The wall portion has an inner wall facing the side portion of the wafer and an outer wall opposite to the inner wall. The phosphor layer is provided on at least the wafer. The distance between the side portion of the wafer and the inner wall of the wall portion is smaller than the thickness of the wafer. The upper surface of the lead frame and the inner wall form an angle smaller than an angle formed by the upper surface of the lead frame and the outer wall.

11‧‧‧1st lead frame

11a‧‧‧ Wafer loading area

11b‧‧‧Metal wire joint area

11c‧‧‧Metal wire joint area

12‧‧‧2nd lead frame

12a‧‧‧Upper surface

20‧‧‧ wafer

21‧‧‧矽 substrate

22‧‧‧Lighting elements (LED chips)

22p‧‧‧p side pad

22n‧‧‧n side pad

30‧‧‧Resin frame

31‧‧‧Inter-wire insulation

32‧‧‧ reflector

32a‧‧‧ wall

32b‧‧‧ inner wall

33‧‧‧ wall

33a‧‧‧ inner wall

33b‧‧‧ outer wall

35‧‧‧White resin

36‧‧‧White resin

38‧‧‧Electrical paste

39‧‧‧Mastic paste

41‧‧‧bonding line

42‧‧‧bonding line

43‧‧‧bonding line

47‧‧‧bonding line

49‧‧‧bonding line

51‧‧‧Zina diode

60‧‧‧Fluorescent layer

61‧‧‧Fertior

62‧‧‧Combined materials

63‧‧‧Light scattering materials

64‧‧‧Fluorescent layer

65‧‧‧ transparent layer

66‧‧‧resin tablets

71‧‧‧ lead frame

71a‧‧‧ Wafer loading area

71b‧‧‧ Wafer loading area

71c‧‧‧External lead

71d‧‧‧External lead

71e‧‧‧Internal wire section

72‧‧‧2nd lead frame

72a‧‧‧Metal wire joint area

72b‧‧‧Metal wire joint area

72c‧‧‧Back

80‧‧‧Resin frame

81‧‧‧ wall

81a‧‧‧ inner wall

81b‧‧‧ outer wall

82‧‧‧One part of the resin frame

83‧‧‧One part of the resin frame

91‧‧‧ lens

92‧‧‧ side

93‧‧‧ convex

98‧‧‧ lens

98a‧‧‧Part 2

98b‧‧‧Part 1

A‧‧‧Anode terminal

C‧‧‧cathode terminal

D‧‧‧distance

X‧‧‧ direction

Y‧‧‧ direction

1A to 1C are schematic views of a semiconductor light emitting device according to an embodiment.

Fig. 2 is a schematic cross-sectional view showing a semiconductor light-emitting device of an embodiment.

3A and 3B are schematic views of a package of an embodiment.

4A and 4B are schematic views of a semiconductor light emitting device according to an embodiment.

Fig. 5 is an equivalent circuit diagram of a semiconductor light-emitting device of an embodiment.

6A and 6B are schematic views of a semiconductor light emitting device according to an embodiment.

7A and 7B are schematic views of a semiconductor light emitting device according to an embodiment.

8A to 8C are schematic views of a package of an embodiment.

Fig. 9 is a schematic cross-sectional view showing a semiconductor light emitting device according to an embodiment.

Fig. 10 is a schematic cross-sectional view showing a semiconductor light emitting device according to an embodiment.

11A and 11B are schematic cross-sectional views showing a semiconductor light emitting device according to an embodiment.

Fig. 12 is a schematic side view showing a lens of the semiconductor light-emitting device of the embodiment.

Fig. 13A is a ΔCx characteristic diagram of the semiconductor light-emitting device of the embodiment, and Fig. 13B is a ΔCy characteristic diagram of the semiconductor light-emitting device of the embodiment.

Fig. 14 is a schematic plan view showing a semiconductor light emitting device according to an embodiment.

Hereinafter, embodiments will be described with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals.

Fig. 1A is a schematic plan view of a semiconductor light emitting device according to an embodiment.

Figure 1B is a cross-sectional view taken along line A-A of Figure 1.

Figure 1C is a cross-sectional view taken along line B-B of Figure 1.

In Fig. 1A, the illustration of the phosphor layer 60 shown in Figs. 1B and C is omitted.

The semiconductor light-emitting device of the embodiment has a wafer 20 and a package for holding the wafer 20.

Fig. 2 is an enlarged cross-sectional view showing a portion A in Fig. 1B.

The wafer 20 is an LED (Light Emitting Diode) wafer, and has a light-emitting element (LED element) 22 and a substrate 21 that supports the light-emitting element 22.

The light emitting element 22 has, for example, a semiconductor layer containing gallium nitride. The semiconductor layer has an n-type GaN layer, a p-type GaN layer, and a light-emitting layer (activation layer) provided between the n-type GaN layer and the p-type GaN layer. The luminescent layer contains a material that emits blue, purple, blue-violet, ultraviolet light, or the like. The emission peak wavelength of the light-emitting layer is, for example, 430 to 470 nm.

Further, the light-emitting element 22 has a p-side electrode connected to the p-type GaN layer and an n-side electrode connected to the n-type GaN layer. As shown in FIG. 1A, a p-side pad 22p and an n-side pad 22n are provided on the upper surface of the light-emitting element 22. The p-side pad 22p is electrically connected to the p-type GaN layer via the p-side electrode. The n-side pad 22n is electrically connected to the n-type GaN layer via the n-side electrode.

The substrate 21 is, for example, a tantalum substrate. The substrate 21 is thicker than the light-emitting element 22 and supports the light-emitting element 22.

Fig. 3A is a schematic plan view of a package of the embodiment.

Figure 3B is a cross-sectional view taken along line C-C of Figure 3A.

The package has a first lead frame 11, a second lead frame 12, and a resin holder 30.

The first lead frame 11 and the second lead frame 12 are metal molded bodies and contain, for example, copper as a main component. The first lead frame 11 and the second lead frame 12 are spaced apart from each other.

The resin holder 30 has an inter-wire insulating portion 31, a reflector 32, and a wall portion 33. The inter-wire insulating portion 31, the reflector 32, and the wall portion 33 are formed of, for example, an anthrone-based white resin.

The inter-wire insulating portion 31 is provided between the first lead frame 11 and the second lead frame 12. The upper surface of the first lead frame 11 (the boundary portion with the phosphor layer 60), the upper surface of the second lead frame 12 (the boundary portion with the phosphor layer 60), and the upper surface of the inter-wire insulating portion 31 (with the firefly) The boundary portion of the photo body layer 60 is substantially continuous. The lower surface of the first lead frame 11 not covered by the resin frame 30, the lower surface of the second lead frame 12 not covered by the resin frame 30, and the lower surface of the inter-wire insulating portion 31 are substantially continuous.

The reflector 32 is disposed on the outer edge of the first lead frame 11 and the outer edge of the second lead frame 12 unit. The inner wall (the boundary portion with the phosphor layer 60) 32b of the reflector 32 is inclined with respect to the upper surface and the lower surface of the first lead frame 11, and the upper surface and the lower surface of the second lead frame 12. The upper portion of the upper surface of the first lead frame 11 and the upper portion of the upper surface of the second lead frame 12 are continuously surrounded by the inner wall 32b of the reflector 32, and are formed into an inverted ladder shape as viewed in the cross section shown in Fig. 3B. .

As shown in FIG. 3B, the wall portion 33 is provided on the upper surface of the first lead frame 11. The wall portion 33 divides the upper surface of the first lead frame 11 into three regions. The three regions include a first region 11a on which the wafer 20 is mounted, and second regions 11b and 11c to which the metal wires are bonded. In other words, the upper surface of the first lead frame 11 is partitioned by the wall portion 33 into the wafer mounting region 11a, the wire bonding region 11b, and the wire bonding region 11c.

The wall portion 33 has an inner wall 33a and an opposite side outer wall 33b. The inner wall 33a faces the wafer mounting region 11a. The outer wall 33b faces the wire bonding regions 11b, 11c.

The wafer mounting region 11a is continuously surrounded by the inner wall 33a of the wall portion 33 and the inner wall of the wall portion 32a of the reflector 32 shown in Fig. 1C. As shown in FIGS. 1A to 1C, a wafer 20 is mounted on the wafer mounting region 11a.

The back surface of the substrate 21 of the wafer 20 is bonded to the upper surface of the first lead frame 11 by a die bonding paste 39. The adhesive paste 39 is, for example, a silver (Ag) paste.

The heat generated by the light emission of the light-emitting element 22 is radiated to the mounting substrate (not shown) through the substrate 21, the paste paste 39, and the first lead frame 11.

The p-side pad 22p of the wafer 20 is electrically connected to the first lead frame 11 via a bonding wire 42. One end of the bonding wire 42 is bonded to the p-side pad 22p, and the other end is bonded to the wire bonding region 11b of the first lead frame 11. The bonding wire 42 is bonded over the wall portion 33 to be bonded to the p-side pad 22p and the wire bonding region 11b.

The n-side pad 22n of the wafer 20 is electrically connected to the second lead frame 12 via a bonding wire 41. One end of the bonding wire 41 is bonded to the n-side pad 22n, and the other end is bonded to the upper surface 12a of the second lead frame 12. The bonding wire 41 is joined to the n-side pad 22n and the upper surface 12a of the second lead frame 12 across the wall portion 33 and the inter-wire insulating portion 31.

A Zener diode wafer (hereinafter simply referred to as a Zener diode) 51 is mounted on the upper surface 12a of the second lead frame 12. An anode electrode is formed on the lower surface of the Zener diode 51, and a cathode electrode is formed on the upper surface of the Zener diode 51.

The anode electrode on the lower surface of the Zener diode 51 is connected to the upper surface 12a of the second lead frame 12 via a conductive paste (for example, silver paste) 38.

The cathode electrode on the upper surface of the Zener diode 51 is electrically connected to the first lead frame 11 via a bonding wire 43. One end of the bonding wire 43 is bonded to the cathode electrode on the upper surface of the Zener diode 51, and the other end is joined to the wire bonding region 11c of the first lead frame 11.

FIG. 5 is a circuit diagram showing the electrical connection relationship between the LED chip 22 and the Zener diode 51.

The LED chip 22 and the Zener diode 51 are connected in parallel between the anode terminal A and the cathode terminal C. The first lead frame 11 is connected to the anode terminal A, and the second lead frame 12 is connected to the cathode terminal C.

The LED chip 22 is forwardly connected between the anode terminal A and the cathode terminal C. The Zener diode 51 is reversely connected between the anode terminal A and the cathode terminal C.

The Zener diode 51 functions as an ESD (Electro Static Discharge) protection element. When a surge voltage exceeding the maximum rated voltage of the LED chip 22 is applied between the anode terminal A and the cathode terminal C, a surge current flows between the anode terminal A and the cathode terminal C through the Zener diode 51.

As shown in FIG. 1B, a phosphor layer 60 is provided in a region on the first lead frame 11 surrounded by the reflector 32 and a region on the second lead frame 12. The phosphor layer 60 covers the wafer 20, the Zener diode 51, the metal wires 41 to 43, the wall portion 33, the upper surface of the first lead frame 11, and the upper surface of the second lead frame 12.

The phosphor layer 60 includes a plurality of particulate phosphors 61. The phosphor 61 is excited by the emitted light of the light-emitting element 22 to emit light of a different wavelength from the emitted light. The particulate phosphor 61 emits light in all directions around it.

A plurality of phosphors 61 are dispersed in a bonding material (adhesive) 62 and bonded to the bonding material 62. Integration. The bonding material 62 transmits the emitted light of the light-emitting element 22 and the emitted light of the phosphor 61. Here, the term "transmission" is not limited to the case where the transmittance is 100%, and includes a case where one part of the light is absorbed.

The phosphor layer 60 has a structure in which a plurality of particulate phosphors 61 are dispersed in the bonding material 62. As the bonding material 62, a transparent resin such as an anthrone resin can be used. In the present specification, "transparent" means that the emitted light of the light-emitting element and the emitted light of the phosphor are transparent.

Light emitted from the light-emitting element 22 is incident on the phosphor layer 60, and a part of the light excites the phosphor 61 to obtain, for example, white light which is a mixed light of the emitted light of the light-emitting element 22 and the emitted light of the phosphor 61.

The resin holder 30 including the reflector 32 and the wall portion 33 is formed of a white resin which is reflective to the emitted light of the light-emitting element 22 and the emitted light of the phosphor 61. The white resin contains, for example, an anthrone resin as a main component.

The phosphor layer 60 is disposed in a region surrounded by the inner wall 32b of the reflector 32. The inner wall 32b of the reflector 32 forms an obtuse angle with the upper surface of the lead frames 11, 12. The inner wall 32b of the reflector 32 forms an acute angle with the upper surface of the phosphor layer 60. The inner wall 32b of the reflector 32 is inclined so as to widen the distance between the inner walls from the lower end toward the upper end. Therefore, the emitted light of the light-emitting element 22 and the emitted light of the phosphor 61 are easily reflected upward by the inner wall 32b of the reflector 32.

Further, on the upper surface of the first lead frame 11 and the upper surface of the second lead frame 12, the emitted light of the light-emitting element 22 and the emitted light of the phosphor 61 are formed to have high reflectance by, for example, a plating method. Silver (Ag). Therefore, the emitted light of the phosphor 61 toward the lead frames 11 and 12 and the emitted light of the light-emitting element 22 can be reflected on the upper surfaces of the lead frames 11 and 12 and emitted upward.

When manufacturing the package, the first lead frame 11 and the second lead frame 12 are placed in a mold. A white resin is poured into the mold, and is heated and pressurized to be cured. Thereby, the package shown in FIGS. 3A and 3 in which the first lead frame 11, the second lead frame 12, and the resin holder 30 are integrated is formed.

Thereafter, the wafer 20 is mounted on the wafer mounting region 11a surrounded by the wall portion 33 and the wall portion 32a (FIG. 1C) of the reflector 32 via the bonding paste 39.

The outer dimension (area) of the wafer mounting region 11a is slightly larger than the outer dimension (upper surface area or bottom surface area) of the wafer 20, so that the wafer 20 can be attached to the wafer mounting region 11a without interfering with the wall portions 33, 32a. Therefore, a gap is formed between the wall portions 33, 32a and the side surface of the wafer 20.

The side of the wafer 20 opposes the inner wall 33a of the wall portion 33. The side portion of the crucible substrate 21 (the portion facing the inner wall 33a of the wall portion 33) is exposed on the side portion of the wafer 20. In this case, the emitted light of the phosphor 61 or the emitted light that is reflected by the reflector 32 and returned to the light-emitting element 22 on the wafer side is incident on the side of the ruthenium substrate 21 and is absorbed by the ruthenium substrate 21, thereby directional packaging. Concerns about the decrease in luminous flux extracted from the outside of the body.

According to the embodiment, the inner walls of the wall portions 33, 32a oppose the side portions of the wafer 20 and continuously surround the sides of the wafer 20. The distance between the side of the wafer 20 and the inner wall of the wall portions 33, 32a (d shown in Fig. 2) is smaller than the thickness of the wafer 20.

The wall portions 33, 32a are close to the side portions of the wafer 20, whereby the return light toward the side portions of the wafer 20 is shielded (reflected) by the wall portions 33, 32a and is hard to be incident on the side portions of the wafer 20. As a result, the absorption loss of light in the ruthenium substrate 21 can be suppressed, and the light extraction efficiency to the outside of the package can be improved.

In order to prevent light from entering the side portion of the wafer 20, it is conceivable that the wall portions 33, 32a are in contact with the side portions of the wafer 20, and the side portions of the wafer 20 are covered by the wall portions 33, 32a. However, in the case where the package including the wall portions 33, 32a is formed first, and the subsequent mounting of the wafer 20, it is preferable to form a gap between the wall portions 33, 32a and the side portions of the wafer 20.

The smaller the gap, the lower the incidence of light toward the side of the wafer 20. The decrease in the incidence of light to the side of the wafer 20 suppresses the absorption loss of light in the ruthenium substrate 21 and improves the light extraction efficiency to the outside of the package. According to the embodiment, the distance d between the side portion of the wafer 20 and the inner wall of the wall portions 33 and 32a is preferably 30 μm or more and 150 μm in consideration of both workability of wafer mounting and reduction of light incidence to the wafer side portion. the following.

Further, the distance d here indicates the shortest distance between the side portion of the wafer 20 and the inner wall of the wall portions 33, 32a, the maximum distance, or the average distance of the wall portion height direction (wafer thickness direction).

Moreover, the height of the wall portions 33 and 32a is preferably (1/2) or more and twice or less the thickness of the wafer 20 in consideration of both workability of wafer mounting and reduction in incidence of light incident on the wafer side. According to the embodiment shown in Fig. 2, the height of the wall portion 33 is greater than the thickness of the wafer 20.

The inner wall 32b of the reflector 32 functions as a reflecting portion that reflects light above the package. In order to make the light easily reflected upward, the inner wall 32b of the reflector 32 is inclined at an obtuse angle with respect to the upper surface of the lead frames 11, 12.

On the other hand, the wall portions 33 and 32a provided close to the side portions of the wafer 20 do not reflect light from the side portions of the wafer and function as a wall that blocks light incident on the wafer side portion.

If the inner walls of the wall portions 33, 32a are inclined such that the upper end of the inner wall of the wall portions 33, 32a is further away from the side portion of the wafer 20 than the lower end, light is easily incident on the side portion of the wafer 20.

On the other hand, when the inner walls of the wall portions 33 and 32a are inclined such that the upper end of the inner wall of the wall portions 33 and 32a is closer to the side portion of the wafer 20 than the lower end, the workability of wafer mounting is lowered.

Therefore, in consideration of both the workability of wafer mounting and the reduction of light incidence to the side portion of the wafer, the inner walls of the wall portions 33, 32a are preferably opposed to each other substantially in parallel with respect to the side portion of the wafer 20, and are surrounded. The side of the wafer 20.

Here, the term "parallel" is not limited to the case where the inner walls of the wall portions 33, 32a are mathematically strictly parallel to the side portions of the wafer 20, and the light incident on the side portions of the wafer is not significantly increased. The degree of inclination is as long as the inner walls of the wall portions 33, 32a are substantially parallel to the side portions of the wafer 20.

That is, it is not limited to the case where the inner walls of the wall portions 33, 32a are accurately perpendicular to the upper surfaces of the lead frames 11, 12, and may be the wall portions 33, 32a with respect to the lead frame depending on the molding aspect or the like. The upper surface of 11, 12 is slightly inclined.

The side wall of the wall portion 33 is provided with a wedge shape for making it easy to demold from the mold. However, if the angle of inclination of the inner wall 33a opposite to the side of the wafer is increased, the return light is easily incident on the wafer side. unit. Therefore, the inner wall 33a of the wall portion 33 is slightly inclined.

Conversely, the inclination of the wall portion 33 not to the outer side wall 33b of the wafer side portion functions as the light reflecting surface in the same manner as the inner wall 32b of the reflector 32.

Therefore, as shown in Fig. 2, the inner wall 33a of the wall portion 33 and the upper surface of the lead frame 11 form an angle smaller than the angle formed by the outer wall 33b of the wall portion 33 and the upper surface of the lead frame 11. The inner wall 33a becomes closer to a vertical angle than the outer wall 33b with respect to the upper surface of the lead frame 11.

The inclination angle of the inner wall 33a of the wall portion 33 is smaller than the inclination angle of the inner wall 32b of the reflector 32 functioning as the reflection surface. The inner wall 33a of the wall portion 33 forms an angle with the upper surface of the lead frames 11, 12 which is smaller than the angle formed by the inner wall 32b of the reflector 32 and the upper surface of the lead frames 11, 12.

Further, it is not limited to the case where the distance between the lower end of the side portion of the wafer 20 and the wall portions 33, 32a and the distance between the upper end portion of the side portion of the wafer 20 and the wall portions 33, 32a are equal. In the case of a difference, the inner walls of the wall portions 33, 32a may be substantially parallel to the side portions of the wafer 20.

4A is a schematic plan view of a package of another embodiment.

4B is a schematic plan view of a semiconductor light emitting device according to another embodiment.

4A and FIG. 4B correspond to FIG. 3A and FIG. 1A of the above-described embodiment, and the same reference numerals will be given to the same elements, and detailed description thereof will be omitted.

As described above, on the surfaces of the lead frames 11, 12, a silver film is formed by, for example, plating. Silver is easily vulcanized with long-term use. The reflectivity of the vulcanized silver decreases.

Therefore, according to the embodiment shown in FIGS. 4A and 4B, the surfaces of the lead frames 11 and 12 other than the wafer mounting region and the metal wire bonding region are covered with the white resins 35 and 36.

The surface of the lead frame 11 of the lead frame 11 and the upper surface of the wire bonding regions 11b and 11c and the upper surface of the lead frame 12 and the wire bonding region 12a are covered with white resin 35 and 36.

By reducing the exposed area of silver, it is possible to make the silver less susceptible to vulcanization, thereby maintaining a higher reflectance of silver.

Similarly to the embodiment shown in Fig. 1A, wall portions 33 are provided under the white resins 35 and 36.

The white resins 35 and 36 are integrally formed as one of the resin holders 30, and have high reflectance to the light emitted from the light-emitting element 22 and the phosphor 61.

Fig. 6A is a schematic perspective view of a semiconductor light emitting device according to another embodiment.

Fig. 6B is a schematic plan view of a semiconductor light emitting device according to another embodiment.

Figure 7A is a cross-sectional view taken along line A-A of Figure 6B.

Figure 7B is a bottom view of Figure 7A.

Further, in Fig. 6B, the illustration of the lens 91 shown in Fig. 6A is omitted. Further, in Fig. 6A, illustration of the bonding wires 47, 49 shown in Figs. 6B and 7A is omitted.

The semiconductor light-emitting device shown in FIGS. 6A to 7B has a wafer 20 and a package for holding the wafer 20.

The wafer 20 is an LED (Light Emitting Diode) wafer. As shown in FIG. 2, the wafer 20 has a light-emitting element (LED element) 22 and a substrate 21 that supports the light-emitting element 22.

In this embodiment, for example, a p-side electrode is formed on one side (lower surface) in the thickness direction of the light-emitting element 22, and an n-side pad 22n is formed on the other side (upper surface) in the thickness direction of the light-emitting element 22.

Fig. 8A is a schematic plan view showing a package of the semiconductor light emitting device shown in Figs. 6A to 7B.

Figure 8B is a cross-sectional view taken along line B-B of Figure 8A.

Figure 8C is a cross-sectional view taken along line C-C of Figure 8A.

The package has a first lead frame 71, a second lead frame 72, and a resin holder 80.

The first lead frame 71 and the second lead frame 72 are metal molded bodies and contain, for example, copper as a main component. The first lead frame 71 and the second lead frame 72 are spaced apart from each other.

The first lead frame 71 has wafer mounting regions 71a and 71b. The second lead frame 72 has a metal Wire bonding regions 72a, 72b.

The resin holder 80 is formed of, for example, an anthrone-based white resin. The resin holder 80 has a wall portion 81. The wall portion 81 has an inner wall 81a and an opposite side outer wall 81b. The inner wall 81a faces the wafer mounting region 71a. The inner wall 81a of the wall portion 81 continuously surrounds the periphery of the wafer mounting region 71a of the first lead frame 71.

The wafer 20 is mounted on the wafer mounting region 71a. The back surface of the substrate 21 of the wafer 20 is bonded to the upper surface of the first lead frame 71 by a die bond paste (for example, a silver paste). The lower surface electrode (p-side electrode) of the light-emitting element 22 is connected to the first lead frame 71 via a conductive substrate (矽 substrate) 21.

The heat generated by the light emission of the light-emitting element 22 passes through the substrate 21 and the first lead frame 71, and is radiated toward the mounting substrate (not shown).

The n-side pad 22n of the wafer 20 is electrically connected to the second lead frame 72 via a bonding wire 49. One end of the bonding wire 49 is bonded to the n-side pad 22n, and the other end is joined to the bonding region 72a of the second lead frame 72. The bonding wire 49 is bonded over the wall portion 81 and joined to the bonding region 72a of the n-side pad 22n and the second lead frame 72.

A Zener diode 51 is mounted on the wafer mounting region 71b of the first lead frame 71. An anode electrode is formed on the lower surface of the Zener diode 51, and a cathode electrode is formed on the upper surface of the Zener diode 51.

The anode electrode on the lower surface of the Zener diode 51 is connected to the wafer mounting region 71b of the first lead frame 71 via a conductive paste (for example, a silver paste).

The cathode electrode on the upper surface of the Zener diode 51 is electrically connected to the second lead frame 72 via a bonding wire 47. One end of the bonding wire 47 is bonded to the cathode electrode on the upper surface of the Zener diode 51, and the other end is bonded to the wire bonding region 72b of the second lead frame 72.

In the present embodiment, the LED chip 20 and the Zener diode 51 are also connected in parallel between the anode terminal and the cathode terminal. The Zener diode 51 functions as an ESD (Electro Static Discharge) protection element.

As shown in FIG. 7A, the first lead frame 71 and the second lead frame 72 are spaced apart from each other in the first direction (X direction). The first lead frame 71 has an inner lead portion 71e and outer lead portions 71c and 71d. The inner lead portion 71e has wafer mounting regions 71a and 71b (FIG. 8A) and is provided in a plate shape continuous in the X direction.

The outer lead portions 71c and 71d are integrally provided in the inner lead portion 71e and protrude to the opposite side of the wafer mounting regions 71a and 71b. The outer lead portion 71c and the outer lead portion 71d are separated in the X direction.

The back surface (portion not covered by the resin holder 80) 72c of the second lead frame 72 functions as a cathode side external electrode. The back surface of the lead portions 71c and 71d (the portion not covered by the resin holder 80) outside the first lead frame 71 is separated into two anode-side external electrodes by a portion 82 of the resin holder 80.

Fig. 7B is a schematic view showing the back surface (mounting surface) of the semiconductor light-emitting device, and showing the back surface 72c of the second lead frame 72 and the back surfaces of the lead portions 71c and 71d outside the first lead frame 71. The back surface 72c of the second lead frame 72 and the back surfaces of the lead portions 71c and 71d other than the first lead frame 71 are formed, for example, in a rectangular pattern.

The back surface 72c of the second lead frame 72 and the back surface of the lead portions 71c and 71d other than the first lead frame 71 have the same width in the second direction (Y direction). In the back surface (mounting surface) of the semiconductor light-emitting device shown in FIG. 7B, the second direction (Y direction) is orthogonal to the first direction (X direction). The width of the back surface of the outer lead portion 71c in the X direction is larger than the width of the back surface 72c of the second lead frame 72 in the X direction and the width of the back surface of the outer lead portion 71d in the X direction. Therefore, the area of the back surface of the lead portion 71c other than the wafer mounting region 71a is larger than the area of the back surface of the outer lead portion 71d and the area of the back surface 72c of the second lead frame 72. Therefore, the heat of the phosphor layer 60 and the heat of the wafer 20 can be radiated toward the mounting substrate through the lead portion 71c which is provided outside the phosphor layer 60 and the wafer 20 and has a wide area.

The width of the back surface 72c of the second lead frame 72 in the X direction is equal to the width of the back surface of the outer lead portion 71d in the X direction. The area of the back surface 72c of the second lead frame 72 is equal to the area of the back surface of the outer lead portion 71d. The pitch between the back surface of the outer lead portion 71d and the back surface of the outer lead portion 71c is equal to the distance between the back surface of the outer lead portion 71c and the back surface 72c of the second lead frame 72.

The back surface of the outer lead portion 71c is provided between the back surface of the outer lead portion 71d and the back surface 72c of the second lead frame 72. A portion 82 of the resin holder 80 is provided between the back surface of the outer lead portion 71d and the back surface of the outer lead portion 71c. On a portion 82 of the resin holder 80, the inner lead portions 71c are connected without being separated. A portion 83 of the resin holder 80 is provided between the back surface of the outer lead portion 71c and the back surface 72c of the second lead frame 72.

The back surface 72c of the second lead frame 72 is bonded to the cathode side land pattern of the mounting substrate (circuit board) via solder. The back surfaces of the lead portions 71c and 71d other than the first lead frame 71 are bonded to the anode side land pattern of the mounting substrate (circuit board) via solder.

According to the layout of the mounting surface shown in FIG. 7B, the external electrodes (the back surface 72c of the second lead frame 72 and the back surfaces of the lead portions 71c and 71d outside the first lead frame 71) are arranged symmetrically with respect to the center of the mounting surface. Therefore, the molten solder does not symmetrically wet and spread to the external electrode with respect to the center of the mounting surface, and the semiconductor light-emitting device is less inclined at the time of mounting, and the desired light distribution characteristics are easily formed. In addition, in the first lead frame 71 on the anode side, the lead portions 71c and 71d are separated into two, but one component (the first lead frame 71) is integrally formed via the inner lead portion 71e. Therefore, it does not cause an increase in the number of parts.

The phosphor layer 60 is provided in the wafer mounting region 71a of the first lead frame 71 surrounded by the inner wall 81a of the wall portion 81. The phosphor layer 60 covers the wafer 20.

A lens 91 is provided on the upper surface of the package so as to cover the wafer 20, the phosphor layer 60, and the wall portion 81. The lens 91 is formed of a transparent resin that is transparent to the emitted light of the light-emitting element 22 and the emitted light of the phosphor 61.

The wall portion 81 is formed of a white resin having a high reflectance of the emitted light of the light-emitting element 22 and the emitted light of the phosphor 61.

In the present embodiment, when the package is manufactured, the first lead frame 71 and the second lead frame 72 are placed in a mold. A white resin is poured into the mold, and is heated and pressurized to be cured. Thereby, the package shown in FIGS. 8A to 8C in which the first lead frame 71, the second lead frame 72, and the resin holder 80 are integrated is formed.

Thereafter, the wafer 20 is mounted on the wafer mounting region 71a surrounded by the inner wall 81a of the wall portion 81 via the bonding paste.

The outer dimension (area) of the wafer mounting region 71a is slightly larger than the outer dimension of the wafer 20 (the upper surface area or the bottom surface area of the wafer 20), and the wafer 20 can be attached to the wafer mounting region 71a without interfering with the wall portion 81. Therefore, a gap is formed between the inner wall 81a of the wall portion 81 and the side portion of the wafer 20.

The inner wall 81a of the wall portion 81 faces the side of the wafer 20 and continuously surrounds the periphery of the side portion of the wafer 20. The distance between the side of the wafer 20 and the inner wall 81a of the wall portion 81 is smaller than the thickness of the wafer 20.

The wall portion 81 is close to the side portion of the wafer 20, whereby the return light reflected from the inside of the lens 91 is hard to be incident on the side portion of the wafer 20. As a result, the absorption loss of light in the ruthenium substrate 21 can be suppressed, and the light extraction efficiency to the outside of the package can be improved.

Further, in the present embodiment, the distance between the side portion of the wafer 20 and the inner wall 81a of the wall portion 81 (the shortest distance) is considered in consideration of both the workability of wafer mounting and the decrease in light incidence to the wafer side portion. The maximum distance or the average distance is preferably 30 μm or more and 150 μm or less.

The wall portion 81 facing the side portion of the wafer 20 does not reflect the light from the side portion of the wafer and functions as a wall that blocks light incident on the side portion of the wafer.

If the inner wall 81a of the wall portion 81 is inclined such that the upper end of the inner wall 81a of the wall portion 81 is farther from the side portion of the wafer 20 than the lower end, light is easily incident on the side portion of the wafer 20.

On the other hand, when the inner wall 81a of the wall portion 81 is inclined such that the upper end of the inner wall 81a of the wall portion 81 is closer to the side portion of the wafer 20 than the lower end, the workability of wafer mounting is lowered.

Therefore, the inner wall 81a of the wall portion 81 faces the side portion of the wafer 20 in parallel and surrounds the side portion of the wafer 20 in consideration of both workability of wafer mounting and reduction in light incidence toward the wafer side portion.

Here, "parallel" is also not limited to the case where the inner wall 81a of the wall portion 81 is mathematically strictly parallel to the side portion of the wafer 20, and does not include the wafer. The inclination of the light incident on the side portion is significantly increased as long as the inner wall 81a of the wall portion 81 is substantially parallel to the side portion of the wafer 20.

That is, it is not limited to the case where the inner wall 81a of the wall portion 81 is accurately perpendicular to the upper surface of the lead frame 71, and the inner wall 81a of the wall portion 81 may be opposed to the lead frame 71 depending on the molding aspect or the like. The upper surface is slightly tilted.

The side wall of the wall portion 81 is provided with a wedge shape for facilitating demolding from the mold. However, when the inclination angle of the inner wall 81a opposed to the wafer side portion is increased, the return light is easily incident on the wafer side portion. Therefore, the inner wall 81a of the wall portion 81 is slightly inclined. The angle formed by the inner wall 81a of the wall portion 81 and the upper surface of the lead frames 71, 72 is smaller than the angle formed by the outer wall 81b of the wall portion 81 and the upper surface of the lead frames 71, 72. The inner wall 81a becomes an angle closer to the vertical than the upper surface of the lead frames 71, 72 than the outer wall 81b.

Further, it is not limited to the case where the distance between the lower end of the side portion of the wafer 20 and the inner wall 81a of the wall portion 81 is equal to the difference between the distance between the upper end portion of the side portion of the wafer 20 and the inner wall 81a of the wall portion 81. In the case where there is a difference between the above distances, the inner wall 81a of the wall portion 81 may be substantially parallel to the side portion of the wafer 20.

In the same manner as in the above embodiment, a silver film is formed on the surfaces of the lead frames 71 and 72. According to the present embodiment, the surfaces of the lead frames 71 and 72 other than the wafer mounting region and the metal wire bonding region are covered by the resin holder 80.

The outer surface other than the wafer mounting regions 71a and 71b of the lead frame 71 and the upper surface of the lead wire bonding regions 72a and 72b of the lead frame 72 are covered with a resin holder 80 which is a white resin having high reflectance. Therefore, by reducing the exposed area of silver, it is possible to make the silver less susceptible to vulcanization, thereby maintaining a higher reflectance of silver.

Further, according to the present embodiment, the height of the wall portion 81 is larger than the thickness of the wafer 20. A phosphor layer 60 is provided on a region of the wafer 20 surrounded by the wall portion 81. The phosphor layer 60 is limited to be disposed on the wafer 20 within the range of the region surrounded by the wall portion 81.

The phosphor layer 60 is not provided on the resin 80 between the lead frames 71 and 72. Phosphor layer 60 It is accommodated on the lead frame 71 of the metal which is superior in heat dissipation to the resin 80.

Therefore, the heat generated in the phosphor layer 60 can be radiated to the mounting substrate through the wafer 20 and the first lead frame 71 directly under the phosphor layer 60 in a relatively short path.

Further, the lens 91 covers a region where the wafer 20 and the phosphor layer 60 are provided, and does not cover the Zener diode 51. Therefore, the return light reflected on the inner side of the lens 91 is not incident on the Zener diode 51. Therefore, the Zener diode 51 is not deteriorated due to the return light.

Fig. 9 is a schematic cross-sectional view showing a modification of the semiconductor light-emitting device shown in Fig. 1B.

According to the semiconductor light-emitting device shown in FIG. 9, the region in which the wafer 20, the wall portion 33, and the Zener diode 51 are provided is covered by the transparent layer 65. A phosphor layer 60 is provided on the transparent layer 65.

The transparent layer 65 is formed of a transparent resin that is transparent to the emitted light of the light-emitting element 22 and the emitted light of the phosphor 61. Alternatively, the transparent layer 65 functions as a light scattering layer. In other words, the transparent layer 65 includes a plurality of particulate scattering materials (for example, titanium compounds) that scatter the emitted light of the light-emitting elements 22, and a bonding material that integrates a plurality of scattering materials and transmits the emitted light of the light-emitting elements 22 (for example, Transparent resin).

Fig. 10 is a schematic cross-sectional view showing a modification of the semiconductor light emitting device shown in Fig. 7A.

A resin containing a phosphor is potted on the wafer 20. At this time, no anti-precipitation agent was added to the resin. Since the specific gravity of the phosphor is heavier than that of the resin component, it precipitates on the surface of the wafer 20 due to its own weight.

Due to the precipitation of the phosphor, the phosphor is present in the vicinity of the surface of the wafer 20. Therefore, the surface (upper surface and side surface) of the wafer 20 can be covered by the thinner phosphor layer 60. The thickness of the phosphor layer 60 is thinner than the thickness of the wafer 20.

By causing the fluorescent light to be emitted in the region (directly above) close to the wafer 20, it is easy to cause the heat of the phosphor to escape through the wafer 20 to the lead frame 71. Therefore, it is possible to suppress an increase in temperature at the time of light emission of the phosphor, and it is possible to suppress deterioration in characteristics and life due to heat.

Further, it is easy to form the phosphor layer 60 on the surface of the wafer 20 with a uniform thickness, and color separation due to uneven thickness of the phosphor layer 60 can be suppressed.

Fig. 11A is a schematic cross-sectional view of the semiconductor light-emitting device of another embodiment, which is the same as Fig. 7A. The same elements as those in the embodiment of FIG. 7A are denoted by the same reference numerals, and the detailed description thereof will be omitted.

A phosphor layer 64 is provided in a region surrounded by the wall portion 81. The phosphor layer 64 has a resin (adhesive), a plurality of phosphors 61 dispersed in the resin, and a plurality of light-scattering materials 63 dispersed in the resin. The resin is, for example, an anthrone resin.

A resin containing the phosphor 61 and the light-scattering material 63 is potted on the wafer 20. At this time, no anti-precipitation agent was added to the resin. Since the specific gravity of the phosphor 61 is heavier than that of the resin component and the light-scattering material 63, it is deposited on the surface of the wafer 20 by its own weight. Due to the precipitation of the phosphor 61, the phosphor 61 is present in the vicinity of the surface of the wafer 20. On the wafer 20 side, the concentration (density) of the phosphor 61 is higher than the concentration (density) of the light-scattering material 63. Therefore, it is easy to cause the heat of the phosphor 61 to escape to the lead frame 71 through the wafer 20.

The light scattering material 63 is, for example, cerium oxide particles. Light emitted from the light-emitting element 22 (for example, blue light) is scattered by the light-scattering material 63 to be diffused in the lateral direction. Therefore, it is possible to suppress color separation of the color (for example, yellow hue) of the light emitted from the phosphor 61 from the light emitted from the lateral direction and the light emitted in the direction directly above. It is possible to suppress chromaticity unevenness depending on the angle at which the semiconductor light-emitting device is observed, thereby achieving uniform light emission of a desired color.

When the light-scattering material is dispersed in the lens 91, the lens effect is impaired by the diffusion of light. This phenomenon may cause the light extraction efficiency to decrease and the light-emitting point to shift from the center of the hemispherical lens. The shift of the light-emitting point from the center of the lens may make it difficult to match the alignment of the secondary lens optical axis.

On the other hand, according to the embodiment, the light-scattering material is not dispersed in the lens 91, and is dispersed in the resin containing the phosphor 61. Therefore, the desired lens effect of the lens 91 can be exerted.

Further, as shown in FIG. 11B, a resin sheet (phosphor resin layer) 60 in which the phosphor 61 is dispersed may be attached to the wafer 20, and a light-scattering material 63 may be attached to the resin sheet 60. Resin sheet (light scattering resin layer) 66.

In this case, since the phosphor 61 is present in the vicinity of the surface of the wafer 20, it is easy to cause the heat of the phosphor 61 to escape to the lead frame 71 through the wafer 20. Further, the light emitted from the light-emitting element 22 (for example, blue light) is scattered by the light-scattering material 63 and diffused in the lateral direction, thereby suppressing the light emitted from the phosphor 61 from the light emitted from the lateral direction and the light emitted in the direction directly upward. The color of the hue (for example, yellow tone) is separated. Further, since the lens 91 does not contain a light scattering material, the desired lens effect of the lens 91 can be exhibited.

Figure 12 is a schematic side view of the lens 91. The lens 91 shown in Fig. 12 can be applied to the above-described semiconductor light-emitting device shown in Figs. 7A, 10, 11A, and 11B.

The lens 91 has, for example, a convex surface 93 as a part of a spherical surface, and a side surface 92 having a curvature (curvature radius) different from that of the convex surface 93. The outer line of the lens 91 is a part of an ellipse, or is approximately one part of an ellipse. Here, the "ellipse" is not only a mathematical ellipse but also a continuum of lines of different curvatures.

The center of the convex surface 93 is located at the highest point of the lens 91. The height here is the height based on the side of the wafer 20, and indicates the height in the direction perpendicular to the wafer 20. In the side view shown in Fig. 12, the lower end of the convex surface 93 farthest from the center of the convex surface 93 is calculated by the creeping distance, and the side surface 92 is continuous. The height of the side surface 92 is lower than the height of the convex surface 93.

The curvature of the side surface 92 is less than the curvature of the convex surface 93. The convex surface 93 and the side surface 92 are continuous without passing through the inflection point. That is, the convex surface 93 has the same sign of curvature as the side surface 92, and the side surface 92 does not protrude toward the inner side of the lens 91.

The lens 91 of such a shape suppresses the separation of the color of the light emitted from the phosphor (for example, a yellow tone) from the light emitted from the lateral direction and the light emitted in the direction directly above.

Figs. 13A and 13B show the results obtained by simulating ΔCx and ΔCy of the semiconductor light-emitting device of the embodiment having the lens 91 shown in Fig. 12.

Cx and Cy represent the coordinates of the CIE (International Commission on Illumination) chromaticity diagram. The horizontal axis in Figs. 13A and B indicates the light outgoing direction in which the direction directly above the semiconductor light-emitting device (0°) is used as a reference. (angle).

The vertical axis in Fig. 13A indicates the relative change ΔCx of the value of Cx with respect to Cx with respect to 0°.

The vertical axis in Fig. 13B indicates the relative change ΔCy of the value of Cy with respect to Cy at 0°.

From the results of Fig. 13A, it is known that ΔCx converges within 0.06 of the ANSI (American National Standards Institute) standard.

From the results of Fig. 13B, it is known that ΔCy converges within 0.12 of the ANSI standard.

That is, the lens 91 of the shape of Fig. 12 suppresses color separation.

Fig. 14 is a plan view showing the superimposed lens 98 in the plan view shown in Fig. 6B.

The lens 98 is formed in a shape in which a single first portion 98b and a plurality of (for example, four) second portions 98a are combined in a plan view as shown in FIG. When the second portion 98a is removed and the first portion 98b is joined together, it has a circular shape.

The first portion 98b covers the outside of the four corners of the light-emitting region including the four sides of the wafer 20 and the phosphor layer 60. The four second portions 98a respectively cover the four corners of the light-emitting area of the quadrilateral shape. The second portion 98a protrudes toward the outer peripheral side of the first portion 98b so as to cover the corner of the light-emitting region.

The embodiments of the present invention have been described, but are not intended to limit the scope of the invention. The present invention can be implemented in various other forms, and various omissions, substitutions and changes can be made without departing from the scope of the invention. The embodiments and variations thereof are included in the scope of the invention and the scope of the invention as set forth in the appended claims.

11‧‧‧1st lead frame

20‧‧‧ wafer

21‧‧‧矽 substrate

22‧‧‧Lighting elements (LED chips)

33‧‧‧ wall

33a‧‧‧ inner wall

33b‧‧‧ outer wall

39‧‧‧Mastic paste

41‧‧‧bonding line

42‧‧‧bonding line

60‧‧‧Fluorescent layer

D‧‧‧distance

Claims (20)

A semiconductor light-emitting device comprising: a lead frame; a wafer mounted on the lead frame, having a substrate; and a light-emitting element disposed on the substrate; and a wall portion having an inner wall opposite to a side of the wafer And an outer wall opposite to the inner wall; and a phosphor layer disposed on the wafer within the inner region of the inner wall of the wall portion and thinner than the wafer; and the side portion of the wafer The distance from the inner wall of the wall portion is smaller than the thickness of the wafer. A semiconductor light-emitting device comprising: a lead frame; a wafer mounted on the lead frame, having a substrate; and a light-emitting element disposed on the substrate; and a wall portion having an inner wall opposite to a side of the wafer And an outer wall opposite to the inner wall; and a phosphor layer disposed on at least the wafer; and a distance between the side of the wafer and the inner wall of the wall is less than a thickness of the wafer, The upper surface of the lead frame and the inner wall form an angle smaller than an angle formed by the upper surface of the lead frame and the outer wall. The semiconductor light-emitting device of claim 2, wherein the inner wall of the wall portion faces the side portion of the wafer in parallel. The semiconductor light emitting device of claim 2, wherein said side portion of said wafer is as described above The distance between the inner walls of the wall portion is 30 μm or more and 150 μm or less. The semiconductor light-emitting device of claim 2, wherein the wall portion contains a resin. A semiconductor light-emitting device according to claim 2, wherein said phosphor layer is provided on said wafer within an inner region of said inner wall of said wall portion. The semiconductor light-emitting device of claim 2, wherein the substrate is a germanium substrate. The semiconductor light emitting device of claim 2, further comprising a metal line connecting the upper surface of the wafer and the lead frame across the wall portion. The semiconductor light-emitting device of claim 2, wherein the lead frame has a first region on which the wafer is mounted and a second region on which the metal wire is to be bonded, and the first region and the second region of the lead frame are The surface of the area is covered with resin. The semiconductor light-emitting device of claim 2, further comprising a Zener diode mounted on the lead frame and electrically connected in parallel with the light-emitting element. The semiconductor light-emitting device of claim 10, further comprising a lens covering a region where the wafer and the phosphor layer are disposed, and not covering the Zener diode. The semiconductor light-emitting device of claim 2, wherein the phosphor layer has a resin, a plurality of phosphors dispersed in the resin, and a plurality of light-scattering materials dispersed in the resin. The semiconductor light-emitting device of claim 12, wherein the phosphor has a concentration higher than a concentration of the light-scattering material on a side close to the wafer. The semiconductor light-emitting device of claim 2, further comprising a resin layer disposed on the phosphor layer and having a plurality of light-scattering materials dispersed therein. The semiconductor light-emitting device of claim 12, further comprising a lens covering a region in which the wafer and the phosphor layer are disposed. The semiconductor light emitting device of claim 11, wherein the lens has: a convex surface; and a side surface continuing from the convex surface and having a curvature smaller than the convex surface. The semiconductor light-emitting device of claim 16, wherein the convex surface and the side surface are continuous without passing through an inflection point. The semiconductor light-emitting device of claim 15, wherein the lens has a convex surface; and a side surface continuing from the convex surface and having a curvature smaller than the convex surface. The semiconductor light-emitting device of claim 18, wherein the convex surface and the side surface are continuous without passing through an inflection point. A lead frame comprising: a first lead frame having an inner lead portion continuous in a first direction; and a plurality of outer lead portions integrally provided with the inner lead portion and separated in the first direction; and The second lead frame is spaced apart from the first lead frame in the first direction.