TW201608683A - MCSP power semiconductor device and fabrication method - Google Patents

Abstract

A power semiconductor device includes a MCSP package type fabricated at wafer level chip size packaging level. A conductive adhesive layer is disposed on backside of wafer. A metal foil-laminating layer is laminated on the backside of wafer wherein the conductive adhesive layer functions as adhesives material. Composite tape is attached to the metal foil-laminating layer. The stacked layer having molding layer, wafer, conductive adhesive layer and foil-laminating layer, composite tape is cut with a sawing process.

Description

MCSP power semiconductor device and preparation method

The present invention relates to the field of power semiconductor devices, and more particularly to a power semiconductor device in the form of an MCSP package and a corresponding preparation method under the premise of implementing a wafer level packaging method.

Common drain dual MOSFET power device is mainly used for battery charge and discharge management of notebook computers, tablets or mobile phones. Due to the recent trend, the charging time is getting shorter and shorter, so the charge and discharge current is correspondingly increased. Therefore, it is desirable that the on-resistance of the device becomes smaller and smaller. And the tablet, the ultra-thin design of the mobile phone also requires the size of the device to be smaller and smaller.

1A to 1C illustrate a novel power transistor package structure. In the top view of FIG. 1A, a lead frame 101 is utilized, and a wafer 102 having a plurality of solder balls disposed on the front surface is pasted on the lead frame 101, cured, and then plastically sealed. Grinding the front of the device exposes the solder balls. In addition to the high cost, the lead frame 101 introduced also increases the height/thickness of the device, which is disadvantageous for reducing the size of the device because the clamping pressure of the mold is generally too thick, otherwise it is easy to be at a large clamping pressure. The lower deformation is damaged, which is disadvantageous for reducing the size of the device. In addition, in the package of FIG. 1A, at least a separate molding process is required to mold the lead frame and the wafer, and the wafer 102 on the lead frame 101 is pasted by a standard mounting process, so the package is not In the complete sense of wafer-level packaging, the corresponding cost burden will also increase significantly due to the use of more processes.

In the cross-sectional views of FIGS. 1B to 1C, the lead frame is discarded, and a metal layer 121 is directly deposited on the back surface of the wafer 122. It is emphasized that it is difficult to wear a label on a bare metal such as the metal layer 121. And too thin metal layer 121 (one Generally only a few microns) is not conducive to reducing on-resistance or other types of parasitic resistance. 1C also forms a plastic encapsulation layer 123 on the metal layer 121. Although the label can be printed or etched on the plastic encapsulation layer 123, in many cases, in order to realize wafer level packaging, it is often necessary to grind the thinned plastic encapsulation layer 123. However, the problem that comes with it is that the plane in which the plastic seal layer 123 is subjected to grinding is microscopically observed, and is not a perfect polished surface but a rough surface with pits, so that the inconvenience of making a label is also induced.

Therefore, it is necessary to obtain a wafer-level package in a complete sense, so that the device has a low on-resistance, and the device can be smoothly compatible with all packaging processes (for example, at least for the smooth printing of clearly visible labels). A new packaging approach is required to balance these tough challenges.

In a method of fabricating a power semiconductor device of the present invention, the method comprises the steps of: providing a wafer with a plastic encapsulation layer on the front side; in one alternative, providing a conductive adhesive layer on the back side of the wafer, or alternatively In one embodiment, a surface of a metal foil layer pre-bonded to the back surface of the wafer is plated with a conductive adhesive layer such as tin (Sn); the metal foil layer is laminated to the back surface of the wafer and the conductive adhesive layer is utilized. Bonding and bonding; attaching a composite tape to the metal foil layer; cutting a laminate between adjacent wafers, the laminate including a plastic seal layer, a wafer, a conductive adhesive layer, a metal foil layer, and a composite tape Forming a plurality of independent power semiconductor devices.

In the above method, the identification mark is printed on the composite tape before the laminate is cut.

In the above method, in the step of laminating the metal foil layer, the wafer is heated simultaneously and pressure is applied to the metal foil layer to closely press the metal foil layer to the back surface of the wafer; or after the bonding of the composite tape is completed, The wafer is heated while applying pressure to the composite tape and metal foil layer to closely press the metal foil layer to the back side of the wafer.

In the above method, before laminating the metal foil layer to the back side of the wafer, a metal coating is applied on one side of the metal foil layer, and then the metal coated side is laminated to the back side of the wafer.

In an alternative embodiment, the method includes: firstly arranging metal bumps on the pads on the front side of each wafer before forming the plastic seal layer; then molding the front side of the wafer with a plastic seal layer and each metal bump Both are coated; the thinned plastic sealing layer is further polished until the top end of the metal bump is partially ground and exposed, thereby forming a top surface of each metal bump flattened and exposed from the top surface of the plastic sealing layer, The grinding step needs to be completed before the conductive bonding layer is disposed on the back side of the wafer.

In an optional embodiment, the method includes bonding a dummy wafer to the wafer and bonding the top surface of the plastic layer before completing the conductive adhesive layer on the back surface of the wafer. After the bonding step of the composite tape, the dummy wafer is peeled off before the cutting step is performed.

In an alternative embodiment, the method includes: firstly placing metal bumps on the pads on the front side of each wafer before forming the plastic seal layer; then molding the front side of the wafer with a plastic seal layer and each metal bump Wrapped; after finishing the bonding step of the composite tape and before cutting the laminate, the thinned plastic sealing layer is ground until the top end of the metal bump is partially ground to be exposed, thereby forming the top of each metal bump flattened And the top end faces of these metal bumps are exposed from the top surface of the plastic seal layer.

In a power semiconductor device of the present invention, comprising: a wafer; a top molding layer covering the front surface of the wafer, wherein the pad on the front surface of the wafer is provided with metal bumps, and the top plastic sealing layer surrounds the sidewall of the metal bump Around, the top surface of each metal bump is flattened from the top surface of the top molding layer; a bottom metal foil layer laminated on the back surface of the wafer, and the bottom metal foil is laminated and bonded by a conductive adhesive layer On the back side of the wafer; a bottom composite tape layer affixed to the bottom metal foil layer.

In the above power semiconductor device, the wafer is integrated with a pair of conjugated metal oxide semiconductor field effect transistors, and the bottom metal foil layer constitutes a common drain electrode of the pair of conjugated metal oxide semiconductor field effect transistors. And the power semiconductor device has a gate pad and a source pad respectively contacting the pair of the common drain metal oxide semiconductor field effect transistors Multiple metal bumps.

In the above power semiconductor device, the bottom metal foil is laminated on the back side of the wafer with a precious metal coating.

201‧‧‧ cushion

205‧‧‧Metal bumps

205G1‧‧‧metal bumps

205G2‧‧‧metal bumps

205S1‧‧‧metal bumps

205S2‧‧‧metal bumps

206‧‧‧plastic layer

206'‧‧‧Top plastic layer

300‧‧‧ wafer

300'‧‧‧ wafer

305‧‧‧metallization

306‧‧‧ Conductive bonding layer

307‧‧‧metal foil layer

307'‧‧‧metal foil layer

308‧‧‧Composite tape

308'‧‧‧Composite tape layer

325‧‧‧ID symbol

350‧‧‧ Wafer

500‧‧‧Power semiconductor devices

M1, M2‧‧‧ metal oxide semiconductor field effect transistor

D1, D2‧‧‧ bungee

G1, G2‧‧‧ gate

S1, S2‧‧‧ source

1A to 1C are schematic views of the background art; FIGS. 2A to 2E are schematic diagrams showing the flow of molding and thinning the wafer on the front side of the wafer; FIGS. 3A to 3G are schematic views showing the flow of the wafer level packaging according to the present invention; FIGS. 4A to 4B It is based on the steps of FIGS. 3A to 3G but additionally introduces a schematic diagram of a dummy wafer; FIGS. 5A to 5C are steps based on the steps of FIGS. 3A to 3G but changing the thinning timing of the plastic sealing layer on the front side of the wafer; FIGS. 6A to 6B are Embodiments of the invention for use in a conjugated bimetal oxide semiconductor field effect transistor device; Figures 7A-7C are embodiments in which LC Tape is applied; and Figures 8A-8C are examples of tin plating as an adhesion layer.

In FIG. 2A, wafer 300 includes a plurality of wafers that are cast together to each other, and the wafers define boundaries between each other with pre-defined lateral or longitudinal scribe lanes on the wafer. A plurality of spacers 201 are disposed on the front surface of each wafer as electrode terminals. As shown in FIG. 2B, metal bumps are implanted on the front side of the wafer, for example, a metal bump 205 is correspondingly disposed or soldered to a spacer 201. Metal bumps 205 are available in a variety of options, such as typical solder balls, gold bumps, and the like. In FIG. 2C, a molding process is performed to form a molding layer 206 on the front surface of the wafer 300 using a molding material such as an epoxy resin. The molding layer 206 may be required to have a predetermined thickness to All metal bumps 205 are encapsulated and sealed. Then, as shown in FIG. 2D, by increasing the mechanical strength brought by the plastic sealing layer 206, the wafer 300 can be prevented from being easily chipped or warped, and the wafer can be polished from the opposite back surface of the wafer 300. Although not shown in the figure, it is also possible to perform wet etching on the thinned back side of the wafer, release the residual residual stress on the back surface and repair the lattice damage, and then on the back side of the wafer 300. The heavily doped ion implantation and the deposition of a metallization layer on the backside of the thinned surface allow the metallization layer to form an ohmic contact with the heavily doped regions implanted on the backside of the wafer. Subsequently, as shown in FIG. 2E, the thinned plastic encapsulation layer 206 is ground until the top end of the metal bump 205, which is originally convex or irregular, is partially ground away, so that all the metal bumps 205 are thinned. The plastic encapsulation layer 206 is exposed while each of the metal bumps 205 has a flattened top end surface obtained by grinding, which are exposed from the top surface of the thinned plastic encapsulation layer 206.

In FIG. 3A, a layer of conductive adhesive layer 306 is disposed to the thinned back side of wafer 300, if the thinned back side of wafer 300 is provided with a patterned metallization layer 305 (eg, Ti/Ni/Ag, ie, titanium/nickel/ The silver or Ti/Ni/Au is a plurality of options such as titanium/nickel/gold, and the conductive adhesive layer 306 is actually pasted on the metallization layer 305. The mechanism for forming the conductive adhesive layer 306 on the back side of the wafer has various options. If the conductive adhesive layer 306 is selected to be a conductive material such as solder paste or conductive silver paste, it can be realized by direct coating if conductive. The adhesive layer 306 is selected to be a conductive film with a bonding function, and it can be directly attached to the back side of the wafer 300. In some embodiments, the preparation of conductive bonding layer 306 can be accomplished directly using Wafer backside coating. In FIG. 3B, a metal foil layer 307 is laminated to the back side of the wafer 300, during which the conductive bonding layer 306 is used for press bonding, so that the metal foil layer 307 is closely laminated to the back of the wafer 300 or On the metallization layer 305, the effective metal thickness on the back side of the wafer is uniformly increased over the entire back surface of the wafer to make the thickness uniform. Note that the metal foil layer 307 has a relatively precisely controlled thickness to increase the effective thickness of the back metal to facilitate the reduction of on-resistance or other types of parasitic resistance, while requiring the elimination of the original lead frame in the background art, which cannot effectively reduce the device. Thickness or size concerns, such as metal foil layer 307 may have a thickness of 0.5 to 3 mils to maintain the metal foil layer Softness and toughness. For ease of understanding and differentiation, the metal foil layer 307 can be stored in a roll-to-roll manner for use or transport, while FIG. 3B shows the metal foil layer 307 being drawn from the rolled metal foil layer 307 cylinder and laid flat. While laminating to the back side of the wafer 300, it is conceivable that the lead frame has a stronger hardness and a thicker thickness, so that the lead frame itself cannot be laminated on the back surface of the wafer 300, but only in the manner of picking up. The individual wafers are separated from the wafer and placed onto the lead frame one by one, which embodies a distinct feature of the present invention that distinguishes it from the prior art. There are many options for the metal foil layer 307, a typical and cost effective material such as copper foil.

In some alternative embodiments, a more conductive metal coating, such as a precious metal coating such as gold or silver, may be plated on one side of the metal foil layer 307 facing the back side of the wafer. The role of the precious metal coating is enhanced. The connection to the conductive adhesive layer 306 makes the connection more reliable. The metallization coating onto the metal foil layer 307 can be accomplished in a variety of ways, including electroplating or electroless plating or other sputter deposition. The metal foil layer 307 is coated with a metal coated side for contacting the conductive adhesive layer 306, which is laminated to the back side of the wafer 300. In some alternative embodiments, in the lamination step of the metal foil layer 307, it is necessary to additionally heat the wafer 300 with the encapsulation layer 206 to conduct heat to the conductive adhesion layer 306 if the conductive adhesive layer 306 is a conductive material of solder paste, which can promote the adhesion effect of the back surface of the wafer 300 and the metal foil layer 307 under the condition of being heated and melted, so that the metal foil layer 307 is more firmly and tightly laminated to the wafer 300. At the same time, it is also possible to uniformly apply pressure on the entire laminated metal foil layer 307 region, so that the respective bonding regions of the entire metal foil layer 307 are balanced and stressed, so as to further closely press the metal foil layer 307 to The back of the wafer. If the planarized top end face of the metal bump 205 is exposed from the plastic encapsulation layer 206 during this heating phase, as shown in FIG. 3B, the melting point of the metal bump 205 must also be required to be slightly lower than the melting point of the conductive adhesive layer 306 to avoid The metal bump 205 is melted and overflowed.

In FIG. 3C, a layer of composite tape 308 is further adhered to the metal foil layer 307. In addition to the simple bonding, the bonding operation here can also apply external pressure to the composite tape 308 at the same time and use a lamination method to reinforce the adhesive. Cohesion. The composite tape 308 should comprise at least one adhesive layer and a protective film layer (preferably black), and the adhesive layer is firmly bonded to the metal foil layer 307. It faces away from one side of the wafer, and the protective film layer needs to be used for subsequent printed labels in addition to physically protecting the wafer or wafer, as will be described in detail later. The composite tape 308 can be, for example, a Japanese LC TAPE, or a composite layer of a common adhesive layer and a polyamide-imide (PI) layer (PI layer as a protective film layer). In addition, as an alternative, but not limited, the foregoing step of heating the wafer 300 may be moved to completion of the bonding of the composite tape 308, that is, without the stage of laminating the metal foil layer 307 to the back side of the wafer. After heating, the bonding of the composite tape 308 is completed, and then the entire wafer with the plastic sealing layer and the composite tape is heated, as shown in Fig. 3D. Because the adhesive layer of the partially selected type of composite tape 308 can be cured substantially after being heated, its temporary tack is thereby converted into permanent adhesion, while the conductive adhesive layer 306 is just needed. Melted by heat, resulting in better results and lower costs. During this heating phase, pressure can also be applied uniformly across the bond area of the composite tape 308, which is naturally transferred to the metal foil layer 307 to promote and enhance the close fit between the metal foil layer 307 and the wafer 300. degree.

It is easy to understand that the manner of using the composite tape 308 is different from the process of forming a plastic seal on the back side of the wafer. If it is intended to perform a molding process on the back side of the wafer (for example, in FIG. 1C, an attempt is made to obtain the plastic-clad layer 123 on the back side of the wafer) At least the use of plastic packaging equipment, but also involves grinding and thinning the plastic coating layer on the back of the wafer, the thickness is not very accurate, which will encounter various problems revealed by the background art. It will be apparent that the wafer back side does not require any plastic sealing process and the preparation of the plastic sealing layer, which is another distinct feature of the present invention that distinguishes it from the prior art.

In Fig. 3E, the standard printing labeling process (Marking) can be realized, although direct coating printing can be realized, in order to ensure that the marking can last longer, more often using laser etching to print, thereby The back side of the exposed side of the composite tape 308 is printed on the back side to form an identification mark 325, which is substantially printed on the protective film layer of the composite tape 308. The identification mark 325 generally includes various attribute information of the product, such as manufacturer, model, specification, etc. The area where the composite tape 308 overlaps each wafer is printed with an identification mark 325. The thickness of the composite tape 308 is preset. As described above, the composite tape 308 is not a plastic seal layer, and has abandoned one. A plastic sealing process does not require additional thinning, so the difficult problem of difficult printing that is mentioned in the background art is completely lost during this period. In Figures 3F-3G, along the scribe line to perform a standard wafer saw step, wafer 300 can be diced to separate a plurality of individual wafers 300'. Mainly to cut the laminate between adjacent wafers 300', the laminate includes a plastic sealing layer 206, a wafer 300, a conductive adhesive layer 306, a metal foil layer 307 and a composite tape 308, and a metallization layer 305, thereby forming a plurality of A separate power semiconductor device 500. In the power semiconductor device 500, a top molding layer 206' is formed on the front surface of the wafer 300', which is cut by the plastic sealing layer 206, and the pad 201 on the front surface of the wafer 300' is provided with metal bumps 205, and the top molding is provided. The layer 206' surrounds the sidewall of the metal bump 205 such that the top surface of each of the metal bumps 205 is exposed from the top surface of the top molding layer 206'. A metallization layer 305 on the back side of the wafer 300 is also diced to form a back metallization layer disposed on the backside of each wafer 300'. The semiconductor device 500 further includes a laminate on the back or back metallization layer 305 of the wafer 300'. The bottom metal foil layer 307' is cut by the metal foil layer 307, and the bottom metal foil layer 307' is firmly bonded to the back surface of the wafer 300' by the conductive adhesive layer 306. The semiconductor device 500 further includes a bottom composite tape layer 308' cut from the composite tape 308 adhered to the bottom metal foil layer 307', and the printing or identification symbol 325 previously printed on the composite tape 308 is transferred to the end. On the composite tape layer 308'. The power semiconductor device 500 is opposite to the prior art. Although the wafer 300' is front coated with a top molding layer 206', it is still considered to be a Molded Chip Scale Package (MCSP), but the back side of the wafer 300' is The outer composite tape layer 308' is replaced by any plastic body and replaced by a sealant.

In an optional but non-limiting embodiment, as in Figures 4A-4B, the only difference compared to the flow of Figures 3A-3G is that in view of the transport of thinner wafers 300 or at various stages of operation The wafer 300 still has the potential to be fragile, so an additional carrier wafer or dummy wafer 350 is additionally introduced, and the dummy wafer 350 is bonded to the thinned wafer 300, and the wafer 350 is A top surface or a bottom surface is bonded to the thinned top surface of the polished plastic sealing layer 206, and then the wafer 300 is thinned on the back side of the conductive bonding layer 306 and the metal according to the processes of FIGS. 3A to 3G. Foil layer 307, composite tape 308. In Figures 4A-4B, a composite glue is to be formed After the strip 308, the dummy wafer 350 can be peeled off. It is noted that the timing of the stripping may be after the step of obtaining the composite tape 308 in FIG. 3C, or after the heating step in FIG. 3D, or even after the printing step in FIG. 3E. , but usually before the cutting step of Figure 3F. The mechanical strength of the dummy wafer 350 to the wafer 300, in addition to shipping and conventional operational steps, is a further advantage that the metal foil layer 307 and/or the composite tape 308 are placed in a step that is subject to lamination. During this period, an external force must be applied. This external force directly transmits a thin wafer 300, which brings a certain risk of fragility. The dummy wafer 350 can avoid and eliminate these risks to a certain extent.

In another alternative, but non-limiting embodiment, as in Figures 5A-5C, the difference is that the step of polishing the plastic encapsulation layer 206 of Figure 2E is skipped, as in Figure 2D, as compared to the flow of Figures 3A-3G. The process of FIGS. 3A-3G is performed after the step, that is, the original thickness of the encapsulation layer 206 is retained, at least before the composite tape 308 forming the back side of the wafer, the encapsulation layer 206 is not ground and thinned. 5A-5B, the original thickness of the plastic encapsulation layer 206 is retained, and then the conductive adhesive layer 306, the metal foil layer 307, and the composite tape 308 are sequentially formed on the thinned back surface of the wafer 300 according to the flow of FIGS. 3A to 3G. In FIG. 5C, after the composite tape 308 is formed, the thinned plastic sealing layer 206 can be ground. It is noted that the timing of polishing the plastic sealing layer 206 may be after the step of obtaining the composite tape 308 in FIG. 3C, or may be implemented in FIG. 3D. After the heating step, even after the printing step of Figure 3E, but typically before the cutting step of Figure 3F. In some advantageous embodiments, if the thickness of the plastic encapsulation layer 206 is left unthinned in the step of FIG. 3B or 3C, the metal bumps 205 are coated in the plastic encapsulation layer 206 without being exposed, at this time, the metal The melting point requirement between the bumps 205 and the conductive adhesive layer 306 is less severe, because the metal bumps 205 are covered without being lost by the melt overflow. In the embodiment of FIGS. 5A to 5C, before the plastic sealing layer 206 is ground and thinned, the plastic sealing layer 206 provides the mechanical strength to the wafer 300. Similarly, the direct transfer of the laminated external force to the thinner wafer 300 brings a certain degree. The risk of brittleness, while the plastic layer 206 can circumvent and eliminate these risks to a certain extent.

6B is a perspective view of the MCSP power semiconductor device 500 flipping the device of FIG. 3G to the underside of the identification symbol 325. Based on the detailed description of the structure of the layers on the back side of the wafer and for explanation, the thickness of the back layers is not completely in accordance with the actual product and the wafer. Thickness ratio relationship Draw. In an alternative embodiment, for example, the package form of the present invention can be applied to a wafer of a common drain dual MOSFET of a widely used battery charge and discharge circuit. The wafer 300' of FIG. 6B integrates the power metal oxide semiconductor field effect transistors M1 and M2 shown in FIG. 6A, wherein the gate oxide D1 of the metal oxide semiconductor field effect transistor M1 and the metal oxide semiconductor field effect The drain D2 of the transistor M2 is connected together, and the opening or closing of the gate G1 of the metal oxide semiconductor field effect transistor M1 and the gate G2 of the metal oxide semiconductor field effect transistor M2 is controlled by the power management circuit, based on Reducing the resistance or Rss (resistance of the source S1 to the source S2) of the metal oxide semiconductor field effect transistors M1, M2 connected in series, considering that the original metallization layer 305 on the back side of the wafer is thin, cannot effectively achieve this purpose The bottom metal foil layer 307' additionally laminated to the back side of the wafer 300' shown in FIG. 6B of the present invention constitutes a common drain electrode of the metal oxide semiconductor field effect transistors M1, M2 integrated in the wafer 300'. In the semiconductor device 500, one of the metal bumps 205S1 having a flattened tip end surface is contacted and soldered to the conjugated metal oxide semiconductor field effect transistor M1 as a metal oxide semiconductor field effect transistor M1 source pad. The pad 201, the metal bump 205G1 having the flattened top end surface is in contact with and soldered to the ytterbium metal oxide semiconductor field effect transistor M1, and is embodied as a metal oxide semiconductor field effect transistor M1 gate pad. Pad 201. A metal bump 205S2 having a flattened top end surface is in contact with and soldered to the spacer 201 of the metal oxide semiconductor field effect transistor M2 source pad, which is contacted and soldered to the common gate metal oxide semiconductor field effect transistor M2, A metal bump 205G2 of the flattened top surface contacts and is soldered to the liner 201 of the MOSFET etched metal gate M2 gate pad. The top plastic encapsulation layer 206' covers the front side of the wafer 300', and the top plastic encapsulation layer 206' surrounds the respective sidewalls of the metal bumps 205S1, 205S2, 205G1, 205G2, and the top end surface of each of the metal bumps is flattened from the top molding layer 206. 'The top surface of the top is exposed. The bottom metal foil layer 307' is press-bonded to the back side of the wafer 300' by the conductive adhesive layer 306, and the bottom composite tape layer 308' is bonded or laminated to the bottom metal foil layer 307'. Alternatively, a single metal foil layer 307' may be bonded to a single side of the back side of the wafer 300' with a precious metal coating.

In an alternative embodiment of Figures 7A-7C, in particular Figures 7B-7C, a lamination step of the composite tape 308 using a specific backside coating TAPE (e.g., using LC TAPE) is illustrated. FIG. 7A is a process obtained by the steps of FIGS. 2A to 2E, through plastic sealing, wafer thinning, and sputtering of the back metallization layer, which have been described in detail in the foregoing, and thus will not be further described in this embodiment. The conductive adhesive layer 306 is applied to the metallization layer 305 first, and the metal foil layer 307 is pressed onto the metallization layer 305 on the back side of the wafer 300 by using the conductive adhesive layer 306. The key point is: FIG. 7B The step of laminating LC TAPE on the metal foil layer 307 on the back side of the wafer 300 is exemplarily shown, and FIG. 7C corresponds to FIG. 7B, and the specific structure of the wafer 300 and the plastic seal layer 206 and the back layers are taken. A part of the fragment is used as an example. The other subsequent steps after FIG. 7C are substantially the same as FIGS. 3C to 3G. In this embodiment, some necessary or non-essential steps that have been fully explained above have been omitted, and other standard processes such as laser printing labels, implementation of cutting, test packaging, etc. on LC TAPE are not here. Repeat them one by one.

The LC TAPE may include a thermosetting component, a binder polymer component, an energy curable component, and the like. In order to avoid the doubt that LC TAPE may be considered “not a regular term”, several ingredients disclosed by Lintec Corporation of Japan are cited: thermosetting components include epoxy resin, phenol resin, melamine resin, urea resin, polyester resin, polyurethane resin. , an acrylic resin, a polyimide resin, a benzoxazine resin, and a mixture thereof. In addition, to provide suitable adhesive tape and improve processability, it is necessary to use a binder polymer component such as an acrylic polymer, a polyester resin, a polyurethane resin, an organic resin and a rubber. The polymer is preferably an acrylic polymer. Energy ray curable components, including a compound that can be polymerized or cured by radiant energy rays such as ultraviolet light and electron beams. In addition, the composite tape can be colored, and the composite tape forming layer is colored by adding a pigment or a dye thereto, and the colored composite tape such as black can improve the appearance of the final wafer.

In an alternative embodiment of 8A-8C, the material of the conductive adhesive layer 306 and the corresponding lamination mode may be modified slightly from the previous embodiments. As shown in FIG. 8B, before attempting to laminate the metal foil layer 307 on the metallization layer 305 of FIG. 8A, it is also necessary to first advance the metal foil layer 307. Tin is applied to the bonding surface for lamination bonding to the back side of the wafer 300, and the tin plating layer serves as a conductive bonding layer 306 different from the conductive silver paste. If the joint is additionally plated with some precious metallization coating such as silver or gold, the tin plating layer should be plated on the precious metallization coating. Thereafter, in order to make the tin plating layer have a better bonding effect in the laminating step, as an option, a lamination force of about 100 to 2500 gram force (gf) may be applied to the metal foil layer 307, and This step is selected to be carried out at ambient temperature conditions of about 200 to 400 degrees Celsius to laminate a metal foil layer 307 with a tin plating layer onto the metallization layer 305 on the back side of the wafer 300. In addition, the embodiment of FIG. 8C does not plate tin on one side of the metal foil layer 307, but directly deposits tin on the back side of the wafer 300, such as on the metallization layer 305 of FIG. 8A, and then layers. The metal foil layer 307 is pressed to the back side of the wafer 300, and the tin layer is used as the conductive adhesive layer 306 for press bonding, thereby laminating the metal foil layer 307 to the metallization of the tinned layer on the back side of the wafer 300. On layer 305.

The exemplary embodiments of the specific structures of the specific embodiments have been described above by way of illustration and the accompanying drawings. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are to cover all such modifications and modifications The scope and content of any and all equivalents are intended to be within the scope and spirit of the invention.

205G1‧‧‧metal bumps

205G2‧‧‧metal bumps

205S1‧‧‧metal bumps

205S2‧‧‧metal bumps

206'‧‧‧Top plastic layer

300'‧‧‧ wafer

305‧‧‧metallization

306‧‧‧ Conductive bonding layer

307'‧‧‧metal foil layer

308'‧‧‧Bottom composite tape layer

500‧‧‧Power semiconductor devices

Claims (10)

A method for preparing a power semiconductor device, comprising the steps of: providing a wafer having a plurality of wafers with a plastic layer on the front side; providing a conductive adhesive layer on one side of the wafer or a metal foil layer; a metal foil layer is applied to the back surface of the wafer and pressed and bonded by the conductive adhesive layer; a composite tape is pasted onto the metal foil layer; and a laminate between adjacent wafers is cut, the laminate includes the laminate The plastic seal layer, the wafer, the conductive adhesive layer, the metal foil layer and the composite tape form a plurality of independent power semiconductor devices. The method of claim 1, wherein the composite tape is printed on the composite tape to form an identification symbol prior to cutting the laminate. The method of claim 1, wherein in the step of laminating the metal foil layer, the wafer is heated simultaneously and pressure is applied to the metal foil layer; or the bonding of the composite tape is completed. After the step, the wafer is heated and pressure is applied to the composite tape and the metal foil layer to tightly press the metal foil layer to the back side of the wafer. The method of claim 1, wherein before laminating the metal foil layer, a precious metal coating is plated on one side of the metal foil layer, and then the metal foil layer is coated with the noble metal coating. One side is laminated to the back side of the wafer. The method of claim 1, wherein: before forming the plastic sealing layer, a plurality of metal bumps are respectively disposed on a plurality of pads on the front surface of each of the wafers; and then the plastic sealing layer is molded Forming the front surface of the wafer and covering each of the metal bumps; grinding and thinning the plastic sealing layer until the top ends of the metal bumps are partially ground and exposed, thereby forming each of the metal bumps The flattened top surface is exposed from the top surface of the molding layer. The method of claim 1, wherein before the conductive adhesive layer is disposed on the back surface of the wafer, a dummy wafer is bonded to the wafer and bonded to the plastic seal layer. On the top surface, the dummy wafer is peeled off after the bonding step of the composite tape is completed. The method of claim 1, wherein: before forming the plastic sealing layer, a plurality of metal bumps are respectively disposed on a plurality of pads on the front surface of each of the wafers; and then the plastic sealing layer is molded Forming the front side of the wafer and covering each of the metal bumps; after completing the bonding step of the composite tape but before cutting, grinding and thinning the plastic sealing layer until the top end of each of the metal bumps is partially Grinding and exposing, thereby forming a top end surface of each of the metal bumps flattened, and being exposed from the top surface of the plastic sealing layer. A power semiconductor device comprising: a wafer; a top molding layer covering the front surface of the wafer, wherein a plurality of metal bumps are respectively disposed on the plurality of pads on the front surface of the wafer, and the top plastic sealing layer surrounds the metal bumps Around the sidewall of the block, a top surface of each of the metal bumps is exposed from the top surface of the top molding layer; a bottom metal foil layer laminated on the back surface of the wafer, and the electrically conductive layer is used to conduct the The bottom metal foil is laminated and bonded on the back side of the wafer; a bottom composite tape layer adhered to the bottom metal foil layer. The power semiconductor device according to claim 8, wherein the wafer is integrated with a pair of conjugated metal oxide semiconductor field effect transistors, and the bottom metal foil layer constitutes the field effect of the pair of conjugated metal oxide semiconductors. A common drain electrode of the transistor, and the power semiconductor device has a plurality of metal bumps respectively contacting the gate pad and the source pad of the pair of conjugated MOSFETs. The power semiconductor device according to claim 8, wherein the bottom metal foil is laminated on a side of the back surface of the wafer with a precious metal coating.