TW201604869A - Resistance random access memory apparatus and operation method thereof - Google Patents

Abstract

A resistance random access memory apparatus and an operation method thereof are provided. A default bias current is respectively provided to each resistance random access memory cell during a forming period, so as to uniform an impedance value of each resistance random access memory cell.

Description

Resistive random access memory device and operation method thereof

The present invention relates to a memory device, and more particularly to a resistive random access memory device and method of operation thereof.

Non-volatile memory has the advantage that the stored data will not disappear after power-off, so it is a necessary memory element for many electronic products to maintain normal operation. At present, Resistive Random Access Memory (RRAM) is a non-volatile memory actively developed in the industry, which has low write operation voltage, short write erase time, long memory time, and non-destructive memory. Sexual reading, multi-state memory, simple structure and small required area have great potential for application in personal computers and electronic devices in the future.

Resistive random access memory uses oxygen vacancies or oxygen ions to form conductive filaments. Externally applied voltage polarity and current values cause the conductive material to break. The regenerated phenomenon causes a difference in resistance values. However, process variations often occur in semiconductor processes, such as oxide thickness or ion doping concentration. As a result, the bias potential of the transistor is shifted, and the resistance value of the formed conductive filament is different, thereby affecting the writing of the bit.

The invention provides a resistive random access memory device and an operation method thereof, which can improve the reliability of data access.

The resistive random access memory device of the present invention comprises a plurality of resistive random access memory cells and a plurality of current sources. The plurality of current sources are respectively coupled between the corresponding bit line and the corresponding resistive random access memory cell, and respectively provide the same preset bias current to each resistive random access memory cell during formation, The impedance values of the respective resistive random access memory cells are homogenized.

In an embodiment of the invention, the predetermined bias current is a minimum current required for the resistive random access memory cells to form a low resistance state.

In an embodiment of the invention, each of the resistive random access memory cells includes a variable impedance unit and a switching unit. The variable impedance unit is coupled to the corresponding current source. The switching unit is coupled to the variable impedance unit and is controlled by the control voltage to be turned on during formation.

In an embodiment of the invention, the switch unit is a transistor, and the gate of the transistor is coupled to the word line to receive the control voltage, and the drain of the transistor is coupled to the variable impedance unit, the source of the transistor. The pole is coupled to the source line.

Embodiments of the present invention provide a method of operating a resistive random access memory device, wherein the resistive random access memory device includes a plurality of resistive random access memories Taking the memory cell, the operation method of the resistive random access memory device includes the following steps. The preset bias current is set according to the process difference of the plurality of resistive random access memory cells. When entering the formation period, the same preset bias current is respectively supplied to each of the resistive random access memory cells to equalize the impedance values of the respective resistive random access memory cells.

In an embodiment of the invention, the step of setting the preset bias current according to the process difference of the plurality of resistive random access memory cells comprises the following steps. A minimum current required to cause the plurality of resistive random access memory cells to form a low resistance state is detected. Set this minimum current to the preset bias current.

In an embodiment of the invention, each of the resistive random access memory cells includes a variable impedance unit and a switch unit, wherein the variable impedance unit is coupled to the switch unit, and the operation method of the resistive random access memory device further includes A control voltage is supplied to the switching unit to turn on the switching unit during formation.

In an embodiment of the invention, the switch unit is a transistor, and the gate of the transistor is coupled to the word line to receive the control voltage, and the drain of the transistor is coupled to the variable impedance unit, the source of the transistor. The pole is coupled to the source line.

Based on the above, the embodiment of the present invention provides a predetermined bias current for each resistive random access memory cell during formation to homogenize the impedance values of the respective resistive random access memory cells, thereby improving data access. Reliability.

The above described features and advantages of the invention will be apparent from the following description.

102‧‧‧Resistive random access memory cells

104‧‧‧current source

BL‧‧‧ bit line

Is‧‧‧Preset bias current

202‧‧‧Variable impedance unit

204‧‧‧Switch unit

M1‧‧‧O crystal

WL‧‧‧ character line

SL‧‧‧ source line

S302~S304‧‧‧Method of operation of resistive random access memory device

1 is a schematic diagram of a resistive random access memory device according to an embodiment of the invention.

2 is a schematic diagram of a resistive random access memory device according to another embodiment of the present invention.

3 is a flow chart showing an operation method of a resistive random access memory device according to an embodiment of the present invention.

1 is a schematic diagram of a resistive random access memory device according to an embodiment of the invention. Please refer to FIG. 1. The resistive random access memory device includes a plurality of resistive random access memory cells 102 and a plurality of current sources 104. The current sources 104 are respectively coupled to the corresponding bit lines BL and the corresponding resistive random access memory cells 102. In order to simplify the description, FIG. 1 only shows a single resistive random access memory cell 102 and its corresponding current source 104. The resistance value of the resistive random access memory cell 102 can be set to a low impedance state (representing a logic level "1") or a high impedance state (representing a logic level "0") depending on the data to be written. Before the data is written, the resistive random access memory cell 102 is first set to a low impedance state during the formation period, and then the impedance of the resistive random access memory cell 102 is changed according to the written data during the set period. status.

In this embodiment, the current source 104 will provide the above separately during formation. The plurality of resistive random access memory cells have the same preset bias current Is, wherein the predetermined bias current Is is such that each of the resistive random access memory cells 102 in the resistive random access memory device can be formed low The minimum current required in the case of a resistive state. In this way, the current flowing to each of the resistive random access memory cells 102 can be prevented from being different due to the process variation of the semiconductor process, and the impedance values of the respective resistive random access memory cells can be uniformized, thereby improving the resistive type. Data storage capability and read reliability of random access memory devices.

2 is a schematic diagram of a resistive random access memory device according to another embodiment of the present invention. Please refer to FIG. 2 . In detail, the resistive random access memory cell 102 can be, for example, as shown in FIG. 2, including a variable impedance unit 202 and a switch unit 204, wherein the variable impedance unit 202 is coupled to the switch unit 204 and the resistive random access memory. A current source 104 corresponding to cell 102. In this embodiment, the switch unit 204 is implemented by a transistor M1, but is not limited thereto. The gate of the transistor M1 is coupled to the word line WL, and the drain and the source of the transistor M1 are respectively coupled to the variable impedance unit 202 and the source line SL, wherein the variable impedance unit 202 can be, for example, an oxide base. (oxide-based) resistive random access memory. When the resistive random access memory cell 102 is in formation, the transistor M1 is turned on by the control voltage from the word line WL, while the current source 104 supplies the preset bias current Is to the variable impedance unit 202, The oxygen ions in the variable impedance unit 202 are displaced to form oxygen vacancies to form a conductive filament. Due to the generation of the conductive filaments, the impedance value of the variable impedance unit 202 is greatly reduced, that is, the variable impedance unit 202 is set to a low impedance state (representing a logic level "1").

In addition, when the resistive random access memory cell 102 is in the set period, if the logic level "0" is to be written into the resistive random access memory cell 102, a bias voltage can be applied to the source line SL. The crystal M1 also receives the control voltage from the word line WL and is in an on state. Therefore, the current will flow from the end of the transistor M1 coupled to the source line SL to the variable impedance unit 202, so that the oxygen ions move back into the variable impedance unit 202, and the oxygen vacancy in the original variable impedance unit 202 will disappear. That is, the conductive filaments will disappear. Due to the disappearance of the conductive filaments, the impedance value of the variable impedance unit 202 is greatly increased, that is, the variable impedance unit 202 is set to a high impedance state (representing a logic level "0").

The manner in which the variable impedance unit 202 is set to the high impedance state is not limited to applying the bias voltage to the source line SL. In some embodiments, the resistive random access memory may also be transmitted through the current source 104. The cell 102 draws current to set the variable impedance unit 202 to a high impedance state. In addition, since the preset bias current Is provided during the formation of the current source 104 is such that each of the resistive random access memory cells 102 in the resistive random access memory device can form a low resistance state, The minimum current, so that when the resistive random access memory cell 102 is set to the high impedance state during the setting period, an excessive bias voltage is applied to the source line SL to cause the conductive filament to be regenerated, and the resistance is lowered. Data access reliability of a random access memory device.

3 is a schematic flow chart showing an operation method of a resistive random access memory device according to an embodiment of the present invention. Please refer to FIG. 3. It can be seen from the above embodiments that the operation method of the resistive random access memory device includes at least the following steps. The preset bias current is set according to the process difference of the plurality of resistive random access memory cells (step S302). In detail, the preset bias current may be determined by, for example, first detecting a minimum current required to form the plurality of resistive random access memory cells into a low resistance state (step S302A), and then minimizing the current. The current is set to a preset bias current (step S302B). Next, when entering the formation period, preset bias currents are respectively supplied to the respective resistive random access memory cells to equalize the impedance values of the respective resistive random access memory cells (step S304). In detail, each of the resistive random access memory cells may include, for example, a variable impedance unit and a switching unit coupled to the variable impedance unit, during which a control voltage may be supplied to the switching unit to turn on the switching unit to uniformly The variable impedance unit of the plurality of resistive random access memory cells forms a conductive filament. The switching unit can be, for example, a transistor, and the gate of the transistor is coupled to the word line to receive the control voltage, and the drain and the source of the transistor are respectively coupled to the variable impedance unit and the source line.

In summary, the embodiment of the present invention provides a predetermined bias current for each resistive random access memory cell during formation to homogenize the impedance values of the respective resistive random access memory cells, thereby improving data access. The reliability, wherein the preset bias current is a minimum current required in the case where each of the resistive random access memory cells in the resistive random access memory device can form a low resistance state.

102‧‧‧Resistive random access memory cells

104‧‧‧current source

BL‧‧‧ bit line

Is‧‧‧Preset bias current

Claims (8)

A resistive random access memory device includes: a plurality of resistive random access memory cells; and a plurality of current sources respectively coupled to corresponding bit lines and corresponding resistive random access memory cells During the formation, the resistive random access memory cells are respectively provided with a predetermined bias current to equalize the impedance values of the resistive random access memory cells. The resistive random access memory device of claim 1, wherein the predetermined bias current is a minimum current required for the resistive random access memory cells to form a low resistance state. The resistive random access memory device of claim 1, wherein each of the resistive random access memory cells comprises: a variable impedance unit coupled to a corresponding current source; and a switching unit coupled The variable impedance unit is connected to be turned on by a control voltage during the formation. The resistive random access memory device of claim 3, wherein the switching unit is a transistor, and the gate of the transistor is coupled to a word line to receive the control voltage. The drain of the crystal is coupled to the variable impedance unit, and the source of the transistor is coupled to a source line. A method for operating a resistive random access memory device, the resistive random access memory device comprising a plurality of resistive random access memory cells, the method of operating the resistive random access memory device comprising: And setting a preset bias current according to the process difference of the resistive random access memory cells; and providing the resistive random access memory cells to the predetermined bias current when entering a forming period to homogenize The impedance value of each of the resistive random access memory cells. The method for operating a resistive random access memory device according to claim 5, wherein the step of setting the preset bias current according to a process variation of the resistive random access memory cells comprises: detecting The resistive random access memory cells each form a minimum current required for a low resistance state; and the minimum current is set to the preset bias current. The method of operating a resistive random access memory device according to claim 5, wherein each of the resistive random access memory cells comprises a variable impedance unit and a switching unit, wherein the variable impedance unit is coupled Connected to the switch unit, the method of operating the resistive random access memory device further includes: providing a control voltage to the switch unit to turn on the switch unit during the forming. The method of operating a resistive random access memory device according to claim 7, wherein the switching unit is a transistor, and the gate of the transistor is coupled to a word line to receive the control voltage. The drain of the transistor is coupled to the variable impedance unit, and the source of the transistor is coupled to a source line.