CN105321559B - Resistive random access storage device and its operating method - Google Patents
Resistive random access storage device and its operating method Download PDFInfo
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- CN105321559B CN105321559B CN201410372747.XA CN201410372747A CN105321559B CN 105321559 B CN105321559 B CN 105321559B CN 201410372747 A CN201410372747 A CN 201410372747A CN 105321559 B CN105321559 B CN 105321559B
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Abstract
A kind of resistive random access storage device and its operating method.There is provided respectively during formation and preset bias current per each and every one resistive random access memory cell one, to homogenize the impedance value of each resistive random access memory cell, and then improve the reliability of data access.
Description
Technical field
The invention relates to a kind of storage device, and in particular to a kind of resistive random access storage device and
Its operating method.
Background technology
Nonvolatile memory has the advantages that the data of deposit will not disappear after a loss of power, therefore is many electronics productions
Product maintain memory cell essential to normal operating.At present, resistive random access memory (Resistive Random
Access Memory；RRAM) be a kind of nonvolatile memory that industry actively develops, its with write operation voltage it is low, write
Enter the time of erasing is short, memory time is long, non-destructive is read, multimode memory, the advantages that simple in structure and required area is small,
The great application potential on following PC and electronic equipment.
Resistive random access memory is to utilize Lacking oxygen (oxygen vacancies) or oxonium ion (oxygen
Ions) move to form conductive filiform (conductive filament), apply polarity of voltage and current value by external,
Promote conductive shape thing fracture and the phenomenon of regeneration, cause the difference of resistance value.But often made in manufacture of semiconductor
The situation of Cheng Bianyi, if such as oxidated layer thickness or ion doping concentration it is inconsistent, the bias for causing transistor is sent out
Raw offset, and the resistance value for the conductive filiform for be formed produces difference, and then influence the write-in of bit.
The content of the invention
The present invention provides a kind of resistive random access storage device and its operating method, can improve the reliable of data access
Property.
The resistive random access storage device of the present invention, including multiple resistive random access memory cells and multiple electricity
Stream source.Plurality of current source is respectively coupled between corresponding bit line and corresponding resistive random access memory cell,
Identical default bias current is provided during formation respectively to each resistive random access memory cell, to homogenize each resistance
The impedance value of formula random access memory born of the same parents.
In one embodiment of this invention, above-mentioned default bias current is to be respectively formed resistive random access memory cell
Minimum current needed for low resistance state.
In one embodiment of this invention, above-mentioned each resistive random access memory cell include variable impedance unit with
Switch element.Wherein variable impedance unit couples corresponding current source.Switch element couples variable impedance unit, is controlled by control
Voltage and during formation be switched on.
In one embodiment of this invention, above-mentioned switch element is transistor, and the grid of transistor is coupled to word-line,
Voltage is controlled to receive, the drain electrode coupling variable impedance unit of transistor, the source electrode of transistor is coupled to source electrode line.
The embodiment of the present invention provides the operating method of a resistive random access storage device, and wherein resistor type random access is deposited
Taking storage device includes multiple resistive random access memory cells, under the operating method of resistive random access storage device includes
Row step.The default bias current of processing procedure difference setting according to above-mentioned multiple resistive random access memory cells.Formed when entering
During period, identical default bias current is provided respectively to each resistive random access memory cell, to homogenize each resistance
The impedance value of formula random access memory born of the same parents.
In one embodiment of this invention, the above-mentioned processing procedure difference setting according to multiple resistive random access memory cells is pre-
If the step of bias current, comprises the following steps.Detection makes above-mentioned multiple resistive random access memory cells be respectively formed low resistance state
Required minimum current.This minimum current is set as default bias current.
In one embodiment of this invention, it is above-mentioned per each and every one resistive random access memory cell include variable impedance unit with
And switch element, wherein variable impedance unit coupling switch element, the operating method of resistive random access storage device are also wrapped
Include, control voltage is provided during formation to switch element to turn on switch element.
In one embodiment of this invention, above-mentioned switch element is transistor, and the grid of transistor is coupled to word-line,
Voltage is controlled to receive, the drain electrode coupling variable impedance unit of transistor, the source electrode of transistor is coupled to source electrode line.
Based on above-mentioned, the embodiment of the present invention by providing each resistive random access memory cell respectively during formation
One default bias current, to homogenize the impedance value of each resistive random access memory cell, and then improve data access can
By property.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and attached drawing appended by cooperation
It is described in detail below.
Brief description of the drawings
Fig. 1 is the schematic diagram of the resistive random access storage device of one embodiment of the invention.
Fig. 2 is the schematic diagram of the resistive random access storage device of another embodiment of the present invention.
Fig. 3 is the flow diagram of the operating method of the resistive random access storage device of one embodiment of the invention.
Wherein, the reference numerals are as follows：
102：Resistive random access memory cell
104：Current source
BL：Bit line
Is：Default bias current
202：Variable impedance unit
204：Switch element
M1：Transistor
WL：Word-line
SL：Source electrode line
S302~S304：The operating method step of resistive random access storage device
Embodiment
Fig. 1 is the schematic diagram of the resistive random access storage device of one embodiment of the invention, refer to Fig. 1.Resistance-type
Random access storage device includes multiple resistive random access memory cells 102 and multiple current sources 104, and current source 104 divides
It is not coupled between corresponding bit line BL and corresponding resistive random access memory cell 102, illustrates to simplify, Fig. 1 only shows
Go out single a resistive random access memory cell 102 and its corresponding current source 104.Wherein resistive random access memory cell
102 resistance value can be set to low impedance state (representing logic level " 1 ") or high resistant according to the difference of write data
Anti- state (representing logic level " 0 ").Before data write-in is carried out, resistive random access memory cell 102 can be during formation
Low impedance state is first set to, then changes resistive random access note according to the different of the data that writes again during setting
Recall the impedance state of born of the same parents 102.
In the present embodiment, current source 104 will provide above-mentioned multiple resistive random access memories respectively during formation
The identical default bias current Is of born of the same parents, wherein default bias current Is is each electricity made in resistive random access storage device
Resistive random access memory born of the same parents 102 can form minimum current required in the case of low resistance state.Consequently, it is possible to it can avoid
It is different because of the processing procedure difference of manufacture of semiconductor to flow to the electric current of each resistive random access memory cell 102, and can be equal
The impedance value of each resistive random access memory cell is homogenized, and then the data for improving resistive random access storage device preserves
Ability and reading reliability.
Fig. 2 is the schematic diagram of the resistive random access storage device of another embodiment of the present invention, refer to Fig. 2.In detail
For, above-mentioned resistive random access memory cell 102 can be for example shown in Fig. 2, including variable impedance unit 202 and switch are singly
Member 204, wherein variable impedance unit 202 couple 102 corresponding electric current of switch element 204 and resistive random access memory cell
Source 104.In the present embodiment, switch element 204 is to be realized with a transistor M1, but is not limited thereto.Transistor M1
Grid be coupled to word-line WL, drain electrode and the source electrode of transistor M1 are then respectively coupled to variable impedance unit 202 and source electrode line SL,
Wherein variable impedance unit 202 may be, for example, basic (oxide-based) resistive random access memory of oxide.Work as resistance
When formula random access memory born of the same parents 102 are in during forming, transistor M1 is controlled by be led from the control voltage of word-line WL
It is logical, while current source 104 provides default bias current Is to variable impedance unit 202 so that the oxygen in variable impedance unit 202
Ion is displaced and forms Lacking oxygen (oxygen vacancies) and form conductive filiform.Due to the production of conductive filiform
Raw, the impedance value of variable impedance unit 202 can be greatly reduced, that is, variable impedance unit 202 is set to low impedance state (generation
Table logic level " 1 ").
In addition, when resistive random access memory cell 102 is in during setting, if being intended to logic level " 0 " writing electricity
Resistive random access memory born of the same parents 102, can be biased voltage to source electrode line SL, and transistor M1 is also received from word-line WL at this time
Control voltage and it is in the conduction state.Therefore, electric current will couple source electrode line SL one end from transistor M1 and flow to variable impedance list
Member 202, and make it that oxonium ion is moved back in variable impedance unit 202, the Lacking oxygen in script variable impedance unit 202 will disappear
Lose, that is, conductive filiform can disappear.Due to conductive Filamentous thing's vanished, the impedance value of variable impedance unit 202 can be carried significantly
Height, that is, variable impedance unit 202 is set to high impedance status (representing logic level " 0 ").
Wherein, variable impedance unit 202 is set as that the mode of high impedance status is not limited to be biased voltage to source
On polar curve SL, in some embodiments, also electric current can be drawn to resistive random access memory cell 102 by current source 104
Mode variable impedance unit 202 is set as high impedance status.Further, since what current source 104 provided during formation
Default bias current Is is to make each resistive random access memory cell 102 in resistive random access storage device can shape
Required minimum current in the case of into low resistance state, therefore can avoid resistive random access memory cell during setting
102 when being set as high impedance status, applies excessive bias voltage to source electrode line SL and causes conductive filiform to regenerate, and
Reduce the data access credibility of resistive random access storage device.
Fig. 3 is the flow diagram of the operating method of the resistive random access storage device of one embodiment of the invention, please
With reference to Fig. 3.From above-described embodiment, the operating method of resistive random access storage device includes at least the following steps, first
First, the default bias current (step S302) of processing procedure difference setting according to multiple resistive random access memory cells.Specifically,
The deciding means of default bias current may be, for example, that first detection makes above-mentioned multiple resistive random access memory cells be respectively formed low electricity
Minimum current (step S302A) needed for resistance state, is then set as default bias current (step by this minimum current again
S302B).Then, when enter formed during when, provide default bias current respectively to each resistive random access memory cell,
To homogenize the impedance value (step S304) of each resistive random access memory cell.Specifically, each resistor type random access is deposited
The switch element for taking memory cell to be coupled for example including variable impedance unit and with variable impedance unit, can carry during formation
For control voltage to switch element to turn on switch element, with equably in above-mentioned multiple resistive random access memory cells
Variable impedance unit forms conductive filiform.Wherein switch element may be, for example, a transistor, and the grid of transistor is coupled to word
First line, to receive control voltage, drain electrode and the source electrode of transistor are then respectively coupled to variable impedance unit and source electrode line.
In conclusion to provide each resistive random access memory cell one respectively during formation pre- for the embodiment of the present invention
If bias current, to homogenize the impedance value of each resistive random access memory cell, and then the reliability of data access is improved,
Wherein default bias current is to make each resistive random access memory cell in resistive random access storage device can shape
Required minimum current in the case of into low resistance state.
Claims (8)
1. a kind of resistive random access storage device, including：
Multiple resistive random access memory cells；And
Multiple current sources, are respectively coupled between corresponding bit line and corresponding the plurality of resistive random access memory cell,
The plurality of resistive random access memory cell one is provided respectively during one forms and presets bias current, to homogenize each electricity
The impedance value of resistive random access memory born of the same parents,
Wherein the default bias current is the plurality of resistive random access memory cell is respectively formed the minimum needed for low resistance state
Electric current.
2. resistive random access storage device as claimed in claim 1, wherein each resistive random access memory cell
Including：
One variable impedance unit, couples corresponding current source；And
One switch element, couples the variable impedance unit, and a control voltage is controlled by during the formation and is switched on.
3. resistive random access storage device as claimed in claim 2, the wherein switch element are a transistor, the crystal
The grid of pipe is coupled to a word-line, and to receive the control voltage, the drain electrode of the transistor couples the variable impedance unit, the crystalline substance
The source electrode of body pipe is coupled to source line.
4. resistive random access storage device as claimed in claim 2, wherein the plurality of current source during setting with to
The plurality of resistive random access memory cell draws the mode of electric current, which is set as high impedance status.
5. a kind of operating method of resistive random access storage device, which includes multiple electricity
Resistive random access memory born of the same parents, the operating method of the resistive random access storage device include：
According to the one default bias current of processing procedure difference setting of the plurality of resistive random access memory cell, wherein, detection makes this
Multiple resistive random access memory cells are respectively formed the minimum current needed for low resistance state and the minimum current are set as this
Default bias current；And
When during entering one and formed, the default bias current is provided to the plurality of resistive random access memory cell respectively, with
The impedance value of each resistive random access memory cell of homogenization.
6. the operating method of resistive random access storage device as claimed in claim 5, wherein each resistor type random access
Access/memory born of the same parents include a variable impedance unit and a switch element, and the wherein variable impedance unit couples the switch element,
The operating method of the resistive random access storage device further includes：
A control voltage is provided during the formation to the switch element to turn on the switch element.
7. the operating method of resistive random access storage device as claimed in claim 6, the wherein switch element are brilliant for one
Body pipe, the grid of the transistor are coupled to a word-line, and to receive the control voltage, the drain electrode of the transistor couples this can variable resistance
Anti- unit, the source electrode of the transistor are coupled to source line.
8. the operating method of resistive random access storage device as claimed in claim 6, wherein during setting with to this
Multiple resistive random access memory cells draw the mode of electric current, which is set as high impedance status.
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| CN102667947A (en) * | 2010-09-28 | 2012-09-12 | 松下电器产业株式会社 | Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device |
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| US7881096B2 (en) * | 2008-10-08 | 2011-02-01 | Seagate Technology Llc | Asymmetric write current compensation |
| US7855923B2 (en) * | 2008-10-31 | 2010-12-21 | Seagate Technology Llc | Write current compensation using word line boosting circuitry |
| JP2011198445A (en) * | 2010-03-24 | 2011-10-06 | Toshiba Corp | Semiconductor memory |
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| CN102667947A (en) * | 2010-09-28 | 2012-09-12 | 松下电器产业株式会社 | Forming method of performing forming on variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device |
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