TW201603192A - Hybrid wafer dicing approach using an ultra-short pulsed laguerre gauss beam laser scribing process and plasma etch process - Google Patents

Abstract

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The method also involves patterning the mask with an ultra-short pulsed Laguerre Gauss laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The ultra-short pulsed Laguerre Gauss laser beam laser scribing process involves scribing with a laser beam having axially symmetrical polarization. The method also involves plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

Description

Ultra-short pulse Laguerre Gaussian beam laser scribing process and plasma etching process Hybrid wafer cutting method [Cross-reference to related applications]

The present application claims the benefit of U.S. Provisional Application Serial No. 61/994,385, filed on May 16, 2014, the entire disclosure of which is hereby incorporated by reference.

Embodiments of the present invention relate to the field of semiconductor processing and, more particularly, to a method of dicing a semiconductor wafer having a plurality of integrated circuits on each wafer.

In semiconductor wafer processing, an integrated circuit is formed on a wafer (also referred to as a substrate) composed of germanium or other semiconductor material. In general, integrated circuits are formed using layers of various materials, such as semiconductors, conductors or insulators. The materials are doped, deposited, and etched using various well known processes to form an integrated circuit. Each wafer is processed to form a plurality of individual regions containing integrated circuits, referred to as grains.

Follow the integrated circuit forming process to "cut" the wafer to separate individual dies from each other for packaging or in an unpackaged form In a larger circuit. The two main techniques used for wafer cutting are scribing and sawing. In the case of scribing, the diamond insert scribe is moved across the surface of the wafer along a preformed scribe line. The scribe lines extend along the space between the dies. These spaces are often referred to as "streets". The diamond scriber forms shallow scratches in the wafer surface along the scribe lane. After the pressure is applied, such as by the roller, the wafer is separated along the scribe line. The fracture of the wafer follows the lattice structure of the wafer substrate. Scribing can be used for wafers of about 10 mils (thousandths of a mile) or less. For thicker wafers, sawing is currently the preferred method of cutting.

When sawing, a diamond insert saw rotating at a high revolutions per minute contacts the wafer surface and saws the wafer along the scribe. The wafer is mounted on a support member that is an adhesive film such as stretched across a film frame, and the saw is repeatedly applied to both vertical and horizontal scribes. One problem with scribing or sawing is that debris and grooves can be formed along the cut edges of the grains. In addition, cracks can be formed, and the cracks can propagate from the edge of the die into the substrate and cause the integrated circuit to be inoperable. Fragmentation and cracking are particularly problematic for scribing because only one of the square or rectangular grains can be scribed in the <110> direction of the crystalline structure. Therefore, the fracture on the other side of the crystal grain produces a zigzag separation line. Due to chipping and cracking, additional spacing between the dies on the wafer is required to prevent damage to the integrated circuitry, for example, to keep debris and cracks away from the actual integrated circuitry. Due to the spacing requirements, there are not many dies formed on standard sized wafers, and the wafer area available for the circuitry is wasted. Using a saw to emphasize the semiconductor wafer Use area wasted. The thickness of the saw blade is about 15 microns. Therefore, in order to ensure that cracks and other damage around the slit created by the saw do not damage the integrated circuit, it is generally necessary to separate the circuitry of each die by three hundred to five hundred microns. In addition, after dicing, each die requires extensive cleaning to remove particles and other contaminants that result from the sawing process.

Plasma cutting has also been used, but plasma cutting can also have limitations. For example, one limitation that hinders the implementation of plasma cutting can be cost. Standard lithography operations for patterning resists can result in costly implementations. Another limitation that may hinder the implementation of plasma cutting is that plasma processing of such common metals can cause production problems or yield constraints when cutting common metals (e.g., copper) along the scribe.

Embodiments of the invention include methods and apparatus for dicing semiconductor wafers.

In one embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask over the semiconductor wafer, the mask including a layer covering and protecting the integrated circuit. The method also involves patterning the mask with an ultrashort pulse Laguerre laser beam laser scribing process to provide a patterned mask having a gap to expose the semiconductor wafer between the integrated circuits Area. The ultrashort pulse Laguerre Gaussian laser beam laser scribing process involves scribing with a laser beam having axially symmetric polarization. The method also involves plasma etching the semiconductor wafer via a gap in the patterned mask to singulate the integrated circuit.

In another embodiment, a system for cutting a semiconductor wafer having a plurality of integrated circuits includes a factory interface. A laser scribing apparatus is coupled to the factory interface and the laser scribing apparatus includes a laser assembly configured to provide an ultrashort pulse Laguerre laser beam having axially symmetric polarization. The plasma etch chamber is also coupled to the factory interface.

In another embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask over the semiconductor wafer, the mask including a layer covering and protecting the integrated circuit. The method also relates to the use of an ultra-short pulse Laguerre laser beam laser scribing process to pattern the mask and cut the integrated circuit. The ultrashort pulse Laguerre Gaussian laser beam laser scribing process involves scribing with a laser beam having axially symmetric polarization.

100‧‧‧ Flowchart

102‧‧‧ operation

104‧‧‧Operation

106‧‧‧ operation

108‧‧‧ operation

202‧‧‧ mask

204‧‧‧Semiconductor wafer/substrate

206‧‧‧ integrated circuit

207‧‧‧ 划道

208‧‧‧ patterned mask

210‧‧‧ gap

212‧‧‧ trench

Section 302‧‧‧

Section 304‧‧‧

Section 306‧‧‧

Section 308‧‧‧

310‧‧‧Linear or circular polarization

312‧‧‧radial and azimuthal polarization

314‧‧‧ Schematic

316‧‧‧ Schematic

Section 318‧‧‧

320‧‧‧Parts

Section 322‧‧‧

Section 324‧‧‧

Section 326‧‧‧

328‧‧‧ light spots

330‧‧‧Parts

Section 332‧‧‧

Section 334‧‧‧

336‧‧‧ light spots

338‧‧‧Laser beams with different intensity structures

340‧‧‧Laser beam with cylindrically symmetric strength structure

Section 342‧‧‧

Section 344‧‧‧

Section 346‧‧‧

Section 348‧‧‧

350‧‧‧ light spots

Section 402‧‧‧

Section 404‧‧‧

500A‧‧‧through hole

500B‧‧‧through hole

500C‧‧‧through hole

600‧‧ ‧ scribing area

602‧‧‧矽Top part of the substrate

604‧‧‧First bismuth oxide layer

606‧‧‧First etch stop layer

608‧‧‧First low dielectric constant dielectric layer

610‧‧‧second etch stop layer

612‧‧‧Second low dielectric constant dielectric layer

614‧‧‧ Third etch stop layer

616‧‧‧Undoped bismuth oxide glass layer

618‧‧‧Second dioxide layer

620‧‧‧ photoresist layer

622‧‧‧ copper metallized materials

702‧‧‧ mask layer

704‧‧‧Device layer

706‧‧‧矽 substrate

708‧‧‧ die attach film

710‧‧‧With tape

712‧‧‧ Ultrashort pulse Laguerre Gauss laser beam laser marking process

714‧‧‧ trench

716‧‧‧Deep deep plasma etching process

800‧‧‧Processing tools

802‧‧‧Factory interface

804‧‧‧Load lock

806‧‧‧Cluster Tools

808‧‧‧plasma etching chamber

810‧‧‧Laser marking equipment

812‧‧‧Deposition room

814‧‧ Wetting/drying station

900‧‧‧Computer system

902‧‧‧ processor

904‧‧‧ main memory

906‧‧‧ Static memory

908‧‧‧Network interface device

910‧‧ ‧Video display unit

912‧‧‧Text input device

914‧‧‧ cursor control device

916‧‧‧Signal generating device

918‧‧‧secondary memory

920‧‧‧Network

922‧‧‧Software

926‧‧‧ Processing logic

930‧‧ ‧ busbar

932‧‧‧ Machine accessible storage media

1 is a flow chart showing the operation in a method of dicing a semiconductor wafer including a plurality of integrated circuits in accordance with an embodiment of the present invention.

2A illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during a method of performing a dicing of a semiconductor wafer, the view corresponding to operation 102 of the flowchart of FIG. 1 in accordance with an embodiment of the present invention. .

2B illustrates a plurality of integrated bodies during a method of performing a dicing of a semiconductor wafer in accordance with an embodiment of the present invention. A cross-sectional view of a semiconductor wafer of circuitry corresponding to operation 104 of the flowchart of FIG.

2C illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during a method of performing a dicing of a semiconductor wafer, the view corresponding to operation 108 of the flowchart of FIG. 1 in accordance with an embodiment of the present invention. .

Fig. 3A illustrates the plane of the electrical component as a plane of polarization.

Figure 3B illustrates the concept of P-polarization and S-polarization of a laser beam.

Figure 3C illustrates different types of polarization of conventional and vector laser beams as indicated by the arrows in accordance with an embodiment of the present invention.

Figure 3D schematically illustrates the polarization effect on the laser energy coupled into the material in accordance with an embodiment of the present invention.

Figure 3E illustrates the direction of polarization versus the direction of the laser scribing in accordance with an embodiment of the present invention.

Figure 3F illustrates the effect of polarization direction versus laser scribe direction in accordance with an embodiment of the present invention.

Figure 3G illustrates a laser beam having a simple intensity structure and a conventional polarization.

Figure 3H illustrates a laser beam having a complex intensity structure and polarization in accordance with an embodiment of the present invention.

Fig. 3I illustrates an example of a laser beam having different intensity structures and an example of a laser beam having a cylindrically symmetric intensity structure according to an embodiment of the present invention.

Figure 3J illustrates a laser beam having both complex polarization and complex intensity structures in accordance with an embodiment of the present invention.

Figure 4 illustrates the formation of a TEM01* laser beam having radial and/or azimuthal polarization in accordance with an embodiment of the present invention.

Figure 5 illustrates the effect of using a femtosecond range, a picosecond range, and a laser pulse width in the nanosecond range, in accordance with an embodiment of the present invention.

Figure 6 illustrates a cross-sectional view of a stack of materials that may be used in a scribe region of a semiconductor wafer or substrate in accordance with an embodiment of the present invention.

7A through 7D illustrate cross-sectional views of various operations in a method of dicing a semiconductor wafer in accordance with an embodiment of the present invention.

Figure 8 illustrates a block diagram of a tool arrangement for laser and plasma dicing wafers or substrates in accordance with an embodiment of the present invention.

Figure 9 illustrates a block diagram of an exemplary computer system in accordance with an embodiment of the present invention.

The present invention describes a method of dicing a semiconductor wafer having a plurality of integrated circuits on each wafer. Numerous specific details are set forth in the description below, such as the ultrashort pulse Laguerre Gaussian laser scribing method And plasma etching conditions and material ranges to provide a thorough understanding of embodiments of the invention. It will be apparent to those skilled in the art that the embodiments of the invention may be practiced without the specific details. In other instances, well-known aspects such as the fabrication of integrated circuits have not been described in detail so as not to unnecessarily obscure the embodiments of the invention. In addition, the various embodiments shown in the drawings are intended to be illustrative and not necessarily to scale.

A hybrid wafer or substrate dicing process involving initial laser scribe and subsequent plasma etch can be performed for die singulation. A laser scribing process can be used to cleanly remove the mask layer, the organic and inorganic dielectric layers, and the device layer. The laser etch process can then be terminated after the wafer or substrate has been exposed or partially etched. Subsequently, a plasma etched portion of the dicing process can be employed to etch a block through the wafer or substrate, such as through a bulk single crystal germanium, to produce a singulation or dicing of the die or wafer. More specifically, one or more embodiments are directed to implementing an ultrashort pulsed Laguerre laser beam laser scribing process for, for example, a cutting application. In a particular such embodiment, the laser beam has an axially symmetric polarization.

In order to provide context, femtosecond laser scribing and subsequent plasma etching for wafer dicing have proven to be feasible for wafer singulation. Depending on the particular application, the laser scribing depth may be limited to the mask opening and device layer removal until the underlying germanium (Si) substrate is exposed, or may extend into the Si substrate. At the very end of the spectrum, laser scribing is performed substantially across the entire wafer thickness, and plasma etching is used to repair the cut single crystal Granular sidewalls. The cover mask layer may be thick or thin depending on the bump height and the wafer thickness. In the general scope, the following two aspects may need to be improved: (1) the surface roughness of the trench sidewalls generated by the laser scribing may be required to be reduced; (2) the laser material removal rate may need to be increased, In order to use a given laser power to improve laser process throughput.

Conventionally, a circularly polarized Gaussian mode TEM00 laser beam is implemented to perform laser scribing or cutting in laser micromachining to avoid a trench associated with the linearly polarized laser beam when the direction of the laser scribing changes. The groove width changes. However, the use of circularly polarized beams may be achieved at the expense of reducing the laser absorption coefficient, which may affect process throughput. In addition, although relatively low sidewall roughness of the laser scribe trenches may be achieved with the application of appropriate laser spot overlap, for example by reducing the scribe speed or increasing the laser pulse frequency, it may be at a lower scribe speed or More expensive lasers always come at a cost to achieve this relatively low sidewall roughness. Since the minimum laser pulse energy must still be achieved at higher pulse frequencies, this can result in increased costs. Moreover, the sidewall surface roughness of the laser scribing trench can be improved to reduce the cost of the plasma etching-based post-cut sidewall flattening process.

In accordance with one or more embodiments described herein, an ultrashort pulse Laguerre laser beam (such as a TEM01* mode with axially symmetric polarization) is implemented for laser scribing. Subsequent plasma etching operations can then be performed for wafer dicing. In one embodiment, the axially symmetric polarization comprises one of radial polarization and azimuthal polarization. Or both. An axially polarized laser beam with a TEM01* mode provides up to twice the high laser absorption coefficient compared to that provided by a circularly polarized Gaussian beam (eg, TEM00 mode). Furthermore, the sidewall surface roughness on the trench created by the axially polarized laser beam can be lower than that achieved by a circularly polarized laser beam. Both the axially polarized laser beam and the azimuthal polarized laser beam provide a deeper penetration depth, and the azimuthal polarized beam can produce a sidewall with a steeper taper. In one embodiment, an annular ring shaped laser beam (eg, TEM01* mode) having an axially symmetric polarization mode (eg, radial or azimuthal polarization or both) may be an initial linearly polarized Gaussian beam (TEM00 mode) Converted. In one or more embodiments described herein, a laser beam having axially symmetric polarization is implemented to improve the smoothness of the laser opening trench, which can be converted to a smoother plasma etch. Groove profile. In one or more embodiments described herein, higher energy coupling efficiencies associated with axial polarization improve laser scribing yield and/or energizing thick mask openings, thick device layer removal, or wider slits Forming, any of the above may have been difficult to accomplish under a circularly polarized beam of the same laser power level.

Thus, in one aspect of the invention, the semiconductor wafer can be diced into a singulated-integral circuit using a combination of an ultrashort pulse Laguerre laser beam laser scribe process and a plasma etch process. 1 is a flow chart showing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits in accordance with an embodiment of the present invention. 100. 2A through 2C illustrate cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during a method of performing a dicing of a semiconductor wafer, the views corresponding to the flowchart 100, in accordance with an embodiment of the present invention. operating.

Referring to operation 102 of flowchart 100 and corresponding FIG. 2A, a mask 202 is formed over the semiconductor wafer or substrate 204. The mask 202 is composed of a layer formed on the surface of the semiconductor wafer 204 that covers and protects the integrated circuit 206. The mask 202 also covers the interventional tract 207 formed between each of the integrated circuits 206.

In accordance with an embodiment of the invention, forming the mask 202 involves forming a layer such as, but not limited to, a photoresist layer or an I-line patterned layer. For example, a polymer layer such as a photoresist layer can be composed of materials that are otherwise suitable for use in lithography processes. In one embodiment, the photoresist layer is comprised of a forward photoresist material such as, but not limited to, 248 nanometer (nm) resist, 193 nm resist, 157 nm resist, ultra-ultraviolet ( Extreme ultra-violet; EUV) resist or a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another embodiment, the photoresist layer is comprised of a negative photoresist material such as, but not limited to, polycis isoprene and polyvinyl cinnamate.

In another embodiment, forming the mask 202 involves forming a layer deposited in a plasma deposition process. For example, in one such embodiment, the mask 202 ₍₂ polymerizable CF) layer is deposited by a plasma Teflon polytetrafluoroethylene or the like. In a particular embodiment, it relates to a gas in a plasma deposition process C ₄ F ₈ in CF ₂ layer deposition polymerization.

In another embodiment, forming the mask 202 involves forming a water soluble mask layer. In one embodiment, the water soluble mask layer is readily soluble in an aqueous medium. For example, in one embodiment, the water soluble mask layer is comprised of a material that is soluble in one or more of an alkaline solution, an acidic solution, or deionized water. In one embodiment, the water soluble mask layer maintains the water solubility of the mask layer after exposure to a heating process, such as heating in the range of about 50-160 degrees Celsius. For example, in one embodiment, the water soluble mask layer is soluble in the aqueous solution after exposure to the chamber conditions used in the laser and plasma etch dicing process. In one embodiment, the water soluble mask layer is comprised of a material such as, but not limited to, polyvinyl alcohol, polyacrylic acid, dextran, polymethacrylic acid, polyethyleneimine, or polyethylene oxide. In a particular embodiment, the water soluble mask layer has an etch rate in the aqueous solution of about 1-15 microns per minute, and more specifically an etch rate of about 1.3 microns per minute.

In another embodiment, forming the mask 202 involves forming an ultraviolet curable mask layer. In one embodiment, the mask layer has a susceptibility to ultraviolet light that reduces the adhesion of the ultraviolet curable layer by at least about 80%. In one such embodiment, the ultraviolet layer is comprised of a polyvinyl chloride or acrylic based material. In one embodiment, the ultraviolet curable layer is comprised of a stack of materials or materials having adhesive properties that are attenuated upon exposure to ultraviolet light. In a real In the examples, the UV curable adhesive film is sensitive to about 365 nm ultraviolet light. In one such embodiment, this sensitivity enables the use of LED light to perform curing.

In one embodiment, the semiconductor wafer or substrate 204 is comprised of a material that is suitable for undergoing a fabrication process, and a semiconductor processing layer can be suitably disposed over the material. For example, in one embodiment, the semiconductor wafer or substrate 204 is comprised of a Group IV based material such as, but not limited to, crystalline germanium, ruthenium or iridium/ruthenium. In a particular embodiment, providing semiconductor wafer 204 includes providing a single crystal germanium substrate. In a particular embodiment, the single crystal germanium substrate is doped with impurity atoms. In another embodiment, the semiconductor wafer or substrate 204 is comprised of a III-V material such as, for example, a III-V material substrate used in the fabrication of light emitting diodes (LEDs).

In one embodiment, an array of semiconductor devices as part of integrated circuit 206 is disposed on or in semiconductor wafer or substrate 204. Examples of such semiconductor devices include, but are not limited to, memory devices or complementary metal-oxide-semiconductor (CMOS) transistors fabricated in a germanium substrate and encapsulated in a dielectric layer. A plurality of metal interconnects can be formed over the devices or transistors and in surrounding dielectric layers and can be used to electrically couple the devices or transistors to form integrated circuits 206. The materials comprising the scribe lines 207 may be similar or identical to the materials used to form the integrated circuit 206. Lift For example, the scribe line 207 can be composed of a dielectric material layer, a semiconductor material layer, and a metallized material. In one embodiment, one or more of the lanes 207 include a test device similar to the actual device of the integrated circuit 206.

Referring to operation 104 of flowchart 100 and corresponding FIG. 2B, the ultra-short pulse LaGail's laser beam laser scribing process patterning mask 202 is utilized to provide a patterned mask 208 having a gap 210 for exposure. A region of the semiconductor wafer or substrate 204 that is between the integrated circuits 206. Therefore, the material of the scribe line 207 originally formed between the integrated circuits 206 is removed using a laser scribing process. In accordance with an embodiment of the present invention, the ultra-short pulsed Laguerre laser beam laser scribing process patterning mask 202 includes a portion of the semiconductor wafer 204 that is partially formed on the semiconductor wafer 204. In the area between, as depicted in Figure 2B.

In accordance with an embodiment of the present invention, an ultrashort pulse Laguerre laser beam laser scribing process involves scribing with a laser beam having axially symmetric polarization. In one embodiment, the laser beam has a radial polarization element. In another embodiment, the laser beam has an azimuthal polarization element. In another embodiment, the laser beam has both a radial polarization element and an azimuthal polarization element. In another embodiment, the laser beam has a TEM01* mode. In another embodiment, the laser beam has an annular ring shape.

In order to provide further context, the polarization of the laser radiation is the fundamental optical property inherent in all laser beams. Laser light system A transverse electromagnetic wave containing both electrical and magnetic components, and the electric field and magnetic field vector are directed perpendicular to the direction of travel of the wave. The polarization direction of the electromagnetic wave has been conventionally defined to oscillate along the direction of the electric field vector. When light strikes an optical surface (such as a beam splitter) at a non-perpendicular angle, the reflection and transmission characteristics depend on the polarization. Light having a polarization vector in a plane containing incident and reflected beams is referred to as P-polarized, and light perpendicular to the plane containing the incident and reflected beams is referred to as S-polarized. Any arbitrary state of the incident polarization can be expressed as a vector sum of the S and P components.

Fig. 3A illustrates the plane of the electrical component as a plane of polarization. Referring to portion 302 of Figure 3A, the orientation of the electric and magnetic field vectors relative to the direction of travel of the beam is illustrated. Referring to portion 304 of Figure 3A, the linearly polarized light propagating in the z-direction (or k-direction) and the electric field amplitude Y and the magnetic field amplitude X are illustrated. Referring to portion 306 of Figure 3A, the direction of propagation and the plane of polarization and the magnetic field and electric field vector are illustrated. Figure 3B illustrates the concept of P-polarization and S-polarization of a laser beam. Referring to Figure 3B, portion 308 illustrates the S-polarization and P-polarization of the reflected and transmitted beams from the beam splitter relative to the direction of propagation of the laser beam.

It should be understood that there are different types of polarization. Conventional polarization states include linear polarization and circular polarization. In both cases, the direction of the electrical vector does not depend on the spatial position in the beam section. Linearly polarized lasers have a fixed electrical vector that extends in a fixed direction. A laser with circular polarization causes its own electrical vector to rotate uniformly in a circular pattern. Non-conventional polarization states include radial polarization in which the direction of the electrical vector in the plane of the beam section is parallel to the radial direction. Non-known polarization The state also includes azimuthal polarization, wherein the direction of the electrical vector in the plane of the beam section is perpendicular to the radial direction. Within a laser beam, an electrical vector (rather than a magnetic vector) contains processing power. Thus, the electrical vector orientation (ie, polarization state/direction) affects the laser material interaction and thus the material handling capabilities. In particular, in accordance with an embodiment of the present invention, the polarization direction can have a significant impact on the quality and yield/efficiency of the laser scribing/cutting process.

Figure 3C illustrates different types of polarization of conventional and vector laser beams as indicated by the arrows in accordance with an embodiment of the present invention. Referring to Figure 3C, for conventional polarization states, such as linear or circular polarization 310, the direction of the electrical vector does not depend on the spatial position in the beam section. In a vector beam, the polarization state is a spatial variant such as radial and azimuthal polarization 312.

Figure 3D schematically illustrates the polarization effect on the laser energy coupled into the material in accordance with an embodiment of the present invention. Referring to Figure 3D, diagram 314 shows that the total energy (expressed as 1 or 100%) of the incident laser radiation can be divided into transmittance (T), reflectance (R), and absorption (A), where A+ R+T=1, or A=1-RT. The energy coupling efficiency represented by A is affected by R and T. One known effect of polarization on laser radiation is that polarization can affect the reflectivity of a laser beam on the surface of a material.

In accordance with an embodiment of the present invention, the polarization effect of the laser energy coupled into the material can be attributed to the observation that the polarization direction affects coupling to a given by affecting the laser reflectivity on the surface of the material. The laser energy in the material. For example, Figure 3E illustrates a polarization direction versus a laser scribe line direction in accordance with an embodiment of the present invention. Referring to FIG. 3E, schematic 316 illustrates that the polarization direction can be varied, and thus the quality and yield/efficiency of the laser scribing/cutting process can be affected depending on the relationship between the polarization direction and the cutting/scoping (laser motion) direction. . The correlation samples and laser beam positions in the coordinate system used are depicted in Figure 3E.

Figure 3F illustrates the effect of polarization direction versus laser scribe direction in accordance with an embodiment of the present invention. Referring to section 318 of Figure 3F, in the case of linear polarization, the parameters of the beam interacting with matter depend on the direction of polarization. Referring to portion 320 of Figure 3F, a change in the width of the slit can occur when the direction of the laser scribing is changed. The reason for this change may be that the laser power absorbed is different when the polarization is linear and perpendicular to the direction of travel of the laser beam.

More generally, in accordance with an embodiment of the present invention, in the case of linear polarization, the parameters of the beam interacting with matter depend on the direction of polarization. In addition, a change in the depth of the scribe line may occur when the direction of the laser scribe line is changed because the absorbed laser power is different when the polarization is linear and perpendicular to the direction of travel of the laser beam. In some cases, energy efficiency is defined as the product of the depth of cut multiplied by the cutting speed. In the case of a circular or randomly polarized beam, the electrical vector changes rapidly over time. That is, the electric vector is uniformly oriented in all cutting directions such that the effect of polarization on the cutting quality is time averaged and it can be seen that there is no effect on the slit width or depth of cut. However, according to an embodiment of the present invention, the efficiency of coupling from laser energy or the relationship between cutting and associated cutting yield From a point of view, circular polarization is not optimal for minimum loss or maximum absorption.

Figure 3G illustrates a laser beam having a simple intensity structure and a conventional polarization. Referring to Figure 3G, section 322 illustrates the circular and linear polarization modes for a conventional Gaussian beam. Portion 324 illustrates the Gaussian intensity structure of the TEM00 beam. Portion 326 is a power plot that varies with beam profile function and has a corresponding spot 328.

Figure 3H illustrates a laser beam having a complex intensity structure and polarization in accordance with an embodiment of the present invention. Referring to Figure 3H, section 330 illustrates a linearly polarized Laguerre Gaussian beam polarization mode that is plotted as a function of time. Portion 332 illustrates the annular ring shape strength structure of the TEM01* beam. Portion 334 is a power plot that varies with beam profile function and has a corresponding spot 336. To provide a context, FIG. 3I illustrates an example of a laser beam (338) having different intensity structures and a laser beam (340) having a cylindrically symmetric intensity structure in accordance with an embodiment of the present invention.

Figure 3J illustrates a laser beam having both complex polarization and complex intensity structures in accordance with an embodiment of the present invention. Referring to portion 342 of Figure 3J, (a) illustrates a radially polarized beam, and (b) illustrates an azimuthally polarized beam. Portion 344 is illustrated as a radially polarized Laguerre Gaussian beam polarization mode as a function of time. Portion 346 illustrates an annular ring shape strength structure. Portion 348 is a power plot that varies with beam profile function and has a corresponding spot 350. In one implementation In the example, the combination of non-conventional polarization and unique intensity profile provides improved efficiency and precision in laser ablation.

In an embodiment, laser ablation is then performed using a laser beam having both complex polarization and complex intensity structures. In one embodiment, a radially polarized beam is used. For comparison, a radially polarized beam contrasts with a circularly polarized beam, and the effective absorption coefficient in the case of radial polarization is twice the effective absorption coefficient of circular polarization. Thus, for a radially polarized beam, the product of the depth of cut multiplied by the cutting speed is about 1.5-2.0 times higher than the product of the circularly polarized beam. In one embodiment, improved scribing/cutting quality is achieved with respect to the roughness of laser machining. In a particular embodiment, the radially polarized beam produces a smoother sidewall than the circularly polarized beam. In a particular example, the radially polarized beam TEM01* exhibits approximately twice the absorption of the laser compared to the circularly polarized Gaussian beam TEM00, and the lower sidewall passing through the cut thickness (eg, the upper and lower portions) Surface roughness (Rz).

Figure 4 illustrates the formation of a TEM01* laser beam having radial and/or azimuthal polarization in accordance with an embodiment of the present invention. Referring to Figure 4, portion 402 illustrates path (a) in which radial polarization is achieved to provide TME01*. Portion 404 illustrates path (b) in which azimuthal polarization is achieved to provide TME01*. In one embodiment, the polarization is formed as an overlap of two plane polarization modes TEM01. In an embodiment, such linear to radial/azimuth polarization conversion (radial/azimuthal polarization) Conversion; LRAC) is based on segmented half-wave plates. When comparing the radially polarized beam TEM01* with the azimuthal polarized beam TEM01*, the azimuthal polarized beam can achieve twice the depth of penetration compared to the radially polarized beam with respect to the cutting efficiency. The azimuthal polarized beam produces a narrower cut with a larger taper than the radially polarized beam relative to the slit profile.

In one embodiment, a femtosecond-based laser is used as a source of ultrashort pulse Laguerre's laser beam laser scribing process. For example, in one embodiment, a laser with a wavelength in the visible spectrum plus ultraviolet (infra-red; IR) and infrared (infra-red; IR) ranges (collectively referred to as a broadband spectrum) is used to provide femtosecond-based femtoseconds. The laser, that is, a laser with a pulse width on the order of femtoseconds (10 ^-15 seconds). In one embodiment, the ablation is not or substantially independent of wavelength, and thus, the ablation is suitable for complex films such as a film of mask 202, a film of scribe 207, and, where possible, a semiconductor crystal. A film of a portion of a circle or substrate 204.

Figure 5 illustrates the effect of using a femtosecond range, a picosecond range, and a laser pulse width in the nanosecond range, in accordance with an embodiment of the present invention. Referring to Fig. 5, the thermal damage problem is achieved by using a laser beam profile having a contribution from the femtosecond range compared to using a longer pulse width (e.g., through hole 500A yielding significant damage 502A after nanosecond processing). It can be slowed or eliminated (for example, the damage of the through hole 500C after femtosecond treatment is minimized to no damage 502C). Through hole During the formation of 500C, the elimination or slowing of damage can be attributed to the lack of low-energy back-coupling (as seen in picosecond-based laser ablation of 500B/502B) or thermal equilibrium (as seen in nanosecond-based laser ablation), such as section 5. It is depicted in the figure.

Laser parameter selection such as beam profile may be critical to the development of successful laser scribing and cutting processes that minimize fragmentation, microcracking and delamination for clean laser scribing . The cleaner the laser markings, the smoother the etching process that can be performed when the final die is singulated. In a semiconductor device wafer, a plurality of functional layers of different material types (eg, conductors, insulators, semiconductors) and thicknesses are typically placed on the wafer. Such materials may include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as cerium oxide and tantalum nitride.

The scribes between the individual integrated circuits disposed on the wafer or substrate may include layers similar or identical to the integrated circuits themselves. For example, Figure 6 illustrates a cross-sectional view of a stack of materials that can be used in a scribe region of a semiconductor wafer or substrate in accordance with an embodiment of the present invention.

Referring to FIG. 6, the scribe region 600 includes a top portion 602 of the germanium substrate, a first ruthenium dioxide layer 604, a first etch stop layer 606, and a first low-k dielectric layer 608 (eg, having a dielectric constant) The dielectric constant is lower than the dielectric constant of the germanium dioxide 4.0), the second etch stop layer 610, the second low-k dielectric layer 612, the third etch stop layer 614, and the undoped bismuth oxide glass. An undoped silica glass (USG) layer 616, a second hafnium oxide layer 618, and a photoresist layer 620 are depicted in relative thicknesses. A copper metallization material 622 is disposed between the first etch stop layer 606 and the third etch stop layer 614 and through the second etch stop layer 610. In a particular embodiment, the first etch stop layer 606, the second etch stop layer 610, and the third etch stop layer 614 are composed of tantalum nitride, and the low-k dielectric layers 608 and 612 are doped with carbon.矽 material composition.

Under conventional laser illumination (such as nanosecond-based illumination), the material of the scribe 600 varies greatly in optical absorption and erosion mechanisms. For example, a dielectric layer such as hafnium oxide is substantially transparent under normal conditions for all commercially available laser wavelengths. In contrast, metals, organics (eg, low dielectric constant materials), and germanium can couple photons very easily, especially in response to nanosecond-based illumination. In one embodiment, an ultrashort pulse Laguerre laser beam laser scribing process is used to pattern the ceria layer by ablation of the hafnium oxide layer followed by ablation of the low dielectric constant material layer and the copper layer. , low dielectric constant material layer and copper layer.

The scribing process can be performed in a single pass or in multiple passes, but in one embodiment, it is preferred to perform 1 to 2 passes. In one embodiment, the scribe depth in the workpiece is in the range of from about 5 microns to about 50 microns deep, preferably from about 10 microns to about 20 microns deep. In one embodiment, the resulting laser beam kerf width is in the range of approximately 2 microns to 15 microns, but is scribed on the wafer The preferred slit width in the cut is approximately in the range of 6 microns to 10 microns, and the width of the slits is measured at the device/tank interface.

Laser parameters with benefits and advantages can be selected, such as providing a sufficiently high laser intensity to effect the dissociation of the inorganic dielectric (eg, cerium oxide) and the damage caused by the underlying damage prior to direct ablation of the inorganic dielectric Layers and fragmentation are minimized. In addition, parameters can be selected to provide meaningful industrial application process throughput with precise control of the ablation width (eg, slit width) and depth. In one embodiment, an ultrashort pulse Laguerre's laser beam laser scribing process is suitable to provide these advantages.

It should be understood that in the case of patterning a mask using a laser scribing line and scribing through the wafer or substrate completely to cut a single crystal grain, the cutting or singulation may be stopped after the laser scribing described above. Process. Therefore, no further singulation processing will be required in this case. However, in the case where the laser scribing is not performed for the overall singulation, the following embodiments can be considered.

Referring now to optional operation 106 of flowchart 100, an intermediate mask opening post-cleaning operation is performed. In one embodiment, the cleaning operation of the mask opening is based on a plasma cleaning process. In the first example, the plasma-based cleaning process is reactive to the area of the substrate 204 exposed by the gap 210, as described below. In the case of a reactive plasma based cleaning process, the cleaning process itself may form or extend the trenches 212 in the substrate 204 because the reactive plasma based cleaning operation at least to some extent is an etchant for the substrate 204. In the first In two different examples, as described below, the plasma based cleaning process is non-reactive with respect to the area of substrate 204 that is exposed by gap 210.

According to a first embodiment, the plasma based cleaning process is reactive to the exposed areas of the substrate 204 because the exposed areas are partially etched during the cleaning process. In one such embodiment, Ar or another non-reactive gas (or mixture) is used in combination with SF ₆ for high bias plasma processing to clean the cut openings. Using a mixed gas of Ar + SF ₆ plasma processing performed under a high bias power, in order to mask the opening area is achieved bombardment cleaning opening area mask. In the reaction of the penetration process, the physical bombardment from Ar and SF ₆ and SF ₆ due to etch both the chemical and the F ions are masked help clean the opening region. The method can be adapted to photoresist or plasma deposited polytetrafluoroethylene mask 202, wherein the penetration treatment results in a fairly uniform mask thickness reduction and a mild Si etch. However, such through etching processes may not be most suitable for water soluble mask materials.

According to a second embodiment, the plasma based cleaning process is non-reactive with respect to the exposed areas of the substrate 204 because the exposed areas are not etched or negligibly etched during the cleaning process. In one such embodiment, only non-reactive gas plasma cleaning is used. For example, high bias plasma processing is performed using Ar or another non-reactive gas (or mixture), both for mask condensation and cleaning of the cut openings. The method can be adapted to a water soluble mask or a thinner plasma deposited polytetrafluoroethylene 202. In another such embodiment, separate mask coagulation and diced trench cleaning operations are used, for example, Ar or non-reactive gas (or mixture) high bias plasma treatment is performed first to mask condensation, and then Perform Ar+SF ₆ plasma cleaning of the laser that has been cut into the groove. This embodiment may be suitable for the case where Ar cleaning is insufficient for trench cleaning because the mask material is too thick. Improved cleaning efficiency for thinner masks, but the mask etch rate is much lower and there is almost no consumption in subsequent deep etch processes. In yet another such embodiment, three operational cleanings are performed: (a) Ar or a non-reactive gas (or mixture) high bias plasma treatment to mask condensation, and (b) the laser has been scribed. Ar+SF ₆ high bias plasma cleaning, and (c) Ar or non-reactive gas (or mixture) high bias plasma treatment to mask condensation. In accordance with another embodiment of the present invention, the plasma cleaning operation involves first using a reactive plasma cleaning process, such as the cleaning process described above in the first aspect of operation 106. The reactive plasma cleaning process is then followed by a non-reactive plasma cleaning process, such as the cleaning process described in association with the second aspect of operation 106.

Referring to operation 108 of flowchart 100, and corresponding FIG. 2C, semiconductor wafer 204 is etched via gap 210 in patterned mask 208 to singulate integrated circuit 206. In accordance with an embodiment of the present invention, etching the semiconductor wafer 204 includes: etching the trench 212 initially formed by an ultrashort pulse Raggahl's laser beam laser scribing process, and finally etching completely through the semiconductor wafer 204, As depicted in Figure 2C.

According to an embodiment of the present invention, the roughness of the mask opening obtained from the laser scribing may affect the quality of the sidewall of the die due to subsequent formation of the plasma etched trench. The lithographic opening masks often have a smooth profile, resulting in a corresponding sidewall of the plasma etched trench that is smooth. In contrast, if an inappropriate laser process parameter is selected, the conventional laser opening mask can have a very rough profile along the scribe line direction (such as dot overlap, resulting in plasma etching the trench in the horizontal direction of the sidewall Rough). Although surface roughness can be smoothed by an additional plasma process, there are cost and yield blows in remedying such problems. Thus, the embodiments described herein may be advantageous in providing a smoother scribing process for the laser scribing portion of the self-cutting process.

In an embodiment, etching the semiconductor wafer 204 includes using a plasma etch process. In one embodiment, a through-via via etch process is used. For example, in a particular embodiment, the etch rate of the material of semiconductor wafer 204 is greater than 25 microns/minute. Ultra-high density plasma sources can be used in the plasma etched portion of the die singulation process. Examples of suitable execution chamber of the plasma etching process such as the process of the system of Applied Centura ^® Silvia ^TM etching system available from Sunnyvale, California, United States Applied Materials. The Applied Centura ^® Silvia ^TM etch system combines capacitive and inductive RF coupling to provide ion density and ion energy control that is more independent than using only capacitive coupling, even with the improvements provided by magnetic enhancement. This combination energizes the effective decoupling of ion density from ion energy to achieve a relatively high density plasma that does not have potentially damaging high DC bias levels even at very low pressures. This feature causes the process window to be extra wide. However, any plasma etch chamber capable of etching ruthenium can be used. In an exemplary embodiment, a deep germanium etch is used to etch a single crystal germanium substrate or wafer 204 using an etch rate that is about 40% faster than conventional etch rates while maintaining substantially accurate contour control and virtually fan-free sidewalls. . In a particular embodiment, a through-via via etch process is used. The etching process is based on a plasma generated by a reactive gas, typically a fluorine-based gas, such as SF ₆ , C ₄ F ₈ , CHF ₃ , XeF ₂ , or any other that can be etched at a relatively faster etch rate. The reactant reactant gas. In one embodiment, the mask layer 208 is removed after the singulation process, as depicted in Figure 2C. In another embodiment, the plasma etch operation described in association with FIG. 2C is etched through substrate 204 using a conventional Bosch type deposition/etch/deposition process. In general, Bosch-type processes consist of three sub-operations: deposition, directed bombardment etching, and isotropic chemical etching, which are performed many iterations (cycles) until etching passes through the crucible.

Therefore, referring again to flowchart 100 and FIGS. 2A-2C, initial ablation can be performed by using an ultrashort pulse Laguerre laser beam laser scribing process to ablate through the mask layer and through the wafer. Wafer cutting is performed by scribe (including metallized material) and partially into the ruthenium substrate. The die singulation can then be completed by subsequent deep plasma etching. According to an embodiment of the present invention, the following will be with the 7A Figures to 7D relate to a specific example of a stack of materials for cutting.

Referring to FIG. 7A, the material stack for hybrid laser ablation and plasma etch cutting includes a mask layer 702, a device layer 704, and a substrate 706. A mask layer, a device layer, and a substrate are disposed on the die attach film 708 adhered to the tape 710. In an embodiment, the mask layer 702 is a water soluble layer, such as the water soluble layer described above in association with the mask 202. Device layer 704 includes an inorganic dielectric layer (such as two) disposed on one or more metal layers (such as a copper layer) and one or more low-k dielectric layers (such as a carbon-doped oxide layer) Osmium oxide). The device layer 704 also includes scribes arranged between the integrated circuits, the scribes including the same or similar layers as the integrated circuits. The substrate 706 is a bulk single crystal germanium substrate.

In one embodiment, the tantalum substrate is thinned from the back side before the bulk single crystal germanium substrate 706 is adhered to the die attach film 708. This thinning operation can be performed by a back side grinding process. In one embodiment, the bulk single crystal germanium substrate 706 is thinned to a thickness in the range of approximately 50-100 microns. It should be noted that in one embodiment, it is important to perform this thinning operation prior to the laser ablation and plasma etch cutting processes. In one embodiment, the photoresist layer 702 has a thickness of about 5 microns and the device layer 704 has a thickness in the range of about 2-3 microns. In one embodiment, the die attach film 708 (or any suitable alternative capable of bonding a thinned or thin wafer or substrate to the backing tape 710) has a thickness of about 20 microns.

Referring to FIG. 7B, a portion of mask 702, device layer 704, and substrate 706 is patterned with ultrashort pulsed LaGalger laser beam laser scribing process 712 to form trenches 714 in substrate 706. Referring to FIG. 7C, trench 714 is extended down to die attach film 708 using a deep plasma etch process 716 to expose the top portion of die attach film 708 and singulate substrate 706. Device layer 704 is protected by mask layer 702 during the deep plasma etch process 716.

Referring to FIG. 7D, the dicing process can further include patterning the die attach film 708 to expose the top portion of the liner 710 and dicing the single die attach film 708. In one embodiment, the single die attach film is diced by a laser process or by an etch process. Further embodiments may include subsequently removing the singulated portion of the substrate 706 from the backing strip 710 (eg, as an individual integrated circuit). In one embodiment, the diced die attach film 708 remains on the back side of the singulated portion of the substrate 706. Other embodiments may include removing the mask layer 702 from the device layer 704. In an alternate embodiment, where the thickness of the substrate 706 is less than about 50 microns, the ultra-short pulse Laguergain laser beam laser scribing process 712 is used to completely sing the single substrate 706 without the need for an additional plasma process.

A single process tool can be configured to perform many or all of the hybrid laser series using ultrashort pulse Laguerre laser beam ablation and plasma etch singulation processes. For example, Figure 8 illustrates a block diagram of a tool arrangement for laser and plasma dicing wafers or substrates in accordance with an embodiment of the present invention.

Referring to FIG. 8, the process tool 800 includes a factory interface (FI) coupled to a plurality of load locks 804. Cluster tool 806 is coupled to factory interface 802. Cluster tool 806 includes one or more plasma etch chambers, such as plasma etch chamber 808. Laser scribing device 810 is also coupled to factory interface 802. In one embodiment, the total footprint of the process tool 800 can be about 3500 millimeters (3.5 meters) by about 3800 millimeters (3.8 meters), as depicted in FIG.

In an embodiment, the laser scribing device 810 houses a laser assembly that is configured to provide an ultrashort pulse Laguerre laser beam. In one such embodiment, the laser beam has an axially symmetric polarization. In a particular embodiment, the laser assembly is configured to provide a laser beam having a radial polarization element. In another particular embodiment, the laser assembly is configured to provide a laser beam having an azimuthal polarization component. In another particular embodiment, the laser assembly is configured to provide a laser beam having both a radial polarization component and an azimuthal polarization component. In another particular embodiment, the laser assembly is configured to provide a laser beam having a TEM01* mode. In another particular embodiment, the laser assembly is configured to provide a laser beam having an annular ring shape. In an embodiment, the laser scribing apparatus is configured to provide linear to radial conversion, or linear to azimuthal conversion, or linear to both radial and azimuth conversion based on the segmented half wave plate.

In one embodiment, the laser is adapted to perform a laser ablation portion in a hybrid laser and etch singulation process, such as the laser ablation process described above. In one embodiment, the laser scribing apparatus 810 also includes a movable platform configured to move the wafer or substrate (or the carrier of the wafer or substrate) relative to the laser. In a particular embodiment, the laser is also movable. In one embodiment, the total footprint of the laser scribing device 810 can be about 2240 millimeters by about 1270 millimeters, as depicted in FIG.

In an embodiment, one or more plasma etch chambers 808 are configured to etch a wafer or substrate via a gap in the patterned mask to singulate a plurality of integrated circuits. In one such embodiment, one or more plasma etch chambers 808 are configured to perform a deep ruthenium etch process. In a particular embodiment, the one or more plasma etch chambers 808 based Applied Centura ^® Silvia ^TM etching system available from Applied Materials, Inc., California Sunnyvale. The etch chamber can be specifically designed for deep ruthenium etching, which is used to create tangential integrated circuits that are housed on or in a single crystal germanium substrate or wafer. In one embodiment, a high density plasma source is included in the plasma etch chamber 808 to promote a high erbium etch rate. In one embodiment, more than one etch chamber is included in the cluster tool 806 portion of the process tool 800 to enable high manufacturing throughput for the singulation or cutting process.

The factory interface 802 can be a suitable atmosphere that is externally fabricated and clustered with the laser scribing device 810 An interface is established between 806. The factory interface 802 can include a robot with an arm or a blade for transferring a wafer (or carrier of a wafer) from a storage unit (such as a front open wafer cassette) to a cluster tool 806 or a laser scribing device 810 or two Inside.

Cluster tool 806 can include other chambers suitable for performing various functions in the singulation method. For example, in one embodiment, a deposition chamber 812 is included in place of the additional etch chamber. The deposition chamber 812 can be configured to perform mask deposition on or over the wafer or substrate device layer prior to laser scribing of the wafer or substrate. In one such embodiment, the deposition chamber 812 is adapted to deposit a photoresist layer. In another embodiment, a wetting/drying station 814 is included in place of the additional etching chamber. The wetting/drying station can be adapted to clean residues and debris, or remove the mask after laser scribe and plasma etch dicing processes on the substrate or wafer. In an embodiment, a metering station is also included as an element in the process tool 800.

Embodiments of the invention may be provided as a computer program product or software, which may include a machine readable medium having instructions stored thereon, the computer program product or software being usable for use in a programmed computer system ( Or other electronic device) to perform a process in accordance with an embodiment of the present invention. In one embodiment, the computer system is coupled to the process tool 800 described in association with FIG. Machine readable media includes any mechanism for storing or transmitting information in a form readable by a machine (eg, a computer). For example, a machine readable (eg, computer readable) medium includes a machine (eg, a computer) Readable storage medium (for example, read only memory ("ROM"), random access memory (RAM), disk storage media, optical storage media, flash memory A device (eg, a computer) can read a transmission medium (a telecommunication number, an optical signal, an audio signal, or other forms of propagation signals (eg, an infrared signal, a digital signal, etc.)).

9 illustrates a graphical representation of an exemplary form of computer system 900 in which a set of instructions can be executed for causing the machine to perform any one or more of the methods described herein. In an alternate embodiment, the machine can be connected (e.g., networked) to other machines in a local area network (LAN), an internal network, an external network, or the Internet. The machine can operate as a server or client machine in a master-slave network environment or as a peer machine in a peer-to-peer (or decentralized) network environment. The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, A network router, switch, or bridge, or any machine capable of executing a set of instructions (in order or otherwise) that specifies the actions to be taken by the machine. Further, although only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (eg, computers) that individually or collectively perform one An instruction set (or sets of instructions) to perform any one or more of the methods described herein.

The exemplary computer system 900 includes a processor 902, main memory 904 (eg, read only memory (ROM), flash memory, dynamic random access memory such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM) ( Dynamic random access memory; DRAM), static memory 906 (eg, flash memory, static random access memory (SRAM), etc.) and secondary memory 918 (eg, data storage device) Each of the above communicates with each other via the bus 930.

Processor 902 represents one or more general purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processor 902 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, or a very long instruction word (very long instruction). Word; VLIW) A microprocessor, a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processor 902 can also be one or more dedicated processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (field programmable gate array; FPGA), digital signal processor (DSP), network processor or the like. Processor 902 is configured to execute processing logic 926 for performing the operations described herein.

Computer system 900 can further include a network interface device 908. The computer system 900 can also include a video display unit 910 (eg, a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), A digital input device 912 (eg, a keyboard), a cursor control device 914 (eg, a mouse), and a signal generating device 916 (eg, a speaker).

The secondary memory 918 can include a machine-accessible storage medium (or more specifically, a computer-readable storage medium) 932 on which one or more sets of instructions (eg, software 922) are stored, such The set of instructions specifically implements any one or more of the methods or functions described herein. The software 922 may also be located entirely or at least partially within the main memory 904 and/or within the processor 902 during execution of the software by the computer system 900. The main memory 904 and the processor 902 also form a machine readable storage medium. Software 922 can be further transmitted or received over network 920 via network interface device 908.

Although the machine-accessible storage medium 932 is shown as a single medium in an exemplary embodiment, the term "machine-readable storage medium" shall be taken to include a single storage of one or more instruction sets. Media or multiple media (eg, centralized or decentralized repositories, and/or associated caches and servers). The term "machine readable storage medium" shall also be taken to include any medium capable of storing or encoding a set of instructions executed by the machine and causing the machine to perform any one or more of the methods of the present invention. By. Therefore, the term "machine readable storage medium" shall be taken to include, but is not limited to, solid state memory and optical media and magnetic media.

In accordance with an embodiment of the present invention, a machine-accessible storage medium stores instructions that cause a data processing system to perform a method of cutting a semiconductor wafer having a plurality of integrated circuits. The method includes forming a mask over a semiconductor wafer, the mask including a layer covering and protecting the integrated circuit. The mask is then patterned using an ultrashort pulse Laguerre's laser beam laser scribing process to provide a patterned mask with a gap to expose the area of the semiconductor wafer between the integrated circuits. The ultrashort pulse Laguerre Gaussian laser beam laser scribing process involves scribing with a laser beam having axially symmetric polarization. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuit.

Thus, a hybrid wafer dicing method using an ultrashort pulse Laguerre laser beam laser scribing process and plasma etching has been disclosed.

100‧‧‧ Flowchart

102‧‧‧ operation

104‧‧‧Operation

106‧‧‧ operation

108‧‧‧ operation

Claims (20)

A method of cutting a semiconductor wafer comprising a plurality of integrated circuits, the method comprising the steps of: forming a mask over the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits; An ultrashort pulsed Laguerre laser beam laser scribing process patterning the mask to provide a patterned mask having a gap to expose an area of the semiconductor wafer between the integrated circuits The ultrashort pulse Laguerre Gaussian laser beam laser scribing process includes scribing with a laser beam having axially symmetric polarization; and etching through the gap plasma in the patterned mask The semiconductor wafer is singulated to form the integrated circuit. The method of claim 1, wherein the step of scribing with a laser beam having an axially symmetric polarization comprises the step of scribing with a laser beam having a radial polarization component. The method of claim 1, wherein the step of scribing with a laser beam having an axially symmetric polarization comprises the step of scribing with a laser beam having an azimuthal polarization component. The method of claim 1, wherein the step of scribing with a laser beam having axially symmetric polarization comprises The following step: scribing with a laser beam having both a radial polarization component and an azimuthal polarization component. The method of claim 1, wherein the step of scribing with a laser beam having an axially symmetric polarization comprises the step of scribing with a laser beam having a TEM01* mode. The method of claim 1, wherein the step of scribing with a laser beam having axially symmetric polarization comprises the step of scribing with an annular ring shape. The method of claim 1, wherein the step of patterning the mask by the laser scribing process comprises the step of forming a trench in the regions of the semiconductor wafer between the integrated circuits The trench, and wherein the step of plasma etching the semiconductor wafer comprises the step of extending the trenches to form corresponding trench extensions. The method of claim 7, wherein each of the grooves has a width, and wherein each of the corresponding groove extensions has the width. The method of claim 1, further comprising the step of: patterning the mask with the ultrashort pulse Laguerre laser beam laser scribing process and plasma etching through the gaps Prior to engraving the semiconductor wafer, the exposed regions of the semiconductor wafer are cleaned using a plasma process. A system for cutting a semiconductor wafer including a plurality of integrated circuits, the system comprising: a factory interface; a laser scribing device coupled to the factory interface and including a laser assembly The laser assembly is configured to provide an ultrashort pulse Laguerre laser beam having axially symmetric polarization; and a plasma etch chamber coupled to the factory interface. The system of claim 10, wherein the laser assembly is configured to provide the laser beam having a radially polarized component. The system of claim 10, wherein the laser assembly is configured to provide the laser beam having an azimuthal polarization component. The system of claim 10, wherein the laser assembly is configured to provide the laser beam having both a radial polarization component and an azimuthal polarization component. The system of claim 10, wherein the laser assembly is configured to provide the laser beam having a TEM01* mode. The system of claim 10, wherein the laser assembly is configured to provide the laser beam having an annular ring shape. The system of claim 10, wherein the laser scribing apparatus is configured to provide a linear to radial transition, or a linear to azimuthal transition, or linear to both radial and azimuthal, based on the segmented half-wave plate Conversion. A method of cutting a semiconductor wafer comprising a plurality of integrated circuits, the method comprising the steps of: forming a mask over the semiconductor wafer, the mask comprising a layer covering and protecting the integrated circuits; and utilizing An ultrashort pulse Laguerre Gaussian laser beam laser scribing process patterning the mask and cutting the integrated circuit, the laser scribing process comprising the steps of: utilizing a laser beam having axially symmetric polarization Dash. The method of claim 17, wherein the step of scribing with a laser beam having axially symmetric polarization comprises the step of utilizing a radial polarization component, an azimuthal polarization component or a radial polarization component and A laser beam of both azimuthal polarization components is scribed. The method of claim 17, wherein the step of scribing with a laser beam having axially symmetric polarization is performed The method includes the steps of: scribing with a laser beam having a TEM01* mode. The method of claim 17, wherein the step of scribing with a laser beam having an axially symmetric polarization comprises the step of scribing with an annular ring shape.