TW201602993A - Driving circuit and display device - Google Patents

Abstract

A driving circuit and a display device are disclosed herein. The driving circuit includes a control module and a shift register module. The control module is enabled by a start pulse signal and is configured to generate a first control signal to an Nth control signal sequentially according to a first operation signal to an Nth operation signal, respectively. The shift register module includes a first stage shift register unit to an Nth stage shift register unit. The first stage shift register unit to the Nth stage shift register unit are enabled by the first control signal to the Nth control signal, respectively. The first stage shift register unit to the Nth stage shift register unit are configured to generate a first driving signal to an Nth driving signal according to a first clock signal to an Nth clock signal, respectively.

Description

Drive circuit and display device

The present invention relates to a display device, and more particularly to a display device having a drive circuit.

Recently, various liquid crystal display products have become quite popular. In order to save costs, the gate driving circuit on the driver IC for generating signals is usually fabricated directly on a glass substrate, that is, a so-called Gate Driver on Array (GOA). The gate driving circuit includes a plurality of shift register circuits connected in series to generate a plurality of gate driving signals to the pixel array on the glass substrate. The gate drive signal is used to drive the pixel transistor in the pixel array.

The invention provides a driving circuit, and the driving circuit comprises a control module. The control module is configured to generate a corresponding plurality of control signals to the shift register module according to the plurality of sequential clock signals.

One aspect of the present disclosure is directed to a drive circuit. The driving circuit includes a control module and a shift register module. The control module is enabled by the start signal and used to divide the first operation signal to the Nth operation signal according to the sequence Do not generate the first control signal to the Nth control signal. The shift register module includes a first stage shift register unit to an Nth stage shift register unit. The first stage shift register unit to the Nth stage shift register unit are respectively enabled by the first control signal to the Nth control signal, and are respectively used according to the sequentially first clock signal to the Nth The clock signal generates a first driving signal to an Nth driving signal, where N is an integer greater than one.

Another aspect of the present disclosure is directed to a display device. The display device includes a pixel array, M scanning lines, and a driving circuit. The M scan lines are electrically coupled to the pixel array. The driving circuit is electrically coupled to the M scanning lines. The driving circuit comprises a control module and K shift register modules. The control module is configured to generate a first control signal to an Nth control signal according to the first operation signal to the Nth operation signal. The K shift register modules are used to generate M driving signals, and transmit M driving signals to the pixel array through the M scanning lines. One of the K shift register modules includes a first stage shift register unit to an Nth stage shift register unit. The first stage shift register unit to the Nth stage shift register unit are respectively enabled by the first control signal to the Nth control signal, and are respectively used according to the sequentially first clock signal to the Nth The clock signal generates a first driving signal to an Nth driving signal among the M driving signals, wherein K, M and N are integers greater than 1 and M=K×N.

In summary, the initial control signals are generated according to the sequential operation signals, so that the initial control signals have the same wave width and the voltage levels can be controlled at a fixed position, thereby improving the brightness unevenness of the picture.

100‧‧‧ gate drive circuit

110‧‧‧ starting circuit

120‧‧‧ level shift register circuit

300‧‧‧ display device

310‧‧‧ pixel array

320‧‧‧ drive circuit

321‧‧‧Control Module

322‧‧‧Shift register module

323‧‧‧Shift register module

324‧‧‧Shift register module

325‧‧‧Shift register module

400‧‧‧ drive circuit

410‧‧‧Control Module

420‧‧‧Shift register module

421‧‧‧Level 1 shift register unit

422‧‧‧Level 2 shift register unit

430‧‧‧Shift register module

431‧‧‧Level 3 shift register unit

432‧‧‧Level 4 shift register unit

440‧‧‧Shift register module

441‧‧‧Level 5 shift register unit

442‧‧‧Level 6 shift register unit

450‧‧‧Shift register module

451‧‧‧7th level shift register unit

452‧‧‧Level 8 shift register unit

500‧‧‧Control Module

510‧‧‧Enable unit

520‧‧‧Upper unit

530‧‧‧Upper unit

540‧‧‧Upper unit

550‧‧‧Upper unit

STP‧‧‧ start signal

HC1‧‧‧ first clock signal

HC2‧‧‧ second clock signal

HC3‧‧‧ third clock signal

HC4‧‧‧ fourth clock signal

HC5‧‧‧ fifth clock signal

HC6‧‧‧ sixth clock signal

HC7‧‧‧ seventh clock signal

HC8‧‧‧ eighth clock signal

Q(1)‧‧‧Level 1 control signal

Q(2)‧‧‧Level 2 control signals

Q(3)‧‧‧ Level 3 control signals

Q(4)‧‧‧Level 4 control signals

Q(5)‧‧‧Level 5 control signals

Q(6)‧‧‧Level 6 control signal

Q(7)‧‧‧Level 7 control signal

Q(8)‧‧‧8th level control signal

G(1)‧‧‧Level 1 drive signal

G(2)‧‧‧Level 2 drive signal

G(3)‧‧‧Level 3 drive signal

G(4)‧‧‧Level 4 drive signal

G(5)‧‧‧Level 5 drive signal

G(6)‧‧‧6th level drive signal

G(7)‧‧‧7th level drive signal

G(8)‧‧‧8th level drive signal

G(9)‧‧‧9th level drive signal

G(10)‧‧‧10th level drive signal

G(11)‧‧‧11th level drive signal

G(12)‧‧‧12th level drive signal

G(13)‧‧‧13th level drive signal

G(14)‧‧‧14th level drive signal

G(15)‧‧‧15th level drive signal

G(16)‧‧‧16th level drive signal

OP1‧‧‧ first operation signal

OP2‧‧‧Second operation signal

OP3‧‧‧ third operation signal

OP4‧‧‧ fourth operation signal

EN1‧‧‧First enable signal

EN2‧‧‧Secondary signal

EN3‧‧‧third enable signal

EN4‧‧‧ fourth enable signal

VGH‧‧‧ working voltage signal

SCN1~SCN16‧‧‧ scan line

T1~T8‧‧‧O crystal

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 2A is a timing diagram showing a start signal and a clock signal; FIG. 2B is a timing diagram showing another start signal and a clock signal; and FIG. 2C is a further start signal and A timing diagram of a clock signal; FIG. 3 is a schematic diagram of a display device according to an embodiment of the invention; FIG. 4 is a schematic diagram of a driving circuit according to an embodiment of the invention; and FIG. A schematic diagram of a control module according to an embodiment of the invention.

The following embodiments are described in detail with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of structural control is not intended to limit the order of execution, any The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For ease of understanding, the same elements in the following description will be denoted by the same reference numerals.

Terms used throughout the specification and patent application (terms), unless otherwise noted, usually have the usual meaning of each term used in this field, in the context of the disclosure and in the particular content. Certain terms used to describe the disclosure are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in the description of the disclosure.

As used herein, "about", "about" or "substantially" generally means that the error or range of the index value is within 20%, preferably within 10%, and more preferably It is within 5 percent. In the text, unless otherwise stated, the numerical values referred to are regarded as approximations, such as an error or range indicated by "about", "about" or "substantial", or other approximations.

The terms "first", "second", etc., as used herein, are not intended to refer to the order or the order, and are not intended to limit the invention, only to distinguish the elements described in the same technical terms. Or control only.

Secondly, the words "including", "including", "having," "containing," etc., as used herein are all terms of an open term, meaning, but not limited to.

In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components control or act on each other.

Please refer to FIG. 1 , which is a schematic diagram of a gate driving circuit 100 according to an embodiment of the present disclosure. The gate drive circuit 100 includes a start circuit 110 and a plurality of stage shift register circuits 120. As number 1 As shown, the gate drive circuit 100 is a circuit architecture of a pass 5 (i.e., the first stage control signal Q(1) is passed to the fifth stage shift register circuit 120). Specifically, the first stage shift register circuit 120 to the fourth stage shift register circuit 120 are respectively configured to generate the fifth level control signal Q(5) to the eighth level control signal Q(8), and The fifth stage control signal Q(5) to the eighth stage control signal Q(8) are respectively sent to the fifth stage shift register circuit 120 to the eighth stage shift register circuit. The fifth-stage shift register circuit 120 to the eighth-stage shift register circuit 120 are respectively enabled by the fifth-level control signal Q(5) to the eighth-order control signal Q8), and are respectively in accordance with the order The fifth clock signal HC5 to the eighth clock signal HC8 generate the fifth-level driving signal G(5) to the eighth-order driving signal G(8) to the corresponding pixel transistor. In general, the Nth stage shift register circuit 120 is configured to generate the (N+4)th level control signal and transmit the (N+4)th stage control signal to the (N+4)th stage shift register. The circuit 120 causes the (N+4)th stage shift register circuit 120 to generate the (N+4)th stage drive signal.

The start circuit 110 is configured to generate the first level control signal Q(1) to the fourth level control signal Q(4) and respectively transmit the first level control signal Q(1) to the fourth level control signal Q(4) to The first stage shift register circuit 120 to the fourth stage shift register circuit 120. The first stage shift register circuit 120 to the fourth stage shift register circuit 120 are respectively enabled by the first level control signal Q(1) to the fourth level control signal Q(4), and respectively according to the The first clock signal HC1 to the fourth clock signal HC4 sequentially generate the first level driving signal G(1) to the fourth level driving signal G(4).

The starting circuit 110 includes transistors T1 to T4. The drains of the transistors T1 to T4 are connected to each other, and the drains of the transistors T1 to T4 are also connected to respective gates, and together receive a start pulse STP. Since the start circuit 110 of the embodiment is controlled by the start signal STP signal, the first stage control signal Q(1) to the transistor T1~T4 is generated under the start signal STP of different timing conditions. The voltage level of the 4-level control signal Q(4) will make a difference. Please refer to Figures 2A and 2B. Figure 2A is a timing diagram showing a start signal and a clock signal. Figure 2B is a timing diagram showing another start signal and clock signal. In the first case, as shown in FIG. 2A, the start signal STP does not cover (not overlap) the first clock signal HC1 to the fourth clock signal HC4. At this time, the charging of the transistors T1~T4 The time is the same. However, since the respective hold times T _Hold (Hold time) between the start signal STP and the first clock signal HC1 to the fourth clock signal HC4 are different, the leakage levels of the output terminals of the transistors T1 to T4 are different.

In the second case, as shown in FIG. 2B, the start signal STP covers (overlaps) a part of the clock signal (for example, the start signal STP covers the first clock signal HC1), at this time, the transistor The charging time of T1~T4 is not the same. In addition, since the start signal STP completely covers the first clock signal HC1, the voltage across the drain and the source of the transistor T1 is the high level voltage of the control signal minus the high level voltage of the start signal STP. . However, since the start signal STP does not cover the third clock signal HC3 to the fourth clock signal HC4, and there is a hold time between the fourth clock signal HC4 and the start signal STP, the transistor T3~T4 is defective. The voltage across the pole and the source is the low level voltage of the control signal minus the low level voltage of the start signal STP. In addition, the start signal STP also partially covers the second clock signal HC2. therefore, The voltage across the drain and source of transistor T1 is not the same as the voltage across the drain and source of transistor T3~T4, and is not the same between the drain and source of transistor T2. The cross-voltage causes the leakage levels of the output terminals of the transistors T1~T4 to be different.

When any of the above occurs, a difference occurs in the voltage level between the first level control signal Q(1) to the fourth level control signal Q(4). This difference is amplified during the signal transmission (that is, the control signal transmitted to the next stage is caused by insufficient charging so that its voltage level is lower and lower), which causes the brightness of the picture to be uneven.

In addition, please refer to Figure 2C together. Figure 2C is a timing diagram showing still another start signal and clock signal. In the third case, the start signal STP completely covers the first clock signal HC1 to the fourth clock signal HC4. At this time, the charging times of the transistors T1 to T4 are not the same. Although the voltage between the drain and the source of the transistors T1 to T4 is the same. However, in the circuit architecture in which the clock signal is precharged to the next stage of the shift register circuit, the start signal STP will still partially cover the fifth clock signal HC5. In such a case, the fifth-stage shift register circuit 120 causes the fifth-stage driving signal G(5) to return to the operating point of the first-stage shift register circuit 120 to the low-level voltage. (ie, the N+4 stage pull back the Nth stage architecture), the operating point of the first stage shift register circuit 120 is still charged by the start signal STP through T1, thereby causing the first stage shift temporary storage to be unable to be pulled down. The operating point of the circuit 120 is to a low level voltage. Therefore, in the third case, the gate drive circuit 100 may cause an operation error.

The present disclosure provides an embodiment of another drive circuit. The driving circuit comprises a control module and K shift register modules. The control module is configured to generate a first control signal to an Nth control signal according to the first operation signal to the Nth operation signal. The K shift register modules are used to generate M driving signals, and transmit M driving signals to the pixel array through the M scanning lines. The M driving signals are respectively used to drive the pixel transistors in the pixel array. The first shift register module in the K shift register modules includes a first stage shift register unit to an Nth stage shift register unit. The first stage shift register unit to the Nth stage shift register unit are respectively enabled by the first control signal to the Nth control signal, and are respectively used according to the sequentially first clock signal to the Nth The clock signal generates a first driving signal to an Nth driving signal among the M driving signals. K, M and N are integers greater than 1 and M = K x N.

For convenience and clarity, please refer to FIG. 3, which is a schematic diagram of a display device 300 according to an embodiment of the invention. The display device 300 includes a pixel array 310, a drive circuit 320, and scan lines SCN1 to SCN16. The scan lines SCN1 S SCN16 are electrically coupled to the pixel array 310 and the driving circuit 320. The driving circuit 320 is configured to generate the first-stage driving signal G(1) to the 16th-level driving signal G(16), and drive the first-level driving signal G(1) to the 16th-level driving signal through the scanning lines SCN_1~SCN_16, respectively. G(16) is transferred to the corresponding pixel transistor (not shown) in the pixel array 310, and each pixel transistor is connected to the corresponding pixel electrode (not shown). In this embodiment, the driving circuit 320 is a circuit structure of 1 to 5 and can generate a total of 16 stages of driving signals to the pixel array 310. That is, in this reality In the embodiment, M=16, K=4 and N=4, but the embodiment is not limited thereto; in other words, those skilled in the art can select the driving circuit 320 as 1 or 3 or 1 according to actual needs. Pass 4 circuit structure.

The driving circuit 320 includes a control module 321 and shift register modules 322-325. The control module 321 is enabled by the start signal STP, and is configured to generate the first level control signal Q according to the first operation signal OP1, the second operation signal OP2, the third operation signal OP3, and the fourth operation signal OP4. 1) The second level control signal Q(2), the third level control signal Q(3) and the fourth level control signal Q(4) are given to the shift register module 322.

The shift register module 322 is caused by the first level control signal Q(1), the second level control signal Q(2), the third level control signal Q(3), and the fourth level control signal Q(4). The first stage driving signal G(1) and the second level driving signal are generated according to the first clock signal HC1, the second clock signal HC2, the third clock signal HC3, and the fourth clock signal HC4. G(2), level 3 drive signal G(3) and level 4 drive signal G(4). In addition, the shift register module 322 further generates a fifth-level control signal Q(5) according to the first clock signal HC1, the second clock signal HC2, the third clock signal HC3, and the fourth clock signal HC4. The sixth level control signal Q (6), the seventh level control signal Q (7) and the eighth level control signal Q (8) are supplied to the shift register module 323.

Similarly, the shift register module 323 is composed of a level 5 control signal Q (5), a level 6 control signal Q (6), a level 7 control signal Q (7), and a level 8 control signal Q (8). Generating energy, and generating the fifth-order driving signal G(5), the sixth according to the fifth clock signal HC5, the sixth clock signal HC6, the seventh clock signal HC7, and the eighth clock signal HC8. Level drive signal G(6), The seventh stage drive signal G (7) and the eighth stage drive signal G (8). In addition, the shift register module 323 also generates the next four levels of control signals to the shift register module 324, and the shift register module 324 is controlled by the shift register module 323. a signal, and generating a ninth-order driving signal G(9) and a tenth-level driving signal according to the first clock signal HC1, the second clock signal HC2, the third clock signal HC3, and the fourth clock signal HC4. G (10), the 11th stage drive signal G (11) and the 12th stage drive signal G (12), and also generate the next four levels of control signals to the shift register module 325, and so on. Therefore, the shift register modules 322-325 can sequentially generate the first stage driving signal G(1) to the 16th stage driving signal G(16) to the pixel array 310.

In the present embodiment, the drive circuit 320 is an eight-phase drive mode. Therefore, the shift register modules 322 and 324 generate drive signals according to the first clock signal HC1, the second clock signal HC2, the third clock signal HC3, and the fourth clock signal HC4. The shift register modules 323 and 325 generate driving signals according to the fifth clock signal HC5, the sixth clock signal HC6, the seventh clock signal HC7, and the eighth clock signal HC8, but this embodiment does not This is limited.

In an embodiment, the enable period of the start signal STP is greater than the sum of the enable periods of the first operation signal OP1, the second operation signal OP2, the third operation signal OP3, and the fourth operation signal OP4. Thereby, the control module 321 has sufficient time to sample the start signal STP.

In an embodiment, the first operation signal OP1, the second operation signal OP2, the third operation signal OP3, and the fourth operation signal OP4 are respectively the first four clock signals of the corresponding first clock signal HC1, Corresponding second The first four clock signals of the clock signal HC2, the first four clock signals of the corresponding third clock signal HC3, and the first four clock signals of the corresponding fourth clock signal HC4. In other words, before the control module 321 generates the first level control signal Q(1) to the fourth level control signal Q(4), the control module 321 receives four clock signals in advance for sampling the start signal STP. Therefore, in this embodiment, the first operation signal OP1, the second operation signal OP2, the third operation signal OP3, and the fourth operation signal OP4 are respectively the fifth clock signal HC5, the sixth clock signal HC6, and the seventh. Clock signal HC7 and eighth clock signal HC8.

In this way, according to the same wave width and sequential enabling characteristics of the clock signal, the first level control signal Q(1), the second level control signal Q(2), and the third level generated by the control module 321 can be made. The level control signal Q(3) and the fourth level control signal Q(4) have the same wave width and their voltage levels can be controlled at a fixed position, thereby improving the brightness unevenness of the picture.

Referring to FIG. 4, FIG. 4 is a schematic diagram of a driving circuit 400 according to an embodiment of the invention. The driving circuit 400 can be applied to the display device 300 in FIG. 3, but the embodiment is not limited thereto. In this embodiment, the driving circuit 400 is a circuit structure of 1 to 3, but the embodiment is not limited thereto. As shown in FIG. 4, the drive circuit 400 includes a control module 410 and shift register modules 420-450. The control module 410 is enabled by the start signal STP, and is configured to generate the first level control signal Q(1) and the second level control signal Q(2) according to the first operation signal OP1 and the second operation signal OP2. . Each of the shift register modules 420-450 includes two stages of shift register units.

The shift register module 420 includes a level 1 shift register unit 421 and 2nd stage shift register unit 422. The first stage shift register unit 421 and the second stage shift register unit 422 are respectively enabled by the first level control signal Q(1) and the second level control signal Q(2), and respectively The first clock signal HC1 and the second clock signal HC2 of the sequence generate the first stage driving signal G(1) and the second level driving signal G(2). In addition, the first stage shift register unit 421 and the second stage shift register unit 422 further generate the third level control signal Q(3) according to the first clock signal HC1 and the second clock signal HC2, respectively. Level 4 control signal Q (4).

Similarly, the shift register module 430 includes a level 3 shift register unit 431 and a level 4 shift register unit 432. The third stage shift register unit 431 and the fourth stage shift register unit 432 are respectively enabled by the third level control signal Q(3) and the fourth level control signal Q(4), and respectively The third clock signal HC3 and the fourth clock signal HC4 of the sequence generate the third level driving signal G(3) and the fourth level driving signal G(4). In addition, the third stage shift register unit 431 and the fourth stage shift register unit 432 further generate the fifth level control signal Q(5) according to the third clock signal HC3 and the fourth clock signal HC4, respectively. Level 6 control signal Q (6). Similarly, the shift register module 440 includes a fifth-stage shift register unit 441 and a sixth-stage shift register unit 442, and the shift register module 450 includes a level 7 shift register. The operation of the unit 451 and the eighth-stage shift register unit 452 are as described above, and are not described herein. Therefore, the first stage shift register unit 421 to the eighth stage shift register unit 452 can sequentially generate the first stage driving signal G(1) to the eighth level driving signal G(8) to the pixel array. (not shown in the figure) corresponding to the pixel transistor (not shown in the figure), and each pixel transistor will be connected to the pair The pixel electrode (not shown) should be.

In the present embodiment, the driving circuit 400 is a four-phase (4-phase) driving method. Therefore, the shift register modules 420 and 440 generate drive signals according to the first clock signal HC1 and the second clock signal HC2. The shift register modules 430 and 450 generate driving signals according to the third clock signal HC3 and the fourth clock signal HC4, but the embodiment is not limited thereto.

In an embodiment, the enable period of the start signal STP is greater than the sum of the enable periods of the first operation signal OP1 and the second operation signal OP2. Thereby, the control module 410 has enough time to sample the start signal STP.

In an embodiment, the first operation signal OP1 and the second operation signal OP2 are respectively the first two-level clock signal of the corresponding first clock signal HC1 and the previous two-level time of the corresponding second clock signal HC2. Pulse signal. In other words, during the generation of the first level control signal Q(1) to the second level control signal Q(2) by the control module 410, the control module 410 receives the two clock signals and samples the start signal STP. Therefore, in the embodiment, the first operation signal OP1 and the second operation signal OP2 are respectively the third clock signal HC3 and the fourth clock signal HC4.

Referring to FIG. 5, FIG. 5 is a schematic diagram of a control module 500 according to an embodiment of the invention. The control module 500 can be applied to the driving circuit 320 in FIG. 3 or in FIG. The driving circuit 400, but the embodiment is not limited thereto. In this embodiment, the control module 500 is a driving circuit applied to the circuit structure of 1 to 5, but this embodiment is not This is limited to this. As shown in FIG. 5, the control module 500 includes an enabling unit 510 and pull-up units 520-550. The enabling unit 510 is enabled by the start signal STP, and sequentially generates the first enable signal EN1 and the second according to the first operation signal OP1, the second operation signal OP2, the third operation signal OP3 and the fourth operation signal OP4. The enable signal EN2, the third enable signal EN3, and the fourth enable signal EN4 are applied to the pull-up units 520-550. The pull-up units 520-550 are respectively enabled by the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, and the fourth enable signal EN4, and are sequentially generated according to the working voltage signal VGH. Level 1 control signal Q (1), level 2 control signal Q (2), level 3 control signal Q (3) and level 4 control signal Q (4). The working voltage signal VGH is a voltage signal having a high voltage level and can be provided by a power supply circuit (not shown).

In an embodiment, the enabling unit 510 includes transistors T1~T4. Each of the transistors T1 to T4 includes a control end, a first end, and a second end. The control terminals of the transistors T1~T4 are all used to receive the start signal STP. The first ends of the transistors T1 to T4 receive the first operation signal OP1, the second operation signal OP2, the third operation signal OP3, and the fourth operation signal OP4, respectively. The second ends of the transistors T1~T4 respectively output a first enable signal EN1, a second enable signal EN2, a third enable signal EN3 and a fourth enable signal EN4.

The pull-up units 520 to 550 respectively include transistors T5 to T8. Each of the transistors T5~T8 includes a control end, a first end, and a second end. The control terminals of the transistors T5 to T8 are electrically coupled to the second ends of the transistors T1 to T4, respectively, and are respectively configured to receive the first enable signal EN1, the second enable signal EN2, the third enable signal EN3, and The fourth enable signal is EN4. Transistor T5 The first end of ~T8 is used to receive the working voltage signal VGH. The second ends of the transistors T5~T8 are respectively used for outputting the first level control signal Q(1), the second level control signal Q(2), the third level control signal Q(3) and the fourth level control signal Q ( 4).

In an embodiment, the enable period of the start signal STP is greater than the sum of the enable periods of the first operation signal OP1, the second operation signal OP2, the third operation signal OP3, and the fourth operation signal OP4.

Similarly, the first operation signal OP1 to the fourth operation signal OP4 may be the first four clock signals of the corresponding first clock signal HC1 and the first four clock signals of the corresponding fourth clock signal HC4. That is, four clock signals are provided in advance to the control module 500 for sampling the start signal STP.

Further, when the driving circuit is an N-transmitted (N+X) circuit structure, the initial control signal can be generated by providing X clock signals in advance to sample the start signal STP, where X is greater than 1. Integer. Under the design of the above control module, it is only necessary to change the layout of the clock signal to complete the routing without changing any timing settings. Therefore, the implementation of the driver circuit provided by the disclosure does not require too complicated design and excessive cost. Furthermore, the embodiments of FIGS. 3 to 5 are compared with the embodiments of FIGS. 1 to 2, and the embodiments of FIGS. 3 to 5 can more effectively solve the problems shown in FIGS. 1 to 2, such as screen brightness. Uneven and operational errors, etc.

According to the embodiment of the present invention, in the circuit structure in which the driving circuit is N-transmitted (N+X), the X-phase clock signal is provided in advance to the driving circuit to sample the start signal, and the clock signal has the same signal. Wave width and sequential enabling characteristics enable the initial control signal generated by the driver circuit It has the same wave width and its voltage level can also be controlled at a fixed position, thereby improving the uneven brightness of the picture.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

500‧‧‧Control Module

510‧‧‧Enable unit

520‧‧‧Upper unit

530‧‧‧Upper unit

540‧‧‧Upper unit

550‧‧‧Upper unit

STP‧‧‧ start signal

Q(1)‧‧‧Level 1 control signal

Q(2)‧‧‧Level 2 control signals

Q(3)‧‧‧ Level 3 control signals

Q(4)‧‧‧Level 4 control signals

OP1‧‧‧ first operation signal

OP2‧‧‧Second operation signal

OP3‧‧‧ third operation signal

OP4‧‧‧ fourth operation signal

EN1‧‧‧First enable signal

EN2‧‧‧Secondary signal

EN3‧‧‧third enable signal

EN4‧‧‧ fourth enable signal

VGH‧‧‧ working voltage signal

T1~T8‧‧‧O crystal

Claims (11)

A driving circuit comprising: a control module for generating a first control signal to an Nth control signal according to a first operation signal to an Nth operation signal; and a shift register module comprising a first stage shift register unit to an Nth stage shift register unit, wherein the first stage shift register unit is shifted to the Nth stage The register unit is respectively enabled by the first control signal to the Nth control signal, and is configured to generate a first driving signal to the first one according to the sequence of the first clock signal to the Nth clock signal. Nth drive signal. The driving circuit of claim 1, wherein the first operation signal to the Nth operation signal are respectively a first N-level clock signal corresponding to the first clock signal to a corresponding N-th clock. The first N-level clock signal of the signal. The driving circuit of claim 1, wherein the enabling period of the start signal is greater than a sum of the enabling periods of the first operation signal to the Nth operation signal. The driving circuit of claim 1, wherein the control module comprises: a matching energy unit for generating energy from the start signal, and according to the An operation signal to the Nth operation signal sequentially generates a first enable signal to an Nth enable signal; and N pull-up units for respectively from the first enable signal to the N-th enable signal The first control signal is sequentially generated to the Nth control signal according to a working voltage signal. The driving circuit of claim 4, wherein the enabling unit comprises: N transistors, respectively comprising a control end, a first end and a second end, wherein the control terminals of the N transistors are used Receiving the start signal, the first ends of the N transistors are respectively configured to receive the first operation signal to the Nth operation signal, and the second ends of the N transistors are respectively used to output the The first consistent signal can be sent to the Nth enable signal. The driving circuit of claim 4, wherein one of the N pull-up units comprises: a transistor, comprising a control end, a first end and a second end, wherein the control end is used for Receiving the Nth enable signal, the first end is configured to receive the working voltage signal, and the second end is configured to output the Nth control signal. A display device includes: a pixel array; M scan lines electrically coupled to the pixel array; and a driving circuit electrically coupled to the M scan lines, wherein the driving power The circuit includes: a control module configured to generate a first control signal to an Nth control signal according to a first operation signal to an Nth operation signal; and K shifts a bit buffer module for generating M driving signals, and transmitting the M driving signals to the pixel array through the M scanning lines; wherein one of the K shift register modules A shift register module includes a first stage shift register unit to an Nth stage shift register unit, wherein the first stage shift register unit to the Nth stage shift The memory unit is respectively enabled by the first control signal to the Nth control signal, and is configured to generate one of the M driving signals according to a first clock signal to an Nth clock signal. The first driving signal to an Nth driving signal, wherein M=K×N. The display device of claim 7, wherein the first operation signal to the Nth operation signal are respectively a first N-level clock signal corresponding to the first clock signal to a corresponding N-th clock. The first N-level clock signal of the signal. The display device of claim 7, wherein the control module comprises: a matching energy unit for generating energy from the start signal, and generating a first sequence according to the first operation signal to the Nth operation signal Consistent signal to And the Nth pull-up unit is configured to respectively generate the first control signal from the first enable signal to the N-th enable signal, and sequentially generate the first control signal according to a working voltage signal to The Nth control signal. The display device of claim 7, wherein the control module comprises: N first transistors, respectively comprising a control end, a first end and a second end, wherein the N first transistors The control terminals are configured to receive the start signal, and the first ends of the N first transistors are respectively configured to receive the first operation signal to the Nth operation signal, and the N first transistors The second end is configured to output the first enable signal to the Nth enable signal; and the N second transistors respectively include a control end, a first end, and a second end, wherein the N The control terminals of the two transistors are electrically coupled to the second ends of the N first transistors, and the first ends of the N second transistors are configured to receive the working voltage signal, the N The second ends of the second transistors are respectively configured to output the first control signal to the Nth control signal. The display device of claim 7, wherein the first stage shift register unit to the Nth stage shift register unit further according to the first clock signal to the Nth clock respectively The signal generates an (N+1) control signal to a 2N control signal, and one of the K shift register modules The second shift register module includes an (N+1)th shift register unit to a 2Nth shift register unit, wherein the (N+1)th shift register unit The second NN shift register unit is configured to generate energy from the (N+1)th control signal to the second N control signal, respectively, and according to a sequence of (N+1)th clock signals respectively. The 2Nth clock signal generates one (N+1)th driving signal to the 2Nth driving signal of the M driving signals.