TWI643171B - Shift register and control method thereof - Google Patents

Abstract

A shift register includes a control circuit and a shift register circuit. The control circuit includes a first-level control unit. The first-level control unit includes a first transistor, a second transistor, and a third transistor. The first transistor outputs a first-level control signal. The second transistor turns on the first transistor according to a start signal. The third transistor turns off the first transistor according to a first-level pull-down signal. The second transistor and the third transistor are coupled to an operation node. A control terminal of the first transistor has the same voltage level as the operating node. The shift temporary storage circuit outputs a first-stage shift signal according to the first-stage control signal.

Description

Shift register and control method thereof

The embodiment described in the present disclosure is related to a shift register.

The shift register is used to drive the display device. Generally speaking, the shift register has a multi-stage architecture, and the first few stages are driven by an external control circuit. In the existing driving method, the external control circuit uses a single transistor to charge the control nodes (such as the Q point) of the first-stage shift temporary storage circuits, and the transistors are all subject to the same Signal control. In this case, the control signals (for example, Q (n)) transmitted to the control nodes may cause inconsistent leakage levels. This may cause the display panel to generate local bright and dark lines.

An embodiment of the present disclosure relates to a shift register. The shift register includes a control circuit and a shift register circuit. The control circuit includes a first-level control unit. The first-level control unit includes a first transistor, a second transistor, and a third transistor. First transistor output Level 1 control signal. The second transistor turns on the first transistor according to a start signal. The third transistor turns off the first transistor according to a first-level pull-down signal. The second transistor and the third transistor are coupled to an operation node. A control terminal of the first transistor has the same voltage level as the operating node. The shift temporary storage circuit outputs a first-stage shift signal according to the first-stage control signal.

One embodiment of the present disclosure relates to a method for controlling a shift register. The control method includes: transmitting a control signal corresponding to a first constant voltage to a shift register circuit by a first transistor according to a start signal; and transmitting the start signal to a first transistor by a second transistor. A control terminal of a transistor; a voltage level of the control terminal of the first transistor is pulled down by a third transistor according to a pull signal and a second constant voltage; and a control signal output by a shift register circuit A shift signal.

In summary, by applying the at least one embodiment described above, the leakage levels of the first few control signals (for example, Q (n)) can be nearly the same, thereby improving the problem of local bright and dark lines.

100‧‧‧ shift register

120, 200, 500, 600‧‧‧ control circuits

140 (1) ~ 140 (12), 300, 140 (n) ‧‧‧ shift temporary storage circuit

Q (1), Q (2), Q (3), Q (4), Q (n), Q (n + k) ‧‧‧Control signal

LC1, LC2‧‧‧ operation signal

HC (1) ~ HC (8), HC (n) ‧‧‧clock signal

G (1) ~ G (12), G (n), G (n + k) ‧‧‧ shift signal

202, 204, 206, 208, 502, 504, 506, 508, 602, 604, 606, 608‧‧‧ control units

T11, T12, T13, T21, T14, T15, T31, T41, T51, T52, T53, T54, T32, T42, T61, T62, T63, T64, T43, T33‧‧‧Transistors

VGH, VGL‧‧‧constant voltage

ST‧‧‧Start signal

N (1) ~ N (4) ‧‧‧ Operation node

V1, V2, V3, V4, V5‧‧‧ voltage

VSS‧‧‧Reference voltage

T1, T2, T3, T4‧‧‧ time

FS, F1 ‧‧‧ falling edge

R4‧‧‧ rising edge

D1, D2‧‧‧‧stage

302‧‧‧Drive circuit

304‧‧‧pull-up circuit

306, 308, 310‧‧‧ pull-down circuit

A (n), A (1), A (2), A (3), A (4) ‧‧‧ internal nodes

ST (n), ST (1), ST (2), ST (3), ST (4) ‧‧‧ Internal node signals

P (n), K (n) ‧‧‧regulated nodes

C1‧‧‧capacitor

700‧‧‧Control method

S710, S720, S730, S740‧‧‧ steps

In order to make the above and other objects, features, advantages and embodiments of the present disclosure more comprehensible, the description of the drawings is as follows: FIG. 1 is a shift register according to some embodiments of the present disclosure FIG. 2 is a circuit diagram of the control circuit of FIG. 1 according to some embodiments of the present disclosure; FIG. 3 is a diagram of a shift register circuit according to some embodiments of the present disclosure. Circuit diagram; FIG. 4 is a timing diagram of some signals of the shift register according to FIG. 1 according to some embodiments of the present disclosure; FIG. 5 is a diagram of FIG. 1 according to some embodiments of the present disclosure; FIG. 6 is a circuit diagram of the control circuit of FIG. 1 according to some embodiments of the present disclosure; and FIG. 7 is a shift register according to some embodiments of the present disclosure. Flow chart of the control method.

The following is a detailed description with examples and the accompanying drawings, but the examples provided are not intended to limit the scope covered by this disclosure, and the description of the structure operation is not intended to limit the order of its execution, and any recombination of components The structure of the device and the device with the same effect are all covered by the present disclosure. In addition, the drawings are for illustrative purposes only, and are not drawn to the original dimensions. In order to facilitate understanding, the same elements or similar elements in the following description will be described with the same symbols.

The terms used throughout the specification and the scope of patent applications, unless otherwise specified, usually have the ordinary meaning of each term used in this field, in the content disclosed here, and in special content.

Please refer to Figure 1. FIG. 1 is a schematic diagram of a shift register 100 according to some embodiments of the present disclosure. In some embodiments, the shift register 100 includes a control circuit 120 and a plurality of shift registers. plural The shift register circuits are, for example, shift register circuits 140 (1) to 140 (12). The number of the shift register circuits in the above-mentioned shift register 100 is merely used as an example, and the various numbers of the shift register circuits are all within the consideration range of the present disclosure.

In some embodiments, the control circuit 120 outputs the first-level control signal Q (1) to the k-th control signal. k is a positive integer. For the example in FIG. 1, k is equal to 4, but this disclosure is not limited by this value. In other words, in some other embodiments, k may be another positive integer. Taking the example in the first figure, the control circuit 120 outputs the first-level control signal Q (1), the second-level control signal Q (2), the third-level control signal Q (3), and the fourth-level control signal Q, respectively. (4) To the first stage shift register circuit 140 (1), the second stage shift register circuit 140 (2), the third stage shift register circuit 140 (3), and the fourth stage shift register Circuit 140 (4).

In some embodiments, the first-stage shift register circuit 140 (1) outputs a fifth-stage control signal to the fifth-stage shift register circuit 140 (5) to drive the fifth-stage shift register circuit 140 ( 5). The second-stage shift register circuit 140 (2) outputs the sixth-stage control signal to the sixth-stage shift register circuit 140 (6) to drive the sixth-stage shift register circuit 140 (6). And so on.

In some embodiments, each shift register circuit receives an operation signal LC1, an operation signal LC2, a clock signal HC (1) ~ HC (8) and a corresponding control signal to output a shift signal G (1 ) ~ G (12). For example, the first-stage shift register circuit 140 (1) receives the operation signal LC1, the operation signal LC2, the first-stage clock signal HC (1), and the first-stage control signal Q (1) to output the first signal. Step shift signal G (1). The other stage shift temporary storage circuits have similar contents, so they are not repeated here.

Please refer to Figure 2. FIG. 2 is a diagram illustrating some embodiments according to the present disclosure. A circuit diagram of the control circuit 200 is shown. In some embodiments, the control circuit 200 is used to implement the control circuit 120 of FIG. 1. In some embodiments, the control circuit 200 includes a complex stage control unit. In the example of FIG. 2, the control circuit 200 includes a first-level control unit 202, a second-level control unit 204, a third-level control unit 206, and a fourth-level control unit 208.

Taking the first-level control unit 202 as an example, the first-level control unit 202 includes a transistor T11, a transistor T12, and a transistor T13. The first terminal of the transistor T11 is used to receive a first constant voltage VGH. The second terminal of the transistor T11 is used to output the first-stage control signal Q (1) to the first-stage shift register circuit 140 (1). The first terminal of the transistor T12 is coupled to the control terminal of the transistor T12. Transistor T12 forms a diode-connected transistor. The first terminal of the transistor T12 and the control terminal of the transistor T12 are used to receive the start signal ST. The second terminal of the transistor T12, the control terminal of the transistor T11, and the first terminal of the transistor T13 are coupled to the operation node N (1). The control terminal of the transistor T13 is used to receive the first-stage clock signal HC (1). The second terminal of the transistor T13 is used to receive a second constant voltage VGL. In some embodiments, the first constant voltage VGH is higher than the second constant voltage VGL.

Since the control terminal of the transistor T11 is coupled to the operation node N (1), the control terminal of the transistor T11 and the operation node N (1) have the same voltage level. The other operation nodes N (2) ~ N (4) have similar contents, so they will not be repeated here.

In operation, the transistor T12 turns on the transistor T11 according to the start signal ST. Transistor T13 turns off transistor T11 based on the first-stage clock signal HC (1). Specifically, the transistor T12 is turned on or off according to the start signal ST. When the transistor T12 is turned on (for example, the start signal ST has a high voltage), the transistor T12 is turned on. The start signal ST is transmitted to the operation node N (1), so that the transistor T11 is turned on according to the start signal ST. Then, the transistor T11 transmits the first constant voltage VGH as the first-level control signal Q (1). At this time, the first-level control signal Q (1) corresponds to the first constant voltage VGH. Transistor T13 is turned on or off according to the first pull-down signal. Taking the example in Figure 2 as an example, the first level pull-down signal is implemented by the first level clock signal HC (1). When the third transistor T13 is turned on (for example, the first-stage clock signal HC (1) has a high voltage), the transistor T13 pulls down the voltage level of the operating node N (1) to the second constant voltage VGL, so that the voltage The crystal T11 is turned off. The first stage shift temporary storage circuit 140 (1) outputs the first stage shift signal G according to the first stage control signal Q (1), the first stage clock signal HC (1), the operation signal LC1, and the operation signal LC2. (1). Since other stage control units have similar circuit architecture and operation, they are not repeated here.

Please refer to Figure 3. FIG. 3 is a circuit diagram of a shift register circuit 300 according to some embodiments of the present disclosure. In some embodiments, the shift register circuit 300 of FIG. 3 is used to implement the n-th stage shift register circuit 140 (n) of FIG. 1. n is a positive integer. For example, when the shift register circuit 300 in FIG. 3 is used to implement the first stage shift register circuit in FIG. 1, n is equal to 1.

In some embodiments, the shift register circuit 300 includes a driving circuit 302, a pull-up circuit 304, a first pull-down circuit 306, a second pull-down circuit 308, and a third pull-down circuit 310.

In some embodiments, the driving circuit 302 is configured to output the n-th stage shift signal G (n) according to the n-th stage clock signal HC (n). In some embodiments, the driving circuit 302 includes a transistor T21. The first terminal of the transistor T21 is used to receive the n-th clock signal HC (n). The second terminal of the transistor T21 is used to output the n-th stage shift signal G (n). The control terminal of the transistor T21 is used to receive the n-th level control signal Q (n). In operation, when the transistor T21 is turned on according to the n-th stage control signal Q (n), the transistor T21 transmits the n-th stage clock signal HC (n) as the n-th stage shift signal G (n).

In some embodiments, the pull-up circuit 304 includes an internal node A (n) and is used to output the (n + k) th level control signal Q (n + k) according to the nth level clock signal HC (n). In some embodiments, the pull-up circuit 304 includes a transistor T14 and a transistor T15. The first terminal of the transistor T14 is used to receive the n-th clock signal HC (n). The second terminal of the transistor T14 is coupled to the internal node A (n). The control terminal of the transistor T14 is used to receive the n-th level control signal Q (n). The first terminal of the transistor T15 is used to output the (n + k) th stage control signal Q (n + k). The second terminal of the transistor T15 is used to receive the n-th shift signal G (n). The control terminal of the transistor T15 is coupled to the internal node A (n). In operation, when the transistor T14 is turned on according to the n-th control signal Q (n), the transistor T14 transmits the n-th clock signal HC (n) to the internal node A (n). The voltage level at the internal node A (n) is regarded as the internal node signal ST (n). Transistor T15 is turned on or off according to the voltage level at internal node A (n). When the transistor T15 is turned on, the transistor T15 transmits the n-th stage shift signal G (n) as the (n + k) -th stage control signal Q (n + k). The nth stage shift register circuit 140 (n) transmits the (n + k) th stage control signal Q (n + k) to the (n + k) stage shift register circuit to drive the (n + k) th stage ) Stage shift temporary storage circuit.

In some embodiments, the first pull-down circuit 306 is used to pull down the n-th stage control signal Q (n) and the n-th stage shift signal G (n). In some embodiments, the first pull-down circuit 306 includes a transistor T31 and a transistor T41. The first terminal of the transistor T31 is used to receive the n-th stage shift signal G (n). The second terminal of the transistor T31 is used to receive the reference voltage VSS. The control terminal of the transistor T31 is used to receive the (n + k) th stage shift signal G (n + k). The first end of transistor T41 is used to receive the nth Control signal Q (n). The second terminal of the transistor T41 is used to receive the reference voltage VSS. The control terminal of the transistor T41 is used to receive the (n + k) th stage shift signal G (n + k). In operation, when the transistor T31 and the transistor T41 are turned on according to the (n + k) th stage shift signal G (n + k), the transistor T31 and the transistor T41 respectively shift the nth stage shift signal G (n ) And the n-th level control signal Q (n) is pulled down to the reference voltage VSS.

In some embodiments, the second pull-down circuit 308 is used to pull down the n-th stage control signal Q (n) and the n-th stage shift signal G (n). In some embodiments, the second pull-down circuit 308 includes a transistor T51, a transistor T52, a transistor T53, a transistor T54, a transistor T32, and a transistor T42. The first terminal and the control terminal of the transistor T51 are used to receive the operation signal LC1. Transistor T51 forms a diode-type transistor. The second terminal of the transistor T51 is coupled to the control terminal of the transistor T53. The first end of the transistor T53 is used to receive the operation signal LC1. The second terminal of the transistor T53 is coupled to the n-th voltage stabilizing node P (n). The first terminal of the transistor T52 is coupled to the second terminal of the transistor T51. The second terminal of the transistor T52 is used to receive the reference voltage VSS. The first terminal of the transistor T54 is coupled to the n-th level regulator node P (n). The second terminal of the transistor T54 is used to receive the reference voltage VSS. The control terminals of the transistor T52 and the transistor T54 are used to receive the n-th level control signal Q (n). The first terminal of the transistor T32 is coupled to the capacitor C1 and configured to receive the n-th stage shift signal G (n). The second terminal of the transistor T32 is used to receive the reference voltage VSS. The first terminal of the transistor T42 is used to receive the n-th level control signal Q (n). The second terminal of the transistor T42 is used to receive the reference voltage VSS. The control terminal of the transistor T32 and the control terminal of the transistor T42 are coupled to the n-th level regulator node P (n).

In operation, when the transistor T51 is based on the operating signal LC1 (for example For example, when the operation signal LC1 has a high voltage, the transistor T51 transmits the operation signal LC1 to the control terminal of the transistor T53. When the transistor T53 is turned on according to the operation signal LC1, the transistor T53 transmits the operation signal LC1 to the n-th level voltage stabilization node P (n). When the transistor T32 and the transistor T42 are turned on according to the voltage level at the n-th voltage stabilizing node P (n), the transistor T32 and the transistor T42 respectively shift the n-th stage by the signal G (n) and the n-th The control signal Q (n) is pulled down to the reference voltage VSS. When the transistor T54 and the transistor T52 are turned on according to the n-th level control signal Q (n), the transistor T54 and the transistor T52 will be at the voltage level of the n-th voltage stabilization node P (n) and at the transistor T53, respectively. The voltage level of the control terminal is pulled down to the reference voltage VSS.

In some embodiments, the third pull-down circuit 310 is used to pull down the n-th stage control signal Q (n) and the n-th stage shift signal G (n). In some embodiments, the third pull-down circuit 310 includes a transistor T61, a transistor T62, a transistor T63, a transistor T64, a transistor T43, and a transistor T33. The first terminal and the control terminal of the transistor T61 are used to receive the operation signal LC2. Transistor T61 forms a diode-type transistor. The second terminal of the transistor T61 is coupled to the control terminal of the transistor T63. The first end of the transistor T63 is used to receive the operation signal LC2. The second terminal of the transistor T63 is coupled to the n-th voltage stabilizing node K (n). A first terminal of the transistor T62 is coupled to a second terminal of the transistor T61. The second terminal of the transistor T62 is used to receive the reference voltage VSS. The first terminal of the transistor T64 is coupled to the n-th voltage stabilizing node K (n). The second terminal of the transistor T64 is used to receive the reference voltage VSS. The control terminals of the transistor T62 and the transistor T64 are used to receive the n-th level control signal Q (n). The first terminal of the transistor T33 is used to receive the n-th shift signal G (n). The second terminal of the transistor T33 is used to receive the reference voltage VSS. The first end of transistor T43 is used to receive the nth stage Control signal Q (n). The second terminal of the transistor T43 is used to receive the reference voltage VSS. The control terminal of the transistor T33 and the control terminal of the transistor T43 are coupled to the n-th voltage stabilizing node K (n).

In operation, when the transistor T61 is turned on according to the operation signal LC2 (for example, the operation signal LC2 has a high voltage), the transistor T61 transmits the operation signal LC2 to the control terminal of the transistor T63. When the transistor T63 is turned on according to the operation signal LC2, the transistor T63 transmits the operation signal LC2 to the n-th voltage stabilizing node K (n). When the transistor T33 and the transistor T43 are turned on according to the voltage level at the n-th voltage stabilizing node K (n), the transistor T33 and the transistor T43 shift the n-th stage by the signal G (n) and the n-th stage The control signal Q (n) is pulled down to the reference voltage VSS. When the transistor T64 and the transistor T62 are turned on according to the nth stage control signal Q (n), the transistor T64 and the transistor T62 will be at the voltage level of the nth voltage stabilizing node K (n) and the transistor T63, respectively. The voltage level of the control terminal is pulled down to the reference voltage VSS.

In some embodiments, the transistors are implemented by N-type transistors. In some other embodiments, the transistors may be implemented as P-type transistors. This disclosure does not limit the types of these transistors.

Please refer to Figure 4. FIG. 4 is a timing diagram of some signals of the shift register 100 shown in FIG. 1 according to some embodiments of the present disclosure.

Please refer to Figure 4. In some embodiments, the start signal ST has two voltages. These two voltages are voltage V1 and voltage V2, respectively. In some embodiments, the voltage V1 is higher than the voltage V2. In some embodiments, the voltage V1 corresponds to a logic value 1 and the voltage V2 corresponds to a logic value 0. In some embodiments, the voltage V1 is substantially equal to the first constant voltage VGH and the voltage V2 is substantially equal to the second constant voltage VGH. Constant voltage VGL. The clock signals HC (1) ~ HC (8) have two voltages. These two voltages are respectively voltage V3 and voltage V4. In some embodiments, the voltage V3 is higher than the voltage V4. In some embodiments, the voltage V3 corresponds to a logic value 1 and the voltage V4 corresponds to a logic value 0.

Please also refer to Figures 2 to 4. From time T1 to time T2 (for example, the first charging phase D1), the start signal ST has a voltage V1. The transistor T12 of the first-level control unit 202 is turned on according to the start signal ST. Transistor T12 transmits the start signal ST to the operating node N (1). At this time, the voltage level at the operation node N (1) is substantially equal to the voltage V1. Transistor T11 is turned on according to the voltage level at the operating node N (1). The transistor T11 transmits the first constant voltage VGH to the first-stage shift register circuit 140 (1) as the first-stage control signal Q (1). At this time, the voltage level of the first stage control signal Q (1) is substantially equal to the first constant voltage VGH, so the transistor T21 is turned on, and the transistor T21 transmits the first stage clock signal HC (1) as the nth stage shift Bit signal G (n). Since the first-stage clock signal HC (1) has a voltage V4 from time T1 to time T2, the transistor T13 is turned off.

At time T2, the first-stage clock signal HC (1) rises from voltage V4 to voltage V3. The transistor T13 of the first-stage control unit 202 is turned on according to the first-stage clock signal HC (1). The transistor T13 pulls down the voltage level at the operating node N (1) to a second constant voltage VGL. At this time, the voltage level at the operation node N (1) is substantially equal to the second constant voltage VGL. Since the transistor T21 transmits the first-stage clock signal HC (1) as the n-stage shift signal G (n) and the n-stage shift signal G (n) is coupled to the first-stage control signal Q through the capacitor C1 (1), so the first level control signal Q (1) rises from the first constant voltage VGH to the voltage V5 based on the coupling effect of the capacitor C1.

At time T3, the first-stage clock signal HC (1) drops from voltage V3 to voltage V4. The transistor T13 of the first-stage control unit 202 is turned off according to the first-stage clock signal HC (1). The first level control signal Q (1) drops from the voltage V5 to the first constant voltage VGH.

At time T4, the first-stage control signal Q (1) is pulled down to the reference voltage VSS according to the fifth-stage clock signal HC (5). For example, when the fifth stage shift register circuit 140 (5) outputs the fifth stage clock signal HC (5) as the fifth stage shift signal G (5), the first stage shift register circuit 140 The transistor T41 of (1) is turned on according to the fifth-stage shift signal G (5). When the transistor T41 is turned on, the transistor T41 pulls down the first-level control signal Q (1) to the reference voltage VSS.

Taking the example in FIG. 4 as an example, the falling edge FS of the start signal ST is earlier in timing than the falling edge F1 of the clock signal HC (1) of the first stage. In some embodiments, the falling edge FS of the start signal ST is not later than the falling edge F1 of the first-stage clock signal HC (1) in timing. Transistor T13 pulls down the voltage level of the control terminal of transistor T11 according to the first-stage clock signal HC (1). Equivalently, the falling edge F1 of the first-stage clock signal HC (1) represents the time point when the transistor T13 completes the pull-down operation. It is assumed that the falling edge FS of the start signal ST is later in timing than the falling edge F1 of the clock signal HC (1) of the first stage. The start signal ST may pull up the voltage level of the control terminal of the transistor T11 again, so that the transistor T11 is turned on by mistake. Therefore, the falling edge FS of the start signal ST is not later than the falling edge F1 of the first-stage clock signal HC (1) in timing. In Figure 4, the falling edge FS of the start signal ST is earlier in timing than the falling edge F1 of the clock signal HC (1) of the first stage, which can ensure that the start signal ST is returned before the transistor T13 completes the pull-down operation. To low voltage. In this way, the voltage level of the control terminal of the transistor T11 can be ensured. The standard will not be pulled up again by the start signal ST.

In some embodiments, the falling edge FS of the start signal ST is aligned in timing with the rising edge of the k-th pull-down signal. Taking the example in FIG. 1, k is equal to 4, and the transistor T13 of the fourth-stage control unit 208 is controlled by the fourth-stage clock signal HC (4) to control the voltage level of the control terminal of the pull-down transistor T11. Equivalently, the fourth-level clock signal HC (4) is used to implement the fourth-level pull-down signal. In FIG. 4, the falling edge FS of the start signal ST is aligned in timing with the rising edge R4 of the fourth-stage clock signal HC (4). Since the pulse width of the start signal ST covers the rising edges of the first-stage clock signal HC (1) to the fourth-stage clock signal HC (4), the first-stage control signal Q (1), the second-stage The first charging stage D1 of the control signal Q (2), the third-level control signal Q (3), and the fourth-level control signal Q (4) are all charged to the same voltage level.

With the configuration of the control circuit 120, in the first charging stage D1 of the first-stage control signal Q (1), the first-stage control signal Q (1) is charged to the first constant voltage VGH. When the clock signal HC (1) of the first stage changes to a high voltage at time T2, the voltage level of the control terminal of the transistor T11 is pulled down to the reference voltage VSS. Thus, in the second charging stage D2 of the first-stage control signal Q (1), the gate-drain voltage (Vgd) of the transistor T11 in the first-stage control unit 202 is substantially equal to the second constant voltage VGL and the first The voltage difference between a certain voltage VGH. The source-drain voltage (Vsd) of the transistor T11 in the first-stage control unit 202 is substantially equal to the voltage difference between the voltage V5 and the first constant voltage VGH. Since the second-level control unit 204, the third-level control unit 206, and the fourth-level control unit 208 have similar circuit architectures, the second-level control signal Q (2), the third-level control signal Q (3), and the The second charging stage of the 4-level control signal Q (4). The gate-drain voltage (Vgd) of the transistor T11 is also substantially equal to the voltage difference between the second constant voltage VGL and the first constant voltage VGH. In this way, the transistor T11 of the first four stages is subjected to the same bias voltage and the control signals of the first four stages (for example, the control signals Q (1) to Q (4)) have the same degree of leakage in the second charging stage. In this case, the output capabilities of the first four stages of the temporary storage circuits can be made similar, thereby improving the problem of local bright and dark lines.

Please refer to Figure 5. FIG. 5 is a circuit diagram of a control circuit 500 according to some embodiments of the present disclosure. In some embodiments, the control circuit 500 is used to implement the control circuit 120 of FIG. 1. In some embodiments, the control circuit 500 includes a complex stage control unit. Taking the example in FIG. 5, the control circuit 500 includes a first-level control unit 502, a second-level control unit 504, a third-level control unit 506, and a fourth-level control unit 508. The content of Figure 5 is similar to Figure 2, so only the main differences between Figure 5 and Figure 2 will be described below. For the rest, please refer to the foregoing embodiments, and details are not described herein again.

Taking the example in FIG. 5 as an example, the control terminals of the transistors T13 are used to receive corresponding shift signals. For example, the control terminal of the transistor T13 of the first-stage control unit 502 is used to receive the first-stage shift signal G (1). In this way, when the first-stage shift signal G (1) has a high voltage, the transistor T13 will be turned on and the voltage level at the control terminal of the transistor T11 will be pulled down to the second constant voltage VGL. Since other levels of control units have similar content, they will not be repeated here.

With the configuration of the control circuit 500, the shift signals (for example, shift signals G (1) to G (4)) at each level are used as the pull-down signals at each level. Because the shift signals at all levels are only pulled up and down once in each frame, compared to the transistor T13 of the control circuit 200, the transistor T13 of the control circuit 500 suffers Less stress.

Please refer to Figure 6. FIG. 6 is a circuit diagram of a control circuit 600 according to some embodiments of the present disclosure. In some embodiments, the control circuit 600 is used to implement the control circuit 120 of FIG. 1. In some embodiments, the control circuit 600 includes a complex stage control unit. Taking the example in FIG. 6, the control circuit 600 includes a first-level control unit 602, a second-level control unit 604, a third-level control unit 606, and a fourth-level control unit 608. The control circuit 600 of FIG. 6 is similar to the control circuit 500 of FIG. 5, so only the main differences between FIG. 6 and FIG. 5 will be described below. For the rest, please refer to the foregoing embodiments, and details are not described herein again.

Taking the example in FIG. 6 as an example, the control terminal of the transistors T13 is coupled to the internal node A (n) of the corresponding pull-up circuit 304. For example, the transistor T13 of the first-stage control unit 602 is coupled to the internal node of the pull-up circuit 304 of the first-stage shift register circuit 140 (1) to receive the internal node signal ST (1). In this way, when the internal node signal ST (1) has a high voltage level, the transistor T13 will be turned on and the voltage level at the control terminal of the transistor T11 will be pulled down to the second constant voltage VGL. Equivalently, the voltage level at the internal node A (1) is used as the first pull-down signal for controlling the transistor T13. In other words, the voltage level of the internal node A (1) is substantially the same as the voltage level of the first-level pull-down signal. Since other levels of control units have similar content, they will not be repeated here.

The control circuit 500 in FIG. 5 uses the shift signals at various stages as the pull-down signals at various stages. Since the shift signals of various stages are connected to the display area of the display panel to drive the pixels of the display area, the shift signals of the stages are affected by a large RC delay. In this case, the waveform of the shift signal at each stage will not be close to the square wave. In contrast, the control circuit 600 uses internal node signals ST (1) ~ ST (4) are used as the first four pull-down signals. Compared with the shift signals at various levels, the internal node signals ST (1) ~ ST (4) are closer to the square wave, so the pull-down capability of the control circuit 600 is better.

Please refer to Figure 7. FIG. 7 is a flowchart of a control method 700 for a shift register according to some embodiments of the present disclosure. In order to better understand the present disclosure, the control method 700 will be discussed in conjunction with the first-level control unit 202 of the shift register 100 in FIG. 1, but the present disclosure is not limited thereto.

In step S710, the transistor T11 of the first-stage control unit 202 transmits the first-stage control signal Q (1) corresponding to the first constant voltage VGH to the first-stage shift register circuit according to the start signal ST. 140 (1).

In step S720, the start signal ST is transmitted to the control terminal of the transistor T11 of the first-stage control unit 202 through the transistor T12 of the first-stage control unit 202. In some embodiments, when the transistor T12 is turned on according to the start signal ST (for example, the start signal ST has a high voltage), the transistor T12 transmits the start signal ST to the control terminal of the transistor T11. In this way, the transistor T11 is turned on according to the start signal ST. Then, the transistor T11 transmits the first constant voltage VGH as the first-level control signal Q (1). At this time, the first-level control signal Q (1) corresponds to the first constant voltage VGH.

In step S730, the transistor T13 of the first-stage control unit 202 pulls down the transistor of the first-stage control unit 202 according to the pull-down signal (for example, the first-stage clock signal HC (1)) and the second constant voltage VGL. Voltage level of the control terminal of T11. In some embodiments, the transistor T13 is turned on according to the first-stage clock signal HC (1) (eg, when the first-stage clock signal HC (1) has a high voltage), the transistor T13 is turned on. Pull down the voltage level of the operating node N (1) to the second constant voltage VGL. In this way, the transistor T11 is turned off.

In step S740, the first-stage shift register circuit 140 (1) outputs the first-stage shift signal G (1) according to the first-stage control signal Q (1). In some embodiments, the first-stage shift register circuit 140 (1) receives the first-stage control signal Q (1), the first-stage clock signal HC (1), the operation signal LC1, and the operation signal LC2 according to The above signals output the first-stage shift signal G (1).

The control method 700 in the above description includes exemplary operations, but these operations need not be performed in the above order. According to the spirit and scope of the present disclosure, the order of operations in the control method 700 of the present disclosure can be changed, or these operations can be performed simultaneously or partially simultaneously as the case may be.

In summary, by applying the at least one embodiment described above, the leakage levels of the first few control signals (for example, Q (n)) can be nearly the same, thereby improving the problem of local bright and dark lines.

Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Any person with ordinary knowledge in the field can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, this disclosure The scope of protection shall be determined by the scope of the attached patent application.

Claims (8)

A shift register includes: a control circuit including a first-level control unit; the first-level control unit includes: a first transistor that outputs a first-level control signal; a second transistor, according to An initial signal turns on the first transistor; and a third transistor, the first transistor is turned off according to a first-level pull-down signal, wherein the second transistor and the third transistor are coupled to an operation node, A control terminal of the first transistor has the same voltage level as the operation node; and a shift temporary storage circuit, which outputs a first-stage shift signal according to the first-stage control signal; A falling edge is earlier in timing than a falling edge of the level 1 pull-down signal. The shift register according to claim 1, wherein the control circuit outputs the first-level control signal to a k-level control signal, and the falling edge of the start signal is aligned with a k-level pull-down in time sequence. A rising edge of the signal, where k is a positive integer. The shift register according to claim 1, wherein the first-level pull-down signal is the first-level shift signal. The shift register according to claim 1, wherein the control circuit outputs the first-level control signal to a k-th control signal, and the shift temporary storage circuit includes: a driving circuit according to a first stage The clock signal outputs the first-level shift signal; a pull-up circuit including an internal node and outputs a (1 + k) -level control signal according to the first-level clock signal; a first pull-down circuit, pull-down The first-level control signal and the first-level shift signal; a second pull-down circuit that pulls down the first-level control signal and the first-level shift signal; and a third pull-down circuit that pulls down the first-level control Signal and the first-stage shift signal, wherein the first-stage pull-down signal has the same voltage level as the internal node, where k is a positive integer. The shift register according to claim 4, wherein the pull-up circuit includes: a fourth transistor, a first end of the fourth transistor receives the first-stage clock signal, and the fourth transistor A second terminal is coupled to the internal node; and a fifth transistor, a first terminal of the fifth transistor outputs the (1 + k) level control signal, and a control terminal of the fifth transistor Coupled to the internal node. The shift register according to claim 1, wherein the first transistor receives a first constant voltage, the third transistor receives a second constant voltage, and the first constant voltage is higher than the second constant voltage. Voltage. The shift register according to claim 1, wherein a control terminal of the second transistor receives the start signal, and one end of the second transistor is coupled to the control terminal of the second transistor. A control method for a shift register includes: transmitting a control signal corresponding to a first constant voltage to a shift register circuit by a first transistor according to a start signal; and using a second transistor The crystal transmits the start signal to a control terminal of the first transistor; a third transistor pulls down a voltage level of the control terminal of the first transistor according to a pull signal and a second constant voltage; And outputting a shift signal according to the control signal by the shift register circuit; wherein a falling edge of the start signal is earlier in timing than a falling edge of the pull-down signal.