TW201601315A - Semiconductor device having metal layer over drift region - Google Patents

Abstract

A semiconductor device includes a substrate, an insulation layer disposed over the substrate, covering a drift region, and including a first edge and a second edge opposite to the first edge, a gate layer covering the first edge of the insulation layer, and a metal layer including a metal portion connected to the gate layer and overlapping the first edge of the insulation layer. The metal portion includes a first edge located closer to a central portion of the insulation layer than an opposite second edge of the metal portion. A distance from the first edge of the metal portion to the first edge of the insulation layer along a channel length direction is a. A distance from the first edge of the insulation layer to the second edge of the insulation layer is L. A ratio of a/L is equal to or higher than 0.46.

Description

Semiconductor component having a metal layer over the drift region 【0001】

The present disclosure relates to a semiconductor component, and more particularly to a semiconductor component having a metal layer over a drift region.

【0002】

Ultra-high voltage semiconductor devices are widely used in display elements, portable elements, and many other applications. Ultra high voltage semiconductor components are designed to include high breakdown voltages, low specific on-resistance, and high reliability in both room temperature and high temperature environments. However, as the size of ultra-high voltage semiconductor components is reduced, it is extremely challenging to achieve these design goals.

[0003]

According to an embodiment of the invention, a semiconductor device includes a substrate, a drift region, an insulating layer, a gate layer, and a metal layer. The drift region is disposed in the substrate. The insulating layer is disposed on the substrate and covers the drift region. The insulating layer includes a first edge and a second edge, and the second edge is opposite to the first edge. The gate layer is disposed over the substrate and covers the first edge of the insulating layer. The metal layer is disposed on the substrate and the insulating layer. The metal layer includes a metal portion connected to the gate layer and overlapping the first edge of the insulating layer. The metal portion includes a first edge, the first edge of the metal portion being located closer to a central portion of the insulating layer than a second edge opposite the metal portion. A distance a from the first edge of the metal portion to the first edge of the insulating layer along a length direction of the channel. A distance L from the first edge of the insulating layer to the second edge of the insulating layer. The a/L ratio is equal to or higher than 0.46.

[0004]

In accordance with another embodiment of the present invention, a semiconductor device includes a substrate, a drift region, an insulating layer, a gate layer, and a metal layer. The drift region is disposed in the substrate. The insulating layer is disposed on the substrate and covers the drift region. The insulating layer includes a first edge and a second edge, and the second edge is opposite to the first edge. The gate layer is disposed over the substrate and covers the first edge of the insulating layer. The metal layer is disposed on the substrate and the insulating layer. The metal layer includes a metal portion connectable to receive a turn-on voltage and overlap the insulating layer. The metal portion includes a first edge that is closer to a central portion of the insulating layer than a second edge opposite the metal portion. A distance a from the first edge of the metal portion to the second edge of the insulating layer along the length of one channel. A distance L from the first edge of the insulating layer to the second edge of the insulating layer. The b/L ratio is equal to or lower than 0.3.

[0005]

According to still another embodiment of the present invention, an integrated circuit includes a substrate, a drift region, an insulating layer, a gate layer, and a metal layer. The substrate includes a high side operation region, a low side operation region and an ultrahigh voltage metal oxide semiconductor region, and the ultrahigh voltage metal oxide semiconductor region is disposed between the high side operation region and the low side operation region. The drift region is disposed in the ultrahigh voltage metal oxide semiconductor region of the substrate. The insulating layer is disposed on the substrate and covers the drift region. The insulating layer includes a first edge and a second edge, and the second edge is opposite to the first edge. The gate layer is disposed over the substrate and covers the first edge of the insulating layer. The metal layer is disposed on the substrate and the insulating layer. The metal layer includes a metal portion connected to the gate layer and overlapping the first edge of the insulating layer. The metal portion includes a first edge positioned closer to a central portion of the insulating layer than a second edge opposite the metal portion. A distance a from the first edge of the metal portion to the first edge of the insulating layer along a length direction of the channel. A distance L from the first edge of the insulating layer to the second edge of the insulating layer. The a/L ratio is equal to or higher than 0.46.

[0039]

100‧‧‧ integrated circuit
100a, 100b‧‧‧ well
110‧‧‧High-voltage side operating area
120‧‧‧Low-side operating area
130, 140‧‧‧UHV metal oxide semiconductor components
150‧‧‧metal layer
160‧‧‧Ultra-high voltage metal oxide semiconductor region
170‧‧‧Self-shielded area
180‧‧‧High pressure interconnected area
200‧‧‧Substrate
211, 212, 213‧‧‧N type buried layer
221, 222‧‧‧High pressure N-type well
231, 232, 233‧‧‧P type well
240‧‧‧ drift zone
240a‧‧‧Part 1
240b‧‧‧Part II
242‧‧‧P type top
244‧‧‧N-class
250‧‧‧Insulation
251, 252, 253, 254‧‧ ‧ field oxidation
Edge of 252a, 252b, 343a, 343b, 344a, 344b‧‧
260‧‧‧ gate oxide layer
270‧‧ ‧ gate layer
280‧‧‧ spacers
291, 292, 293‧‧‧N ⁺
300‧‧‧P ⁺ District
310‧‧‧Interlayer dielectric layer
320‧‧‧First metal layer
321 , 322 , 323 , 324 , 325 , 326‧‧‧ the first metal layer
330‧‧‧Metal dielectric layer
340‧‧‧Second metal layer
341, 342, 343, 344, 345‧‧‧ second metal layer
C‧‧‧Central Part
a, b, L‧‧‧ distance
A-A'‧‧‧ hatching
Body voltage V _bulk ‧‧‧
V _B ‧‧‧Starting voltage
V _D ‧‧‧汲polar voltage
V _G ‧‧‧ gate voltage
V _S ‧‧‧ source voltage
OD‧‧‧Oxidation defined area
B‧‧‧ base extreme
D‧‧‧汲 Extreme
G‧‧‧ gate extreme
S‧‧‧ source extreme

[0006]

1 is a top view of an integrated circuit having an Ultra-High Voltage Metal-Oxide-Semiconductor device (UHV MOS device) according to an embodiment of the present invention.
2A is a top view of an ultrahigh voltage metal oxide semiconductor device in accordance with an embodiment of the present invention.
FIG. 2B is another top view of the ultrahigh voltage metal oxide semiconductor device of FIG. 2A showing only the metal layer and the Oxide Defined area (OD area) formed without the insulating layer.
Fig. 2C is a cross-sectional view showing the ultrahigh voltage metal oxide semiconductor device taken along line AA' of Fig. 2A.
FIG. 3 is a schematic diagram showing the results of the breakdown voltage (BVD) test of different samples 1 to 6.

【0007】

Embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used to refer to the same or.

[0008]

1 is a top view of an integrated circuit (IC) 100 having an Ultra-High Voltage Metal-Oxide-Semiconductor device (UHV MOS device) according to an embodiment of the present invention. As shown in Fig. 1, the integrated circuit 100 is formed on a substrate having two wells 100a and 100b. The substrate includes a High Voltage Side Operating Region (HSOR) 110 and a Low Voltage Side Operating Region (LSOR) 120. The high side operating zone 110 is located within the area surrounded by the two wells 100a and 100b. The low pressure side operating zone 120 is located on the left and lower sides of the area surrounded by the two wells 100a and 100b. The integrated circuit 100 includes two ultrahigh voltage metal oxide semiconductor elements 130 and 140 between the high side operating region 110 and the low side operating region 120. The ultrahigh voltage metal oxide semiconductor devices 130 and 140 have a similar structure, but may have different operating voltages, such as gate voltage, source voltage, drain voltage, and Bulk voltage. Both of the ultrahigh voltage metal oxide semiconductor devices 130 and 140 have a relatively high breakdown voltage of more than 500 volts (V). Although FIG. 1 shows only two ultrahigh voltage metal oxide semiconductor devices 130 and 140, another semiconductor device (for example, a low voltage metal oxide semiconductor device (Low-Voltage Metal-Oxide-Semiconductor device, LVMOS device) can be formed. ), Bipolar Junction Transistors (BJTs), capacitors, resistors, etc., in the high side operating region 110. The semiconductor element formed in the high side operation region 110 is connected to a ground voltage of more than 500 volts. Similarly, additional semiconductor components (eg, low voltage metal oxide semiconductor components, bipolar junction transistors, capacitors, resistors, etc.) may be formed in the low side operating region 120. The semiconductor element formed in the low side operation region 120 is connected to a ground voltage of about 0 volts. The ground voltage described herein refers to a reference voltage. The integrated circuit 100 also includes a metal layer 150 surrounding the high side operating region 110. During the operation of the integrated circuit 100, a boot voltage (V _B ) is applied to the metal layer 150.

【0009】

2A is an enlarged top view of the ultrahigh voltage metal oxide semiconductor device 130 according to an embodiment. 2B is another enlarged top view of the ultrahigh voltage metal oxide semiconductor device 130 of FIG. 2A, showing only the metal layer and the Oxide Defined (OD) region formed without the insulating layer. Fig. 2C is a cross-sectional view of the ultrahigh voltage metal oxide semiconductor device 130 connected along the line A-A' of Fig. 2A. Since the structure of the ultrahigh voltage metal oxide semiconductor device 140 is similar to that of the ultrahigh voltage metal oxide semiconductor device 130, an additional description of the ultrahigh voltage metal oxide semiconductor device 140 is not provided.

[0010]

The ultrahigh voltage metal oxide semiconductor device 130 is provided on a P-type substrate 200. Referring to FIGS. 2A to 2C , the high-voltage side operation region 110 is disposed on the right side portion of the substrate 200 , and the low-voltage side operation region 120 is disposed on the left side portion of the substrate 200 . The ultrahigh voltage metal oxide semiconductor region 160 and the self-shielding region 170 are disposed between the high side operation region 110 and the low voltage side operation region 120. A high voltage interconnection region 180 is disposed over the self-shielding region 170 and overlaps the right edge of the ultrahigh voltage MOS region 160 and the left edge of the high side operation region 110. The high side operation region 110 is separated from the ultrahigh voltage metal oxide semiconductor region 160 by the self-shielding region 170 and the high voltage interconnect region 180.

[0011]

The substrate 200 includes a first N-type Buried Layer (NBL) 211, a second N-type buried layer 212, and a third N-type buried layer 213. The first N-type buried layer 211 is disposed in the ultrahigh voltage metal oxide semiconductor region 160. The second N-type buried layer 212 is disposed in the ultrahigh voltage metal oxide semiconductor region 160. The third N-type buried layer 213 is disposed in the high-voltage side operation region 110. Each of the first N-type buried layer to the third N-type buried layer 211 to 213 is formed by an N-type dopant (for example, arsenic or antimony) at about 10 ¹³ to 10 ¹⁶ atoms. Doping is carried out at a concentration of / square centimeter (atoms/cm ² ). A first high-voltage N-Well (HVNW) 221 is disposed in the ultra-high voltage metal oxide semiconductor region 160 of the substrate 200. A second high voltage N-type well 222 is disposed in the high side operating region 110 of the substrate 200. The first high pressure N-type well 221 is spaced apart from and electrically isolated from the second high pressure N-type well 222. The first high-pressure N-well 221 and the second high-pressure N-well 222 are at about 10 ¹¹ to 10 ¹³ atoms/cm ² by an N-type dopant (for example, phosphorus or arsenic). Doping is carried out at a concentration. The first N-type buried layer 211 is connected to the left side of the bottom of the first high-pressure N-type well 221. The second N-type buried layer 212 is connected to the right side of the bottom of the first high-pressure N-type well 221. The third N-type buried layer 213 is connected to the bottom of the second high pressure N-type well 222.

[0012]

A first P-well (PW) 231 is disposed in the first high-pressure N-well 221, and the first P-well 231 extends to connect to the first at the bottom of the first high-pressure N-well 221 N-type buried layer 211. The second P-well 232 and the third P-well 233 are disposed in the self-shielding region 170 of the substrate 200 between the first high-pressure N-well 221 and the second high-pressure N-well 222. The first P-type well to the third P-type wells 231 to 233 are doped by a P-type dopant (for example, boron) at a concentration of about 10 ¹¹ to 10 ¹⁴ atoms/cm 2 . The second P-well 232 is adjacent to the right side of the first high pressure N-type well 221, and the third P-type well 233 is adjacent to the left side of the second high pressure N-type well 222. The second P-well 232 and the third P-well 233 are separated from each other to electrically isolate the high-pressure side operating zone 110 from the low-pressure side operating zone 120. Although the ultrahigh voltage metal oxide semiconductor device 130 illustrated in FIGS. 2A to 2C includes only the second P-well 232 and the third P-well 233 to electrically isolate the first high-voltage N-well 221 from the second high-voltage N The well 222, the ultra-high voltage metal oxide semiconductor device 130 may include more than two P-type wells, and the P-type wells are disposed between the first high-pressure N-type well 221 and the second high-pressure N-type well 222 to electrically isolate A high pressure N-type well 221 and a second high pressure N-type well 222. In addition, the second high pressure P-well 232 and the third high pressure P-well 233 promote a reduced surface field (RESURF) effect such that a drift region (described in detail below) can be completely Lack of space.

[0013]

A drift region 240 is disposed in the first high pressure N-well 221 and is separated from the first P-well 231. The drift region 240 includes a plurality of first portions 240a and second portions 240b alternately along the width direction of the channel of the ultrahigh voltage metal oxide semiconductor device 130 (ie, as shown in FIGS. 2A to 2C) Y direction) configuration. Each of the first portions 240a includes a P-top layer 242 and an N-grade layer 244 formed on the P-type top layer 242. Each of the second portions 240b does not include any P-type top or N-type levels. The P-type top layer 242 is doped by a P-type dopant (e.g., boron) at a concentration of about 10 ¹¹ to 10 ¹⁴ atoms/cm 2 . The N-type layer 244 is doped by an N-type dopant such as phosphorus or arsenic at a concentration of about 10 ¹¹ to 10 ¹⁴ atoms/cm 2 . Although FIG. 2C only shows a cross-sectional view of one of the first portions 240a, the cross-sectional view of the second portion 240b is similar to the cross-sectional view of the first portion 240a, except for the first high-pressure N-well in the cross-sectional view of the second portion 240b. 221 forms the entirety of the drift region 240. The function of the drift region 240 is to reduce the operating voltage from a relatively high voltage of more than 500 volts in the high side operating region 110 to a voltage of 0 volts in the low side operating region 120. Therefore, the operating voltage of the element formed in the high-voltage side operating region 110 is higher than 500 volts, and the operating voltage of the element formed in the low-voltage side operating region 120 is about 0 volt.

[0014]

An insulating layer 250 is disposed on the substrate 200. The insulating layer 250 may form a field oxide (FOX). Hereinafter, the insulating layer 250 is meant to be a field oxide layer (FOX layer) 250. The field oxide layer 250 includes a first field oxide portion 251, a second field oxide portion 252, a third field oxide portion 253, and a fourth field oxide portion 254. The first field oxidation portion 251 covers the left side edge portion of the first high pressure N-type well 221 and the left side edge portion of the first P-type well 231. The second field oxidation portion 252 covers the drift region 240. The third field oxidation portion 253 covers the space between the right edge portion of the first high pressure N-type well 221, the second P-type well 232, the third P-type well 233, the second P-type well 232, and the third P-type well 233. And a left side edge portion of the second high pressure N-type well 222. The fourth field oxidation portion 254 covers the right edge portion of the second high pressure N-type well 222.

[0015]

A gate oxide layer 260 is disposed on the substrate 200, and the gate oxide layer 260 covers the right portion of the first P-well 231 and the first P-well 231 and the second field oxide portion 252. Space between. A gate layer 270 is disposed over the substrate 200, and the gate layer 270 covers the left side portion of the gate oxide layer 260 and the second field oxide portion 252. A spacer 280 is disposed on the sidewall of the gate layer 270. A first N ⁺ region 291 (hereinafter referred to as source region 291) is disposed in the right portion of the first P-well 231 adjacent to the left portion of the gate oxide layer 260. A second N ⁺ region 292 (hereinafter referred to as the drain region 292) is disposed in the first high voltage N-well region 221 between the second field oxide portion 252 and the third field oxide portion 253. The third N ⁺ region 293 is disposed in the second high voltage N-well 222 between the third field oxide portion 253 and the fourth field oxide portion 254. The first N ⁺ region to the third N ⁺ regions 291 to 293 are doped by an N-type dopant such as phosphorus or arsenic at a concentration of about 10 ¹⁵ to 10 ¹⁶ atoms/cm 2 . A P ⁺ region 300 (hereinafter referred to as a bulk region 300) is disposed in a left side portion of the first P-well 231 adjacent to a right edge portion of the first field oxide portion 251. The P ⁺ region 300 is doped by a P-type dopant such as boron at a concentration of about 10 ¹⁵ to 10 ¹⁶ atoms/cm 2 . Therefore, the gate layer 270 covers the region between the source region 291 and the second field oxide portion 252 and extends to cover the left portion of the second field oxide portion 252.

[0016]

An interlayer dielectric layer (ILD layer) 310 is disposed on the substrate 200 and has a through hole corresponding to the body region 300, the source region 291, the gate layer 270, and the drain A region 292 and a third N ⁺ region 293. A first metal layer (M1 layer) 320 is disposed on the interlayer dielectric layer 310, and the first metal layer 320 includes a first first metal layer portion to a sixth first electrically isolated from each other. Metal layer portions 321 to 326. The first first metal layer portion 321 is overlapped with the body region 300, and the first first metal layer portion 321 is connected to the body region 300 via a corresponding via hole in the interlayer dielectric layer 310. The second first metal layer portion 322 is overlapped with the source region 291, and the second first metal layer portion 322 is connected to the source region 291 via a corresponding via hole in the interlayer dielectric layer 310. The third first metal layer portion 323 is overlapped with the gate layer 270 and the second field oxide portion 252, and the third first metal layer portion 323 is connected to the gate layer 270 via a corresponding via hole in the interlayer dielectric layer 310. . The fourth part of the first metal layer 324 overlaps the field oxide portion 252 to the second, the fourth and the first metal layer portion 324 may be connected to receive a power voltage _(boot voltage, V boot). The fifth first metal layer portion 325 is overlapped with the drain region 292, and the fifth first metal layer portion 325 is connected to the drain region 292 via a corresponding via hole in the interlayer dielectric layer 310. The sixth first metal layer portion 326 overlaps the third N ⁺ region 293, and the sixth first metal layer portion 326 is connected to the third N ⁺ region 293 via a corresponding via hole in the interlayer dielectric layer 310. Although it is not shown in FIGS. 2A to 2C, the fourth first metal layer portion 324 may be connected to a resistor or a Zener diode formed on the substrate 200 to lower the boot voltage (V _boot ). The voltage is applied to a lower voltage, thereby providing a voltage difference to be applied to an element (not shown) formed in the high side operation region 110, and having an operating voltage equivalent to the voltage difference. For example, if the turn-on voltage is 500 volts, the fourth first metal layer portion 324 can be connected to a resistor or Zener diode to step down the 500 volt startup voltage to about 485 volts, thus providing a voltage of 15 volts. The difference is given to the element formed in the high side operating region 110 and has an operating voltage of about 15 volts.

[0017]

An inter-metal dielectric layer (IMD layer) 330 is disposed on the first metal layer 320, and the inter-metal dielectric layer 330 has a portion corresponding to the first first metal layer, respectively. Through holes (so-called vias) of the six first metal layer portions 321 to 326. A second metal layer (M2 layer) 340 is disposed over the intermetal dielectric layer 330 and includes a first second metal layer portion to a fifth second metal layer portion 341 to 345. The first second metal layer portion 341 is overlapped with the body region 300, and the first second metal layer portion 341 is via the first first metal layer portion 321 and between the interlayer dielectric layer 310 and the intermetal dielectric layer 330. Corresponding via holes are connected to the body region 300. The second second metal layer portion 342 is overlapped with the source region 291, and the second second metal layer portion 342 is via the second first metal layer portion 322 and the interlayer dielectric layer 310 and the intermetal dielectric layer 330. Corresponding via holes in the middle are connected to the source region 291. The third second metal layer portion 343 is overlapped with the gate layer 270 and the second field oxide portion 252, and the third second metal layer portion 343 is via the third first metal layer portion 323 and the interlayer dielectric layer 310. A corresponding via hole in the inter-metal dielectric layer 330 is connected to the gate layer 270. The fourth second metal layer portion 344 is overlapped with the second field oxide portion 252, and the fourth second metal layer portion 344 is connected to the power-on voltage (V _B ) via a via hole (not shown in FIG. 2C). Four first metal layer portions 324. The fifth portion 345 of the second metal layer to the drain region 292 overlaps with the third N ⁺ type region 293, a second metal layer and the fifth portion 345 of the first metal layers are respectively the fifth portion 325 via a sixth The first metal layer portion 326 and the corresponding via holes in the interlayer dielectric layer 310 and the inter-metal dielectric layer 330 are connected to the drain region 292 and the third N ⁺ -type region 293. The fifth second metal layer portion 345 is formed in the high voltage interconnection region 180 and functions to provide the ultrahigh voltage metal oxide semiconductor device 130 and the element formed in the high side operation region 110. An internal link.

[0018]

In operation, a bulk voltage (V _bulk ) of about 0 volts is applied to the first second metal layer portion 341, and a source voltage (V _S ) of about 0 volts is applied to the second The second metal layer portion 342, a gate voltage (V _G ) is applied to the third second metal layer portion 343, and a turn-on voltage (V _B ) is applied to the fourth second metal layer portion 344. And a drain voltage (V _D ) is applied to the fifth second metal layer portion 345. The turn-on voltage (V _B ) is above 500 volts and is higher than or equal to the drain voltage (V _D ). Power voltage (V _B) is also higher than the source voltage (V _S), the gate voltage (V _G) of the body voltage (V _bulk).

[0019]

As shown in FIGS. 2B and 2C, the second field oxide portion 252 includes a left side edge 252a proximate to the source region 291 and a right side edge 252b proximate to the drain region 292. The third second metal layer portion 343 includes an edge 343a located closer to the central portion C of the second field oxide portion 252 than the opposite edge 343b of the third second metal layer portion 343. The fourth second metal layer portion 344 includes an edge 344a that is located closer to the central portion C of the second field oxide portion 252 than an opposite edge 344b. Along the channel length direction of the ultrahigh voltage metal oxide semiconductor device 130 (i.e., the direction in which the carrier flows (the X direction depicted in FIGS. 2A to 2C)), the third second metal layer portion 343 The distance from the edge 343a to the left edge 252a of the second field oxidizing portion 252 is meant to be the distance "a". The distance from the edge 344a of the fourth second metal layer portion 344 to the right edge 252b of the second field oxide portion 252 is referred to as the distance "b" along the length direction of the channel. The distance from the left edge 252a of the second field oxidizing portion 252 to the right edge 252b of the second field oxidizing portion 252 is meant to be the distance "L" along the length of the channel. The distance L can range from 30 micrometers (μm) to 150 micrometers.

[0020]

According to an embodiment of the present invention, when the a/L ratio is equal to or higher than 0.46 and the b/L ratio is equal to or lower than 0.3, the ultrahigh voltage metal oxide semiconductor device 130 has a relatively high breakdown voltage and is at a high temperature. The environment is reliable.

[0021]

Experimental Example 1: Breakdown test

[0022]

The crash test was performed on Samples 1 to 6, and Samples 1 through 6 were fabricated to have the structures as shown in Figures 2A through 2C. The sizes of Samples 1 to 6 are the same except for the distances a, b, and L. Table 1 summarizes the distances a, b, and L in samples 1 through 6, and the ratios a/L and b/L.
Table I

[0023]

During the crash test, the first second metal layer portion 341, the second second metal layer portion 342, and the third second metal layer portion 343 are grounded and applied by a voltage system that is continuously increased by 0 volts. The fourth second metal layer portion 344 and the fifth second metal layer portion 345 are until the component collapses (i.e., a sudden increase in the drain-source current) to confirm the breakdown voltage of the device.

[0024]

Figure 3 shows a schematic diagram confirming the breakdown voltage of Sample 1 to Sample 6 by a crash test. According to Fig. 3, samples 2, 4 and 6 of distance a2 have higher breakdown voltages than samples 1, 3 and 5 of distance a1, respectively. That is, the breakdown voltage increases with an increased distance "a". This is because when the distance "a" increases, the right edge 343a of the third second metal layer portion 343 more closely extends toward the central portion C of the second field oxide portion 252, thereby causing the source region 291 and the drain region The potential distribution between 292 becomes more uniform. Therefore, the breakdown voltage is increased.

[0025]

Further, according to Fig. 3, samples 5 and 6 of distance b3 have higher breakdown voltages than samples 3 and 4 of distance b2, and samples 3 and 4 of distance b2 are compared with samples of distance of b1. 1 and 2 have higher breakdown voltages. That is, the breakdown voltage increases as the distance "b" decreases. This is because when the distance "b" decreases, the left edge 344a of the fourth second metal layer portion 344 extends more closely toward the right edge 252b of the second field oxide portion 252, thereby causing the source region 291 and the drain region The potential distribution between 292 becomes more uniform. Therefore, the breakdown voltage is increased.

[0026]

Further, according to Fig. 3, the sample 6 having the distances a2 and a3 has a breakdown voltage of 600 volts, which is higher than the breakdown voltage of the samples 1 to 5. Further, based on the extrapolation shown by the broken line in FIG. 3, when the distance "a" is larger than a2 and the distance "b" is larger than b3, a breakdown voltage higher than 600 volts can be achieved. That is, when the component is formed with a b/L ratio higher than the a/L ratio of 0.46 and less than 0.3, the component may have a breakdown voltage higher than 600 volts.

[0027]

Experimental Example 2: High temperature reverse bias test

[0028]

A high temperature reverse bias test (HTRB test) was conducted for samples 11 to 30, and samples 11 to 30 were fabricated to have the structures as shown in Figs. 2A to 2C. The high temperature reverse bias test evaluates the long-term reliability and stability of the sample under high reverse bias when the sample is turned-off. The distance "a" of the samples 11 to 20 is a1 = 26 μm, and the distance "b" is b3 = 20 μm, and the distance "a" of the samples 21 to 30 is a2 = 30 μm, and the distance "b" is b3. Samples 11 through 30 were the same size except for 20 microns. During the high temperature reverse bias test, the first second metal layer portion 341 (ie, the bulk terminal), the second second metal layer portion 342 (ie, the source terminal), and The third second metal layer portion 343 (ie, the gate terminal) is grounded, and a voltage of 400 volts is applied to the fourth second metal layer portion 344 and the fifth portion in an environment of 150 ° C. The two metal layer portion 345 (i.e., the drain terminal) is 168 hours. The threshold voltage (V _T ) is the value of the gate-source voltage when the conduction channel is initially connected to the source and drain regions of the transistor to allow significant current flow. When a small voltage (e.g., 0.1 volt) is applied to the drain region before and after the test, the threshold voltage of each sample between the gate terminal and the source terminal is measured. When an operating voltage (for example, 15 volts) is applied to the gate terminal to ensure that the sample cell system is on-state and used to measure the resistance before and after the test, the 汲 extreme and source terminals are measured. The on-state resistance (R _on ) of each sample in between. When the sample is turned-off, the breakdown voltage of each sample between the 汲 extreme and the source terminal is measured after the test.

[0029]

Table 2 summarizes the test results for samples 11 to 30.

[0030]

Table II

[0031]

In Table 2, the threshold voltage change (ΔV _T ) is the change in the threshold voltage measured after the test for the threshold voltage measured before the test. The on-resistance change (ΔR _on ) is the change in on-resistance measured after the test for the on-resistance measured before the test. Standard for high temperature reverse bias test is the amount measured after the test should be higher than the breakdown voltage of 500 volts, and the on-resistance variation (ΔR _on) should be less than 30%.

[0032]

According to Table 2, the samples 21 to 30 having a larger distance from "a" have a lower on-resistance change (ΔR _on ) than the samples 11 to 20 having a smaller distance from "a". That is, as the distance "a" increases, the on-resistance change decreases. In addition, when the distance "a" increases, the component is reliable in the high temperature reverse bias test.

[0033]

Although the ultrahigh voltage metal oxide semiconductor device 130 of the above-described embodiments of the present invention is provided on a P-type semiconductor substrate, those skilled in the art will appreciate that the concepts disclosed in the present invention can be applied to N. A semiconductor substrate, a semiconductor on insulator substrate (SOI substrate), or any other suitable high voltage metal oxide semiconductor device on a substrate.

[0034]

Although the ultrahigh voltage metal oxide semiconductor device 130 in the above embodiment includes two metal layers (ie, the first metal layer 320 and the second metal layer 340), those skilled in the art will appreciate the disclosure of the present invention. The concept can also be applied to ultrahigh voltage metal oxide semiconductor components including any number of metal layers, such as a single metal layer, or three or more metal layers. That is, as long as the uppermost metal layer has a ratio a/L equal to or higher than 0.46 and the ratio b/L is equal to or lower than 0.3, the ultrahigh voltage metal oxide semiconductor device may have a relatively high breakdown voltage and reverse in high temperature. Reliable in a biased environment.

[0035]

Although the insulating layer 250 of the ultrahigh voltage metal oxide semiconductor device 130 in the above embodiment is composed of a field oxide, the insulating layer 250 may be formed by other suitable dielectric insulating structures (for example, a shallow trench isolation structure). , STI structure)).

[0036]

Although the ultrahigh voltage metal oxide semiconductor device 130 illustrated in FIGS. 2A to 2C has a Lateral Drain Metal-Oxide-Semiconductor device (LDMOS device), those having ordinary knowledge in the art will understand The concept disclosed in the present invention is equivalent to application to other semiconductor elements, such as an insulated gate dielectric device (IGBT device) and a diode.

[0037]

Although the ultrahigh voltage metal oxide semiconductor device 130 in the above embodiment includes the first N-type buried layer to the third N-type buried layer 211 to 213, those skilled in the art will understand the first N-type buried. The layer to third N-type buried layers 211 to 213 may be removed by replacing the first P-type well 231 with a shallow P-type well.

[0038]

Other embodiments of the invention will be apparent to those skilled in the <RTIgt; The specification and examples are to be considered as illustrative only, and the scope of the invention is defined by the scope of the appended claims.

110‧‧‧High-voltage side operating area

120‧‧‧Low-side operating area

130‧‧‧Ultra-high voltage metal oxide semiconductor components

160‧‧‧Ultra-high voltage metal oxide semiconductor region

170‧‧‧Self-shielded area

180‧‧‧High pressure interconnected area

200‧‧‧Substrate

211, 212, 213‧‧‧N type buried layer

221, 222‧‧‧High pressure N-type well

231, 232, 233‧‧‧P type well

240‧‧‧ drift zone

242‧‧‧P type top

244‧‧‧N-class

250‧‧‧Insulation

251, 252, 253, 254‧‧ ‧ field oxidation

Edge of 252a, 252b, 343a, 343b, 344a, 344b‧‧

260‧‧‧ gate oxide layer

270‧‧ ‧ gate layer

280‧‧‧ spacers

291, 292, 293‧‧‧N ⁺

300‧‧‧P ⁺ District

310‧‧‧Interlayer dielectric layer

320‧‧‧First metal layer

321 , 322 , 323 , 324 , 325 , 326‧‧‧ the first metal layer

330‧‧‧Metal dielectric layer

340‧‧‧Second metal layer

341, 342, 343, 344, 345‧‧‧ second metal layer

C‧‧‧Central Part

a, b, L‧‧‧ distance

V _bulk ‧‧‧ body voltage

V _S ‧‧‧ source voltage

V _G ‧‧‧ gate voltage

V _B ‧‧‧Starting voltage

V _D ‧‧‧汲polar voltage

Claims (20)

[Item 1] A semiconductor component comprising:
a substrate;
a drift region disposed in the substrate;
An insulating layer disposed on the substrate and covering the drift region, the insulating layer including a first edge and a second edge, the second edge being opposite to the first edge;
a gate layer disposed on the substrate and covering the first edge of the insulating layer; and a metal layer disposed on the substrate and the insulating layer, the metal layer including a metal portion The metal portion is connected to the gate layer and overlaps the first edge of the insulating layer,
Wherein the metal portion includes a first edge, the first edge of the metal portion being closer to a central portion of the insulating layer than a second edge opposite the metal portion,
a distance a from the first edge of the metal portion to the first edge of the insulating layer along a length direction of the channel,
a distance L from the first edge of the insulating layer to the second edge of the insulating layer, and
The a/L ratio is equal to or higher than 0.46. [Item 2] The component of claim 1, wherein the metal portion is a first metal portion, the metal portion being connected to the gate layer and overlapping the first edge of the insulating layer,
The metal layer further includes a second metal portion connectable to receive a boot voltage and overlap the insulating layer.
The second metal portion includes a first edge, the first edge of the second metal portion being tied closer to the central portion of the insulating layer than an opposite second edge of the second metal portion
a distance b from the first edge of the second metal portion to the second edge of the insulating layer along the length of the channel, and
The b/L ratio is equal to or lower than 0.3. [Item 3] The component of claim 2, wherein the metal layer further comprises a third metal portion electrically connected to a drain region disposed in the substrate, and the third metal A portion is connectable to receive a drain voltage different from the turn-on voltage. [Item 4] The element of claim 1, wherein the distance L ranges from 30 microns to 150 microns. [Item 5] The component of claim 1, wherein the metal layer is a first metal layer, and the component further comprises at least one additional metal layer disposed on the substrate and the first metal Between the layers. [Item 6] The element of claim 1, wherein the insulating layer is formed by a field oxide layer. [Item 7] The element of claim 1, wherein the insulating layer is formed in a shallow trench isolation structure. [Item 8] The component of claim 1, wherein the component is a Lateral Drain Metal-Oxide-Semiconductor device (LDMOS device). [Item 9] The component of claim 1, wherein the component is an insulated gate dielectric device (IGBT device). [Item 10] The component of claim 1, wherein the component is a diode. [Item 11] The component of claim 1, wherein the substrate is a P-type semiconductor. [Item 12] The component of claim 1, wherein the substrate is an N-type semiconductor. [Item 13] The element of claim 1, wherein the drift region comprises a plurality of first portions and second portions that are alternately arranged,
Each of the first portions includes a top region and a grade region, the top region having a first conductivity type, the step region having a second conductivity type, and the second portions Each of the sections does not include the top zone and the zone zone. [Item 14] A semiconductor component comprising:
a substrate;
a drift region disposed in the substrate;
An insulating layer disposed on the substrate and covering the drift region, the insulating layer including a first edge and a second edge, the second edge being opposite to the first edge;
a gate layer disposed on the substrate and covering the first edge of the insulating layer; and a metal layer disposed on the substrate and the insulating layer, the metal layer comprising a metal portion, the metal portion Connectable to receive a turn-on voltage and overlap the insulating layer,
Wherein the metal portion includes a first edge, the first edge being located closer to a central portion of the insulating layer than a second edge opposite the metal portion,
a distance a from the first edge of the metal portion to the second edge of the insulating layer along a length direction of the channel,
a distance L from the first edge of the insulating layer to the second edge of the insulating layer, and
The b/L ratio is equal to or lower than 0.3. [Item 15] The component of claim 14, wherein the metal portion is a first metal portion, the metal portion being connectable to receive the startup voltage and overlapping the insulating layer,
The metal layer further includes a second metal portion electrically connected to a drain region disposed in the substrate.
The second metal portion is connected to and receives a drain voltage different from the turn-on voltage, the drain voltage. [Item 16] The element of claim 14, wherein the distance L ranges from 30 microns to 150 microns. [Item 17] The component of claim 14, wherein the metal layer is a first metal layer, and the component further comprises at least one additional metal layer disposed on the substrate and the first metal Between the layers. [Item 18] An integrated circuit comprising:
a substrate comprising a high side operating region, a low side operating region and an ultrahigh voltage metal oxide semiconductor region, the ultrahigh voltage metal oxide semiconductor region being disposed between the high side operating region and the low side operating region;
a drift region disposed in the ultrahigh voltage metal oxide semiconductor region of the substrate;
An insulating layer disposed on the substrate and covering the drift region, the insulating layer including a first edge and a second edge, the second edge being opposite to the first edge;
a gate layer disposed on the substrate and covering the first edge of the insulating layer; and a metal layer disposed on the substrate and the insulating layer, the metal layer comprising a metal portion, the metal portion Connecting to the gate layer and overlapping the first edge of the insulating layer,
Wherein the metal portion includes a first edge, the first edge being located closer to a central portion of the insulating layer than a second edge opposite the metal portion,
a distance a from the first edge of the metal portion to the first edge of the insulating layer along a length direction of the channel,
a distance L from the first edge of the insulating layer to the second edge of the insulating layer, and
The a/L ratio is equal to or higher than 0.46. [Item 19] The integrated circuit of claim 18, wherein the metal portion is a first metal portion connected to the gate layer and overlapping the first side of the insulating layer,
The metal layer further includes a second metal portion connectable to receive a turn-on voltage and overlap the insulating layer.
The second metal portion includes a first edge, the first edge of the second metal portion being tied closer to the central portion of the insulating layer than an opposite second edge of the second metal portion
a distance b from the first edge of the second metal portion to the second edge of the insulating layer along the length of the channel, and
The b/L ratio is equal to or lower than 0.3. [Item 20] The integrated circuit of claim 19, wherein the metal layer further comprises a third metal portion electrically connected to a drain region disposed in the substrate, and the first The tri-metal portion is connectable to receive a drain voltage different from the breakdown voltage.