TW201547215A - Radio frequency transmitting device and radio frequency receiving device - Google Patents

Abstract

A radio frequency transmitting device includes a frequency multiplier circuit, a mixer circuit, a power splitter, a plurality of phase shifting circuits, a plurality of amplifiers, and a plurality of antennas. The frequency multiplier circuit is configured to amplify a fundamental signal to generate a harmonic signal. The mixer circuit is configured to generate a RF signal based on an input signal and the harmonic signal. The power splitter is configured to generate a plurality of sub-RF signals. The phase shifting circuits are configured to shift the phase of the sub-RF signals. The amplifiers are configured to amplify the power of the sub-RF signals. The antennas are configured to transmit the sub-RF signals. Furthermore, a radio frequency receiving device is also disclosed herein.

Description

RF transmission device and radio frequency receiving device

The present invention relates to a wireless communication technology, and more particularly to a radio frequency transmission device and a radio frequency receiving device.

With the advancement of technology, the transmission method between electronic components has gradually changed from a wired transmission method (for example, transmission through a Universal Serial Bus (USB)) to a wireless transmission method. There are many inconveniences in improving the way cable is transmitted.

However, there are still many problems in the wireless transmission mode, such as the linearity of the signal transmitted by the RF transmission device, the AM to AM distortion problem, and the like, in addition, in the variable gain amplifier circuit of the RF transmission device. There are also problems of matching and linearity in the bias tuning or current steering methods.

It can be seen that the above existing methods obviously have inconveniences and defects, and need to be improved. In order to solve the above problems, the related fields are not exhausted. The mind is trying to find a solution, but it has not developed a suitable solution for a long time.

SUMMARY OF THE INVENTION The Summary of the Disclosure is intended to provide a basic understanding of the present disclosure. This Summary is not an extensive overview of the disclosure, and is not intended to be an

One aspect of the present invention relates to a radio frequency transmission device including a frequency multiplying circuit, a mixing circuit, a power distribution circuit, a plurality of phase shift circuits, a plurality of amplifying circuits, and a plurality of antennas. The frequency multiplying circuit is used to amplify the frequency of the fundamental frequency signal to generate a harmonic signal. The mixing circuit is electrically coupled to the frequency multiplying circuit and configured to generate the radio frequency signal according to the input signal and the harmonic signal. The power distribution circuit is electrically coupled to the mixing circuit and configured to generate a plurality of sub-RF signals according to the RF signal. The power distribution circuit includes a first amplifier, a plurality of second amplifiers, and a plurality of third amplifiers. The second amplifier is connected in parallel between the common node and the power source, wherein the common node is electrically coupled to the first amplifier, and the third amplifiers are electrically coupled to the second amplifiers. The phase offset circuits respectively phase shift the sub-radio signals. The amplifying circuits respectively amplify the power of the sub-radio signals, each of the amplifying circuits comprising an input stage, a plurality of fourth amplifiers, a power detector and a voltage clamp, and the input stage is configured to receive the sub-RF signals . The first coupler is electrically coupled to the input stage. The fourth amplifier The first coupler is coupled to the first coupler, wherein the first coupler is configured to couple the power of the partial sub-RF signal to the fourth amplifiers, and the fourth amplifiers are based on the bias voltage to amplify the power of the sub-radio signal. The power detector is electrically coupled to the first coupler, wherein the first coupler is configured to couple the power of the partial sub-RF signal to the power detector, and the power detector is configured to detect the sub-RF signal to output the detection signal. The voltage clamp is electrically coupled to the power detector and configured to control the bias voltage according to the detection signal. The antennas are used to transmit the sub-radio signals.

Another aspect of the present disclosure relates to a radio frequency receiving apparatus including a plurality of antennas, a plurality of variable gain low noise amplifying circuits, a plurality of phase shift circuits, a frequency multiplying circuit, and a mixing circuit. The antennas are configured to receive a plurality of radio frequency signals. The variable gain low noise amplifier circuits are electrically coupled to the antennas for amplifying the RF signals. Each of the variable gain low noise amplifying circuits includes an input stage and a plurality of variable gain amplifiers. The input stage is used to filter out noise of the RF signals. The variable gain amplifiers are connected in series with each other and electrically coupled to the input stage. Each of the variable gain amplifiers includes an amplification unit and a pull down unit. The amplifying unit is configured to amplify the power of the radio frequency signals. The pull-down unit is electrically coupled to the amplifying unit and configured to ground the amplifying unit according to the control signal. The phase shifting circuits are electrically coupled to the variable gain low noise amplifying circuits, and are used for phase shifting the radio frequency signals. The frequency multiplying circuit is used to amplify the frequency of the fundamental frequency signal to generate a harmonic signal. The mixing circuit is electrically coupled to the phase shifting circuit and the frequency multiplying circuit, and is configured to be based on the equalizing The frequency signal and the harmonic signal are used to generate an output signal.

Therefore, according to the technical content of the present invention, an embodiment of the present invention provides a radio frequency transmission device and a radio frequency receiving device, thereby improving linearity problems and AM/AM distortion problems of signals transmitted by the wireless transmission device. In addition, the radio frequency receiving device of the present invention can also improve the problem of matching and linearity in the variable gain amplifying circuit using bias adjustment or current steering.

The basic spirit and other objects of the present invention, as well as the technical means and implementations of the present invention, will be readily apparent to those skilled in the art of the invention.

100‧‧‧RF transmitter

110‧‧‧Multiplier circuit

120‧‧‧mixing circuit

130‧‧‧Power distribution circuit

142, 144, 146, 148‧‧‧ phase offset circuit

152, 154, 156, 158‧‧‧ amplifying circuit

162, 164, 166, 168‧‧ antenna

200‧‧‧RF receiver

212, 214, 216, 218‧‧‧ antenna

222, 224, 226, 228‧‧‧ amplifying circuit

232, 234, 236, 238‧‧‧ phase offset circuit

240‧‧‧mixing circuit

250‧‧‧Multiplier circuit

610‧‧‧Vector Generator

620‧‧‧ phase selector

630‧‧‧Logical Operator

640‧‧‧Digital Analog Converter

650‧‧‧Bar Wheel Converter

660‧‧‧matcher

670‧‧‧Amplifier

710‧‧‧Digital Analog Converter

910‧‧‧Vector Generator

920‧‧‧ phase selector

930‧‧‧ coarse-tuning digital analog converter

940‧‧‧ phase selector

950‧‧‧ fine-tuning digital analog converter

960‧‧‧Logical Encoder

1110‧‧‧Input level

1120‧‧‧Coupling circuit

1130‧‧‧matcher

1140‧‧‧Power Detector

1150‧‧‧matcher

1160‧‧Amplifier

1310‧‧‧Matching circuit

1320‧‧‧Matching circuit

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

2 is a schematic diagram showing a frequency multiplying circuit of the radio frequency transmitting apparatus shown in FIG. 1 according to an embodiment of the invention.

FIG. 3A is a schematic diagram showing experimental data of a frequency multiplying circuit as shown in FIG. 2 according to an embodiment of the invention.

FIG. 3B is a schematic diagram showing experimental data of the frequency multiplying circuit shown in FIG. 2 according to an embodiment of the invention.

4 is a schematic diagram showing a power distribution circuit of the radio frequency transmission device shown in FIG. 1 according to an embodiment of the invention.

FIG. 5A is a schematic diagram showing a gain and phase error of the power distribution circuit shown in FIG. 4 according to an embodiment of the invention.

FIG. 5B is a schematic diagram showing a small signal measurement result of the power distribution circuit shown in FIG. 4 according to an embodiment of the invention.

FIG. 6 is a schematic diagram showing a phase shift circuit of the radio frequency transmitting apparatus shown in FIG. 1 according to an embodiment of the invention.

Figure 7 is a schematic diagram showing an experimental data of a phase shift circuit as shown in Figure 6 in accordance with an embodiment of the present invention.

FIG. 8 is a schematic diagram showing an amplifying circuit of the radio frequency transmitting apparatus shown in FIG. 1 according to an embodiment of the invention.

FIG. 9A is a schematic diagram showing an experimental data of an amplifying circuit as shown in FIG. 8 according to an embodiment of the invention.

FIG. 9B is a schematic diagram showing an experimental data of an amplifying circuit as shown in FIG. 8 according to an embodiment of the invention.

FIG. 9C is a schematic diagram showing an experimental data of an amplifying circuit as shown in FIG. 8 according to an embodiment of the invention.

FIG. 10 is a schematic diagram showing a variable gain low noise amplifying circuit of the radio frequency receiving apparatus shown in FIG. 1 according to an embodiment of the invention.

11A is a schematic diagram showing experimental data of a variable gain low noise amplifying circuit as shown in FIG. 10 according to an embodiment of the invention.

FIG. 11B is a schematic diagram showing experimental data of a variable gain low noise amplifying circuit as shown in FIG. 10 according to an embodiment of the invention.

According to the usual way of operation, the various features and components in the figure are not in accordance with The drawings are drawn to illustrate the specific features and elements associated with the present invention in an optimal manner. In addition, similar elements/components are referred to by the same or similar element symbols throughout the different drawings.

The description of the embodiments of the present invention is intended to be illustrative and not restrictive. The features of various specific embodiments, as well as the method steps and sequences thereof, are constructed and manipulated in the embodiments. However, other specific embodiments may be utilized to achieve the same or equivalent function and sequence of steps.

The scientific and technical terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the invention pertains, unless otherwise defined herein. In addition, the singular noun used in this specification covers the plural of the noun in the case of no conflict with the context; the plural noun of the noun is also included in the plural noun used.

In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components operate or act upon each other.

FIG. 1 is a schematic diagram of a radio frequency transceiver system according to an embodiment of the invention. As shown, the radio frequency transceiver system includes a radio frequency transmitting device 100 and a radio frequency receiving device 200, wherein the radio frequency transmitting device 100 includes multiple times The frequency circuit 110, the mixing circuit 120, the power distribution circuit 130, the plurality of phase shift circuits 142-148, the plurality of amplifier circuits 152-158 and the plurality of antennas 162-168, and the RF receiving device 200 includes a plurality of antennas 212~ 218. A plurality of variable gain low noise amplifying circuits 222-228, a plurality of phase shift circuits 232-238, a mixing circuit 240, and a frequency multiplying circuit 250. In one embodiment, the radio frequency transceiver system shown in FIG. 1 can be used to transmit and receive millimeter waves, whereby the radio frequency transceiver system can be referred to as a millimeter wave phase array transceiver.

Referring to the RF transmission device 100, the frequency multiplying circuit 110 is configured to amplify a frequency of a baseband signal (for example, a local oscillation signal L0) to generate a harmonic signal. The mixing circuit 120 is electrically coupled to the frequency multiplying circuit 110 and configured to generate a radio frequency signal according to an input signal (eg, an intermediate frequency signal IF) and a harmonic signal. The power distribution circuit 130 is electrically coupled to the mixing circuit 120 and configured to generate a plurality of sub-RF signals according to the RF signal. The phase shift circuits 142-148 are electrically coupled to the power distribution circuit 130 and phase-shift the sub-RF signals. The amplifying circuits 152-158 are electrically coupled to the phase shifting circuits 142-148, respectively, and respectively amplify the sub-radio signals to generate a plurality of radio frequency signals. The antennas 162-168 are electrically coupled to the amplifying circuits 152-158, respectively, for transmitting the radio frequency signals.

Please refer to the RF receiving device 200. The antennas 212-218 are configured to receive the RF signals transmitted by the RF transmitting device 100. The variable gain low noise amplifier circuits 222-228 are electrically coupled to the antennas 212-218, respectively, for amplifying the RF signals. Phase shift The shifting circuits 232-238 are electrically coupled to the variable gain low noise amplifying circuits 222-228, respectively, and are respectively used for phase shifting the RF signals. On the other hand, the frequency multiplying circuit 250 is for amplifying the frequency of the fundamental frequency signal (for example, the local oscillation signal L0) to generate a harmonic signal. In addition, the mixing circuit 240 is electrically coupled to the phase shifting circuits 232-238 and the frequency multiplying circuit 250, and is configured to generate an output signal (eg, an intermediate frequency signal IF) according to the radio frequency signals and the harmonic signals.

2 is a schematic diagram showing a frequency multiplying circuit 110, 250 of the radio frequency transmitting device 100 shown in FIG. 1 according to an embodiment of the invention. A 94 GHz frequency multiplier (such as a tripler) in a general RF transmission device must provide a large output amplitude and a wide operating range. To achieve the above number, a common method is to use a capacitor array or a varactor to enhance the frequency doubling. Resonant frequency of the device. However, this practice severely limits the output amplitude of the multiplier.

Therefore, the present invention proposes the frequency multiplying circuits 110, 250 as shown in Fig. 2 to solve the above problems. The frequency multiplying circuits 110, 250 include at least an input stage 111, a differential transistor pair 112, a matcher 113, a converter 114, a resonance stage 115, and an output 116. In implementing the present invention, the frequency multiplying circuits 110, 250 can be a 94 GHz injection-locked tripler.

In this embodiment, the input stage 111 is configured to receive the baseband signal f _o . The differential transistor pair 112 (e.g., M1, M2) and the wideband matcher 113 convert the fundamental frequency signal f _o into a triple frequency signal 3f _o . Furthermore, the converter 114 couples the triple frequency signal 3f _o to the resonance level 115 (eg, cross-coupled pair M3, M4), and the resonance stage 115 amplifies the triple frequency signal 3f _o and outputs the same. The coupling factor k of the converter 114 at a frequency of 94 GHz is about 0.8. In addition, its resonant load further filters out the coupling effect of the fundamental frequency. Here, since the parasitic effect of the differential transistor pair 112 is absorbed by the matcher 113, more third-order overtone 3f _o energy can be supplied to the resonance stage 115. In addition, the converter 114 can be a transformer, and a transformer is used to couple the signals when the first-order and second-order harmonic isolation can be improved.

3A-3B are schematic diagrams showing experimental data of the frequency multiplying circuits 110 and 250 shown in FIG. 2 according to an embodiment of the invention. The frequency multiplying circuits 110 and 250 of the present invention can greatly increase the injection locking range by means of wide frequency matching and coupling by the converter 114. As shown, when the input P _in is 0 dBm, its lock range is about 13 GHz, which is much wider than the frequency multiplier in a general RF transmission device. Further, when the frequency multiplying circuits 110, 250 operate at _{Pout of} about 0 dBm (when P _in is 0 dBm), from 88 GHz to 96 GHz, the attenuation rate is less than 1 dB. Furthermore, the fundamental frequency and the second-order harmonic rejection (rejection) are greater than 35 dB and 25 dB, respectively.

4 is a schematic diagram of a power distribution circuit 130 of the radio frequency transmission device 100 shown in FIG. 1 according to an embodiment of the invention. At 60 GHz, the passive distributor has a larger volume. Further, after being disposed in the passive distributor, the volume of the amplifier for compensating for the signal power is also large, resulting in a large volume of the wafer of the overall power distribution circuit.

Accordingly, the present invention proposes a power distribution circuit 130 as shown in FIG. 4 to solve the above problems. This power distribution circuit 130 is a 1:4 active power distribution circuit of a CMOS architecture. As shown, after input V _in passes through the 50 Ω matcher 131, it is converted to current form by the common source amplifier M1. Furthermore, four equal-divided currents are supplied to the four common-gate amplifiers M2 to M5, and the equal-source currents are compensated by the common source amplifiers A1 to A4 disposed after the common gate amplifiers M2 to M5. Improve its linearity. Based on the low reverse gain characteristic of the common gate amplifiers M2 to M5, the power distribution circuit 130 has a 埠 isolation of 30 dB. As such, the power distribution circuit 130 of the present invention can provide gain for each channel and reduce system power consumption and area.

FIG. 5A is a schematic diagram showing a gain and phase error of the power distribution circuit 130 as shown in FIG. 4 according to an embodiment of the invention. As shown, the maximum deviation of the gain and phase error of the power distribution circuit 130 is only 0.05 dB and 0.2 degrees. FIG. 5B is a schematic diagram showing a small signal measurement result of the power distribution circuit 130 shown in FIG. 4 according to an embodiment of the invention. As shown in the figure, the frequency response of the power distribution circuit 130 between 57 GHz and 67 GHz is measured. The above measurement results are analyzed. It can be seen that the power distribution circuit 130 can provide a gain greater than 5 dB even if the signal is divided into four channels. And a good match. In addition, as can be seen from the figure, the peak gain of the small signal of the power distribution circuit 130 reaches 7.7 dB, and the parameter S ₁₁ and the parameter S ₂₂ are less than -8 dB and -10 dB, respectively.

FIG. 6 is a schematic diagram showing a phase shift circuit 142-148 of the radio frequency transmission device 100 shown in FIG. 1 according to an embodiment of the invention. In general, the phase shift circuits 142-148 can be two-stage phase interpolation phase shifters, and the input signal RF _in first generates two orthogonal sets of differential signals through a vector generator 910, using two groups. The phase selector 920 generates two sets of signals of adjacent phases, and then uses the phase selector 940 to adjust the ratio of the two sets of phases to synthesize the final signal.

In one embodiment, the phase shift circuit is a 7 GHz phase shift circuit of 94 GHz. As shown, vector generator 910 converts RF input RF _in into a differential quadrature signal that is input to phase selector 920 in parallel. The phase selector 920 is controlled by a coarse-tuning digital analog converter (Coarse DAC) 930. The coarse-tuning digital analog converter 930 includes three current sources and three control switches. The current ratio of the three current sources is 2: 5:7, through the control of the coarse-tuning digital analog converter 930, the phase selector 920 can generate 16 phase states with a resolution of 22.5 degrees.

Next, phase selector 940 further processes the output produced by phase selector 920, which is controlled by a fine-tuning digital analog converter (Fine DAC) 950, which includes five current sources. Phase selector 940 is used to synthesize additional 3-bit phase states. In addition, the Logic Encoder 960 is implemented in CMOS. Thus, the logic encoder 960 is capable of 7-bit two-bit encoding to control the remaining components in the phase shift circuits 152-158. By fine-tuning the control of the digital analog converter 950 and the logic encoder 960, the resolution of the output of the phase selector 940 can reach 2.8 degrees.

A phase shift circuit that generally only performs one-stage processing often requires a very high resolution digital analog converter, which increases the complexity of the circuit implementation. Phase offset power of the present invention compared to a general offset circuit Circuits 152-158 are processed in two stages, so that only a low-order resolution digital analog converter can be used to fine-tune the input.

Figure 7 is a diagram showing experimental data of phase shift circuits 152-158 as shown in Figure 6 in accordance with an embodiment of the present invention. As shown in the figure, between 90 and 100 GHz, the phase shift and phase error of the phase shift circuits 152 to 158 are 2.5 degrees and 0.8 dB, respectively. Furthermore, at 94 GHz, the phase and gain errors of the phase shift circuits 152 to 158 are 1.4 degrees and 0.73 dB, respectively.

FIG. 8 is a schematic diagram showing an amplification circuit 152-158 of the radio frequency transmission device 100 shown in FIG. 1 according to an embodiment of the invention. As shown, the input stage 1110 receives and amplifies the RF signal RF _in , and then the coupling circuit 1120 splits the RF signal RF _in into two paths. The coupling circuit 1120 couples part of the RF signal RF _in power (such as 25% of the RF signal RF _in power) to the power detector 1140, and the power detector 1140 detects the RF signal to output the detection signal. In addition, the coupling circuit 1120 couples most of the RF signal RF _in power to the matcher 1150 and performs impedance matching by the matcher 1150 to be transmitted to a plurality of amplifiers 1160, where the plurality of amplifiers 1160 can be three-stage common source. The amplifier uses a three-stage common source amplifier to amplify the RF signal RF _in .

In detail, after the RF signal RF _in is matched via the 50 Ω matcher 1130, the transistor M1 converts the RF signal RF _in power into a current mode, and at the same time, the transistor M2 also generates a current. This current is converted to an appropriate voltage level via transistors M3 to M5 and resistor R1 to generate a detection signal. In addition, if the RF signal RF _{in is} small, the currents of the transistors M1, M2 are small, the power detector 1140 uses its current mirror M3 to copy the current to the transistor M4, and then the power detector 1140 utilizes its resistor R1 and The transistor M5 produces a small voltage V _b . If the RF signal RF _in becomes larger, the current flowing through the current mirror M3 of the power detector 1140 becomes larger, and accordingly, the voltage across the resistor R1 also rises, causing the voltage V _{b to} rise. Thus, when the RF signal RF _{in is} small, the voltage V _b is correspondingly lowered, and therefore, the power consumption is small. The above adaptive biasing mechanism enables the power detector 1140 to achieve optimum efficiency at different input powers.

9A to 9C are diagrams showing an experimental data of the amplifying circuits 152 to 158 shown in Fig. 8 according to an embodiment of the present invention. Referring to FIG. 9A, when the bias voltage Vb of the amplifying circuits 152-158 is higher than a specific voltage (for example, about 0.8 volts (V)), the output power will not grow significantly, however, the DC power will rise significantly. Therefore, the amplifying circuits 152-158 further include a voltage clamping transistor M6 to limit the highest bias voltage Vb to about 0.8 volts (V) according to the detection signal generated by the power detector 1140. The amplifiers 1160 then amplify the power of the radio frequency signal based on the bias voltage Vb. In addition, the amplifying circuits 152-158 further include low-pass filters (for example, 1/gm3 and C1, R2 and C2) to stabilize the power detection state.

In the present embodiment, the amplifier circuit 152 to 158 may dynamically adjust the bias voltage Vb based on the input RF power RF _in, so, due to the bias voltage Vb will increase the gain in the compression section (gain compression region), the amplifier circuit is The output linearity of 152~158 will be improved. In other words, AM/AM distortion can be minimized. In addition, the amplifying circuit of the present invention adopts a feedforward mechanism as compared with an amplifying circuit generally employing feedback control, so that a better power effect can be achieved. Furthermore, the amplifying circuit generally adopts the feedback control needs to output part of the output to the power detector. However, the full analog biasing technique adopted by the amplifying circuit of the present invention does not need to use any data converter or digital bit. Logic circuit. At a bandwidth of 57 to 66 GHz, the amplifying circuits 152 to 158 of the present invention have a gain of 22 dB after consuming 30 mW of the 1 V power supply, the parameter S _{11 is} less than -8 dB and the parameter S _{22 is} less than -11 dB.

Referring to FIG. 9B, it can be seen that the additional power efficiency (PAE) of the amplifying circuits 152-158 of the present invention is maintained at about 12% between P _in of -13 dB and P _in greater than 0 dB. . The additional power efficiency of the amplifying circuits 152-158 of the present invention is significantly improved compared to the existing additional power efficiency of the amplifying circuit using the CMOS architecture of only 4%. In addition, the additional power efficiencies of the amplifying circuits 152-158 of the present invention are 12.1% and 6.5% at OP _1dB (about 9.2dBm) and OP _1dB back-feeding 6dB, respectively. In addition, please refer to FIG. 9C. The curve of No. 1210 is the result of the adaptive biasing technique of the amplifying circuit of the present invention, and the curve of No. 1220 is the result of the adaptive biasing technique of the amplifying circuit of the present invention. As shown, when the amplifying circuit of the present invention employs an adaptive biasing technique, its OP _1dB can be increased by about 1.5 to 3.7 _dB .

FIG. 10 is a schematic diagram showing a variable gain low noise amplifying circuit 222-228 of the radio frequency receiving apparatus 200 shown in FIG. 1 according to an embodiment of the invention. General gain control techniques such as bias adjustment or power Flow manipulation has problems with matching and linearity, respectively. As shown in FIG. 10, the present invention provides a variable gain low noise amplifying circuit 222~228 to solve the above problem. First, the input stage (stage1) is used to filter out the noise of the radio frequency signal, and then, the subsequent serial connection. Variable gain amplifiers (stage2~4) can be used to adjust the gain.

In detail, the input stage includes a matching circuit 1310, a common source transistor M0, and a matching circuit 1320. The matching circuit 1310 is used for impedance matching. The common source transistor M0 generates an output signal according to the input signal and the bias voltage V _b , and the matching circuit 1320 is used for impedance matching with the variable gain amplifier.

In addition, the variable gain amplifiers each include a plurality of transistors, and can provide multi-stage gain control to amplify the power of the input RF signal. For example, when adjusting the gain, the crystal M1 or M2 can be energized according to the control signal to input the RF. Grounding to reduce the gain. Moreover, since these transistors are connected by AC coupling, the bias point and frequency response of the transistor M3 do not change under different stages of gain. In addition, the on-resistance of these transistors is configured such that the controllable gain range of the multi-stage gain control is greater than 23 dB.

Furthermore, since the output P _{1dB of the} variable gain low noise amplifying circuits 222 to 228 is relatively stable, the input P _1dB (IP _1dB ) is increased by at least 11 dB from high gain to low gain. Relatively speaking, current control gain control techniques do not achieve these benefits.

11A-11B are schematic diagrams showing experimental data of variable gain low noise amplifying circuits 222-228 shown in FIG. 10 according to an embodiment of the invention. As shown in Fig. 11A, the multi-stage gain parameter S _{21 is} spread between 23.5 dB and 6 dB, while the parameters S ₁₁ and S ₂₂ are less than -10 dB and -12 dB, respectively. In addition, Figure 11B shows that at 60 GHz, the gain compression measurement is from the highest gain state (indicated by Coded 0) to the lowest state (indicated by Coded 6). As shown, the input P _1dB is improved from -27.8 dBm to -15dBm.

In addition, the phase shift circuits 232-238 of the radio frequency receiving device 200 can be implemented by using the phase shift circuit shown in FIG. 6. For the sake of brevity of the present invention, the phase shift circuit 232 of the radio frequency receiving device 200. For detailed implementation of ~238, please refer to the related description of Figure 6, which will not be described here.

It will be apparent from the above-described embodiments of the present invention that the application of the present invention has the following advantages. The output power and efficiency of the radio frequency transmission device proposed by the invention are high, and the linearity and noise index of the radio frequency receiving device proposed by the invention are effectively improved. Furthermore, the two-stage phase interpolation phase shifter proposed by the present invention can generate a high-resolution phase shift amount, and can increase the resolution of the radiation direction of the overall system antenna.

Although the embodiments of the present invention are disclosed in the above embodiments, the present invention is not intended to limit the invention, and the present invention may be practiced without departing from the spirit and scope of the invention. Various changes and modifications may be made thereto, and the scope of the invention is defined by the scope of the appended claims.

100‧‧‧RF transmitter

110‧‧‧Multiplier circuit

120‧‧‧mixing circuit

130‧‧‧Power distribution circuit

142, 144, 146, 148‧‧‧ phase offset circuit

152, 154, 156, 158‧‧‧ amplifying circuit

162, 164, 166, 168‧‧ antenna

200‧‧‧RF receiver

212, 214, 216, 218‧‧‧ antenna

222, 224, 226, 228‧‧‧ amplifying circuit

232, 234, 236, 238‧‧‧ phase offset circuit

240‧‧‧mixing circuit

250‧‧‧Multiplier circuit

Claims (10)

An RF transmission device includes: a frequency doubling circuit for amplifying a frequency of a fundamental frequency signal to generate a harmonic signal; a mixing circuit electrically coupled to the frequency doubling circuit and configured to The harmonic signal is used to generate a radio frequency signal; a power distribution circuit is electrically coupled to the mixing circuit and configured to generate a plurality of sub-radio signals according to the radio frequency signal, wherein the power distribution circuit comprises: a first amplifier; a plurality of second amplifiers are connected in parallel between a common node and a power source, wherein the common node is electrically coupled to the first amplifier; and a plurality of third amplifiers are electrically coupled to the second amplifiers; a plurality of phase shifting circuits respectively performing phase shifting on the sub-radio signals; and a plurality of amplifying circuits respectively amplifying powers of the sub-radio signals, wherein each of the amplifying circuits comprises: an input stage, Receiving the sub-RF signal; a first coupler electrically coupled to the input stage; a plurality of fourth amplifiers connected in series with each other and electrically coupled To the first coupler, wherein the first coupler is configured Coupling a portion of the power of the sub-radio signal to the fourth amplifier, the fourth amplifier amplifying the power of the sub-radio signal according to a bias voltage; a power detector electrically coupled to the first coupler, The first coupler is configured to couple a portion of the power of the sub-RF signal to the power detector, the power detector is configured to detect the sub-RF signal to output a detection signal; and a voltage clamp, electrical The power detector is coupled to the detection signal to control the bias voltage; and the plurality of antennas are configured to transmit the sub-radio signals. The radio frequency transmitting device of claim 1, wherein each of the amplifying circuits comprises: a first matching device electrically coupled between the first coupler and the power detector; and a first The second matcher is electrically coupled between the first coupler and the fourth amplifiers. The radio frequency transmission device of claim 1, wherein the frequency multiplying circuit is a triple frequency circuit, wherein the triple frequency circuit comprises: an input stage; a differential transistor pair electrically coupled to the input stage a matching device electrically coupled to the differential amplifier; a transformer electrically coupled to the matching device; a cross-transistor pair electrically coupled to the transformer; and an output stage. The radio frequency transmission device of claim 1, wherein the power distribution circuit comprises: a matching device electrically coupled to the first amplifier. The radio frequency transmission device of claim 1, wherein the first amplifier is a common source amplifier, the second amplifiers are common gate amplifiers, and the third amplifiers are common source amplifiers, and the fourth amplifiers are Common source amplifier. The radio frequency transmitting device of claim 1, wherein the phase shifting circuit comprises: a second coupler and at least two bar wheel converters; at least two first phase selectors electrically coupled to the second coupler And the at least two-bar converter; the first digital analog converter is electrically coupled to the first phase selectors; and the second phase selector is electrically coupled to the first phase selectors; a second digital analog converter electrically coupled to the second phase selector; A logic encoder is electrically coupled to the first digital analog converter and the second digital analog converter. A radio frequency receiving device includes: a plurality of antennas for receiving a plurality of radio frequency signals; and a plurality of variable gain low noise amplifying circuits electrically coupled to the antennas for amplifying the radio frequency signals, wherein the Each of the variable gain low noise amplifying circuits includes: an input stage for filtering noise of the RF signals; and a plurality of variable gain amplifiers connected in series and electrically Each of the variable gain amplifiers includes: an amplifying unit for amplifying the power of the radio frequency signals; and a pull-down unit electrically coupled to the amplifying unit and The grounding unit is grounded according to a control signal; and the plurality of phase shifting circuits are respectively electrically coupled to the variable gain low noise amplifying circuits, and are used for phase shifting the radio frequency signals; a frequency multiplying circuit for amplifying a frequency of a fundamental frequency signal to generate a harmonic signal; a mixing circuit electrically coupled to the phase shifting circuit and the frequency multiplying circuit, and for Pilot signal and the harmonic signal to generate an output signal. The radio frequency receiving device of claim 7, wherein the input stage comprises: a first matching unit; a common source amplifier electrically coupled to the first matching unit; and a second matching unit electrically coupled The common source amplifier. The radio frequency receiving device of claim 7, wherein the frequency multiplying circuit is a triple frequency circuit, wherein the triple frequency circuit comprises: an input stage; a differential transistor pair electrically coupled to the input stage a matching device electrically coupled to the differential amplifier; a transformer electrically coupled to the matching device; a cross-transistor pair electrically coupled to the transformer; and an output stage. The radio frequency receiving device of claim 7, wherein the phase shifting circuit comprises: a coupler and at least two bar wheel converters; at least two first phase selectors electrically coupled to the coupler and the at least two a first round digitizer, electrically coupled to the first phase selectors; a second phase selector electrically coupled to the first phase selectors; a second digital analog converter electrically coupled to the second phase selector; and a logic encoder electrically coupled to the second phase selector The first digital analog converter and the second digital analog converter.