TW201546972A - Semiconductor package and method of manufacture - Google Patents

Semiconductor package and method of manufacture Download PDF

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Publication number
TW201546972A
TW201546972A TW103119675A TW103119675A TW201546972A TW 201546972 A TW201546972 A TW 201546972A TW 103119675 A TW103119675 A TW 103119675A TW 103119675 A TW103119675 A TW 103119675A TW 201546972 A TW201546972 A TW 201546972A
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encapsulant
semiconductor package
total weight
weight
electronic component
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TW103119675A
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Chinese (zh)
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TWI552278B (en
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許聰賢
鍾興隆
朱德芳
陳嘉揚
邱志賢
張敬昇
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矽品精密工業股份有限公司
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Priority to CN201410276082.2A priority patent/CN105280570A/en
Publication of TW201546972A publication Critical patent/TW201546972A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

The invention provides a semiconductor package and a method of manufacture thereof, the semiconductor package including a substrate, at least an electronic element and an encapsulant, the electronic element being disposed and electrically connected to the substrate, the encapsulant being formed on the substrate and encapsulating the electronic element, the encapsulant including an exposy resin occupying 5-10% of the total weight of encapsulant; a phenolic occupying 1-5 % of the total weight of the encapsulant; an oxide iron occupying 65-75% of the total weight of the encapsulant; a silica occupying 5-30 % of the total weight of the encapsulant; and a carbon black occupying 0.1-1% of the total weight of the encapsulant, thereby effectively improving on the problem of electromagnetic interference.

Description

半導體封裝件及其製法 Semiconductor package and its manufacturing method

本發明係有關於一種半導體封裝件及其製法，尤指一種具有電磁遮蔽能力的半導體封裝件及其製法。 The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having electromagnetic shielding capability and a method of fabricating the same.

由於電子產業的蓬勃發展，大部份的電子產品均朝向微型化及高速化的目標發展，尤其現今通訊產業的發展已普遍運用整合於各類電子產品，例如行動電話(cell phone)或膝上型電腦(laptop)等等；然而，上述之電子產品均需使用高頻的射頻晶片，且該射頻晶片的位置可能相鄰數位積體電路(digital IC)、數位訊號處理器(Digital Signal Processor，DSP)或基頻(BaseBand，BB)晶片，造成彼此電磁干擾(electromagnetic interference，EMI)的現象，因此，必須進行電磁屏蔽(Electromagnetic Shielding)處理。 Due to the booming electronics industry, most of the electronic products are moving towards miniaturization and high-speed development. Especially in today's communication industry, the development of the communication industry has been widely used in various electronic products, such as cell phones or laps. Laptops, etc.; however, all of the above electronic products require the use of high-frequency RF chips, and the location of the RF chips may be adjacent to digital ICs, digital signal processors (Digital Signal Processors). DSP) or Baseband (BB) wafers cause electromagnetic interference (EMI). Therefore, electromagnetic shielding (Electromagnetic Shielding) must be performed.

第1A與1B圖所示者，分別係習知射頻模組的立體圖與剖視圖。該射頻模組1係將複數半導體元件11a、11b電性連接在一基板10上，再以如環氧樹脂之封裝膠體12包覆各該半導體元件11a、11b及基板10，並於該封裝膠體 12上罩設一金屬薄膜13。該射頻模組1係藉由該封裝膠體12保護該半導體元件11a、11b及基板10，並避免外界水氣或污染物之侵害，且藉由該金屬薄膜13保護該等半導體元件11a、11b免受外界電磁干擾的影響。 The figures 1A and 1B are respectively a perspective view and a cross-sectional view of a conventional RF module. The RF module 1 electrically connects the plurality of semiconductor elements 11a and 11b to a substrate 10, and then encapsulates the semiconductor elements 11a and 11b and the substrate 10 with an encapsulant 12 such as epoxy resin, and the encapsulant is encapsulated. 12 is provided with a metal film 13 on the upper cover. The RF module 1 protects the semiconductor components 11a, 11b and the substrate 10 by the encapsulant 12, and avoids the intrusion of external moisture or contaminants, and protects the semiconductor components 11a, 11b by the metal film 13. Affected by external electromagnetic interference.

第2圖所示者，係另一種習知射頻模組的剖視圖。該射頻模組2係於外圍包覆有屏障(shielding)層23，以避免該射頻模組2與其他模組產生相互電磁干擾。 Figure 2 is a cross-sectional view of another conventional RF module. The RF module 2 is coated with a shielding layer 23 on the periphery to prevent mutual interference between the RF module 2 and other modules.

惟，雖然習知射頻模組1、2可藉由於外圍包覆金屬材以達到避免電磁干擾之目的，然而，該金屬薄膜13或該屏障層23之設置將導致製程時間過長及成本過高之缺點。 However, although the conventional RF modules 1 and 2 can be coated with a metal material to avoid electromagnetic interference, the arrangement of the metal film 13 or the barrier layer 23 will result in excessive processing time and high cost. The shortcomings.

因此，如何避免上述習知技術中之種種問題，實為目前業界所急需解決的課題。 Therefore, how to avoid various problems in the above-mentioned prior art is an urgent problem to be solved in the industry.

有鑒於上述習知技術之缺失，本發明提供一種半導體封裝件，係包括：基板；接置且電性連接於該基板上的至少一電子元件；以及形成於該基板上的封裝膠體，其包覆該電子元件，其中，該封裝膠體係包括：佔該封裝膠體總重5至10重量%之環氧樹脂；佔該封裝膠體總重1至5重量%之酚樹脂；佔該封裝膠體總重65至75重量%之氧化鐵；佔該封裝膠體總重5至30重量%之二氧化矽；以及佔該封裝膠體總重0.1至1重量%之碳黑。 The present invention provides a semiconductor package comprising: a substrate; at least one electronic component connected and electrically connected to the substrate; and an encapsulant formed on the substrate, the package Covering the electronic component, wherein the encapsulant system comprises: epoxy resin accounting for 5 to 10% by weight of the total weight of the encapsulant; phenol resin constituting 1 to 5% by weight of the total weight of the encapsulant; accounting for the total weight of the encapsulant 65 to 75% by weight of iron oxide; cerium oxide in an amount of 5 to 30% by weight based on the total weight of the encapsulating gel; and carbon black in an amount of 0.1 to 1% by weight based on the total weight of the encapsulating colloid.

於前述之半導體封裝件中，該二氧化矽係為非晶形二氧化矽(amorphous silica)，且該電子元件係為主動元件或被動元件。 In the foregoing semiconductor package, the cerium oxide is amorphous a silica, and the electronic component is an active component or a passive component.

於本發明中，該電子元件係為射頻模組，該電子元件係為射頻晶片，且該射頻晶片係為藍牙晶片或Wi-Fi晶片。 In the present invention, the electronic component is a radio frequency module, the electronic component is a radio frequency chip, and the radio frequency chip is a Bluetooth chip or a Wi-Fi chip.

本發明復提供一種半導體封裝件之製法，係包括：基板上接置且電性連接至少一電子元件；以及於該基板上形成包覆該電子元件的封裝膠體，且該封裝膠體係包括：佔該封裝膠體總重5至10重量%之環氧樹脂；佔該封裝膠體總重1至5重量%之酚樹脂；佔該封裝膠體總重65至75重量%之氧化鐵；佔該封裝膠體總重5至30重量%之二氧化矽；以及佔該封裝膠體總重0.1至1重量%之碳黑。 The invention provides a method for fabricating a semiconductor package, comprising: connecting and electrically connecting at least one electronic component on a substrate; and forming an encapsulant covering the electronic component on the substrate, and the encapsulant system comprises: The epoxy resin has a total weight of 5 to 10% by weight of the epoxy resin; the phenol resin accounts for 1 to 5% by weight of the total weight of the encapsulant; and the iron oxide accounts for 65 to 75% by weight of the total weight of the encapsulant; 5 to 30% by weight of cerium oxide; and 0.1 to 1% by weight of carbon black based on the total weight of the encapsulating colloid.

於前述之半導體封裝件之製法中，該二氧化矽係為非晶形二氧化矽(amorphous silica)，且該電子元件係為主動元件或被動元件。 In the above method of fabricating a semiconductor package, the cerium oxide is amorphous amorphous silica, and the electronic component is an active component or a passive component.

本發明之半導體封裝件之製法中，該電子元件係為射頻模組，該電子元件係為射頻晶片，且該射頻晶片係為藍牙晶片或Wi-Fi晶片。 In the method of fabricating the semiconductor package of the present invention, the electronic component is a radio frequency module, the electronic component is a radio frequency chip, and the radio frequency chip is a Bluetooth chip or a Wi-Fi chip.

由上可知，本發明之封裝膠體具有抑制電磁干擾的成分，所以無須再於外表面敷設任何金屬層，進而能縮短製程、提升產品良率、降低製造成本及提高信賴性；此外，該封裝膠體亦具有良好的散熱能力，故無須再處理散熱問題，進而能縮短產品開發時間，並降低成本。 As can be seen from the above, the encapsulant of the present invention has a component for suppressing electromagnetic interference, so that it is no longer necessary to lay any metal layer on the outer surface, thereby shortening the process, improving the product yield, reducing the manufacturing cost, and improving the reliability; further, the encapsulant It also has good heat dissipation capability, so there is no need to deal with heat dissipation problems, which can shorten product development time and reduce costs.

1、2‧‧‧射頻模組 1, 2‧‧‧RF module

10、30‧‧‧基板 10, 30‧‧‧ substrate

11a、11b‧‧‧半導體元件 11a, 11b‧‧‧ semiconductor components

12、32‧‧‧封裝膠體 12, 32‧‧‧Package colloid

13‧‧‧金屬薄膜 13‧‧‧Metal film

23‧‧‧屏障層 23‧‧‧ barrier layer

30a‧‧‧第一表面 30a‧‧‧ first surface

30b‧‧‧第二表面 30b‧‧‧second surface

31‧‧‧電子元件 31‧‧‧Electronic components

第1A與1B圖所示者分別係習知射頻模組的立體圖與剖視圖；第2圖所示者係另一種習知射頻模組的剖視圖；以及 第3A與3B圖所示者係本發明之半導體封裝件之製法的剖視圖。 1A and 1B are respectively a perspective view and a cross-sectional view of a conventional RF module; FIG. 2 is a cross-sectional view of another conventional RF module; 3A and 3B are cross-sectional views showing the method of fabricating the semiconductor package of the present invention.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之用語亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terminology used in the present specification is only for the purpose of illustration, and is not intended to limit the scope of the invention. The change or adjustment of the relative relationship is also considered as The scope of the invention can be implemented.

第3A與3B圖所示者，係本發明之半導體封裝件之製法的剖視圖。 3A and 3B are cross-sectional views showing a method of fabricating the semiconductor package of the present invention.

如第3A圖所示，於一具有相對之第一表面30a及第二表面30b的基板30的該第一表面30a上接置且電性連接至少一電子元件31。 As shown in FIG. 3A, at least one electronic component 31 is electrically connected to the first surface 30a of the substrate 30 having the first surface 30a and the second surface 30b.

於本實施例中，該電子元件31可為主動元件或被動元件，該電子元件31可為射頻模組，該電子元件31可為射頻晶片，且該射頻晶片可為藍牙晶片或Wi-Fi晶片。 In this embodiment, the electronic component 31 can be an active component or a passive component. The electronic component 31 can be a radio frequency module. The electronic component 31 can be a radio frequency chip, and the radio frequency chip can be a Bluetooth chip or a Wi-Fi chip. .

如第3B圖所示，於該基板30之第一表面30a上形成包覆該電子元件31的封裝膠體32，且該封裝膠體32係包括：佔該封裝膠體總重5至10重量%之環氧樹脂(epoxy resin)；佔該封裝膠體總重1至5重量%之酚樹脂(phenol resin)；佔該封裝膠體總重65至75重量%之氧化鐵(Fe2O3)；佔該封裝膠體總重5至30重量%之二氧化矽(silica)；以及佔該封裝膠體總重0.1至1重量%之碳黑(carbon black)。 As shown in FIG. 3B, an encapsulant 32 covering the electronic component 31 is formed on the first surface 30a of the substrate 30, and the encapsulant 32 comprises: a ring of 5 to 10% by weight based on the total weight of the encapsulant. An epoxy resin; a phenol resin in an amount of 1 to 5% by weight based on the total weight of the encapsulant; and an iron oxide (Fe 2 O 3 ) in an amount of 65 to 75% by weight based on the total weight of the encapsulant; The colloid has a total weight of 5 to 30% by weight of silica; and carbon black which is 0.1 to 1% by weight based on the total weight of the encapsulant.

要補充說明的是，該氧化鐵係於燒結後具有高絕緣阻抗、高散熱率及吸收與抑制電磁干擾(EMI)的能力，將研磨成粉狀之該氧化鐵混合至該環氧樹脂中並進行攪拌，以製成該封裝膠體32。 It should be added that the iron oxide has high insulating resistance, high heat dissipation rate, and ability to absorb and suppress electromagnetic interference (EMI) after sintering, and the iron oxide ground into powder is mixed into the epoxy resin. Stirring is performed to form the encapsulant 32.

於本實施例中，該二氧化矽可為非晶形二氧化矽(amorphous silica)。 In this embodiment, the cerium oxide may be amorphous a silica.

本發明復提供一種半導體封裝件，係包括：基板30，係具有相對之第一表面30a及第二表面30b；至少一電子元件31，係接置且電性連接於該基板30之第一表面30a上；以及封裝膠體32，係形成於該基板30之第一表面30a上，且包覆該電子元件31，於該封裝膠體32係包括：佔該封裝膠體總重5至10重量%之環氧樹脂；佔該封裝膠體總重1至5重量%之酚樹脂；佔該封裝膠體總重65至75重量%之氧化鐵；佔該封裝膠體總重5至30重量%之二氧化矽；以及佔該封裝膠體總重0.1至1重量%之碳黑。 The present invention further provides a semiconductor package comprising: a substrate 30 having opposite first and second surfaces 30a, 30b; at least one electronic component 31 electrically connected to the first surface of the substrate 30 The encapsulant 32 is formed on the first surface 30a of the substrate 30 and covers the electronic component 31. The encapsulant 32 comprises: a ring of 5 to 10% by weight based on the total weight of the encapsulant. An oxy-resin; a phenol resin in an amount of from 1 to 5% by weight based on the total weight of the encapsulant; an iron oxide in an amount of from 65 to 75% by weight based on the total weight of the encapsulant; and a cerium oxide in an amount of from 5 to 30% by weight based on the total weight of the encapsulant; The carbon black accounts for 0.1 to 1% by weight of the total weight of the encapsulant.

依上所述之半導體封裝件，該二氧化矽係為非晶形二 氧化矽(amorphous silica)，且該電子元件31係為主動元件或被動元件。 According to the semiconductor package described above, the cerium oxide is amorphous Amorphous silica, and the electronic component 31 is an active component or a passive component.

於本實施例之半導體封裝件中，該電子元件31係為射頻模組，該電子元件31係為射頻晶片，且該射頻晶片係為藍牙晶片或Wi-Fi晶片。 In the semiconductor package of the embodiment, the electronic component 31 is a radio frequency module, the electronic component 31 is a radio frequency chip, and the radio frequency chip is a Bluetooth chip or a Wi-Fi chip.

綜上所述，相較於習知技術，由於本發明之封裝膠體具有抑制電磁干擾(EMI)的成分，所以無須再額外包覆形成金屬材料，進而能縮短製程、提升產品良率、降低製造成本及提高信賴性；此外，該封裝膠體亦具有良好的散熱能力，故無須針對散熱問題再思考對策，以縮短產品開發時間，並降低成本。 In summary, compared with the prior art, since the encapsulant of the present invention has electromagnetic interference suppressing (EMI) components, it is not necessary to additionally form a metal material, thereby shortening the process, improving the yield of the product, and reducing the manufacturing. Cost and reliability; In addition, the encapsulant also has good heat dissipation capability, so there is no need to rethink countermeasures against heat dissipation to shorten product development time and reduce costs.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

30‧‧‧基板 30‧‧‧Substrate

30a‧‧‧第一表面 30a‧‧‧ first surface

30b‧‧‧第二表面 30b‧‧‧second surface

31‧‧‧電子元件 31‧‧‧Electronic components

32‧‧‧封裝膠體 32‧‧‧Package colloid

Claims (12)

一種半導體封裝件，係包括：基板；至少一電子元件，係接置且電性連接於該基板上；以及封裝膠體，係形成於該基板上，且包覆該電子元件，其中，該封裝膠體係包括：佔該封裝膠體總重5至10重量%之環氧樹脂；佔該封裝膠體總重1至5重量%之酚樹脂；佔該封裝膠體總重65至75重量%之氧化鐵；佔該封裝膠體總重5至30重量%之二氧化矽；以及佔該封裝膠體總重0.1至1重量%之碳黑。 A semiconductor package includes: a substrate; at least one electronic component connected to and electrically connected to the substrate; and an encapsulant formed on the substrate and covering the electronic component, wherein the encapsulant The system comprises: an epoxy resin in an amount of 5 to 10% by weight based on the total weight of the encapsulant; a phenol resin in an amount of 1 to 5% by weight based on the total weight of the encapsulant; and an iron oxide in an amount of 65 to 75% by weight based on the total weight of the encapsulant; The encapsulant has a total weight of 5 to 30% by weight of cerium oxide; and 0.1 to 1% by weight of carbon black based on the total weight of the encapsulating colloid. 如申請專利範圍第1項所述之半導體封裝件，其中，該二氧化矽係為非晶形二氧化矽。 The semiconductor package of claim 1, wherein the cerium oxide is amorphous cerium oxide. 如申請專利範圍第1項所述之半導體封裝件，其中，該電子元件係為主動元件或被動元件。 The semiconductor package of claim 1, wherein the electronic component is an active component or a passive component. 如申請專利範圍第1項所述之半導體封裝件，其中，該電子元件係為射頻模組。 The semiconductor package of claim 1, wherein the electronic component is a radio frequency module. 如申請專利範圍第1項所述之半導體封裝件，其中，該電子元件係為射頻晶片。 The semiconductor package of claim 1, wherein the electronic component is a radio frequency chip. 如申請專利範圍第5項所述之半導體封裝件，其中，該射頻晶片係為藍牙晶片或Wi-Fi晶片。 The semiconductor package of claim 5, wherein the radio frequency chip is a Bluetooth chip or a Wi-Fi chip. 一種半導體封裝件之製法，係包括： 於基板上接置且電性連接至少一電子元件；以及於該基板上形成包覆該電子元件的封裝膠體，該封裝膠體係包括：佔該封裝膠體總重5至10重量%之環氧樹脂；佔該封裝膠體總重1至5重量%之酚樹脂；佔該封裝膠體總重65至75重量%之氧化鐵；佔該封裝膠體總重5至30重量%之二氧化矽；以及佔該封裝膠體總重0.1至1重量%之碳黑。 A method of fabricating a semiconductor package, comprising: Attaching and electrically connecting at least one electronic component to the substrate; and forming an encapsulant covering the electronic component on the substrate, the encapsulant system comprising: epoxy resin accounting for 5 to 10% by weight of the total weight of the encapsulant a phenol resin constituting 1 to 5% by weight of the total weight of the encapsulant; an iron oxide constituting 65 to 75% by weight of the total weight of the encapsulant; cerium oxide accounting for 5 to 30% by weight based on the total weight of the encapsulant; The encapsulated colloid has a total weight of carbon black of 0.1 to 1% by weight. 如申請專利範圍第7項所述之半導體封裝件之製法，其中，該二氧化矽係為非晶形二氧化矽。 The method of fabricating a semiconductor package according to claim 7, wherein the cerium oxide is amorphous cerium oxide. 如申請專利範圍第7項所述之半導體封裝件之製法，其中，該電子元件係為主動元件或被動元件。 The method of fabricating a semiconductor package according to claim 7, wherein the electronic component is an active component or a passive component. 如申請專利範圍第7項所述之半導體封裝件之製法，其中，該電子元件係為射頻模組。 The method of fabricating a semiconductor package according to claim 7, wherein the electronic component is a radio frequency module. 如申請專利範圍第7項所述之半導體封裝件之製法，其中，該電子元件係為射頻晶片。 The method of fabricating a semiconductor package according to claim 7, wherein the electronic component is a radio frequency chip. 如申請專利範圍第11項所述之半導體封裝件之製法，其中，該射頻晶片係為藍牙晶片或Wi-Fi晶片。 The method of fabricating a semiconductor package according to claim 11, wherein the radio frequency chip is a Bluetooth chip or a Wi-Fi chip.
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