TWI453836B - Semiconductor package and fabrication method thereof - Google Patents

Semiconductor package and fabrication method thereof Download PDF

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Publication number
TWI453836B
TWI453836B TW100132544A TW100132544A TWI453836B TW I453836 B TWI453836 B TW I453836B TW 100132544 A TW100132544 A TW 100132544A TW 100132544 A TW100132544 A TW 100132544A TW I453836 B TWI453836 B TW I453836B
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Taiwan
Prior art keywords
metal block
semiconductor package
carrier
encapsulant
antenna
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TW100132544A
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Chinese (zh)
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TW201312662A (en
Inventor
邱志賢
蔡宗賢
朱恆正
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矽品精密工業股份有限公司
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Priority to TW100132544A priority Critical patent/TWI453836B/en
Priority to CN201110314733.9A priority patent/CN103000617B/en
Publication of TW201312662A publication Critical patent/TW201312662A/en
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Publication of TWI453836B publication Critical patent/TWI453836B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6661High-frequency adaptations for passive devices
    • H01L2223/6677High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

半導體封裝件及其製法Semiconductor package and its manufacturing method

本發明係有關一種半導體封裝件及其製法,尤指一種具有天線之半導體封裝件及其製法。The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having an antenna and a method of fabricating the same.

具有無線通訊功能,例如藍芽、WiFi或無線區域網路之電子裝置,使得使用者可不受纜線的限制自由地於行動中使用該電子裝置,為使用行為上帶來極大便利。而天線是無線通訊技術的必要元件之一,因此,天線之配置即為一重要的課題。The electronic device with wireless communication function, such as Bluetooth, WiFi or wireless local area network, enables the user to freely use the electronic device in motion without being restricted by the cable, which greatly facilitates the use behavior. The antenna is one of the necessary components of wireless communication technology. Therefore, the configuration of the antenna is an important issue.

請參閱第2圖,係為第7,945,231號美國專利所揭露之具有天線之半導體封裝件。該封裝件具有承載件20;設置於該承載件20上之半導體晶片21;封蓋該半導體晶片21且用於屏蔽電磁波干擾之金屬蓋體22;形成於金屬蓋體22內外,並包覆該半導體晶片21之封裝膠體23;該封裝膠體23中嵌埋有導電元件24;以及形成於該封裝膠體23頂面上並電性連接該導電元件24之天線25。然,是種半導體封裝件之金屬蓋體22埋設於封裝膠體23中,須具備一定剛性,故較耗費成本。再者,由於訊號頻率與天線的面積成反比,天線25形成於封裝膠體23表面上,亦受限於封裝膠體23之尺寸,故此種半導體封裝件具有難以靈活設計天線之問題。Referring to Fig. 2, a semiconductor package having an antenna disclosed in U.S. Patent No. 7,945,231. The package has a carrier 20; a semiconductor wafer 21 disposed on the carrier 20; a metal cover 22 covering the semiconductor wafer 21 for shielding electromagnetic interference; formed inside and outside the metal cover 22, and covering the package The encapsulant 23 of the semiconductor wafer 21; the encapsulation 23 is embedded with a conductive element 24; and an antenna 25 formed on the top surface of the encapsulant 23 and electrically connected to the conductive element 24. However, the metal cover 22 of the semiconductor package is embedded in the encapsulant 23 and has a certain rigidity, so that it is costly. Moreover, since the signal frequency is inversely proportional to the area of the antenna, the antenna 25 is formed on the surface of the encapsulant 23 and is also limited by the size of the encapsulant 23, so that the semiconductor package has a problem that it is difficult to flexibly design the antenna.

因此,如何提供一種半導體封裝件及其製法,並得以靈活調整天線尺寸,便於組裝於終端產品,並降低成本,實為當前急需解決的問題。Therefore, how to provide a semiconductor package and a method for manufacturing the same, and to flexibly adjust the size of the antenna, to facilitate assembly in an end product, and to reduce cost are problems that are urgently needed to be solved.

為克服習知技術之種種缺失,本發明提供一種半導體封裝件,包括:承載件;設置並電性連接於該承載件上之第一金屬塊;設置並電性連接於該承載件上之半導體晶片;形成於該承載件上之封裝膠體,以包覆該第一金屬塊及半導體晶片,並外露出該第一金屬塊頂面;形成於該封裝膠體表面之金屬膜;位於該封裝膠體外之天線,且與該第一金屬塊之間具有間隔;以及電性連接該第一金屬塊與天線之導電元件。In order to overcome the various deficiencies of the prior art, the present invention provides a semiconductor package comprising: a carrier; a first metal block disposed and electrically connected to the carrier; and a semiconductor disposed and electrically connected to the carrier a package body formed on the carrier member to cover the first metal block and the semiconductor wafer, and exposing a top surface of the first metal block; a metal film formed on the surface of the encapsulant; An antenna, and having a space between the first metal block; and electrically connecting the first metal block and the conductive element of the antenna.

本發明復提供一種半導體封裝件之製法,包括:於承載件上形成第一金屬塊及設置半導體晶片,並令該第一金屬塊及半導體晶片電性連接該承載件;於該承載件上形成封裝膠體,以包覆該第一金屬塊及半導體晶片,並外露出該第一金屬塊頂面;於該封裝膠體表面形成金屬膜;以及於該封裝膠體外部藉由導電元件電性連接該第一金屬塊與天線,俾使該天線與第一金屬塊之間具有間隔。The present invention provides a method of fabricating a semiconductor package, comprising: forming a first metal block on a carrier and providing a semiconductor wafer, and electrically connecting the first metal block and the semiconductor wafer to the carrier; forming on the carrier Encapsulating the first metal block and the semiconductor wafer to expose the top surface of the first metal block; forming a metal film on the surface of the encapsulant; and electrically connecting the outer portion of the encapsulant by a conductive element A metal block and an antenna have a spacing between the antenna and the first metal block.

前述之半導體封裝件及其製法中,該導電元件為探針式連接器或導電膠。此外,該天線係可設於一外殼內側,且該外殼具有容置空間,以供遮蓋住該封裝膠體。In the foregoing semiconductor package and method of manufacturing the same, the conductive element is a probe connector or a conductive paste. In addition, the antenna can be disposed inside a casing, and the casing has a receiving space for covering the encapsulant.

由上可知,本發明使天線設於封裝膠體外部並藉由導電元件電性連接嵌埋於封裝膠體中的第一金屬塊,使得天線可不局限在封裝膠體中,而可作靈活設計,例如可調整天線尺寸,再者,用以屏蔽電磁波干擾的金屬膜係透過鍍覆技術形成者,可大幅降低成本。As can be seen from the above, the antenna is disposed on the outside of the encapsulant and electrically connected to the first metal block embedded in the encapsulant by the conductive component, so that the antenna can be flexibly designed without being limited to the encapsulant, for example, By adjusting the size of the antenna, the metal film used to shield electromagnetic interference is formed by the plating technique, which can greatly reduce the cost.

以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“內”、“一”及“頂面”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "inside", "one" and "top" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments to the relative relationship are considered to be within the scope of the invention without departing from the scope of the invention.

請參閱第1A至1D圖,係為本發明半導體封裝件製法之剖面示意圖。Please refer to FIGS. 1A to 1D, which are schematic cross-sectional views showing the manufacturing method of the semiconductor package of the present invention.

如第1A及1B圖所示,提供一承載件10,接著,於該承載件10上形成複數金屬塊11及設置半導體晶片12,並令該金屬塊11及半導體晶片12電性連接該承載件10,其中,形成金屬塊11及設置半導體晶片12時並無特別的優先順序,且該金屬塊11可透過如電鍍的鍍覆技術形成或可直接植設金屬塊11。此外,該半導體晶片12係可為無線通訊晶片,又,該半導體晶片12係可以打線方式或覆晶方式電性連接該承載件10。再者,如第1B圖所示,於進行封膠步驟前,復可包括設置並電性連接被動元件13於該承載件10上,當然,並不限定設置被動元件13之順序。As shown in FIGS. 1A and 1B, a carrier 10 is provided. Then, a plurality of metal blocks 11 and a semiconductor wafer 12 are formed on the carrier 10, and the metal block 11 and the semiconductor wafer 12 are electrically connected to the carrier. 10, wherein the metal block 11 and the semiconductor wafer 12 are not particularly prioritized, and the metal block 11 can be formed by a plating technique such as electroplating or the metal block 11 can be directly implanted. In addition, the semiconductor wafer 12 can be a wireless communication chip, and the semiconductor wafer 12 can be electrically connected to the carrier 10 by wire bonding or flip chip. Furthermore, as shown in FIG. 1B, before the sealing step, the complex includes the provision and electrical connection of the passive component 13 on the carrier 10. Of course, the order in which the passive component 13 is disposed is not limited.

如第1C圖所示,係接續第1B圖,於該承載件10上形成封裝膠體14,以包覆該金屬塊11、半導體晶片12及被動元件13,並外露出該金屬塊11頂面,再於該封裝膠體14表面透過鍍覆技術形成金屬膜15。此外,本發明之該複數金屬塊11包括第一金屬塊11a及第二金屬塊11b,該第一金屬塊11a係電性連接後續形成或設置之導電元件並與該金屬膜15電性隔離,且該第二金屬塊11b係與該金屬膜15電性連接,使金屬膜15得經由第二金屬塊11b連接至承載件10之接地線路。於其他實施例中,金屬膜15可直接連接承載件10之接地線路。As shown in FIG. 1C, the first package is connected to form a package colloid 14 on the carrier 10 to cover the metal block 11, the semiconductor wafer 12 and the passive component 13 and expose the top surface of the metal block 11. The metal film 15 is formed by a plating technique on the surface of the encapsulant 14 . In addition, the plurality of metal blocks 11 of the present invention includes a first metal block 11a and a second metal block 11b. The first metal block 11a is electrically connected to and electrically isolated from the conductive element formed or disposed. The second metal block 11b is electrically connected to the metal film 15, so that the metal film 15 is connected to the ground line of the carrier 10 via the second metal block 11b. In other embodiments, the metal film 15 can be directly connected to the ground line of the carrier 10.

如第1D圖所示,於該封裝膠體14外部藉由導電元件16電性連接該第一金屬塊11a與天線17,俾使該天線17與第一金屬塊11a之間具有間隔,其中,該導電元件為探針式連接器。此外,復可包括將外殼18遮蓋住該封裝膠體14,例如該外殼18覆蓋於終端產品之電路板19上。該外殼18的容置空間係大於該封裝膠體14,以收納其中並留有間隔。As shown in FIG. 1D, the first metal block 11a and the antenna 17 are electrically connected to the outside of the encapsulant 14 by a conductive member 16, so that the antenna 17 and the first metal block 11a are spaced apart. The conductive element is a probe connector. Additionally, the complex includes covering the encapsulant 14 with the outer casing 18, for example, the outer casing 18 overlying the circuit board 19 of the end product. The housing 18 has a larger accommodation space than the encapsulant 14 for receiving therein and leaving a space therebetween.

於本實施例中,該天線17係先設於外殼18內側,藉由將該外殼18遮蓋住該封裝膠體14時,該導電元件16將該天線17電性連接第一金屬塊11a,在此態樣中,該導電元件16以探針式連接器為佳。又,該探針式連接器的一端可連接在天線17或第一金屬塊11a上,在外殼18遮蓋住該封裝膠體14時,即可令探針式連接器與第一金屬塊11a接觸或與天線17接觸。In this embodiment, the antenna 17 is first disposed on the inner side of the outer casing 18. When the outer casing 18 covers the encapsulant 14, the conductive element 16 electrically connects the antenna 17 to the first metal block 11a. In the aspect, the conductive element 16 is preferably a probe type connector. Moreover, one end of the probe connector can be connected to the antenna 17 or the first metal block 11a. When the outer casing 18 covers the encapsulant 14, the probe connector can be in contact with the first metal block 11a or It is in contact with the antenna 17.

於另一實施例中,如第1D’圖所示,該天線17可藉由形成於該封裝膠體14外部的導電膠16’電性連接該第一金屬塊11a’並由例如環氧樹脂之黏膠14’固定該半導體封裝件,而該承載件10與電路板19之間則藉由探針式連接器16a提供電性連接。In another embodiment, as shown in FIG. 1D', the antenna 17 can be electrically connected to the first metal block 11a' by a conductive adhesive 16' formed on the outside of the encapsulant 14 and made of, for example, epoxy resin. The adhesive 14' secures the semiconductor package, and the carrier 10 and the circuit board 19 are electrically connected by the probe connector 16a.

據此,根據上述製法形成如第1D圖所示之半導體封裝件結構。本發明之半導體封裝件包括:承載件10;第一金屬塊11a,係設置並電性連接於該承載件10上;半導體晶片12,係設置並電性連接於該承載件10上;封裝膠體14,係形成於該承載件10上,以包覆該第一金屬塊11a及半導體晶片12,並外露出該第一金屬塊11a頂面;金屬膜15,係形成於該封裝膠體14表面;天線17,係位於該封裝膠體14外,且與該第一金屬塊11a之間具有間隔;以及導電元件16,係電性連接該第一金屬塊11a與天線17。According to this, the semiconductor package structure as shown in Fig. 1D is formed in accordance with the above-described manufacturing method. The semiconductor package of the present invention comprises: a carrier 10; a first metal block 11a is disposed and electrically connected to the carrier 10; a semiconductor wafer 12 is disposed and electrically connected to the carrier 10; 14 is formed on the carrier 10 to cover the first metal block 11a and the semiconductor wafer 12, and expose the top surface of the first metal block 11a; the metal film 15 is formed on the surface of the encapsulant 14; The antenna 17 is located outside the encapsulant 14 and spaced apart from the first metal block 11a. The conductive element 16 is electrically connected to the first metal block 11a and the antenna 17.

於前述之半導體封裝件中,該半導體晶片12係以打線方式或覆晶方式電性連接該承載件10。該半導體晶片12可為無線通訊晶片。又,本發明之半導體封裝件復可包括被動元件13,係設置並電性連接於該承載件10上。In the foregoing semiconductor package, the semiconductor wafer 12 is electrically connected to the carrier 10 by wire bonding or flip chip. The semiconductor wafer 12 can be a wireless communication chip. Moreover, the semiconductor package of the present invention may include a passive component 13 disposed on and electrically connected to the carrier 10.

所述之該導電元件16為探針式連接器或導電膠。The conductive element 16 is a probe connector or a conductive paste.

所述半導體封裝件復可包括外殼18,係具有容置空間,以供遮蓋該封裝膠體14,且該天線17係設於該外殼18內側。The semiconductor package may include a housing 18 having an accommodating space for covering the encapsulant 14 , and the antenna 17 is disposed inside the housing 18 .

前述之該第一金屬塊11a係電性連接該導電元件16並與該金屬膜15電性隔離。此外,復可包括第二金屬塊11b,且該第二金屬塊11b係與該金屬膜15電性連接。The first metal block 11a is electrically connected to the conductive element 16 and electrically isolated from the metal film 15. In addition, the second metal block 11b is electrically connected to the metal film 15 .

綜上所述,本發明使天線設於封裝膠體外部並藉由導電元件電性連接嵌埋於封裝膠體中的金屬塊,使得天線可不局限在封裝膠體中,而可作靈活設計,例如可調整天線尺寸,再者,用以屏蔽電磁波干擾的金屬膜係透過鍍覆技術形成者,可大幅降低成本。此外,本發明利用探針式連接器作電性連接,更具有便於組設半導體封裝件至終端產品之電路板上的優點。In summary, the present invention allows the antenna to be disposed outside the encapsulant and electrically connected to the metal block embedded in the encapsulant by the conductive component, so that the antenna can be flexibly designed, for example, can be adjusted. The antenna size, in addition, the metal film used to shield electromagnetic interference is formed by the plating technology, which can greatly reduce the cost. In addition, the present invention utilizes a probe type connector for electrical connection, and has the advantage of facilitating the assembly of the semiconductor package to the end product.

上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10、20...承載件10, 20. . . Carrier

11...金屬塊11. . . Metal block

11a...第一金屬塊11a. . . First metal block

11b...第二金屬塊11b. . . Second metal block

12...半導體晶片12. . . Semiconductor wafer

13...被動元件13. . . Passive component

14...封裝膠體14. . . Encapsulant

14’...黏膠14’. . . Viscose

15...金屬膜15. . . Metal film

16...導電元件16. . . Conductive component

16’...導電膠16’. . . Conductive plastic

16a...探針式連接器16a. . . Probe connector

17...天線17. . . antenna

18...外殼18. . . shell

19...電路板19. . . Circuit board

21...半導體晶片twenty one. . . Semiconductor wafer

22...金屬蓋體twenty two. . . Metal cover

23...封裝膠體twenty three. . . Encapsulant

24...導電元件twenty four. . . Conductive component

25...天線25. . . antenna

第1A至1D圖係為本發明半導體封裝件製法之剖面示意圖,其中,第1D’圖係顯示本發明半導體封裝件電性連接電路板的另一態樣的示意圖;以及1A to 1D are schematic cross-sectional views showing a method of fabricating a semiconductor package of the present invention, wherein the 1D' is a schematic view showing another aspect of the electrical connection circuit board of the semiconductor package of the present invention;

第2圖係為習知半導體封裝件之剖面示意圖。Figure 2 is a schematic cross-sectional view of a conventional semiconductor package.

10...承載件10. . . Carrier

11a...第一金屬塊11a. . . First metal block

11b...第二金屬塊11b. . . Second metal block

12...半導體晶片12. . . Semiconductor wafer

13...被動元件13. . . Passive component

14...封裝膠體14. . . Encapsulant

15...金屬膜15. . . Metal film

16...導電元件16. . . Conductive component

17...天線17. . . antenna

18...外殼18. . . shell

19...電路板19. . . Circuit board

Claims (18)

一種半導體封裝件,包括:承載件;第一金屬塊,係設置並電性連接於該承載件上;半導體晶片,係設置並電性連接於該承載件上;封裝膠體,係形成於該承載件上,以包覆該第一金屬塊及半導體晶片,並外露出該第一金屬塊頂面;金屬膜,係形成於該封裝膠體表面;天線,係位於該封裝膠體外並與該封裝膠體之間具有間隔,且與該第一金屬塊之間具有間隔;以及導電元件,係電性連接該第一金屬塊與天線。 A semiconductor package includes: a carrier; a first metal block disposed and electrically connected to the carrier; a semiconductor wafer disposed and electrically connected to the carrier; and an encapsulant formed on the carrier And covering the first metal block and the semiconductor wafer, and exposing the top surface of the first metal block; the metal film is formed on the surface of the encapsulant; the antenna is located outside the encapsulant and the encapsulant There is a space between them and a space between the first metal block; and a conductive element electrically connecting the first metal block and the antenna. 如申請專利範圍第1項所述之半導體封裝件,其中,該半導體晶片為無線通訊晶片。 The semiconductor package of claim 1, wherein the semiconductor wafer is a wireless communication chip. 如申請專利範圍第1項所述之半導體封裝件,復包括被動元件,係設置並電性連接於該承載件上。 The semiconductor package of claim 1, further comprising a passive component disposed and electrically connected to the carrier. 如申請專利範圍第1項所述之半導體封裝件,其中,該導電元件為探針式連接器或導電膠。 The semiconductor package of claim 1, wherein the conductive element is a probe connector or a conductive paste. 如申請專利範圍第1項所述之半導體封裝件,復包括外殼,係具有容置空間,以供遮蓋該封裝膠體,且該天線係設於該外殼內側。 The semiconductor package of claim 1, further comprising an outer casing having an accommodating space for covering the encapsulant, and the antenna is disposed inside the outer casing. 如申請專利範圍第1項所述之半導體封裝件,復包括第二金屬塊,係設置並電性連接於該承載件上,並與該金屬膜電性連接。 The semiconductor package of claim 1, further comprising a second metal block disposed and electrically connected to the carrier and electrically connected to the metal film. 如申請專利範圍第1項所述之半導體封裝件,其中,該 第一金屬塊係電性連接該導電元件並與該金屬膜電性隔離。 The semiconductor package of claim 1, wherein the The first metal block is electrically connected to the conductive element and electrically isolated from the metal film. 如申請專利範圍第1項所述之半導體封裝件,復包括電路板以及電性連接該承載件與電路板之探針式連接器。 The semiconductor package of claim 1, further comprising a circuit board and a probe connector electrically connecting the carrier and the circuit board. 一種半導體封裝件之製法,包括:於承載件上形成第一金屬塊及設置半導體晶片,並令該第一金屬塊及半導體晶片電性連接該承載件;於該承載件上形成封裝膠體,以包覆該第一金屬塊及半導體晶片,並外露出該第一金屬塊頂面;於該封裝膠體表面形成金屬膜;以及於該封裝膠體外部藉由導電元件電性連接該第一金屬塊與天線,俾使該天線與第一金屬塊之間具有間隔,該天線並與該封裝膠體之間具有間隔。 A method of manufacturing a semiconductor package, comprising: forming a first metal block on a carrier and providing a semiconductor wafer, and electrically connecting the first metal block and the semiconductor chip to the carrier; forming an encapsulant on the carrier Coating the first metal block and the semiconductor wafer, and exposing the top surface of the first metal block; forming a metal film on the surface of the encapsulant; and electrically connecting the first metal block to the outside of the encapsulant by a conductive element The antenna has a spacing between the antenna and the first metal block, and the antenna is spaced apart from the encapsulant. 如申請專利範圍第9項所述之半導體封裝件之製法,其中,該半導體晶片為無線通訊晶片。 The method of fabricating a semiconductor package according to claim 9, wherein the semiconductor wafer is a wireless communication chip. 如申請專利範圍第9項所述之半導體封裝件之製法,形成該封裝膠體前,復包括設置並電性連接被動元件於該承載件上。 The method for manufacturing a semiconductor package according to claim 9, wherein before forming the encapsulant, the passive component is disposed and electrically connected to the carrier. 如申請專利範圍第9項所述之半導體封裝件之製法,其中,該導電元件為探針式連接器或導電膠。 The method of fabricating a semiconductor package according to claim 9, wherein the conductive element is a probe connector or a conductive paste. 如申請專利範圍第9項所述之半導體封裝件之製法,其中,該天線係設於一外殼內側,且該外殼具有容置空間,以供遮蓋住該封裝膠體。 The method of manufacturing a semiconductor package according to claim 9, wherein the antenna is disposed inside a casing, and the casing has an accommodating space for covering the encapsulant. 如申請專利範圍第9項所述之半導體封裝件之製法,係 以電鍍或植接的方式形成該第一金屬塊。 The method for manufacturing a semiconductor package as described in claim 9 The first metal block is formed by electroplating or grafting. 如申請專利範圍第9項所述之半導體封裝件之製法,復包括於形成封裝膠體前,於該承載件上形成第二金屬塊,並令該第二金屬塊電性連接該承載件,且該第二金屬塊係與該金屬膜電性連接。 The method for manufacturing a semiconductor package according to claim 9 is characterized in that before the forming of the encapsulant, a second metal block is formed on the carrier, and the second metal block is electrically connected to the carrier, and The second metal block is electrically connected to the metal film. 如申請專利範圍第9項所述之半導體封裝件之製法,其中,該第一金屬塊係電性連接該導電元件並與該金屬膜電性隔離。 The method of fabricating a semiconductor package according to claim 9, wherein the first metal block is electrically connected to the conductive element and electrically isolated from the metal film. 如申請專利範圍第9項所述之半導體封裝件之製法,其中,係以鍍覆技術形成該金屬膜。 The method of fabricating a semiconductor package according to claim 9, wherein the metal film is formed by a plating technique. 如申請專利範圍第9項所述之半導體封裝件之製法,復包括以探針式連接器電性連接該承載件與電路板。 The method of fabricating a semiconductor package according to claim 9 further comprises electrically connecting the carrier and the circuit board with a probe connector.
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