CN105280570A - Semiconductor package and fabrication method thereof - Google Patents

Semiconductor package and fabrication method thereof Download PDF

Info

Publication number
CN105280570A
CN105280570A CN201410276082.2A CN201410276082A CN105280570A CN 105280570 A CN105280570 A CN 105280570A CN 201410276082 A CN201410276082 A CN 201410276082A CN 105280570 A CN105280570 A CN 105280570A
Authority
CN
China
Prior art keywords
weight
packing colloid
semiconductor package
electronic component
account
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410276082.2A
Other languages
Chinese (zh)
Inventor
许聪贤
钟兴隆
朱德芳
陈嘉扬
邱志贤
张敬昇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN105280570A publication Critical patent/CN105280570A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package and a method for fabricating the same, the semiconductor package includes a substrate, at least one electronic device and a molding compound, the electronic device is disposed on and electrically connected to the substrate, the molding compound is formed on the substrate and covers the electronic device, and the molding compound includes: 5 to 10 weight percent of epoxy resin based on the total weight of the packaging colloid; a phenol resin in an amount of 1 to 5 wt% based on the total weight of the encapsulant; iron oxide in an amount of 65 to 75 wt% based on the total weight of the encapsulant; silicon dioxide accounting for 5 to 30 weight percent of the total weight of the packaging colloid; and carbon black accounting for 0.1 to 1 weight percent of the total weight of the encapsulation colloid, thereby effectively improving the electromagnetic interference problem.

Description

Semiconductor package part and method for making thereof
Technical field
The present invention relates to a kind of semiconductor package part and method for making thereof, espespecially a kind of semiconductor package part and method for making thereof with ELECTROMAGNETIC OBSCURANT ability.
Background technology
Flourish due to electronic industry, most electronic product is all towards target development that is microminiaturized and high speed, especially the development of communication industry now is generally used and is integrated in each electronic product, such as mobile phone (cellphone) or kneetop computer (laptop) etc.; But, above-mentioned electronic product all needs the RF chip using high frequency, and the position of this RF chip may adjacent digital integrated circuit (digitalIC), digital signal processor (DigitalSignalProcessor, or base band (BaseBand DSP), BB) wafer, cause electromagnetic interference (electromagneticinterference each other, EMI) phenomenon, therefore, electromagnetic shielding (ElectromagneticShielding) process must be carried out.
Figure 1A and Figure 1B those shown, is respectively stereogram and the cutaway view of existing radio frequency module.This radio frequency module 1, for multiple semiconductor element 11a, 11b are electrically connected at a substrate 10, then with coated respectively this semiconductor element 11a, 11b of packing colloid 12 of such as epoxy resin and substrate 10, and establishes a metallic film 13 in this packing colloid 12 upper cover.This radio frequency module 1 protects this semiconductor element 11a, 11b and substrate 10 by this packing colloid 12, and avoids the infringement of extraneous aqueous vapor or pollutant, and protects these semiconductor elements 11a, 11b from the impact of outside electromagnetic interference by this metallic film 13.
That shown in Figure 2 is the cutaway view of the existing radio frequency module of another kind.This radio frequency module 2 is coated with barrier (shielding) layer 23 in periphery, produce mutual electromagnetic disturb to avoid this radio frequency module 2 with other modules.
Although existing radio frequency module 1,2 can by peripheral clad metal material to reach the object avoiding electromagnetic interference, but, the shortcoming arranged causing the long and high cost of processing time of this metallic film 13 or this barrier layer 23.
Therefore, how to avoid above-mentioned variety of problems of the prior art, real be badly in need of by current industry the problem of solution.
Summary of the invention
Because the disappearance of above-mentioned prior art, object of the present invention for providing a kind of semiconductor package part and method for making thereof, effectively to improve electromagnetic interference problem.
Semiconductor package part of the present invention comprises: substrate; Connect and put and at least one electronic component be electrically connected on this substrate; And the packing colloid be formed on this substrate, its this electronic component coated, wherein, this packing colloid comprises: the epoxy resin accounting for this packing colloid gross weight 5 to 10 % by weight; Account for the phenol resin of this packing colloid gross weight 1 to 5 % by weight; Account for the iron oxide of this packing colloid gross weight 65 to 75 % by weight; Account for the silicon dioxide of this packing colloid gross weight 5 to 30 % by weight; And account for the carbon black of this packing colloid gross weight 0.1 to 1 % by weight.
In aforesaid semiconductor package part, this silicon dioxide is amorphous silicas (amorphoussilica), and this electronic component is active member or passive device.
In the present invention, this electronic component is radio frequency module, and this electronic component is RF chip, and this RF chip is bluetooth wafer or Wi-Fi wafer.
The present invention also provides a kind of method for making of semiconductor package part, comprising: substrate connects and puts and be electrically connected at least one electronic component; And on this substrate, form the packing colloid of this electronic component coated, and this packing colloid comprises: the epoxy resin accounting for this packing colloid gross weight 5 to 10 % by weight; Account for the phenol resin of this packing colloid gross weight 1 to 5 % by weight; Account for the iron oxide of this packing colloid gross weight 65 to 75 % by weight; Account for the silicon dioxide of this packing colloid gross weight 5 to 30 % by weight; And account for the carbon black of this packing colloid gross weight 0.1 to 1 % by weight.
In the method for making of aforesaid semiconductor package part, this silicon dioxide is amorphous silicas (amorphoussilica), and this electronic component is active member or passive device.
In the method for making of semiconductor package part of the present invention, this electronic component is radio frequency module, and this electronic component is RF chip, and this RF chip is bluetooth wafer or Wi-Fi wafer.
As from the foregoing, packing colloid of the present invention has the composition suppressing electromagnetic interference, so need not lay any metal level in outer surface again, and then can shorten processing procedure, improving product yield, reduction manufacturing cost and improve reliability; In addition, this packing colloid also has good heat-sinking capability, therefore need not reprocessing heat dissipation problem, and then can shorten time of product development, and reduces costs.
Accompanying drawing explanation
Figure 1A and Figure 1B those shown is respectively stereogram and the cutaway view of existing radio frequency module.
That shown in Figure 2 is the cutaway view of another kind of existing radio frequency module.
Fig. 3 A and Fig. 3 B those shown are the cutaway view of the method for making of semiconductor package part of the present invention.
Symbol description
1,2 radio frequency modules
10,30 substrates
11a, 11b semiconductor element
12,32 packing colloids
13 metallic films
23 barrier layers
30a first surface
30b second surface
31 electronic components.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only for coordinating specification to disclose, for understanding and the reading of those skilled in the art, be not intended to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.Meanwhile, the term quoted in this specification is also only understanding, but not for limiting the enforceable scope of the present invention, the change of its relativeness or adjustment, without under essence change technology contents, when being also considered as the enforceable category of the present invention of being convenient to describe.
Fig. 3 A and Fig. 3 B those shown are the cutaway view of the method for making of semiconductor package part of the present invention.
As shown in Figure 3A, connect on this first surface 30a with the substrate 30 of relative first surface 30a and second surface 30b and put and be electrically connected at least one electronic component 31.
In the present embodiment, this electronic component 31 can be active member or passive device, and this electronic component 31 can be radio frequency module, and this electronic component 31 can be RF chip, and this RF chip can be bluetooth wafer or Wi-Fi wafer.
As shown in Figure 3 B, on the first surface 30a of this substrate 30, form the packing colloid 32 of this electronic component 31 coated, and this packing colloid 32 comprises: the epoxy resin (epoxyresin) accounting for this packing colloid gross weight 5 to 10 % by weight; Account for the phenol resin (phenolresin) of this packing colloid gross weight 1 to 5 % by weight; Account for the iron oxide (Fe of this packing colloid gross weight 65 to 75 % by weight 2o 3); Account for the silicon dioxide (silica) of this packing colloid gross weight 5 to 30 % by weight; And account for the carbon black (carbonblack) of this packing colloid gross weight 0.1 to 1 % by weight.
What remark additionally is, this iron oxide has high insulation resistance, high rate of heat dissipation and absorbs and suppress the ability of electromagnetic interference (EMI) after sintering, this iron oxide grinding to form powdery to be mixed in this epoxy resin and to stir, to make this packing colloid 32.
In the present embodiment, this silicon dioxide can be amorphous silicas (amorphoussilica).
The present invention also provides a kind of semiconductor package part, comprising: substrate 30, and it has relative first surface 30a and second surface 30b; At least one electronic component 31, it connects puts and is electrically connected on the first surface 30a of this substrate 30; And packing colloid 32, it is formed on the first surface 30a of this substrate 30, and this electronic component 31 coated, comprise in this packing colloid 32: the epoxy resin accounting for this packing colloid gross weight 5 to 10 % by weight; Account for the phenol resin of this packing colloid gross weight 1 to 5 % by weight; Account for the iron oxide of this packing colloid gross weight 65 to 75 % by weight; Account for the silicon dioxide of this packing colloid gross weight 5 to 30 % by weight; And account for the carbon black of this packing colloid gross weight 0.1 to 1 % by weight.
According to upper described semiconductor package part, this silicon dioxide is amorphous silicas (amorphoussilica), and this electronic component 31 is active member or passive device.
In the semiconductor package part of the present embodiment, this electronic component 31 is radio frequency module, and this electronic component 31 is RF chip, and this RF chip is bluetooth wafer or Wi-Fi wafer.
In sum, compared to prior art, because packing colloid of the present invention has the composition of suppression electromagnetic interference (EMI), so need not extra coated formation metal material again, and then processing procedure, improving product yield can be shortened, reduce manufacturing cost and improve reliability; In addition, this packing colloid also has good heat-sinking capability, therefore need not think deeply countermeasure again for heat dissipation problem, to shorten time of product development, and reduces costs.
Above-described embodiment only for illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can modify to above-described embodiment.Therefore the scope of the present invention, should listed by claims.

Claims (12)

1. a semiconductor package part, comprising:
Substrate;
At least one electronic component, it connects puts and is electrically connected on this substrate; And
Packing colloid, it is formed on this substrate, and this electronic component coated, wherein, this packing colloid comprises:
Account for the epoxy resin of this packing colloid gross weight 5 to 10 % by weight;
Account for the phenol resin of this packing colloid gross weight 1 to 5 % by weight;
Account for the iron oxide of this packing colloid gross weight 65 to 75 % by weight;
Account for the silicon dioxide of this packing colloid gross weight 5 to 30 % by weight; And
Account for the carbon black of this packing colloid gross weight 0.1 to 1 % by weight.
2. semiconductor package part as claimed in claim 1, it is characterized in that, this silicon dioxide is amorphous silicas.
3. semiconductor package part as claimed in claim 1, it is characterized in that, this electronic component is active member or passive device.
4. semiconductor package part as claimed in claim 1, it is characterized in that, this electronic component is radio frequency module.
5. semiconductor package part as claimed in claim 1, it is characterized in that, this electronic component is RF chip.
6. semiconductor package part as claimed in claim 5, it is characterized in that, this RF chip is bluetooth wafer or Wi-Fi wafer.
7. a method for making for semiconductor package part, comprising:
Connect on substrate and put and be electrically connected at least one electronic component; And
On this substrate, form the packing colloid of this electronic component coated, this packing colloid comprises:
Account for the epoxy resin of this packing colloid gross weight 5 to 10 % by weight;
Account for the phenol resin of this packing colloid gross weight 1 to 5 % by weight;
Account for the iron oxide of this packing colloid gross weight 65 to 75 % by weight;
Account for the silicon dioxide of this packing colloid gross weight 5 to 30 % by weight; And
Account for the carbon black of this packing colloid gross weight 0.1 to 1 % by weight.
8. the method for making of semiconductor package part as claimed in claim 7, it is characterized in that, this silicon dioxide is amorphous silicas.
9. the method for making of semiconductor package part as claimed in claim 7, it is characterized in that, this electronic component is active member or passive device.
10. the method for making of semiconductor package part as claimed in claim 7, it is characterized in that, this electronic component is radio frequency module.
The method for making of 11. semiconductor package parts as claimed in claim 7, it is characterized in that, this electronic component is RF chip.
The method for making of 12. semiconductor package parts as claimed in claim 11, is characterized in that, this RF chip is bluetooth wafer or Wi-Fi wafer.
CN201410276082.2A 2014-06-06 2014-06-19 Semiconductor package and fabrication method thereof Pending CN105280570A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW103119675A TWI552278B (en) 2014-06-06 2014-06-06 Semiconductor package and method of manufacture
TW103119675 2014-06-06

Publications (1)

Publication Number Publication Date
CN105280570A true CN105280570A (en) 2016-01-27

Family

ID=55149348

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410276082.2A Pending CN105280570A (en) 2014-06-06 2014-06-19 Semiconductor package and fabrication method thereof

Country Status (2)

Country Link
CN (1) CN105280570A (en)
TW (1) TWI552278B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030030155A1 (en) * 2001-06-08 2003-02-13 Junichi Toyoda Resin component for encapsulating semiconductor and semiconductor device using it
CN101460404A (en) * 2006-06-06 2009-06-17 日东电工株式会社 Spherical sintered ferrite particle, semiconductor sealing resin composition making use of the same and semiconductor device obtained therewith
CN102181129A (en) * 2011-03-31 2011-09-14 广州友益电子科技有限公司 Epoxy resin composition for semiconductor encapsulation
CN102559085A (en) * 2010-11-18 2012-07-11 日东电工株式会社 Film for the backside of flip-chip type semiconductor, dicing tape-integrated film for the backside of semiconductor, method of manufacturing film for the backside of flip-chip type semiconductor, and semiconductor device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7077919B2 (en) * 1999-05-20 2006-07-18 Magnetic Metals Corporation Magnetic core insulation
JP2012124466A (en) * 2010-11-18 2012-06-28 Nitto Denko Corp Adhesive film for semiconductor device and semiconductor device
TW201402663A (en) * 2012-07-12 2014-01-16 Tennrich Int Corp Polymeric composite with high thermal conductivity and EMI shielding

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030030155A1 (en) * 2001-06-08 2003-02-13 Junichi Toyoda Resin component for encapsulating semiconductor and semiconductor device using it
CN101460404A (en) * 2006-06-06 2009-06-17 日东电工株式会社 Spherical sintered ferrite particle, semiconductor sealing resin composition making use of the same and semiconductor device obtained therewith
CN102559085A (en) * 2010-11-18 2012-07-11 日东电工株式会社 Film for the backside of flip-chip type semiconductor, dicing tape-integrated film for the backside of semiconductor, method of manufacturing film for the backside of flip-chip type semiconductor, and semiconductor device
CN102181129A (en) * 2011-03-31 2011-09-14 广州友益电子科技有限公司 Epoxy resin composition for semiconductor encapsulation

Also Published As

Publication number Publication date
TWI552278B (en) 2016-10-01
TW201546972A (en) 2015-12-16

Similar Documents

Publication Publication Date Title
US10510733B2 (en) Integrated device comprising embedded package on package (PoP) device
KR102522322B1 (en) Semiconductor package
TWI614870B (en) Package structure and a method for fabricating the same
US9673151B2 (en) Semiconductor package having metal layer
TWI699864B (en) Antenna module
TWI688050B (en) Semiconductor package and board for mounting the same
CN107887344A (en) Electronic package structure and method for fabricating the same
CN103165563B (en) Semiconductor package and fabrication method thereof
TWI594390B (en) Semiconductor package and method of manufacture
CN104701273A (en) Chip packaging structure with electromagnetic shielding function
US10923435B2 (en) Semiconductor package with in-package compartmental shielding and improved heat-dissipation performance
TW201731063A (en) Package structure and method for fabricating the same
US20200118985A1 (en) Semiconductor package
US10686008B2 (en) Magnetic shielding package structure for MRAM device and method for producing the same
TW201806042A (en) Electronic package and method for fabricating the same
US11869849B2 (en) Semiconductor package with EMI shielding structure
CN105529312A (en) Packaging structure
CN105280570A (en) Semiconductor package and fabrication method thereof
CN106373926B (en) Package structure, shielding member and method for fabricating the same
US11211340B2 (en) Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding
CN108155107B (en) Semiconductor package and manufacturing method thereof
US20140264958A1 (en) Semiconductor package, fabrication method thereof and molding compound
CN102044529A (en) System packaging structure and manufacture method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20160127

RJ01 Rejection of invention patent application after publication