TW201546807A - Semiconductor memory device, memory system having the same and operating method thereof - Google Patents

Abstract

An embodiment of the invention may provide a semiconductor memory device including a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program operation with respect to a memory cell selected from the plurality of memory cells, wherein first to third program voltage applying operations and first to third verifying operations are alternatively performed, and a control logic configured to control the peripheral circuit unit to perform the first to third program voltage applying operations and the first to third verifying operations and to increase a second program voltage applied during the second program voltage applying operation more than a first program voltage applied during the first program applying operation by a first step voltage and a third program voltage applied during the third program voltage applying operation more than the second program voltage by a second step voltage.

Description

Semiconductor memory device, memory system therewith and method of operating same

Various embodiments of the present invention generally relate to an electronic device and a method, and more particularly to a semiconductor memory device, a memory system having the same, and a method of operating the same.

Cross-references to related applications

The present application claims the priority of the Korean Patent Application No. 10-2014-0071, filed on Jun. 12, 2014, the entire disclosure of which is hereby incorporated by reference.

The semiconductor memory device is a memory device implemented using a semiconductor material such as germanium (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), or the like. Semiconductor memory devices are generally classified as volatile memory devices or non-volatile memory devices.

A volatile memory device is a memory device in which data stored in the volatile memory device is lost when power is supplied to the memory device. Examples of volatile memory devices include a static random access memory (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), and the like. Non-volatile memory device A memory device in which data stored in the non-volatile memory device is still stored or maintained when a power supply to the memory device is turned off. Examples of non-volatile memory devices include a read only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), or the like. A flash memory is usually classified as a NOR type or a NAND type memory device.

An embodiment of the present invention can provide a semiconductor memory device including a memory cell array including a plurality of memory cells. The semiconductor memory device can also include a peripheral circuit unit configured to perform a staging operation associated with a memory cell selected from the plurality of memory cells, wherein the application of the first to third programmed voltages The operations and the first to third verification operations are performed alternately. The semiconductor memory device can also include a control logic configured to control the peripheral circuit unit to perform the first to third stylized voltage application operations and the first to third verify operations, and Adding a second stylized voltage applied during the application operation of the second stylized voltage to a first step of the first stylized voltage applied during the application operation of the first stylized voltage ( Step) a voltage, and adding a third stylized voltage applied during the application operation of the third stylized voltage to exceed the second stylized voltage by a second step voltage.

A memory system in accordance with an embodiment can include a semiconductor memory device including a plurality of programmable memory cells, and a memory device configured to control the semiconductor memory upon receipt of a stylized command from a host A controller for the operation of a device. Place The semiconductor memory device alternately performs the first to fourth stylizing operations and the first to third verifying operations in accordance with a control of the controller. The different step voltages can be further increased by the first to fourth stylized voltages of the first to fourth stylized operations, respectively.

A method of operating a semiconductor memory device according to an embodiment may include performing a first stylized voltage application operation by applying a first programmed voltage to a plurality of memory cells. The method can also include performing a first verify operation by setting a maximum threshold voltage value from a threshold voltage distribution of the plurality of memory cells to a fourth verify voltage. Moreover, the method can include setting a half (1/2) point of a width of the threshold voltage distribution to a first verification voltage, and utilizing the first verification operating voltage. Moreover, the method can include performing, when a failure is determined due to the first verifying operation, by using a second stylized voltage that is increased beyond the first stylized voltage by a first step voltage A second stylized voltage application operation. The method may also include setting a voltage between the first verification voltage and the fourth verification voltage to be a second verification voltage and using the second verification voltage to perform a second verification operating. Furthermore, the method may include utilizing a third stylized voltage that is increased beyond the second stylized voltage by a second step voltage when a failure is determined due to the second verifying operation A third stylized voltage application operation is performed.

10‧‧‧ memory system

100‧‧‧Semiconductor memory device

110‧‧‧Memory Cell Array

120‧‧‧ address decoder

130‧‧‧Read/Write Circuit

140‧‧‧Control logic

150‧‧‧Voltage generating unit

200‧‧‧ controller

1 is a block diagram depicting a memory system including a semiconductor memory device; FIG. 2 is a block diagram showing the semiconductor memory device shown in FIG. 1 in more detail; and FIG. 3 is a diagram depicting a semiconductor memory device. A flowchart of a stylized operation; FIG. 4 is a graph depicting a threshold voltage distribution of a stylized operation of a semiconductor memory device; 5 is a block diagram depicting a memory system included in the semiconductor memory device illustrated in FIG. 1; FIG. 6 is a block diagram depicting an example of an application of the memory system illustrated in FIG. 5; 7 is a block diagram depicting a computing system including the memory system described with reference to FIG.

In the following, an embodiment of the present invention will be described. In the drawings, the thickness and length of the elements may be exaggerated for convenience of description. In describing the present invention, configurations, structures, and methods that are generally known to those skilled in the art may be omitted to avoid obscuring the present invention. Throughout the drawings, the same element symbols refer to like elements. Accordingly, various embodiments of the present invention are directed to a semiconductor memory device capable of reducing stylized time while performing a stylizing operation, a memory system having the same, and an operating method.

Throughout the detailed description, when an element is referred to as "electrically coupled" to another element, it is meant that the element can be "directly electrically coupled" to the other element or Underneath the intermediate component, "indirectly electrically coupled" to the other component. In addition, it will be further understood that the terms "comprising" and / or "comprising", when used, are used to indicate the presence of the features, items, steps, operations, components and/or components. It does not preclude the presence or addition of one or more other features, items, steps, operations, components, components, and/or groups thereof.

Referring to Figure 1, a block diagram depicting a memory system 10 including a semiconductor memory device 100 is shown.

The memory system 10 can include the semiconductor memory device 100 and a controller 200. The semiconductor memory device 100 can include a memory cell array 110 and A read/write circuit 130 electrically coupled to the memory cell array 110.

The memory cell array 110 can include a plurality of memory cells. Each of the plurality of memory cells can be defined as a multi-level memory cell that stores two or more data bits.

The semiconductor memory device 100 can operate in response to control of the controller 200. The semiconductor memory device 100 can be configured to, when receiving a stylized command from the controller 200, perform a memory unit associated with an address received by the address associated with the stylized command ( Stylized operation of the selected memory unit). The semiconductor memory device 100 can include an application operation of alternately executing a plurality of stylized voltages and a plurality of verify operations. A verify operation can be performed after an application operation of a stylized voltage using an incremental step pulse stylization (ISPP) method is performed. If the verify operation is passed, a stylized voltage can be set by halving the one-step voltage. The staging voltage application operation can be performed by utilizing the set stylized voltage. Moreover, a verification level of any of the verification operations can be increased compared to the verification level of the previous verification operation. Furthermore, the increased range can be set to be half of the increased range of the previous verification operation. Stylized operations will be described below.

In an embodiment, the semiconductor memory device 100 can be a flash memory device. However, the invention is not limited thereto.

The controller 200 can be electrically coupled between the semiconductor memory device 100 and a host Host. The controller 200 can be configured to interface the host Host with the semiconductor memory device 100, and vice versa. For example, when a read or stylization operation is performed upon a request from the host Host, the controller 200 can convert one from the main The logical block address received by the host becomes a physical block address. Moreover, the controller 200 can provide the converted physical block address and a corresponding command to the semiconductor memory device 100. Further, when the stylization operation is performed, information about a set stylized voltage can be transmitted to the semiconductor memory device 100.

In an embodiment, the controller 200 can include an error correction block 210. The error correction block 210 can be configured to detect and correct an error in the material received from the semiconductor memory device 100. The error correction function performed by the error correction block 210 may be limited in accordance with the number of error bits in the material received from the semiconductor memory device 100. The error correction block 210 may perform an error detection and correction function when the number of error bits in the material received from the semiconductor memory device 100 is less than a specific value. The error detection and correction function may not be performed when the number of error bits in the material received from the semiconductor memory device 100 is greater than a specific value. If the error detection and correction function is not performed, the controller 200 can control the semiconductor memory device 100 to control a read voltage applied to a selected word line.

Referring to Figure 2, a block diagram depicting the semiconductor memory device shown in Figure 1 is depicted.

The semiconductor memory device 100 can include the memory cell array 110, the address decoder 120, the read/write circuit 130, a control logic 140, and a voltage generating unit 150.

The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be electrically coupled to the word line WL through the address decoder 120. The plurality of memory blocks BLK1 to BLKz can pass through the bit line BL1 The BLm is electrically coupled to the read/write circuit 130. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be non-volatile memory cells. The plurality of memory cells may define a memory cell electrically coupled to the same word line as one page. More specifically, the memory cell array 110 can be a plurality of pages.

The address decoder 120, the read/write circuit 130, and the voltage generating unit 150 can operate as a peripheral circuit that drives the memory cell array 110.

The address decoder 120 can be electrically coupled to the memory cell array 110 via the word line WL. The address decoder 120 can be configured to operate in response to control of the control logic 140. The address decoder 120 can receive the address ADDR through an input/output buffer in the semiconductor memory device 100. The address ADDR can be provided from the controller 200 (refer back to Figure 1).

The address decoder 120 may decode a list of addresses in the received address ADDR when a staging voltage application operation in the stylization operation is performed. Based on the decoded column address, the address decoder 120 can apply a programmed voltage Vpgm generated by the voltage generating unit 150 to a selected one of the plurality of word lines WL. The address decoder 120 can apply a pass voltage Vpass to the remaining unselected word lines. Further, when a verify operation in the stylization operation is performed, the address decoder 120 may apply a verify voltage Vverify generated by the voltage generating unit 150 to a selected word line. Furthermore, the address decoder can apply a pass voltage Vpass to the remaining unselected word lines.

The address decoder 120 can be configured to decode a row of addresses from the address ADDR. The address decoder 120 can transmit the decoded row address Yi to the read/write circuit 130.

A stylized operation of the semiconductor memory device 100 can be performed in a page-by-page manner. The address ADDR received when requesting a read and program operation may include a block address, the column address, and the row address. The address decoder 120 can select a memory block and a word line according to the block address and the column address. The row address can be decoded by the address decoder 120 and then provided to the read/write circuit 130.

The address decoder 120 can include a block decoder, a column of decoders, a row of decoders, a bit address buffer, and the like.

The read/write circuit 130 may include a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm may be electrically coupled to the memory cell array 110 via the bit lines BL1 to BLm. Each of the plurality of page buffers PB1 through PBm can receive and temporarily store a stylized data during a stylized operation. Each of the plurality of page buffers PB1 through PBm can control a potential of a corresponding bit line using a stylized allowable voltage or a stabilizing inhibit voltage based on the stylized data. The stylized allowable voltage can be reset by increasing the voltage to a set voltage according to a result of the verifying operation. Furthermore, each of the plurality of page buffers PB1 to PBm can perform a verify operation by sensing a stylized state of a corresponding memory unit.

The read/write circuit 130 can operate in response to control of the control logic 140.

In an embodiment, the read/write circuit 130 may include a page buffer (or a page register), a row selection circuit, and the like.

The control logic 140 can be electrically coupled to the address decoder 120, read/write The circuit 130 and the voltage generating unit 150. The control logic 140 can receive a command CMD and a control signal CTRL through an input/output buffer of the semiconductor memory device 100. The command CMD may be provided from the controller 200 (refer to FIG. 1). The control logic 140 can be configured to control all operations of the semiconductor memory device 100 in response to the command CMD. In addition, the control logic 140 can control the address decoder 120, the read/write circuit 130, and the voltage generating unit 150 to output a programmed voltage, a verify voltage, and a stylized allowable voltage during a stylized operation. .

The voltage generating unit 150 may generate the stylized voltage Vpgm, the verify voltage Vverify, and the pass voltage Vpass during a stylized operation. The voltage generating unit 150 may generate a plurality of stylized voltages Vpgm according to the control of the control logic 140 each time an application operation of a stylized voltage in the stylizing operation is performed. In each of the application operations of the stylized voltage, a stylized voltage Vpgm that is increased by a step voltage value can be generated. Furthermore, the step voltage values can be different each time. In addition, a verify voltage having a different potential level can be generated in each verify operation.

Referring to Figure 3, a flow chart for describing a semiconductor memory device is shown.

Referring also to Figure 4, a threshold voltage profile for describing an operation of a semiconductor memory device is shown.

In Figures 1 to 4, the operation of the semiconductor memory device is described below.

(1) Applying a first stylized voltage (S310)

a stylized data can be input and temporarily stored in the read/write circuit Each page buffer of 130 (PB1 to PBm). Based on the temporarily stored stylized data, the potential of the bit lines BL1 to BLm can be controlled by a stylized allowable voltage or a stylized inhibit voltage level. The stylized allowable voltage can be set to 0V.

The voltage generating unit 150 can generate a first stylized voltage Vpgm1 and a pass voltage Vpass according to the control of the control logic 140. The first stylized voltage Vpgm1 generated by the voltage generating unit 150 can be applied to a word line selected by the address decoder 120 in the plurality of word lines WL. Further, the pass voltage Vpass may be applied to a word line that is not selected by the address decoder 120 in the plurality of word lines WL.

(2) Setting the verification voltage (S320)

A threshold voltage of a memory cell having a maximum threshold voltage value Max Vt among a threshold voltage distribution of a memory cell that is changed by the first stylized voltage Vpgm1 can be set to a fourth verify voltage Vverify4 .

(3) First verification operation (S330)

The passing or failing of the first verification operation may be determined according to whether a threshold voltage of the memory unit is higher than or equal to or lower than a first verification voltage Vverify1. For example, when all of the memory cells have a threshold voltage higher than or equal to the first verification voltage Vverify1, it can be determined to pass. Moreover, when some of the memory cells have a threshold voltage lower than the first verification voltage Vverify1, it can be determined as a failure. The first verification voltage Vverify1 may preferably be a threshold voltage value of the memory unit of the maximum number of threshold voltage distributions from the memory unit after the step of applying the first stylized voltage (S310). More specifically, it may preferably be 1/2 of the threshold voltage distribution width (W).

(4) Applying a second stylized voltage (S340)

If it is determined that the result of the first verification operation (S330) is a failure because some memory cells have a threshold voltage lower than the first verification voltage Vverify1, a stylization operation may be performed by applying a second stylized voltage Vpgm2. Execute to a selected word line. Each of the page buffers PB1 to PBm of the read/write circuit 130 may control one of the bit lines electrically coupled to the memory cell having a threshold voltage higher than or equal to the first verify voltage Vverify1 The potential is the level of the stabilizing voltage. Each of the page buffers PB1 to PBm may also control a potential electrically coupled to a bit line of the memory cell having a threshold voltage lower than the first verification voltage Vverify1 to a level of a stable allowable voltage. . The stylized allowable voltage can be set to 0V.

The second stylized voltage Vpgm2 may be a voltage that is increased beyond the first stylized voltage Vpgm1 by a first step voltage ΔV1. The first step voltage ΔV1 may preferably be 1/2 of the distribution of the threshold voltage of the memory cell to which the first stylized voltage Vpgm1 is applied. For example, if the threshold voltage distribution width W is 1,800 mV, the first step voltage ΔV1 value can be set to 0.9V. Further, the first step voltage ΔV1 value may be a value obtained by subtracting the first verification voltage Vverify1 from the fourth verification voltage Vverify4.

After the step (S340) of applying the second stylized voltage is performed, it may preferably be performed again from the verifying operation (S330).

(5) Verification operation (S350)

If it is determined that the first verification operation (S330) is passed, the pass or fail of a second verification operation may be determined according to whether the threshold voltage of the memory unit is higher than or equal to the second verification voltage Vverify2. For example, if all of the memory cells have a threshold voltage higher than or equal to the second verification voltage Vverify2, it can be determined to pass. Again, when the note It is judged that the failure is caused by some of the cells having a threshold voltage lower than the second verification voltage Vverify2. The second verification voltage Vverify2 may be set to have an intermediate value between the first verification voltage Vverify1 and the fourth verification voltage Vverify4. More specifically, it may preferably be 1/4 of the width W of the threshold voltage distribution.

(6) Applying a third stylized voltage (S360)

If it is determined that the result of the second verification operation (S350) is a failure because some memory cells have a threshold voltage lower than the second verification voltage Vverify2, a third stylized voltage Vpgm3 may be applied to a selected one. Word lines to perform the stylized operation. Each of the page buffers PB1 to PBm of the read/write circuit 130 may control a potential of a bit line to which a memory cell having a threshold voltage higher than or equal to the second verification voltage Vverify2 is electrically coupled The voltage level is disabled for the stylization. Further, each of the page buffers PB1 to PBm may control a potential of a bit line electrically coupled to a memory cell having a threshold voltage lower than the second verification voltage Vverify2 to be the stylized allowable voltage Level. The stylized allowable voltage can be a set voltage equal to or higher than 0V. For example, the set voltage can be 0.9V. Each of the page buffers PB1 to PBm may be controlled to be electrically coupled to a memory cell having a threshold voltage lower than the second verification voltage Vverify2 after the first stylized voltage is applied (S310) The bit line of the memory cell having the threshold voltage between the first verify voltage Vverify1 and the second verify voltage Vverify2 is the level of the stylized allowable voltage. Further, each of the page buffers PB1 to PBm may be controlled to be electrically coupled to a memory cell having a threshold voltage lower than the second verification voltage Vverify2, having a second stylized voltage due to the applying (S330) The step of being moved from a position lower than the first verification voltage Vverify1 to a bit between the first verification voltage Vverify1 and the second verification voltage Vverify2 The bit line of the memory cell of the set threshold voltage is the level of the stylized allowable voltage. Thus, the stylized speed of each of the memory cells can be controlled in a substantially uniform manner.

The third stylized voltage Vpgm3 may be a voltage that is increased beyond the second stylized voltage Vpgm2 by a second step voltage ΔV2. The second step voltage ΔV2 may be set to 1/2 of the first step voltage ΔV1. For example, if the first step voltage ΔV1 is 0.9V, the second step voltage ΔV2 value can be set to 0.45V.

Preferably, it may be re-executed from the verification operation (S350) step after the step of applying the third stylized voltage (S360) is performed.

(7) Verification operation (S370)

If the result of the second verification operation (S350) is determined to be passed, the pass or fail of a third verification operation may be based on whether the threshold voltage of the memory unit is higher than or equal to or lower than a third verification voltage Vverify3. And was judged. For example, if all of the memory cells have a threshold voltage higher than or equal to the third verification voltage Vverify3, it can be determined to pass. If some of the memory cells have a threshold voltage lower than the third verification voltage Vverify3, it may be judged as a failure. The third verification voltage Vverify3 may be set to have a value of one bit at an intermediate point between the second verification voltage Vverify2 and the fourth verification voltage Vverify4. More specifically, it may preferably be 1/8 of the threshold voltage distribution width W.

(8) Applying a fourth stylized voltage (S380)

If it is determined that the result of the third verifying operation (S370) is a failure because some memory cells have a threshold voltage lower than the third verifying voltage Vverify3, a fourth stylized voltage Vpgm4 may be applied to a selected one. Word lines to perform the stylized operation. The read / Each of the page buffers PB1 to PBm of the write circuit 130 may control the potential of the bit line electrically coupled to the memory cell having a threshold voltage higher than or equal to the third verify voltage Vverify3 as the stylized prohibition The level of the voltage. Furthermore, each of the page buffers PB1 to PBm may control a potential of a bit line to which a memory cell having a threshold voltage lower than the third verification voltage Vverify3 is electrically coupled to the stylized allowable voltage The level of the. The stylized allowable voltage can be 0V, or a voltage that is increased to exceed the set voltage of 0V. For example, the set voltage can be 0.9V. Each of the page buffers PB1 to PBm may be electrically coupled to a memory cell having a threshold voltage lower than the third verification voltage Vverify3 after the application of the first stylized voltage (S310). The bit line of the memory cell at the threshold voltage between the second verify voltage Vverify2 and the third verify voltage Vverify3 is the level of the stylized allowable voltage having the set voltage level. Further, each of the page buffers PB1 to PBm may be controlled to be electrically coupled to a memory cell having a threshold voltage lower than the third verification voltage Vverify3, having a position shifted from a position lower than the second verification voltage Vverify2 The bit line of the memory cell to a threshold voltage at a position between the second verify voltage Vverify2 and the third verify voltage Vverify3 is a stylized allowable level of the 0V. Thus, the stylized speed of each of the memory cells can be controlled in a substantially uniform manner.

The fourth stylized voltage Vpgm4 may be a voltage that is increased beyond the third stylized voltage Vpgm3 by a third step voltage ΔV3. The third step voltage ΔV3 may be set to 1/2 of the second step voltage ΔV2. For example, if the second step voltage ΔV2 is 0.45V, the third step voltage ΔV3 value may be set to 0.225V.

After the step of applying the fourth stylized voltage (S380) is performed, it may preferably be re-executed from the verifying operation (S370).

(9) Operation of status check (S390)

If the result of the verification operation (S380) is judged to be passed, a status check operation can be performed to determine whether or not a page buffer has an erroneous operation. Furthermore, if the result of the operation of the status check is judged to be passed, the stylization operation may be terminated.

Referring to Figure 5, a block diagram depicting a memory system including the semiconductor memory device shown in Figure 1 is depicted.

The memory system 1000 can include the semiconductor memory device 100 and a controller 1100.

The semiconductor memory device 100 can be configured and operated as described above with reference to FIG. In the following, repeated explanations will be omitted.

The controller 1100 can include a function of the controller 200 described with reference to FIG. The controller 1100 can be electrically coupled to a host Host and the semiconductor memory device 100. The controller 1100 can be configured to access the semiconductor memory device 100 in response to a request from a host Host. For example, the controller 1100 can be configured to control read, write, erase, and background operations of the semiconductor memory device 100. The controller 1100 can be configured to provide an interface between the semiconductor memory device 100 and the host Host. The controller 1100 can be configured to drive a firmware to control the semiconductor memory device 100.

The controller 1100 can include a random access memory (RAM) 1110, a processing unit 1120, a host interface unit 1130, a memory interface unit 1140, and an error correction block 1150. The RAM 1110 can be used as an arithmetic memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host, and a buffer between the semiconductor memory device 100 and the host Host. At least one of the memories One. The processing unit 1120 can control various operations of the controller 1100. The controller 1100 can temporarily store the stylized data provided by the host Host during a write operation.

The host interface unit 1130 can include a protocol to support data communication operations between the host Host and the controller 1100. In an embodiment, the controller 1200 can utilize a unidirectional serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-Express protocol, An Advanced Technology Attachment (ATA) protocol, a tandem ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated electronic drive interface ( At least one protocol selected by the IDE) protocol, a private agreement, etc. to communicate with the host Host.

The memory interface unit 1140 can provide an interface that interfaces with the semiconductor memory device 100. For example, the memory interface unit 1140 can include a NAND interface or a NOR interface.

The error correction block 1150 can perform the same function as the error correction block 210 shown in FIG. The error correction block 1150 is configured to detect an error associated with data received from the semiconductor memory device 100 using an error correction code (ECC). Furthermore, the error correction block 1150 can correct the detected error. The processing unit 1120 can adjust a read voltage according to an error detection result generated by the error correction block 1150. Further, the processing unit 1120 can control the semiconductor memory device 100 to perform a read operation again. In an embodiment, the error correction block 1150 can be a component of the controller 1100.

The controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In an embodiment, the controller 1100 and the semiconductor memory device 100 can be configured as a memory card by being integrated into a single semiconductor device. For example, the controller 1100 and the semiconductor memory device 100 can be configured as, for example, an International Personal Computer Memory Card Association (PCMCIA) card, a Compact Flash (CF) card, by being integrated into a single semiconductor device. , a smart media (SM) card (SMC), a memory stick, an MMC, a reduced-size MMC (RS-MMC), a micro-sized MMC (MMCmicro), a secure digital (SD) card, a mini SD (miniSD) card, a micro SD card, a SD high capacity (SDHC) card, a universal flash storage (UFS) device, and the like.

The controller 1100 and the semiconductor memory device 100 can be configured as a solid state hard disk (SSD) by being integrated into a single semiconductor device. The SSD can include a storage device configured to store data in the semiconductor memory device. When the memory system 1000 is used as an SSD, an operating speed of the host Host electrically coupled to the memory system 1000 can be improved.

In an embodiment, the memory system 1000 can be one of a number of different components of an electronic device, such as a computer, a super mobile personal computer (UMPC), a workstation, a small pen. Electricity, a number of assistants (PDAs), a portable computer, a network tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player, a gaming platform, a Navigation device, a black box, a digital camera, a three-dimensional television, a digital recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, and a A device that wirelessly transmits and receives information, and the like. In addition, the memory system 1000 can be a component of one of a number of different electronic devices to configure a home network, configure a computer network, configure a telematics network, and radio frequency identification (RFID). ) device, or configure a computing system System.

In one embodiment, the memory device 100 or the memory system 1000 can be packaged using one or more of different types of packages. The semiconductor memory device 100 or the memory system 1000 can utilize, for example, a stacked package (PoP), a ball grid array (BGA), a chip size package (CSP), a leaded plastic wafer carrier (PLCC), A plastic dual in-line package (PDIP), a socket module die, a wafer die, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic Metric quad flat package (MQFP), a thin quad flat package (TQFP), a small external integrated circuit (SOIC), a compact shrink package (SSOP), a thin small outline package (TSOP), a system A package (SIP), a multi-chip package (MCP), a wafer level manufacturing package (WFP), a wafer level processing stacked package (WSP), etc. are packaged and mounted.

Referring to Figure 6, a block diagram representing an application of an example of the memory system shown in Figure 5 is depicted.

The memory system 2000 can include a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 can include a plurality of semiconductor memory chips. The plurality of semiconductor memory chips can be divided into a plurality of groups.

The plurality of groups may communicate with the controller 2200 through each of the first through kth channels CH1-CHk. Each of the semiconductor memory chips may have substantially the same structure as the semiconductor memory device 100 described with reference to FIG. 1, and operate in substantially the same manner.

Each of the plurality of groups can be configured to communicate with the controller 2200 via a single common channel. The controller 2200 can be configured to have and refer to FIG. 5 The controller 1100 described has substantially the same structure. In addition, the controller 2200 can control the operation of the plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1-CHk.

Referring to Figure 7, a block diagram representative of a computing system including the memory system described with reference to Figure 6 is depicted.

The computing system 3000 can include a central processing unit 3100, a RAM 3200, a user interface unit 3300, a power supply unit 3400, a system bus 3500, and a memory system 2000.

The memory system 2000 can be electrically coupled to the central processing unit 3100, the RAM 3200, the user interface unit 3300, and the power supply unit 3400 via the system bus 3500. Information provided via the user interface unit 3300 or processed by the central processing unit 3100 can be stored in the memory system 2000.

In FIG. 7, the semiconductor memory device 2100 is shown as being electrically coupled to the system bus 3500 via the controller 2200. However, the semiconductor memory device 2100 can be directly electrically coupled to the system bus 3500. In this example, the functions of the controller 2200 can be performed by the central processing unit 3100 and the RAM 3200.

In FIG. 7, memory system 2000 described with reference to FIG. 6 is shown for use with computing system 3000. However, the memory system 2000 can be replaced with the memory system 1000 described with reference to FIG. In an embodiment, the computing system 3000 can be configured to include both of the memory systems 1000, 2000 described with reference to Figures 6 and 5.

Although certain embodiments have been described above, those skilled in the art will appreciate that the described embodiments are by way of example only. Thus, the semiconductor memory device, The memory system having the semiconductor memory device and the method of operating the semiconductor memory device should not be limited to those according to the embodiment. Rather, the semiconductor memory device, the memory system having the semiconductor memory device, and the method of operating the semiconductor memory device are only limited to the following description in conjunction with the above description and the accompanying drawings. Consider the scope of the patent application described.

Embodiments have been disclosed in the drawings and in the description as described above. The specific terminology used herein is for the purpose of description and is not intended to limit the scope of the invention It will be appreciated by those skilled in the art that various modifications and other equivalents can be made without departing from the scope and spirit of the disclosure. Therefore, the sole scope of the technical protection of the invention will be defined by the technical spirit of the appended claims.

Claims (25)

A semiconductor memory device comprising: a memory cell array comprising a plurality of memory cells; a peripheral circuit unit configured to perform a stylized operation associated with a memory cell selected from the plurality of memory cells, The first to third staging voltage application operations and the first to third verify operations are performed alternately; and a control logic configured to control the peripheral circuit unit to perform the first to third And a first staging voltage applied thereto and adding a second stylized voltage applied during the applying operation of the second stylized voltage to exceed a first stylized voltage And applying a first stylized voltage to the first step voltage during the applying operation, and adding a third stylized voltage applied during the applying operation of the third stylized voltage to exceed the second stylized voltage A second step voltage. The semiconductor memory device of claim 1, wherein the control logic controls the peripheral circuit unit to utilize a first result of the third verifying operation after the third verifying operation is performed The four stylized voltages are applied to perform a fourth stylized voltage application operation, wherein the fourth stylized voltage is a voltage that increases a third step voltage from the third stylized voltage. The semiconductor memory device of claim 2, wherein the second step voltage is half (1/2) of the first step voltage, and the third step voltage is the second Half of the step voltage (1/2). The semiconductor memory device of claim 2, wherein a first verification voltage used in the first verifying operation is performed after the applying operation of the first stylized voltage is performed, A threshold voltage value of a maximum number of memory cells in a threshold voltage distribution of the memory cell. The semiconductor memory device of claim 1, wherein after the applying operation of the first stylized voltage is performed, a first verifying voltage used in the first verifying operation has a bit A half (1/2) point of a threshold voltage distribution width of a memory cell or a voltage value in the vicinity thereof. The semiconductor memory device of claim 4, wherein after the applying operation of the first stylized voltage is performed, a second verifying voltage used in the second verifying operation is one in the memory a threshold voltage of a memory cell having a maximum threshold voltage value in the cell and an intermediate voltage between the first verification voltages. The semiconductor memory device of claim 6, wherein after the applying operation of the first stylized voltage is performed, a third verifying voltage used in the third verifying operation is one in the memory a threshold voltage of a memory cell having a maximum threshold voltage value in the cell and an intermediate voltage between the second verification voltages. The semiconductor memory device of claim 7, wherein the peripheral circuit unit comprises: a read/write circuit configured to control the program according to a stylized data input during a stylizing operation a potential level of the bit line of the memory cell array; and a voltage generating unit configured to apply the first to fourth stylized voltages and the first one according to a control of the controller logic The third verification voltage is to a selected memory unit. The semiconductor memory device of claim 8, wherein the read/write circuit is electrically coupled to a memory sheet that is determined to have failed due to the first verifying operation by setting The potential of the bit line of the element is a level of a stylized allowable voltage to perform the application operation of the second stylized voltage. The semiconductor memory device of claim 8, wherein the read/write circuit is electrically coupled to a bit line of a memory cell that is determined to have failed due to the second verifying operation by setting The potential is a stylized allowable voltage level to perform the third stylized voltage application operation, the setting is electrically coupled to the memory unit determined to have failed, and the first stylized voltage is a bit line of the memory cell having a threshold voltage between the first verify voltage and the second verify voltage after application is a level of a first stylized allowable voltage, and the set is electrically coupled to have a The second stylized voltage application operation moves from a position lower than the first verification voltage to a memory voltage of a threshold voltage between the first verification voltage and the second verification voltage The bit line is a second stylized level that allows verification of the voltage below the level of the first stylized allowable voltage. The semiconductor memory device of claim 8, wherein the read/write circuit is electrically coupled to a bit line of a memory cell that is determined to have failed due to the third verifying operation by setting The potential is a stylized allowable voltage level to perform the third stylized voltage application operation, the setting is electrically coupled to the memory unit determined to have failed, and the first stylized voltage is a bit line of the memory cell having a threshold voltage between the second verify voltage and the third verify voltage after application is a level of a first stylized allowable voltage, and the set is electrically coupled to have a a third stylized voltage applying operation to move from a position lower than the second verification voltage to a memory voltage of a threshold voltage between the second verification voltage and the third verification voltage The bit line is a second stylized level that allows verification of the voltage below the level of the first stylized allowable voltage. A memory system comprising: a semiconductor memory device comprising a plurality of programmable memory cells; and a controller configured to control the semiconductor upon receiving a stylized command from a host A programmatic operation of a memory device, wherein the semiconductor memory device alternately performs first to fourth stylization operations and first to third verify operations in accordance with a control of the controller, wherein The first to fourth stylized voltages of the first to fourth stylized operations are increased by up to different step voltages. The memory system of claim 12, wherein a second stylized voltage applied during an application operation of the second stylized voltage is increased, and more than one at the first stylized voltage Applying a first stylized voltage applied during operation to a first step voltage, wherein a third stylized voltage applied during an application operation of the third stylized voltage is increased beyond a second program a second step voltage, wherein a fourth stylized voltage applied during an application operation of the fourth stylized voltage is increased, and a third step voltage is exceeded . The memory system of claim 13, wherein the second step voltage is half (1/2) of the first step voltage, and the third step voltage is the second step Half of the step voltage (1/2). The memory system of claim 13, comprising: a memory cell array including the plurality of memory cells; a peripheral circuit unit configured to perform a correlation in the plurality of memory cells a programmatic operation of a memory unit; and a control logic configured to control the peripheral circuit unit to perform the first to fourth stylization operations and the first to the first according to control of the controller Three verification operations. The memory system of claim 12, wherein after the applying operation of the first stylized voltage is performed, a first verification voltage used in the first verifying operation has a bit in the memory One half (1/2) of the width of a critical voltage distribution of a cell or a voltage value in its vicinity. The memory system of claim 12, wherein after the applying operation of the first stylized voltage is performed, a second verifying voltage used in the second verifying operation is one in the memory unit a threshold voltage of a memory cell having a maximum threshold voltage value and an intermediate voltage between the first verification voltages, wherein after the application operation of the first stylized voltage is performed, The third verification voltage of the third verification operation is a voltage between a threshold voltage of a memory cell having a maximum threshold voltage value in the memory cell and an intermediate voltage between the second verification voltages. The memory system of claim 15 wherein said peripheral circuit unit comprises: a read/write circuit configured to control said memory based on a stylized data input during a stylizing operation a potential level of the bit line of the cell array; and a voltage generating unit configured to apply the first to fourth stylized voltages and the first to the first according to a control of the controller logic Three verify voltage to a selected memory unit. The memory system of claim 18, wherein the read/write circuit is electrically coupled to a potential of a bit line of the memory cell that is determined to have failed due to the second verifying operation by setting Performing an application operation of the third stylized voltage for a stylized allowable voltage level, the setting is electrically coupled to the memory unit determined to have failed, and the first stylized voltage is applied a bit line of the memory cell having a threshold voltage between the first verification voltage and the second verification voltage is a level of a first stylized allowable voltage, and the electrical coupling is set to have a a second stylized voltage application operation for moving from a position lower than the first verification voltage to a threshold voltage of a position between the first verification voltage and the second verification voltage The bit line is a second stylized level that allows verification of the voltage below the level of the first stylized allowable voltage. The memory system of claim 18, wherein the read/write circuit is electrically coupled to a potential of a bit line of the memory cell that is determined to have failed due to the third verifying operation by setting Performing an application operation of the third stylized voltage for a stylized allowable voltage level, the setting is electrically coupled to the memory unit determined to have failed, and the first stylized voltage is applied Then, a bit line of the memory cell having a threshold voltage between the second verification voltage and the third verification voltage is a level of a first stylized allowable voltage, and is set to be electrically coupled to have a a third stylized voltage application operation for moving from a position lower than the second verification voltage to a threshold voltage of a position between the second verification voltage and the third verification voltage The bit line is a second stylized level that allows verification of the voltage below the level of the first stylized allowable voltage. A method of operating a semiconductor memory device, comprising: performing a first programmed power by applying a first programmed voltage to a plurality of memory cells Pressing operation; performing a first verifying operation by setting a maximum threshold voltage value from a threshold voltage distribution of the plurality of memory cells to a fourth verifying voltage; setting a width of the threshold voltage distribution One half (1/2) point is a first verification voltage, and the first verification operation voltage is utilized; when a failure is determined due to the first verification operation, the utilization is increased beyond the first And stabilizing a second stylized voltage of the first step voltage to perform a second stylized voltage application operation; by setting an intermediate between the first verify voltage and the fourth verify voltage The voltage is a second verification voltage and utilizes the second verification voltage to perform a second verification operation; and when a failure is determined due to the second verification operation, the utilization is increased beyond the second The third stylized voltage of the second step voltage is programmed to perform a third stylized voltage application operation. The method of claim 21, further comprising, after the applying operation of the third stylized voltage, by setting the second verification voltage and an intermediate voltage of the fourth verification voltage to be one a third verification voltage and using the third verification voltage to perform a third verification operation; and when a failure is determined due to the third verification operation, exceeding the third program by utilizing an increase The fourth stylized voltage of the voltage-third step voltage is applied to perform a fourth verify operation. The method of claim 22, wherein the second step voltage is the first One half (1/2) of the step voltage, and the third step voltage is half (1/2) of the second step voltage. The method of claim 22, wherein: setting a potential of a bit line electrically coupled to a memory cell determined to have failed due to the second verifying operation to a level of a stable allowable voltage; Setting to be electrically coupled to the memory cell determined to have failed, having a threshold voltage between the first verification voltage and the second verification voltage after the first stylized voltage is applied The bit line of the memory cell is a level of a first stylized allowable voltage; and the setting is electrically coupled to have a position lower than the first verify voltage due to an application operation of the second stylized voltage a bit line of the memory cell moving to a threshold voltage between the first verification voltage and the second verification voltage is a second program lower than a level of the first stylized allowable voltage The level of the voltage allowed to verify. The method of claim 22, further comprising: setting a potential of the bit line of the memory cell that is determined to have failed due to the third verifying operation to a stylized allowable voltage by setting Leveling to perform an application operation of the third stylized voltage; the setting is electrically coupled to the memory unit determined to have failed, after the first stylized voltage is applied a bit line of the memory cell of the second verification voltage and the threshold voltage between the third verification voltage is a level of a first stylized allowable voltage; and the setting is electrically coupled to have a third stylized voltage a bit line of the memory cell that moves from a position lower than the second verification voltage to a threshold voltage between the second verification voltage and the third verification voltage The first programming permission The second stylization of the level of the voltage allows the level of the voltage to be verified.