KR20120005835A - Semiconductor memory device and the method of programming the same - Google Patents

Semiconductor memory device and the method of programming the same Download PDF

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Publication number
KR20120005835A
KR20120005835A KR1020100066511A KR20100066511A KR20120005835A KR 20120005835 A KR20120005835 A KR 20120005835A KR 1020100066511 A KR1020100066511 A KR 1020100066511A KR 20100066511 A KR20100066511 A KR 20100066511A KR 20120005835 A KR20120005835 A KR 20120005835A
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KR
South Korea
Prior art keywords
program
voltage
latch
verify
data
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KR1020100066511A
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Korean (ko)
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박영수
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주식회사 하이닉스반도체
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Publication of KR20120005835A publication Critical patent/KR20120005835A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/12—Programming voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/14—Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

PURPOSE: A semiconductor memory device and a program method thereof are provided to improve the data reliability of a memory cell by narrowing the width of a threshold voltage distribution. CONSTITUTION: A verification operation is executed by using a first verification voltage after a program operation is execute by using a first program voltage in response to a program pulse which is applied with an odd number(S305). The verification operation is executed by using a target voltage after the program operation is executed by using a second program voltage in response to a program pulse which is applied with an even number(S309). If the first verification voltage is equal to the target voltage, the verification operation is executed by using the target voltage after the program operation is executed by using the second program voltage until the result of the verification operation using the target voltage passes.

Description

Semiconductor memory device and the method of programming the same

The present invention relates to a semiconductor memory device and a program method thereof.

A semiconductor memory device is a memory device that stores data and can be read when needed. Semiconductor memory devices are roughly divided into random access memory (RAM) and read only memory (ROM). Data stored in RAM is destroyed when power supply is interrupted. This type of memory is called volatile memory. On the other hand, the data stored in the ROM does not disappear even if the power supply is interrupted. This type of memory is called nonvolatile memory.

Recently, in order to further improve the integration degree of a semiconductor memory device, a multi-level cell programmable to a plurality of threshold voltage levels has been developed. In comparison, a memory cell programmable to a single threshold voltage level is referred to as a single level cell.

As the threshold voltage level of the multi-level cell increases, the data storage capacity of the memory cell increases. When a plurality of memory cells are programmed to a specific threshold voltage level, the threshold voltages of the memory cells are not the same but are distributed at various levels.

In addition, the interval between neighboring threshold voltage distributions is becoming narrower.

Therefore, the semiconductor memory device is intended to increase the reliability of data by narrowing the width of threshold voltage distribution of memory cells.

A representative method for this is the Increment Step Pulse Program (ISPP) method.

The ISPP method is a program method for applying a program voltage while increasing the unit voltage from the start voltage Vstart in units of step voltages Vstep. After each program execution, program verification is performed to exclude memory cells passed by the program from subsequent program operations.

1A and 1B illustrate a general ISPP program.

FIG. 1A illustrates a voltage applied to a word line selected for a program, and FIG. 1B illustrates a threshold voltage distribution of memory cells formed according to a program execution result.

1A and 1B, a program start voltage Vstart is initially applied to a word line selected for a program.

The program start voltage is applied for a time t1, after which the program verify voltage Vverify is applied.

After the program verification is completed, the program is applied by applying a voltage increased by the step voltage Vstep from the initial program start voltage Vstart, and the program verification is repeated again.

As a result, as shown in FIG. 1B, the threshold voltages of the memory cells in the sour state become high to generate a threshold voltage distribution above the verify voltage Vverify.

When the program is executed in the ISPP method as described above, the width of the threshold voltage distribution of the memory cells can be narrowed. However, since memory cells have fast cells that are programmed fast and slow cells that are slow programmed according to their characteristics, there is a limit in narrowing the threshold voltage distribution.

A semiconductor memory device according to an embodiment of the present invention provides a program method of a semiconductor memory device in which a program voltage and a verification voltage are differently applied to a slow cell and a fast cell to perform a program to narrow a width of a threshold voltage distribution.

Program method of a semiconductor memory device according to an embodiment of the present invention,

In response to an odd number of program pulses, a program operation using a first program voltage gradually rising from the first start voltage is performed, and then a verification operation using a first verify voltage gradually rising from the second start voltage is performed. A first program step; And a second operation of performing a verification operation using a target voltage after performing a program operation using a second program voltage gradually rising from a third start voltage higher than the first start voltage in response to an even-numbered program pulse. And a program step, wherein the first verify voltage is lower than the target voltage, repeating the first and second program steps, and verifying using the target voltage when the first verify voltage is equal to the target voltage. After performing the program operation using the second program voltage until the result of the operation passes, only the third program step of performing the verify operation using the target voltage is repeatedly performed.

Program method of a semiconductor memory device according to another embodiment of the present invention,

In response to an odd number of program pulses, after performing a program operation according to data stored in a first latch of a page buffer in which data to be programmed is stored using a first program voltage gradually rising from a first start voltage, and then A first program step of performing a verify operation using a verify voltage gradually rising from a start voltage and storing a result in the first latch; And performing a program operation according to the data stored in the first latch using a second program voltage gradually rising from a third start voltage higher than the first start voltage in response to an even-numbered program pulse. And performing a verify operation using a voltage, and storing the result in a second latch of a page buffer in which the data to be programmed is stored, wherein the verify voltage used in the first program step is lower than the target voltage. If the data of the second latch is copied to the first latch, the first and second program steps are repeated, and if the verify voltage used in the first program step is equal to the target voltage, the target voltage Using the second program voltage until the result of the verify operation using After performing the program operation according to the data stored in the second latch, the verification operation using the target voltage is performed, and only the third program step of storing the result in the second latch is repeatedly performed.

Program method of a semiconductor memory device according to another embodiment of the present invention,

In order to change the threshold voltage of the memory cell connected to the selected word line to a target voltage or more, after performing a program operation according to data to be programmed stored in the first latch of the page buffer using a first program pulse, the first verify voltage is changed. A first program step of performing a verification operation using the result and storing the result in the first latch; After the program operation is performed according to the data stored in the first latch using the second program pulse higher than the first program pulse, the verify operation using the target voltage is performed to copy the data to be programmed. A second program step of storing in a second latch of the page buffer; When the first verify voltage is lower than the target voltage, the data of the second latch is copied to the first latch, and then the third program pulse is raised by using a third program pulse that raises the first program pulse by a first step voltage. After performing a program operation according to data stored in the first latch, performing a verify operation using the second verify voltage that is increased by the second step voltage from the first verify voltage, and storing the result in the first latch. Program step; And performing a program operation according to the data stored in the first latch using a fourth program pulse higher than the second program pulse by a third step voltage, and then performing a verify operation using the target voltage. And a fourth program step of storing in one latch, repeating the third and fourth program steps until the voltage rising by the second step voltage is equal to the target voltage, and performing the second step voltage. If the rising voltage is equal to the target voltage, the data stored in the second latch is changed according to the data stored in the second latch using the program pulse rising by the third step voltage until the threshold voltages of all the memory cells are changed to the target voltage or more. After the program operation, the verification operation using the target voltage is repeatedly performed. do.

A semiconductor memory device according to another embodiment of the present invention,

A memory cell array including a plurality of memory cells; Peripheral circuits operative to perform a program operation for programming data in the memory cell and a read operation for reading data programmed in the memory cell; And performing a program operation using the first program voltage that gradually rises from the first start voltage in response to an odd number of program pulses, and then gradually increasing from the second start voltage when the program operation is performed. A program using a second program voltage that is gradually raised from a third start voltage higher than the first start voltage in response to a program pulse applied evenly, by performing a first program for performing a verify operation using a first verify voltage. After the operation, after performing the second program for performing the verify operation using the target voltage, and if the first verify voltage is lower than the target voltage, the first and second program steps are repeatedly performed, and the first If the verify voltage is equal to the target voltage, the result of the verify operation using the target voltage may be passed. And a control logic for controlling the peripheral circuit so that only the third program performing the verify operation using the target voltage is repeatedly executed after the program operation using the second program voltage is performed.

A semiconductor memory device and a program method thereof according to an embodiment of the present invention control threshold voltages so that program rates of slow cells and fast cells are similar by applying different program voltages and verify voltages to slow cells and fast cells for programming. By narrowing the distribution, the data reliability of the memory cell can be improved.

1A and 1B illustrate a general ISPP program.
2A shows a semiconductor memory device for explaining the present invention.
FIG. 2B briefly illustrates the page buffer of FIG. 2A.
3 is a flowchart illustrating a program method according to an exemplary embodiment of the present invention.
4 illustrates a program pulse provided by the operation of FIG. 3.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

2A shows a semiconductor memory device for explaining the present invention.

Referring to FIG. 2A, the semiconductor memory device 100 may include the memory cell array 110, the page buffer group 120, the X decoder 130, the Y decoder 140, the input / output logic 150, and the voltage supply circuit 160. ), And control logic 170.

The memory cell array 100 includes a plurality of memory blocks BK. Each memory block BK includes a plurality of cell strings CS.

Each cell string includes a 0 th to 31 th memory cell C0 to C31 connected in series between a drain select transistor (DST) and a source select transistor (SST).

A gate of the drain select transistor DST is connected to a drain select line DSL, and a gate of the source select transistor SST is connected to a source select line SSL.

The gates of the 0th to 31st memory cells C0 to C31 are connected to the 0th to 31st word lines WL0 to WL31, respectively.

The drains of the drain select transistors DST are connected to bit lines, respectively. The bit line is divided into an even bit line (BLe) and an odd bit line (BLo).

The source of the source select transistor SST is commonly connected to a common source line SL.

The page buffer group 120 includes a plurality of page buffers PBs that operate for a program or a read operation.

Each page buffer PB is connected to one even bit line BLe and an odd bit line BLO pair. Each page buffer PB includes a plurality of latches.

The Y decoder 140 provides an input / output path between the page buffer group 120 and the input / output logic 150 in response to the control signal from the control logic 170.

The input / output logic 150 performs data input / output with the outside.

The X decoder 130 includes a plurality of block selection circuits 131. Each block selection circuit 131 is connected to each memory block BK.

In response to a control signal from the control logic 170, the block selection circuit 131 may include the drain select line DSL, the source select line SSL, and the 0 th to 31 th word lines of the memory block BK. WL0 to WL31 may be replaced by a global source select line (GSSL), a global drain select line (GDSL), and zeroth to thirty-first global word lines of the voltage supply circuit 160. Line GWL0 to GWL31).

The voltage supply circuit 160 generates an operating voltage in response to the control signal from the control logic 170 and provides the generated operating voltage to the global lines GSSL, GDSL, GWL0 to GWL31.

The control logic 170 is used to control the operation of the page buffer group 120, the X decoder 130, the Y decoder 140, the input / output logic 150, and the voltage supply circuit 160 of the semiconductor memory device 100. Output a control signal.

The page buffer PB is as follows.

FIG. 2B briefly illustrates the page buffer of FIG. 2A.

Referring to FIG. 2B, the page buffer PB includes a bit line selector 121, a precharge unit 122, and first and second latches 123 and 124.

The bit line selector 121 selects one of the even bit line BLe and the odd bit line BLO in response to a control signal from the control logic 170, and selects the selected bit line BLe or BLo. Connect with (SO).

The precharge unit 122 precharges the sensing node SO in response to a control signal from the control logic 170.

The first and second latches 123 and 124 store data input for a program or read and temporarily store data stored in a memory cell.

The first latch 123 is connected to the IO line through the Y decoder 130. Therefore, data to be programmed is input to the first latch 123.

Meanwhile, the program operation of the semiconductor memory device according to the embodiment of the present invention is performed as follows.

3 is a flowchart illustrating a program method according to an exemplary embodiment of the present invention.

3 will be described with reference to FIGS. 2A and 2B.

When a program command is input (S301), the control logic 170 controls the data to be programmed to be input to the first latch 123 of the page buffer PB.

The data to be programmed input to the first latch 123 is also copied to the second latch 124.

The control logic 170 first executes a first program for applying a first program voltage Vpgm1 to the selected word line (S303). When executing the first program, the program according to the data stored in the second latch 124 of the page buffer is executed.

The first program voltage Vpgm is a program voltage applied for fast cells. Therefore, the fast cells are programmed faster by the first program voltage Vpgm, but the slow cells are slower to program.

Therefore, the programmed fast cells are prohibited from program until the threshold voltage of the slow cell becomes higher than the first program verify voltage Vverify1.

After the first program, the first program verification using the first program verify voltage Vverify1 is performed (S305). The first program verify voltage Vverify1 is a voltage gradually rising from the first voltage V1.

That is, like the first program voltage Vpgm, the first program verify voltage Vverify also gradually increases. At this time, the result of the first program verification is also stored in the second latch 124.

If the threshold voltage of the memory cell is to be increased to the second voltage V2 level according to the program command of step S301, the first program verify voltage Vverify1 is set to a second voltage V1 at a lower first voltage V1. Until the voltage gradually rises.

The result of the first program verification does not need to confirm that a pass has been made. The verification of the first program is to exclude the fast cell when executing the second program. That is, the fast cell that has become a program pass in the first program verification is program inhibited in the second program operation.

The second program is executed by applying the second program voltage Vpgm2 (S307). At this time, the program is executed according to the data stored in the second latch 124. Accordingly, a memory cell, that is, a fast cell programmed to have a threshold voltage equal to or greater than the first program verify voltage Vverify1 when the first program is executed is program inhibited in the second program operation.

After performing the second program, program verification using the second program verification voltage Vverify2 is performed (S309). The result of the second program verify is stored in the first latch 123. The second program verify voltage Vverify2 is not changed to the second voltage V2 level.

It is determined whether the second program verification result is a pass according to data stored in the first latch 123. If the result of the program verification passes, the program operation ends.

However, if the program verification result does not pass, it is determined whether the first verification voltage Vverify1 and the second verification voltage Vverify2 are the same voltage. That is, it is determined whether the first verify voltage Vverify1 has risen to the second voltage V2 level.

When the first verify voltage Vverify1 and the second verify voltage Vverify2 are not equal to each other, the first program voltage Vpgm1, the first program verify voltage Vverify1, and the second program voltage Vpgm2 are increased by the respective step voltages. (S315).

In an embodiment of the present invention, the first program voltage Vpgm1 is increased in units of the first step voltage Vstep1, and the second program voltage Vpgm2 is raised in units of the second step voltage Vstep2. The first program verify voltage Vverify1 is raised in units of a third step voltage Vstep3.

As a result of the second program verification, the first latch 123 stores the verification result by the second program verification voltage Vverify2. The second latch 124 stores the verification result by the first program verify voltage Vverify1.

In an embodiment of the present invention, an object of the present invention is to program a threshold voltage of memory cells higher than a second program verify voltage Vverify2.

Therefore, after raising the first and second program voltages Vpgm1 and Vpgm2 and the first program verify voltage Vverify1 in step S315, the data of the first latch 123 is copied to the second latch 124. Accordingly, the data of the second latch 124 is changed to the verification result by the second program verify voltage Vverify2. Previously programmed memory cells having a threshold voltage higher than the first program verify voltage Vverify1 are also programmed in the second program operation.

After copying the data of the first latch 123 to the second latch 124, the first program is executed again (S303). At this time, the first program voltage Vpgm1 is the voltage increased in step S315. The first program verify voltage Vverify1 in the first program verify performed after the first program is also increased in step S315.

The operations of steps S303 to S317 are repeated until the first and second program verify voltages Vverify1 and Vverify2 become equal.

If the first and second program verify voltages Vverify1 and Vverify2 become equal in step S315, the first program does not proceed any further.

Only the second program voltage is increased (S321), and the second program is executed (S323). At this time, the program according to the data of the first latch 123 is executed.

In operation S325, program verification using the second program verification voltage Vverify2 is performed. If the program verification result of step S325 passes (S327), the program ends.

If the program verification result in step S325 has not passed, the process is repeated again from step S321.

That is, after the first program verify voltage Vverify1 becomes equal to the second program verify voltage Vverify2, only the second program proceeds, and the first program no longer proceeds.

When the first program verify voltage Vverify1 is equal to the second program verify voltage Vverify2, the threshold voltage of the fast cell is increased close to the second program verify voltage Vverify2. Therefore, there is no need to distinguish between fast cells and slow cells afterwards.

4 illustrates a program pulse provided by the operation of FIG. 3.

Referring to FIG. 4, a first program is first performed, program verification is performed, and program pulses for performing the second program and verification are applied.

Pulses marked with hatched in FIG. 4 represent the first program and verification, and blackened pulses represent the second program and verification.

As a result of the determination of step S321 of FIG. 3, when the first and second program verify voltages Vverify1 and Vverify2 become equal, only pulses for the second program and the verify are applied.

The first program and the verification according to an embodiment of the present invention are intended to slow down the program speed of fast cells. And the second program and verify is performed for slow cells.

Accordingly, the program speed of the fast cells is controlled similarly to the slow cell. If the program rates of the fast and slow cells are controlled similarly, the width of the threshold voltage distribution is also narrowed.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

100 semiconductor device 110 memory cell array
120: page buffer group 130: X decoder
140: Y decoder 150: input and output logic
160: voltage supply circuit 170: control logic

Claims (9)

In response to an odd number of program pulses, a program operation using a first program voltage gradually rising from the first start voltage is performed, and then a verification operation using a first verify voltage gradually rising from the second start voltage is performed. A first program step; And
A second program performing a verification operation using a target voltage after performing a program operation using a second program voltage gradually rising from a third start voltage higher than the first start voltage in response to an even-numbered program pulse; Including steps
When the first verify voltage is lower than the target voltage, the first and second program steps are repeatedly performed, and when the first verify voltage is equal to the target voltage, a result of the verify operation using the target voltage may be passed. And after performing the program operation using the second program voltage, only the third program step of performing the verify operation using the target voltage is repeated. The method of claim 1,
Before the first program step,
Receiving data to be programmed into a first latch of a page buffer; And
Copying data of the first latch to a second latch of the page buffer. The method of claim 2,
The first program step,
Performing a program operation using the first program voltage according to data stored in the first latch; And
And performing a program verify operation using the first verify voltage and storing the result in the first latch. The method of claim 3, wherein
The second program step,
Performing a program operation using the second program voltage according to data stored in the first latch; And
And performing a program verify operation using the second program verify voltage, and storing the result in the second latch. The method of claim 4, wherein
And after performing the second program step, copying the data of the second latch to the first latch before performing the first program step. In response to an odd number of program pulses, after performing a program operation according to data stored in a first latch of a page buffer in which data to be programmed is stored using a first program voltage gradually rising from a first start voltage, and then A first program step of performing a verify operation using a verify voltage gradually rising from a start voltage and storing a result in the first latch; And
In response to the even-numbered program pulse, after performing a program operation according to the data stored in the first latch using a second program voltage gradually rising from a third start voltage higher than the first start voltage, a target voltage A second program step of performing a verification operation using the second program and storing the result in a second latch of a page buffer in which the data to be programmed is copied;
If the verification voltage used in the first program step is lower than the target voltage, the data of the second latch is copied to the first latch, and then the first and second program steps are repeatedly performed, and the first program is performed. If the verify voltage used in the step is equal to the target voltage, the program operation according to the data stored in the second latch is performed using the second program voltage until the result of the verify operation using the target voltage is passed. And performing only a third program step of performing a verification operation using a voltage and storing the result in the second latch. The method of claim 6,
Before implementing the first program step,
Receiving data to be programmed into a first latch of the page buffer; And
Copying data of the first latch to a second latch of the page buffer. In order to change the threshold voltage of the memory cell connected to the selected word line to a target voltage or more, after performing a program operation according to data to be programmed stored in the first latch of the page buffer using a first program pulse, the first verify voltage is changed. A first program step of performing a verification operation and storing the result in the first latch;
After the program operation is performed according to the data stored in the first latch using the second program pulse higher than the first program pulse, the verify operation using the target voltage is performed to copy the data to be programmed. A second program step of storing in a second latch of the page buffer;
When the first verify voltage is lower than the target voltage, the data of the second latch is copied to the first latch, and then the third program pulse is raised by using a third program pulse that raises the first program pulse by a first step voltage. After performing a program operation according to data stored in the first latch, performing a verify operation using the second verify voltage that is increased by the second step voltage from the first verify voltage, and storing the result in the first latch. Program step; And
After performing a program operation according to the data stored in the first latch using a fourth program pulse higher than the second program pulse by a third step voltage, the verify operation using the target voltage is performed and the result is output to the first program pulse. A fourth program step for storing in a latch,
Repeating the third and fourth program steps until the voltage rising by the second step voltage becomes equal to the target voltage,
When the voltage rising by the second step voltage is equal to the target voltage, the second latch is used by using a program pulse rising by the third step voltage until the threshold voltages of all the memory cells are changed to the target voltage or more. And performing a verification operation using the target voltage after performing a program operation according to the data stored in the memory. A memory cell array including a plurality of memory cells;
Peripheral circuits operative to perform a program operation for programming data in the memory cell and a read operation for reading data programmed in the memory cell; And
In the program operation, in response to an odd number of program pulses, a program operation using a first program voltage that gradually rises from a first start voltage is performed, and thereafter, the first program gradually rises from a second start voltage. A program operation using a second program voltage that is gradually raised from a third start voltage higher than the first start voltage in response to a program pulse applied to an even number, performing a first program for performing a verify operation using a verify voltage. After performing the second program for performing the verify operation using the target voltage, if the first verify voltage is lower than the target voltage, the first and second program steps are repeatedly performed, and the first verify is performed. When the voltage is equal to the target voltage, when the result of the verify operation using the target voltage is passed After performing a program operation using not the second program voltage, the semiconductor memory device includes control logic for controlling the peripheral circuits, only the third application to perform a verification operation with the target voltage to be repeatedly performed.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9508438B2 (en) 2014-06-12 2016-11-29 SK Hynix Inc. Semiconductor memory device, memory system having the same and operating method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9508438B2 (en) 2014-06-12 2016-11-29 SK Hynix Inc. Semiconductor memory device, memory system having the same and operating method thereof

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