TW201545342A - Semiconductor device - Google Patents

Abstract

The first semiconductor device disclosed in the present invention includes a semiconductor substrate having an anode domain and a cathode domain. The anode domain includes: a first domain of a first conductive type, which has the maximum dopant concentration of the first conductive type at a position of a first depth from the surface of the semiconductor substrate; a second domain of the first conductive type, which has the maximum dopant concentration of the first conductive type at a position of a second depth closer to the surface of the semiconductor substrate in comparison to the first depth; and a third domain disposed between the first domain and the second domain. The dopant concentration of the first conductive type is lower than one-tenth the concentration on the surface of the semiconductor substrate.

Description

Semiconductor device

The technology described in this specification relates to a semiconductor device.

In a semiconductor device having a device structure of a diode, the design of the anode region is a property that affects withstand voltage, high speed, low loss, and the like. For example, Japanese Patent Laid-Open Publication No. 2004-88012 (Patent Document 1) discloses a technique for reducing the amount of hole injection into the cathode region in order to improve the high speed and low loss. Specifically, in Patent Document 1, in order to reduce the dose of p-type impurities in the anode region, the amount of hole injection into the cathode region is reduced, and the surface exposed in the semiconductor substrate is alternately arranged to be shallow on the surface of the semiconductor substrate. A high-concentration p-layer and a low-concentration p-layer exposed to the surface of the semiconductor substrate.

[Advanced technical literature]

[Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2004-88012

As described in Japanese Laid-Open Patent Publication No. 2004-88012, in order to reduce the amount of hole injection into the cathode region, the pressure resistance is lowered once the dose of the p-type impurity in the anode region is reduced. The depth or impurity concentration of the anode region, and the dose of the impurity are limited in order to secure the withstand voltage of the semiconductor device. In the conventional semiconductor device, it is difficult to achieve both the withstand voltage and the reduction in the amount of hole injection.

The first semiconductor device disclosed in the present specification includes a semiconductor substrate having an anode region and a cathode region.

The anode field includes a first field of the first conductivity type, which has a maximum value of the impurity concentration of the first conductivity type at a position at a first depth from the surface of the semiconductor substrate, and a second field of the first conductivity type. The second depth of the semiconductor substrate is greater than the first depth, and has a maximum value of the impurity concentration of the first conductivity type; and the third field is between the first field and the second field. The impurity concentration of the one conductivity type is 1/10 or less of the surface of the semiconductor substrate.

According to the first semiconductor device described above, since the first region and the second region include the third region in which the impurity concentration of the first conductivity type is extremely low, it is possible to suppress the influence of the hole injection amount in the first region. In order to ensure the withstand voltage, the impurity concentration of the first conductivity type in the first field is increased, and By suppressing the amount of hole injection, the impurity of the first conductivity type in the second field can be reduced, and both the withstand voltage can be ensured and the amount of hole injection can be reduced.

In the first semiconductor device described above, the third field may be a field containing impurities of the second conductivity type. Further, at least a part of the third field may be exposed on the surface of the semiconductor substrate and bonded to the surface electrode of the semiconductor substrate.

In the above semiconductor device, it is preferable that the impurity concentration at the position of the first depth in the first field is 1 × 10 ¹⁶ atoms/cm ³ or less.

The second semiconductor device disclosed in the present specification is in the field of a diode and an IGBT in the same semiconductor substrate.

The field of diodes includes the anode field and the cathode field.

The anode field includes a first field of the first conductivity type, which has a maximum value of the impurity concentration of the first conductivity type at a position at a first depth from the surface of the semiconductor substrate, and a second field of the first conductivity type. It is the maximum value of the impurity concentration of the first conductivity type at a position closer to the second depth on the surface side of the semiconductor substrate than the first depth.

The IGBT field includes a first conductivity type body field, a second conductivity type drift field, a second conductivity type emitter field, and a first conductivity type collector field, and the body field is on the surface of the semiconductor substrate. The depth of the first conductivity type has a first maximum value of the impurity concentration of the first conductivity type, and has a second maximum value of the impurity concentration of the first conductivity type at a position closer to the surface side of the semiconductor substrate than the first depth.

According to the second semiconductor device, the impurity concentration of the first conductivity type in the first region is increased in order to ensure the withstand voltage, and the second field is reduced in order to suppress the amount of hole injection. 1 Conductive type of impurities. Further, since the first field and the second field include the third field in which the impurity concentration of the first conductivity type is extremely low, it is possible to suppress the influence of the hole injection amount in the first field. Further, in the field of the IGBT, in the field having the first maximum value, the withstand voltage can be secured, and in the field having the second maximum value, the hole can be efficiently extracted during the operation of the IGBT.

10‧‧‧Semiconductor device

11‧‧‧Component field

12‧‧‧Around area

20‧‧‧Semiconductor device

30‧‧‧Semiconductor device

70‧‧‧Semiconductor device

71‧‧‧IGBT field

72‧‧‧II field

100‧‧‧Semiconductor substrate

101‧‧‧ cathode layer

102‧‧‧ drift layer

103‧‧‧1st field

105‧‧‧2nd field

104‧‧‧3rd field

111,112‧‧‧p type FLR layer

120‧‧‧Anode field

131‧‧‧ inside electrode

132‧‧‧Back electrode

133‧‧‧Insulation film

200‧‧‧Semiconductor substrate

204‧‧‧3rd field

205‧‧‧2nd field

300‧‧‧Semiconductor substrate

301‧‧‧n type cathode layer

302‧‧‧n type drift layer

The first field of the 303‧‧‧p type

The third field of the type 304‧‧‧n

The second field of 305‧‧‧p type

500‧‧‧Semiconductor substrate

501‧‧‧n ⁺ layer

502‧‧‧n layer

503‧‧‧Ion implantation layer

504‧‧‧Intermediate

505‧‧‧Ion implantation layer

50‧‧‧Semiconductor substrate

551‧‧‧n ⁺ layer

552‧‧‧n layer

553‧‧‧p type ion implantation layer

554‧‧‧n type ion implantation layer

555‧‧‧Ion implantation layer

700‧‧‧Semiconductor substrate

701‧‧‧ cathode layer

702‧‧‧ drift layer

703‧‧‧1st field

705‧‧‧2nd field

704‧‧‧3rd field

711‧‧‧p type collector layer

712‧‧‧n type buffer layer

713‧‧‧p type 1 body layer

714‧‧‧p type second body layer

715‧‧‧p type body contact layer

716‧‧‧n type emitter layer

731‧‧‧ inside electrode

741‧‧‧Grooved gate

742‧‧‧virtual gate

1 is a plan view of a semiconductor device of Embodiment 1.

Fig. 2 is a sectional view taken along line II-II of Fig. 1;

FIG. 3 is a view conceptually showing an impurity concentration distribution in an anode region of the semiconductor device of FIG. 1. FIG.

4 is a view for explaining a method of manufacturing the semiconductor device of the first embodiment.

FIG. 5 is a view for explaining a method of manufacturing the semiconductor device of the first embodiment.

Fig. 6 is a view for explaining a method of manufacturing the semiconductor device of the first embodiment;

FIG. 7 is a view for explaining a method of manufacturing the semiconductor device of the first embodiment.

Fig. 8 is a longitudinal sectional view showing a semiconductor device according to a modification.

9 is a plan view of a semiconductor device according to a modification.

Fig. 10 is a plan view showing a semiconductor device according to a modification.

Fig. 11 is a longitudinal sectional view showing a semiconductor device of a second embodiment.

FIG. 12 is a view schematically showing an anode field of the semiconductor device of FIG. A diagram of the impurity concentration distribution.

Fig. 13 is a view for explaining a method of manufacturing the semiconductor device of the second embodiment.

Fig. 14 is a view for explaining a method of manufacturing the semiconductor device of the second embodiment.

Fig. 15 is a view for explaining a method of manufacturing the semiconductor device of the second embodiment.

Fig. 16 is a view for explaining a method of manufacturing the semiconductor device of the second embodiment.

Fig. 17 is a view for explaining a method of manufacturing the semiconductor device of the second embodiment.

Fig. 18 is a view for explaining a method of manufacturing the semiconductor device of the second embodiment.

Fig. 19 is a longitudinal sectional view showing a semiconductor device of a third embodiment.

FIG. 20 is a view conceptually showing an impurity concentration distribution in an anode region of the semiconductor device of FIG. 19. FIG.

21 is a view conceptually showing an impurity concentration distribution in the body region of the semiconductor device of FIG. 19 and its vicinity.

Fig. 22 is a longitudinal sectional view showing a semiconductor device according to a modification.

[Example 1]

As shown in FIGS. 1 and 2, the semiconductor device 10 is provided with a semiconductor substrate 100 including a cell region 11 and a peripheral region 12. another In addition, in FIG. 1, the illustration of the surface electrode 132 is omitted.

The semiconductor substrate 100 includes an n-type cathode layer 101 exposed on the back surface (surface in the negative direction of the z-axis), and an n-type drift layer provided on the surface (surface in the positive direction of the z-axis) of the cathode layer 101. 102. The cathode layer 101 and the drift layer 102 constitute a cathode field. The cathode layer 101 is in contact with the back surface electrode 131. The element region 11 includes an anode region 120 on the surface of the drift layer 102, and the anode region 120 includes a first region 103 contacting the surface of the drift layer 102, and a second region 105 exposed on the surface of the semiconductor substrate 100, and The third field 104 is provided between the first field 103 and the second field 105. The second field 105 is in contact with the surface electrode 132. The peripheral region 12 is provided with a p-type FLR layer 111, 112 on the surface of the drift layer 102. The surface of the FLR layer 111 is in contact with the surface electrode 132 on the center side of the semiconductor substrate 100, and is in contact with the insulating film 133 on the peripheral side. The FLR layers 111, 112 are peripheral pressure resistant structures of the semiconductor device 10. The form of the peripheral pressure resistant structure is not limited to the FLR layer, and a conventionally known structure such as a RESURF layer may be used.

FIG. 3 is a view showing a p-type impurity concentration distribution in the depth direction of the anode region 120. The vertical axis indicates the position in the depth direction of the semiconductor substrate 100. A1 is the position of the upper end of the second field 105, B1 is the position of the realm of the second domain 105 and the third domain 104, C1 is the position of the realm of the third domain 104 and the first domain 103, and D1 is the first domain 103 and The position of the boundary of the drift layer 102. Reference numerals 173 and 175 are p-type impurity concentration distributions indicating the first field 103 and the second field 105, respectively. For comparison, the anode field of the conventional semiconductor device is also shown. The p-type impurity concentration distribution is referred to as reference numeral 179.

The maximum value of the p-type impurity concentration of the distribution 173 is located at the first depth from the surface of the semiconductor substrate 100, and the maximum value of the p-type impurity concentration of the distribution 175 is located at the second depth from the surface of the semiconductor substrate 100. The maximum value of the p-type impurity concentration in the first field 103 (the peak concentration value of the distribution 173) is 2 × 10 ¹⁶ atoms/cm ³ . The impurity concentration of the p-type in the second field is the highest on the surface (that is, the depth A1) of the semiconductor substrate 100, and is 1 × 10 ¹⁷ atoms/cm ³ . The p-type impurity concentration of the third field 104 is lower than 1 × 10 ¹⁶ atoms/cm ³ . The p-type impurity concentration of the third field 104 is 1/10 or less of the p-type impurity concentration of the depth A1 of the surface position of the semiconductor substrate 100.

In the conventional semiconductor device, as in the image distribution 179, the p-type impurity concentration in the anode region is such that the surface (depth A1) of the semiconductor substrate is maximized and decreases as it becomes deeper. Therefore, in order to secure the withstand voltage of the semiconductor device, it is necessary to increase the p-type impurity concentration on the surface of the semiconductor substrate when the impurity concentration of the p-type is increased in the field of the cathode field close to the cathode field. When the p-type impurity concentration on the surface of the semiconductor substrate is high, the amount of injection of holes is increased, and the high-speed and low loss of the semiconductor device are lowered.

On the other hand, in the semiconductor device 10, the distribution 173 of the p-type impurity concentration of the first field 103 and the distribution 175 of the p-type impurity concentration of the second field 105 can be individually designed. In order to increase the withstand voltage, it is only necessary to appropriately increase the p-type impurity concentration of the first field 103, and it is not necessary to increase the p-type impurity concentration of the second field 105 as it is. By this, it can be fully reduced Since the p-type impurity concentration of the second field 105 is low, the amount of hole injection can be suppressed. Further, the semiconductor device 10 has the third region 104 having a low p-type impurity concentration between the first region 103 and the second region 105. Therefore, it is possible to suppress the p-type impurity of the first field 103 from affecting the hole injection amount. When the p-type impurity concentration of the third region 104 is 1/10 or less of the p-type impurity concentration of the depth A1 of the surface position of the semiconductor substrate 100 as in the present embodiment, the p-type of the first region 103 can be sufficiently suppressed. The impurity concentration affects the amount of hole injection.

A method of manufacturing the semiconductor device 10 will be described with reference to FIGS. 4 to 6. 4 to 6 are only the element field 11 of FIG. 2, and only the process of forming the anode region 120 in the element region 11 will be described using the drawings. The other configuration of the semiconductor device 10 can be formed by the same method as the conventional method of manufacturing a semiconductor device.

First, as shown in FIG. 4, the semiconductor substrate 500 is prepared. The semiconductor substrate 500 is sequentially laminated from the back surface side: an n ⁺ layer 501 serving as the cathode layer 101 and an n layer 502 serving as the drift layer 102. In this state, as shown in FIG. 4, p-type impurity ions are implanted at a position at a second depth from the surface of the semiconductor substrate 500 in the n-layer 502. The second depth is a position of almost the surface of the semiconductor substrate 500. Thereby, as shown in FIG. 5, a p-type ion implantation layer 505 is formed. In addition, the n ⁺ layer 501 may be formed on the semiconductor substrate 500 after performing the process of forming the surface structure of the semiconductor device 10 shown below.

Next, as shown in FIG. 6, a p-type impurity is implanted at a position at a first depth from the surface of the semiconductor substrate 500 in the n-layer 502. As shown in FIG. 7, a p-type ion implantation layer 503 is formed. The first depth is a position deeper than the second depth (a position in the negative direction of the z-axis). Further, an intermediate layer 504 having a p-type impurity concentration low is formed between the ion implantation layer 503 and the ion implantation layer 505. When the semiconductor substrate 500 in the state shown in FIG. 7 is annealed, as shown in FIG. 2, the semiconductor device 10 having the anode region 120 including the first region 103, the second region 105, and the third region 104 can be manufactured.

(Modification)

In the first embodiment, the second field 105 covers the entire surface of the third field 104, but is not limited thereto. For example, as in the semiconductor device 20 shown in FIGS. 8 and 9, the second region 205 may be formed in a part of the surface of the third region 204 in the field of components. The second field 205 is formed in a stripe shape extending in the y direction when the surface of the semiconductor substrate 200 is planarly viewed. The second region 205 and the third region 204 are exposed on the surface of the semiconductor substrate 200, and are in contact with the surface electrode 132. The second field 205 and the surface electrode 132 are ohmic junctions, and the third field 204 and the surface electrode 132 are Schottky junctions. Further, as shown in FIG. 10, when the surface of the semiconductor substrate 210 is planarly viewed, a circular second region 215 may be distributed on the surface of the third region 214.

[Embodiment 2]

FIG. 11 is a longitudinal cross-sectional view showing an element field of the semiconductor device 30 of the second embodiment. The semiconductor device 30 is provided with a semiconductor substrate 300. The semiconductor substrate 300 is provided with an n-type cathode layer 301, an n-type drift layer 302, a p-type first field 303, an n-type third field 304, and a p-type second layer, which are sequentially stacked from the back side. Field 305. The cathode layer 301 and the drift layer 302 constitute a cathode field. In the first field 303, the third field 304 and the second field 305 constitute the anode region 320. The cathode layer 301 is in contact with the back surface electrode 131, and the second field 305 is in contact with the surface electrode 132. The other configuration of the semiconductor device 30 is the same as that of the semiconductor device 10 shown in FIG. 1, and thus the description thereof is omitted.

FIG. 12 is a view showing an impurity concentration distribution in the depth direction of the anode region 320. The vertical axis indicates the position in the depth direction of the semiconductor substrate 300. A2 is the position of the upper end of the second field 305, B2 is the position of the realm of the second field 305 and the third field 304, C2 is the position of the realm of the third field 304 and the first field 303, and D2 is the first field 303 and The position of the boundary of the drift layer 302. Reference numerals 373, 375 are p-type impurity concentration distributions indicating the first field 303 and the second field 305, respectively, and reference numeral 374 is an n-type impurity concentration distribution indicating the third field 304.

The maximum value of the p-type impurity concentration of the distribution 373 is located at the first depth (the position between the depths C2 and D2) from the surface of the semiconductor substrate 300, and the curve showing the concentration distribution is roughly expanded in the first field 303. The maximum value of the p-type impurity concentration of the distribution 375 is located at the second depth from the surface of the semiconductor substrate 300 (in the present embodiment, the depth A1), and the curve showing the concentration distribution is extended to the first field 303. The maximum value of the n-type impurity concentration of the distribution 374 is located at the third depth from the surface of the semiconductor substrate 300 (the position between the depths B2 and C2), and the curve showing the concentration distribution is Probably expanded in the third field 304.

The maximum value of the p-type impurity concentration in the first field 303 (the peak concentration value of the distribution 373) is 2 × 10 ¹⁶ atoms/cm ³ . The impurity concentration of the p-type in the second field is the highest on the surface (that is, the depth A2) of the semiconductor substrate 300, and is 1 × 10 ¹⁷ atoms/cm ³ . The p-type impurity concentration of the third field 304 is lower than 1 × 10 ¹⁶ atoms/cm ³ . The p-type impurity concentration of the third field 304 is 1/10 or less of the p-type impurity concentration of the depth A2 of the surface position of the semiconductor substrate 300.

A method of manufacturing the semiconductor device 30 will be described with reference to FIGS. 13 to 18. First, as shown in FIG. 13, a semiconductor substrate 550 is prepared. The semiconductor substrate 550 is sequentially laminated from the back surface side: an n ⁺ layer 551 serving as the cathode layer 301 and an n layer 552 serving as the drift layer 302. In this state, as shown in FIG. 13, p-type impurity ions are implanted at a position at a second depth from the surface of the semiconductor substrate 550 in the n-layer 552. The second depth is a position of almost the surface of the semiconductor substrate 550. Thereby, as shown in FIG. 14, a p-type ion implantation layer 555 is formed.

Next, as shown in FIG. 15, a p-type impurity ion is implanted at a position at a first depth from the surface of the semiconductor substrate 550 in the ion implantation layer 555, and a p-type ion implantation layer 553 is formed as shown in FIG. The first depth is a position deeper than the second depth (a position in the negative direction of the z-axis).

Next, as shown in FIG. 17, an n-type impurity ion is implanted at a position between the first depth and the second depth in the ion implantation layer 555, and an n-type ion implantation layer 554 is formed as shown in FIG. Once annealed When the semiconductor substrate 550 in the state shown in FIG. 18 is processed, as shown in FIG. 11, the semiconductor device 30 including the annealing layer 320 including the first region 303, the second region 305, and the third region 304 can be manufactured.

As in the present embodiment, the third field 304 can be formed by performing n-type ion implantation. In this case, the distribution of the p-type impurity concentration having the maximum value in the second field 305 can be expanded to the entire anode region 320 as shown by the distribution 375.

[Example 3]

19 is a longitudinal cross-sectional view showing an element field of the semiconductor device 70 of the third embodiment. The semiconductor device 70 includes a semiconductor substrate 700 in which an IGBT region 71 and a diode region 72 are formed. In the IGBT region 71 of the semiconductor substrate 700, a p-type collector layer 711, an n-type buffer layer 712, an n-type drift layer 702, a p-type first body layer 713, and p are sequentially laminated from the back surface side thereof. A second body layer 714 of the type. A p-type body contact layer 715 and an n-type emitter layer 716 are formed on the surface of the second body layer 714, and are exposed on the surface of the semiconductor substrate 700. The buffer layer 712 and the drift layer 702 extend to the diode region 72. The semiconductor substrate 700 is provided with a trench gate 741 that penetrates the first body layer 713 and the second body layer 714 from the surface thereof and reaches the drift region 702. The trench gate 741 is in contact with the emitter layer 716 on its side. The first body layer 713, the second body layer 714, and the body contact layer 715 function as the body of the IGBT field 71.

In the diode field 72, n is sequentially stacked from the back side thereof. The cathode layer 701, the buffer layer 712, the drift layer 702, the p-type first field 703, and the n-type third field 704. A p-type second region 705 is formed on a part of the surface of the third region 704, and is exposed on the surface of the semiconductor substrate 700. The cathode region of the diode region 72 is composed of a cathode layer 701, a buffer layer 712, and a drift layer 702. The anode region 720 is composed of a first field 703, a second field 705, and a third field 704. The semiconductor substrate 700 is provided with a dummy gate 742 that penetrates the second region 704 and the first region 703 from the surface thereof and reaches the drift region 702.

In the second field 705, the third field 704, the body contact layer 715 and the emitter layer 716 are in contact with the surface electrode 732. The cathode layer 701 and the collector layer 711 are adjacent to each other and exposed on the back surface of the semiconductor substrate 700, and are in contact with the back surface electrode 731.

FIG. 20 is a view showing a p-type impurity concentration distribution in the depth direction of the anode region 720. The vertical axis indicates the position in the depth direction of the semiconductor substrate 700. A3 is the position of the upper end of the second field 705, B3 is the position of the lower end of the second field 705, C3 is the position of the boundary of the third field 704 and the first field 703, and D3 is the boundary of the first field 703 and the drift layer 702. s position. Reference numerals 773, 775 are p-type impurity concentration distributions indicating the first field 703 and the second field 705, respectively.

21 is a view showing a p-type impurity concentration distribution in the depth direction from the main body contact layer 715 to the first main body layer 713. The vertical axis indicates the position in the depth direction of the semiconductor substrate 700. A4 is the position of the upper end of the body contact layer 715, and B4 is the position of the lower end of the body contact layer 715. C4 is a position of the boundary between the second body layer 714 and the first body layer 713, and D4 is a position of the boundary between the first body layer 713 and the drift layer 702. Reference numerals 783, 784, and 785 are p-type impurity concentration distributions indicating the first main body layer 713 and the second field 705, respectively. Distribution 775 and distribution 785 can also be formed by the same process. Further, the distribution 773 and the distribution 783 can also be formed by the same process. As shown in FIG. 21, the body region of the IGBT region 71 has a first maximum value (maximum value of the distribution 783) of a p-type impurity concentration at a position at a first depth from the surface of the semiconductor substrate 700, and is larger than the first The depth also has a second maximum value (maximum value of the distribution 775) of the p-type impurity concentration at the position on the surface side of the semiconductor substrate 700. Between the field having the first maximum value and the field having the second maximum value, there is a field in which the impurity concentration of the p-type is relatively low.

As in the present embodiment, the semiconductor device may have a semiconductor element structure other than a diode. The semiconductor device 70 is an RC-IGBT including the IGBT region 71 and the diode region 72 in the same semiconductor substrate 700. In the RC-IGBT, in the drift layer 702 in the diode field 72, in order to reduce the lifetime of the carrier, the switching characteristics are improved, and the lifetime control field (for example, a high concentration formed by ion irradiation or the like) may be formed. In the field of crystal defects). According to the semiconductor device 70, in the diode field 72, the amount of hole injection from the anode region to the cathode region can be reduced, so that the life control function in the life control field can be reduced. When the life control function is lowered, the deterioration of the characteristics of the IGBT field 71 caused by the field of life control can be suppressed, and the leakage current can be reduced. Further, in the IGBT field 71, in the field having the first maximum value (the first body layer 713), The withstand voltage can be ensured, and in the field having the second maximum value (the body contact layer 715), the hole can be efficiently extracted while the IGBT is operating. By adjusting the impurity concentration of the field having the first maximum value and the field (the second body layer 714) between the domains having the second maximum value, the groove gate 741 can be formed during the IGBT operation. N-type channel control.

(Modification)

The configuration of the IGBT field is not limited to the embodiment described in the third embodiment. For example, like the semiconductor device 70a shown in FIG. 22, the IGBT region 71 of the semiconductor substrate 700a may include a region 71a including the emitter layer 716 and a region 71b not including the emitter layer 716. In the field 71b, the channel is not formed when the gate is turned on, and the channel density of the IGBT field 71 is low, so that the carrier can be accumulated. Therefore, in the semiconductor device 70a, the on-resistance can be lowered.

The embodiments of the present invention have been described in detail above, but these are merely illustrative and are not intended to limit the scope of the claims. The technology described in the patent application scope includes various modifications and modifications of the specific examples described above.

The technical elements described in the specification or the drawings are those that exhibit the usefulness of the technology by a single or various combinations, and are not limited to the combination described in the claims at the time of filing. Moreover, the technique exemplified in the specification or the drawings is a person who can achieve a plurality of numbers at the same time, and one of the objectives is to achieve the usefulness of the technology itself.

10‧‧‧Semiconductor device

11‧‧‧Component field

12‧‧‧Around area

100‧‧‧Semiconductor substrate

101‧‧‧ cathode layer

102‧‧‧ drift layer

103‧‧‧1st field

104‧‧‧3rd field

105‧‧‧2nd field

111,112‧‧‧p type FLR layer

120‧‧‧Anode field

131‧‧‧ inside electrode

132‧‧‧Back electrode

133‧‧‧Insulation film

Claims (5)

A semiconductor device comprising a semiconductor device having a semiconductor substrate in an anode region and a cathode region, wherein the anode region includes a first region of a first conductivity type and is located at a first depth from a surface of the semiconductor substrate. The maximum value of the impurity concentration of the first conductivity type; the second field of the first conductivity type has the impurity concentration of the first conductivity type at a position closer to the second depth on the surface side of the semiconductor substrate than the first depth The maximum value and the third field are provided between the first field and the second field, and the impurity concentration of the first conductivity type is 1/10 or less of the surface of the semiconductor substrate. A semiconductor device according to claim 1, wherein the third field is a field containing impurities of the second conductivity type. A semiconductor device according to claim 2, wherein at least a part of the third field is exposed on a surface of the semiconductor substrate and is bonded to a surface electrode of the semiconductor substrate. The semiconductor device according to any one of the first to third aspects of the first aspect, wherein the impurity concentration at the position of the first depth in the first region is 1 × 10 ¹⁶ atoms/cm ³ or less. A semiconductor device comprising a diode field and an IGBT field in the same semiconductor substrate, wherein the diode field includes an anode field and a cathode field, and the anode field includes a first field of a first conductivity type. On the surface of the semiconductor substrate The first depth position has a maximum value of the impurity concentration of the first conductivity type; and the second field of the first conductivity type has the first depth at a position closer to the second depth on the surface side of the semiconductor substrate than the first depth. The maximum value of the conductivity type impurity concentration includes the first conductivity type body field, the second conductivity type drift field, the second conductivity type emitter field, and the first conductivity type collector field, and the body. The field has a first maximum value of the impurity concentration of the first conductivity type at a position at a first depth from the surface of the semiconductor substrate, and has a first conductivity type impurity concentration at a position closer to the surface side of the semiconductor substrate than the first depth. The 2nd maximum.