TW201541572A - Ceramic wiring board and semiconductor device - Google Patents

Abstract

To provide a ceramic wiring board having a high degree of reliability with low susceptibility to cracking due to heat load and temperature cycles and peeling of a metalization layer and a solder layer, and to provide a semiconductor device. In the present invention, a ceramic wiring board is obtained by filling an up/down conduction hole formed through a ceramic board in the direction of thickness thereof with an up/down conductor comprising a composite material containing at least one low resistance metal selected from the group consisting of Cu, Ag, and Au, and at least one high melting point metal selected from the group consisting of W and Mo, the residual stress being 100 MPa or less. In a semiconductor device of the present invention, a semiconductor element is installed on the ceramic wiring board.

Description

Ceramic wiring substrate and semiconductor device

The present invention relates to a ceramic wiring board including a substrate formed of a ceramic plate and a through-conducting body in a thickness direction of the substrate, and a semiconductor device using the ceramic wiring substrate.

For example, a ceramic is formed in a plate-shaped substrate made of a ceramic such as AlN, Al ₂ O ₃ , Si ₃ N ₄ , or SiC, and a ceramic is formed in the thickness direction to penetrate the upper via hole and fill the upper and lower vias (through holes). The wiring board is used for mounting a semiconductor element or the like.

However, when the entire upper and lower conductive bodies are formed of a low-resistance metal such as Cu, Ag, or Au as a conductive material, the low-resistance metal and the ceramic have a large thermal expansion coefficient, and thus are used for bonding to a semiconductor element or the like. A local stress is applied to the metallization layer or the solder layer, and the metallization layer or the solder layer is likely to be cracked. If cracks occur, the reliability of mounting the semiconductor element is remarkably lowered. Further, there is a possibility that a large thermal stress is applied to the substrate itself or the mounted semiconductor element.

Therefore, it has been studied to form a vertical conductor by a composite material containing a low-resistance metal such as Cu and a high-melting-point metal such as W or Mo, and the thermal expansion coefficient thereof is close to that of the ceramic-containing substrate.

For example, in Patent Document 1, the board of the precursor is used as a raw material for ceramics. The body (ceramic green sheet) is formed by inserting the upper and lower via holes in the thickness direction of the substrate before sintering, filling the paste containing the high melting point metal and the low-resistance metal, and then sintering the whole body, thereby integrally forming the ceramic. The substrate and the upper and lower vias including the composite material are filled in the lower via holes of the substrate.

Further, in Patent Document 2, the ceramic green sheets before sintering are formed into upper and lower via holes, filled with a paste containing high-melting-point metal particles, and then sintered integrally, and a ceramic substrate is integrally formed and filled on the substrate. After a porous structure including a sintered body of a large amount of high-melting-point metal particles in the via hole, a low-resistance metal is immersed in the formed porous structure to form a porous structure having a high-melting-point metal. There is a low-resistance metal composite structure above and below the conductor.

In Patent Document 3, a vertical via hole is formed at a predetermined position of a substrate formed by sintering a ceramic green sheet in advance, and then a paste containing particles of a high melting point metal such as W or Mo is filled in the upper and lower via holes, and sintered to form a paste. After a large amount of the porous structure of the sintered body of the high-melting-point metal particles, the low-resistance metal is immersed in the formed porous structure to form a lower-conducting body having the same composite structure as described above. According to this formation method, the positional accuracy of the upper and lower conductors can be improved as compared with the above two methods.

However, as described in each of the above-mentioned patent documents, a conventional ceramic wiring board having a composite material including a high melting point metal and a low resistance metal has a problem in that a metal for mounting a semiconductor element is formed on the surface thereof. In the case of a chemical layer or a solder layer, or when a semiconductor element is mounted on the formed metallization layer or the solder layer, or a thermal load or temperature cycle such as when the mounted semiconductor element is operated, cracks are particularly likely to occur near the surface of the substrate. Or the metallization layer or the solder layer is easily peeled off, and the reliability is low.

[Previous Technical Literature] [Patent Literature]

Patent Document 1: Japanese Patent Laid-Open Publication No. 2000-22338

Patent Document 2: Japanese Patent Laid-Open No. Hei 5-267849

Patent Document 3: Japanese Patent Special Publication No. 7-107724

An object of the present invention is to provide a ceramic wiring board which is less likely to be cracked by heat load or temperature cycle or which is peeled off from a metallization layer or a solder layer, and which has high reliability.

Moreover, an object of the present invention is to provide a semiconductor device having high reliability in which a semiconductor element is mounted on the ceramic wiring board.

The present invention relates to a ceramic wiring board comprising: a ceramic substrate formed in a plate shape and having a vertical via hole penetrating through the thickness direction thereof; and a vertical conductor that is filled in the upper and lower via holes and containing the selected from the group consisting of Cu And a composite material of at least one of a low-resistance metal selected from the group consisting of Ag and Au and at least one high-melting-point metal selected from the group consisting of W and Mo; and the residual stress is 100 MPa or less.

Moreover, the present invention is a semiconductor device in which a semiconductor element is mounted on the ceramic wiring board of the present invention.

According to the present invention, it is possible to provide a heat cycle or temperature cycle A ceramic wiring board having high reliability and which is cracked or peeled off from the metallization layer or the solder layer.

Moreover, according to the present invention, it is possible to provide a semiconductor device having high reliability in mounting a semiconductor element on the ceramic wiring board.

Ceramic Circuit Board

The present invention relates to a ceramic wiring board comprising: a ceramic substrate formed in a plate shape and having a vertical via hole penetrating through the thickness direction thereof; and a vertical conductive body filled in the upper and lower via holes of the substrate and including A composite material of at least one of a low-resistance metal selected from the group consisting of Cu, Ag, and Au and at least one high-melting-point metal selected from the group consisting of W and Mo is selected; and the residual stress is 100 MPa or less.

According to the present invention, by adjusting the residual stress of the ceramic wiring board to a range of 100 MPa or less as described above, it is possible to suppress cracking or metallization or solder layer peeling in the vicinity of the surface of the substrate when a heat load or temperature cycle is applied. To improve the reliability of the ceramic wiring substrate. It is based on the following reasons.

That is, even if the upper and lower conductive bodies are formed of a composite material of a high melting point metal and a low resistance metal, the difference in thermal expansion coefficient from the substrate is only small, and does not completely disappear. The difference in the small thermal expansion coefficient becomes a residual stress of the ceramic wiring substrate. The reason.

In particular, in the method of forming the upper and lower conductive bodies described in Patent Documents 2 and 3, it is necessary to heat the low-resistance metal when it is immersed in the porous structure. Since the temperature is high to 1000 ° C or higher, a relatively large stress is generated in both the substrate and the upper and lower vias based on the difference in thermal expansion rate, and the residual stress remains on the ceramic wiring substrate.

According to the study by the inventors, when the residual stress exceeds 100 MPa and remains, the thermal load or the temperature cycle described above is applied to the ceramic wiring substrate, which causes cracks to occur near the surface of the substrate, or the metallization layer or the solder layer is easily peeled off. .

Further, in the case where such problems occur, it is of course impossible to operate the semiconductor element normally.

On the other hand, when the residual stress of the ceramic wiring board is adjusted to a range of 100 MPa or less, even if the heat load or the temperature cycle is applied, it is difficult to cause cracks or peeling of the metallization layer or the solder layer in the vicinity of the surface of the substrate.

Further, in consideration of further improving the effect of suppressing the occurrence of cracks in the vicinity of the surface of the substrate or the peeling of the metallized layer or the solder layer when the heat load or the temperature cycle is applied, and further improving the reliability of the ceramic wiring substrate, in the above range, The residual stress is preferably 80 MPa or less.

Further, the lower limit of the residual stress is of course 0 MPa. It is desirable that the residual stress does not remain at all.

In the present invention, the residual stress of the ceramic wiring board is represented by a value obtained by an X-ray stress measurement method, and the X-ray stress measurement method is used according to the method. The 0.3 mm collimator calculates the stress by X-ray diffraction of the portion 0.3 mm away from the upper and lower conductors in the plane direction of the substrate, and the Young's modulus and Poisson's ratio of the ceramic forming the substrate.

The ceramic wiring substrate of the present invention preferably undergoes, for example, the following steps A step of forming a substrate having a high melting point metal by forming a predetermined position of a substrate formed by sintering a precursor such as a ceramic green sheet after sintering in a thickness direction thereof; and forming an upper and lower via hole; The paste is a step of sintering a plurality of particles of a high melting point metal by firing to form a porous structure, and a step of forming a low-resistance metal by immersing the low-resistance metal in the formed porous structure to form a vertical conductor.

<Substrate>

As the ceramic forming the substrate, various ceramics having high heat dissipation properties capable of coping with high output of the semiconductor element can be used. In particular, in order to improve heat dissipation, the thermal conductivity of the ceramic forming the substrate is preferably 80 W/mK or more. Further, the upper limit of the thermal conductivity is not particularly limited, but is preferably 400 W/mK or less.

Further, in order to minimize the difference in thermal expansion coefficient from the mounted semiconductor element, the thermal expansion coefficient of the ceramic forming the substrate is preferably 2.5 × 10 ^-6 /° C or more, and preferably 7.0 × 10 ^-6 /° C or less.

Examples of the ceramic include AlN, Al ₂ O ₃ , Si ₃ N ₄ , SiC, and the like. The substrate containing the ceramics can be formed in the same manner as conventionally known.

That is, as described above, after the ceramic green sheet as a precursor is sintered, the surface or the like is polished as necessary to form a substrate. The conditions, temperature, polishing method, and the like of sintering can be set to be the same as in the prior art. For example, mechanical polishing (fixed abrasive grains, free abrasive grains) or chemical mechanical polishing may be mentioned as the polishing method.

<Upper and lower vias>

The diameter of the upper and lower via holes is preferably 0.1mm or more, preferably 0.3mm or less.

When the pore diameter is less than this range, it is difficult to fill the upper and lower via holes with the paste containing the particles of the high melting point metal which is the raw material of the porous structure. On the other hand, when the pore diameter exceeds the above range, the porous structure formed by sintering the paste to be sintered or the low-resistance metal is immersed in the porous structure to form the upper and lower conductive bodies. It is easy to fall off the substrate in the subsequent steps.

However, for example, the aperture can be set to be smaller than the relationship between the wiring processing in the substrate and the like. 0.1 mm, for example, in order to improve electrical characteristics or thermal characteristics, etc., the aperture is set to be larger than 0.3mm, but it is necessary to study the viscosity of the paste and the like.

The upper and lower via holes are preferably formed on a substrate which is formed into a plate shape by sintering in advance as described above. Thereby, the positional accuracy can be improved compared to the method of punching before sintering. For example, the positional accuracy can be set to approximately ±50 μm or less, but is not limited thereto.

In order to form the upper and lower via holes after the substrate to be sintered in advance, various methods such as a method using a laser, a method using a micro-drilling hole, and a method using micro-blasting may be employed.

Among them, regarding the method of using the laser or the micro-drilling, by forming the position of the upper and lower via holes into the processing machine, the upper and lower via holes can be automatically formed at a predetermined forming position.

On the other hand, regarding the method of using micro-blasting, for example, a photoresist for sandblasting containing a urethane-based resin or the like is used, and a photoresist pattern having a desired pattern is formed by photolithography, from above. Blowing sandblasting, not covered with photoresist After selectively punching, the photoresist is peeled off and removed, whereby the upper and lower via holes can be formed at a predetermined formation position.

<Upper and lower conductors>

Preferably, as described above, first, a plurality of particles of at least one high melting point metal selected from the group consisting of W and Mo are sintered in the upper and lower via holes to form a porous structure, and then, the porous body The low-resistance metal selected from the group consisting of Cu, Ag, and Au is immersed in the mass structure to form a composite structure. Further, the porous structure may further contain C.

In order to adjust the residual stress of the ceramic wiring board having the upper and lower conductors of the composite structure to the above-described range of 100 MPa or less, it is only necessary to adjust the distribution of the particle diameter of the high-melting-point metal particles to form a stronger porous structure.

Specifically, it is preferable to form a ratio N _A of particles having a maximum major axis of 1.0 μm or less (referred to as "A particles") in a cross section of the upper and lower conductive bodies of the porous structure by melting the low-resistance metal. (%) and the maximum number of the longitudinal particle diameter of 5.0 m or more (to "particles C") ratio of N _C (%) and the N _A + N _C is 50 or more and 90 or less, than the N _A / N _C becomes The structure of the porous structure is adjusted in a manner of 2/3 or more and 2 or less.

Further, in the present invention, the sum N _A + N _C and the ratio N _A / N _C can be obtained by the following method.

That is, the upper and lower vias were formed by polishing to expose the cross section, and then the cross-section polishing (CP) by dry etching using Ar plasma was observed using a scanning electron microscope (SEM) at a magnification of 1000 times × 90 μm × 130 μm. When any of the 10 sections of the cross section is processed, the particles of all the high melting point metals exposed in the field of view are classified into the above-mentioned A particles, C particles, and the maximum long diameter between the two is more than 1.0 μm. Particles less than 5.0 μm (set to "B particles"), and count the number of each.

At this time, in the case where a plurality of particles are originally formed, the particles grow as the sintering step and the grain boundary disappears, and the long diameter is measured as one particle, and is classified into any of the A particles to the C particles.

Then, the calculated ratio of the number of percentage of the total number of C ~ A particle in the particle number ratio of particles A N _A (%) and the proportion of particles C N _C (%), based on the results obtained and N _A + N _C , than N _A /N _C .

By setting the sum of N _A + N _C and the ratio N _A / N _C to the above range, the neck growth between the particles of the high melting point metal forming the porous structure can be sufficiently generated to form a strong porous material. In the structure, the residual stress of the ceramic wiring board can be adjusted to a range of 100 MPa or less.

In other words, the C particles function to secure a large space for melting the low-resistance metal between the particles by the contact of the adjacent C particles.

Further, the B particles having a smaller particle diameter than the C particles enter the space formed by the C particles, and function to adjust the size of the space. That is, the function of adjusting the ratio of the porous structure to the low-resistance metal immersed in the porous structure is exhibited.

Further, the A particles having the smallest particle size enter the gap near the contact point of the C particles, and function to promote the growth of the neck between the C particles. In other words, it functions to increase the neck growth between the C particles and to improve the sinterability to form a strong porous structure.

The ratio of N _A + N _C and ratio N _A / N _C satisfying the above range means that the mixing ratio of the three particles of the A particles to C particles is defined as a predetermined range.

When N _A + N _{C is} less than 50, B particles having an intermediate particle diameter are excessively present, and a large amount of B particles enter the space formed by the C particles, and the space is narrowed more than necessary.

Further, there is a problem in that a sufficient amount of low-resistance metal is not immersed in the space to generate voids (voids), or a ratio of low-resistance metals having a high thermal conductivity is small, and the upper and lower sides are turned on. The thermal conductivity of the body is reduced.

On the other hand, when N _A + N _C exceeds 90, the B particles become insufficient, and the B particles cannot be properly filled in the space formed by the C particles.

Further, there is a case where the excessive low-resistance metal is immersed in the space, and the difference in thermal expansion coefficient between the upper and lower conductors and the substrate is large, and the residual stress of the ceramic wiring board cannot be adjusted to a range of 100 MPa or less.

Further, when the ratio of N _A /N _{C is} less than 2/3, the A particles are insufficient, so that the sinterability by the A particles is increased, and the neck growth between the C particles is increased to form a solid porous structure. The effect becomes insufficient.

In addition, there is a case where a part or the whole of the porous structure is destroyed during the immersion of the low-resistance metal, and it is not possible to sufficiently obtain the low-resistance metal and the low-resistance metal based on the high strength of the porous structure. The effect of expansion and contraction of the upper and lower conductive bodies cannot adjust the residual stress of the ceramic wiring board to a range of 100 MPa or less.

Further, in the case where the ratio of N _A / N _{C is} less than the above 2/3, the neck growth between the C particles is greatly reduced, and the particles of the high melting point metal are immersed in the low resistance metal. A part of it is extruded from the upper and lower via holes.

Further, there is a case where the ratio of the low-resistance metal is excessively increased, and the difference between the thermal expansion coefficients of the upper and lower conductors and the substrate is large, so that it cannot be integrally formed. The porous structures having sufficient strength interact with each other, and the residual stress of the ceramic wiring board cannot be adjusted to a range of 100 MPa or less.

On the other hand, when the ratio of N _A /N _C exceeds 2, the C particles are insufficient and the A particles are excessive. Therefore, there is a possibility that the space formed by the C particles is reduced, and the space formed by the A particles is less likely to form a space. The neck growth is increased, and the shrinkage of the porous structure produced by sintering becomes large.

Further, there is a possibility that a large gap (void) is formed between the inner surface of the lower via hole and the porous structure on the substrate, or the porous structure or the upper and lower conductive bodies are easily peeled off from the substrate.

On the other hand, by setting both the sum N _A + N _C and the ratio N _A / N _{C to} the ranges described above, it is possible to form a stronger and less flexible metal having a thermal expansion ratio close to that of the ceramic substrate. A deformed porous structure.

Further, after the low-resistance metal having a large thermal expansion coefficient is melted, the thermal expansion of the low-resistance metal can be suppressed by the porous structure, and the thermal expansion coefficient of the upper and lower conductive bodies can be maintained as close as possible to the thermal expansion coefficient of the substrate. The residual stress of the ceramic wiring board can be adjusted to a range of 100 MPa or less.

Further, it is possible to suppress shrinkage of the porous structure, prevent generation of voids or detachment, or maintain the thermal conductivity of the upper and lower conductors in a good range.

Further, in consideration of further improving the effect, N _A + N _C is preferably 60 or more, and preferably 80 or less in the above range. Further, the ratio N _A /N _C is preferably 1 or more, and more preferably 1.5 or less in the above range.

(formation of porous structure)

When the porous structure is formed, the base after forming the upper and lower via holes is cleaned as needed. After the plate is dried, the upper and lower via holes are filled with a paste containing particles of a high melting point metal, a resin binder, and a solvent. As the filling method, a well-known coating method such as screen printing or dispenser, brush coating, and spin roll coating can be employed.

As the particles of the refractory metal, to form a ratio of the number of exposed particles A will cross-sectional view of the number N _A N _C C ratio of the particles of the sum of N _A + N _C ratio were adjusted and N _A / N _C as above In the above description, the lower conductive body is preferably a plurality of kinds of particles having different average particle diameters.

Specifically, as the particles of the high-melting-point metal, the particles having a smaller average particle diameter as the raw material of the A particles described above, the particles having the average particle diameter of the raw material of the B particles, and the C particles are used. Particles with a larger average particle size of the raw materials. Further, the above-mentioned sum N _A + N _C and the ratio N _A / N _C may be adjusted so as to be within the ranges described above by adjusting the average particle diameter or the blending ratio of the respective particles.

In the present invention, the average particle diameter of the particles of the high-melting-point metal is represented by the value of the measurement of the flow rate and the pressure drop by the air penetration in the state in which the particles are filled in the test tube. The specific surface area was calculated by the Fisher method (FSSS) in the penetration method of the average particle diameter.

In the Fisher method, the following numerical value is defined as the average particle diameter, which is obtained by measuring the height of the sample in a state in which a powder sample having a predetermined true density is filled in a test tube, and Here, the water level of the manometer measured by constant pressure air is read on the calculation table.

Examples of the resin binder include one or two or more of an acrylic binder, ethyl cellulose, nitrocellulose, and wax.

Further, as a solvent, various kinds of resins can be used to dissolve the resin binder well. The solution or dispersion is dispersed, and the particles of the high melting point metal are well dispersed to form various solvents of the paste.

Examples of the solvent include at least one of butyl carbitol and terpineol.

The blending ratio of the resin binder and the solvent is preferably 1 part by mass or more and 3 parts by mass or less per 100 parts by mass of the particles of the high melting point metal, and the solvent is 3 parts by mass or more and 15 parts by mass. In the following, the filling property of the paste for the upper and lower via holes or the amount of residual carbon during the debonding treatment may be considered, and the ratio of the two components may be set outside the ranges.

The composition of the paste is preferably adjusted so as to form a porous structure by sintering in the upper and lower via holes. Further, in order to form a porous structure in which the distribution of the space is as uniform as possible, the distribution of the low-resistance metal and the high-melting-point metal after the immersion is not biased, and it is preferable to adjust the above composition or optimize the coating method.

After the prepared paste is filled in the upper and lower via holes, it is preferred to carry out debonding treatment for removing the resin component in the paste by heating in a non-oxidizing atmosphere such as nitrogen, hydrogen or vacuum before sintering. The temperature at which the debonding agent is treated is preferably 300 ° C or more and 1000 ° C or less, and the time is preferably 0.5 hour or more and 40 hours or less.

Then, the high melting point metal is sintered in a non-oxidizing environment such as nitrogen, hydrogen or vacuum. Usually, the sintering temperature is preferably 600 ° C or more and 1200 ° C or less, and the sintering time is preferably 0.5 hours or more and 10 hours or less.

The resin component in the paste is removed by the debonding agent treatment and sintering, and the particles of the high melting point metal are in a state in which the particles of the high melting point metal are connected to each other, that is, the state in which the particles are in the neck portion, and the particles are grown in the neck portion. In the inside, the above resin component is removed to form a communication space for the low-resistance metal melting, forming three A porous structure of a mesh-like structure.

Further, a metal layer containing, for example, Ti, W, Mo, or the like may be formed on the inner surface of the upper and lower via holes before the formation of the porous structure. When the metal layer is formed, neck growth occurs between the metal layer and the particles of the high melting point metal during sintering of the paste, and the bonding strength of the porous structure to the substrate can be improved, and the bonding strength can be further reliably prevented. The porous structure or the upper and lower conductive bodies are detached from the substrate.

The metal layer can be formed, for example, by a physical vapor deposition method such as a sputtering method or a vacuum deposition method.

Further, a composite material having a composite body having the same composite structure as the upper and lower conductive bodies, that is, a composite material formed by laminating a low-resistance metal in a porous structure including particles of a high-melting-point metal, forms a unitary substrate. Even if the above and N _A + N _C or ratio N _A / N _{C are not} set to a predetermined range, there is no problem of various problems.

The reason for this is that the particles of the high melting point metal are pressed at a relatively high pressure of about 10 GPa to form a pressed body which is a precursor of the porous structure, and then sintered to form the porous structure, and the particles are highly adhered to each other. It is easy to produce neck growth during sintering.

On the other hand, in the step of forming a porous structure in the fine upper and lower via holes in the present invention, as described above, a coating method such as screen printing or dispenser, brush coating, and spin roll coating is used. Since the paste containing the particles of the high melting point metal is filled, it is basically impossible to apply pressure, or even if the pressure can be applied, it is only about 10 MPa, and the particles cannot be strongly adhered to each other.

Further, when the porous structure in the upper and lower via holes is formed by sintering the particles of the high melting point metal, or when the low resistance metal is immersed in the formed porous structure, the temperature changes from the porous structure. The surrounding substrate is subjected to tensile stress Or compressive stress, so it is easy to be destroyed. Moreover, the residual stress of the ceramic wiring board manufactured is easy to become large.

Therefore, in the present invention, unlike the production of the composite material of the block, in order to promote the growth of the neck, it is necessary to adjust the distribution of the particle diameter of the particles of the high melting point metal as described above. That is, the subject of the present invention is a problem unique to the formation of a porous structure and a vertical conductor in a fine upper and lower via.

(melting of low resistance metal)

For example, in a state in which the substrate having the porous structure formed in the upper and lower via holes is sandwiched by a plate including the low-resistance metal to be immersed, or the plate is superposed on only one side of the substrate, nitrogen gas, hydrogen gas, In a non-oxidizing environment such as a vacuum, it is heated to a temperature higher than the melting temperature of the low-resistance metal.

In this manner, the molten low-resistance metal is wet-diffused by the capillary phenomenon in the communication space in the porous structure, thereby being immersed in the porous structure to form the upper and lower conductive bodies.

Usually, the melting temperature is preferably 900 ° C or more and 1500 ° C or less, and the melting time is preferably 0.1 hour or more and 3 hours or less.

(area ratio of low resistance metal and void ratio)

The coefficient of thermal expansion of the upper and lower conductors is determined by the ratio of the presence of the low-resistance metal immersed in the porous structure containing the high-melting-point metal.

In the present invention, the upper and lower vias are formed by polishing to expose the cross section, and then any 10 sections of the cross section after the cross-section polishing (CP) processing by dry etching using Ar plasma are used, and the SEM is used at a magnification of 250 times 350 μm × 500 μm. When observing the field of view, the area S ₁ of the porous structure exposed in the field of view and the area S _{2 of the} low-resistance metal are measured by the two areas S ₁ and S ₂ according to the formula (1): area ratio (%) )=S ₂ /(S ₁ +S ₂ )×100 (1)

The area ratio is determined, and the existence ratio is expressed by the area ratio.

The area ratio is preferably 3% or more, preferably 88% or less.

When the area ratio of the low-resistance metal is less than the range, there is no possibility that the space formed in the porous structure can be completely filled by the low-resistance metal and the pores remain.

Therefore, there is also a decrease in the ratio of the low-resistance metal having a high thermal conductivity to reduce the thermal conductivity of the upper and lower conductive bodies.

On the other hand, when the area ratio of the low-resistance metal is more than the above range, the ratio of the high-melting-point metal is relatively small, so that the porous structure which cannot be maintained strong by the high-melting-point metal cannot be sufficiently obtained based on the porous material. The structure has a high strength and tends to suppress the effects of expansion and contraction of the low-resistance metal or the upper and lower conductive bodies.

Further, the ratio of the low-resistance metal having a large thermal expansion coefficient is excessively increased, and the difference in thermal expansion coefficient between the upper and lower conductors and the substrate tends to be large.

Therefore, due to these two tendencies, the residual stress of the ceramic wiring board cannot be adjusted to a range of 100 MPa or less.

On the other hand, by setting the area ratio of the low-resistance metal to the above range, the thermal conductivity of the upper and lower conductive bodies can be maintained in a good range, and the residual stress of the ceramic wiring substrate can be minimized within a range of 100 MPa or less. .

Further, in consideration of imparting a higher thermal conductivity of, for example, 180 W/mK or more to the upper and lower conductors, the area ratio of the low-resistance metal is preferably 10% in the above range. Above, it is especially good for 20% or more. In addition, when the residual stress of the ceramic wiring board is further reduced in the range of 100 MPa or less, the area ratio of the low-resistance metal is preferably 80% or less, and particularly preferably 75% or less in the above range.

The area ratio of the low-resistance metal can be adjusted by adjusting the particle size distribution of the particles of the high-melting-point metal which is the raw material of the porous structure, the viscosity of the paste, the amount of the resin binder, and the like. Regarding the distribution of the particle diameter, as explained above.

Moreover, if the viscosity of the paste is lowered or the amount of the resin binder is increased to lower the ratio of the high melting point metal contained in the paste, the use of the paste in the upper and lower conductive bodies formed by the above-described steps can be increased. The ratio of the presence of low resistance metals.

Further, the area S ₃ of the pores which are exposed in the field of view which is the same as the area ratio of the low-resistance metal, and the areas S ₁ and S ₂ which are not filled with the low-resistance metal, according to the formula (2): void ratio (%) =S ₃ /(S ₁ +S ₂ +S ₃ )×100 (2)

The void ratio determined is preferably 10% or less.

When the void ratio exceeds this range, the low-resistance metal that is immersed is not sufficiently reflowed in the porous structure, and a large amount of pores are generated in the upper and lower conductive bodies. Further, for example, when a metallization layer is formed on the surface of the substrate including the upper and lower vias, there is a possibility that the adhesion strength of the metallization layer is weakened by the gas generated from the pores, or the metal layer is peeled off, or the metal is not peeled off. The layer or the solder layer thereon or the like is cracked.

Further, the void ratio is preferably 5% or less in the above range. In the case where the void ratio exceeds the range, in the case where the thickness of the metallization layer is, for example, less than 0.5 μm, the metallization layer directly above the upper and lower conductive bodies or the solder layer thereon is strongly affected by the above pores. The cracks.

Furthermore, the pores are generated as voids in the upper and lower conductive bodies. There is also a case where the interface between the upper and lower conductors and the substrate is generated as a gap. Here, not only the void, but also the area ratio of the gap generated at the interface is included in the void ratio.

The lower limit of the void ratio is of course 0%. It is desirable to be completely void-free.

(grinding)

The surface of the substrate after the low-resistance metal is immersed is polished as needed, thereby fabricating the ceramic wiring substrate of the present invention.

The grinding method is the same as described above. That is, as the polishing method, mechanical polishing (fixed abrasive grains, free abrasive grains), chemical mechanical polishing, or the like can be mentioned.

The surface roughness (arithmetic mean roughness of the roughness curve) Ra after polishing is preferably 0.01 μm or more, more preferably 0.02 μm or more, preferably 1 μm or less, and particularly preferably 0.5 μm or less.

If the surface roughness Ra after the polishing is less than the above range, the effect of improving the adhesion of the metallized layer caused by the so-called anchoring effect may be insufficient. On the other hand, in the case where the surface roughness Ra after the polishing exceeds the above range, it becomes difficult to form a metallization layer having a uniform thickness.

The thickness of the substrate after polishing is preferably 0.1 mm or more, more preferably 0.15 mm or more, more preferably 1 mm or less, and particularly preferably 0.5 mm or less, in consideration of both the practical strength and the volume reduction of the semiconductor device.

Semiconductor device

The present invention is a semiconductor device in which a semiconductor element is mounted on the ceramic wiring board of the present invention.

In detail, for example, on the lower side of the ceramic wiring substrate of the present invention A semiconductor device is formed by forming a metallization layer on both surfaces of the upper and lower vias, and mounting a semiconductor element on the metallization layer of at least one surface via a solder layer.

(metallization layer)

The metallization layer is formed on the surface of the substrate which is formed by polishing the upper and lower vias as described above and, if necessary, to have the predetermined surface roughness Ra.

The metallization layer may have a single layer structure of only the conductive layer described below. However, it is generally preferable to form at least two layers of a laminate layer for ensuring adhesion to the substrate and a conductive layer for external connection. Further, a diffusion prevention layer may be interposed between the two layers.

The adhesion layer is formed of, for example, Ti, Cr, NiCr, Ta, Nb, TiW, or the like, to have a thickness of approximately 0.05 μm or more and 1.0 μm or less. Examples of the formation method include a physical vapor deposition method such as a sputtering method and a vacuum deposition method, and a wet plating method.

Further, the diffusion prevention layer is formed of, for example, Pt, Pd, Cu, Ni, Mo, NiCr, or the like to have a thickness of approximately 0.1 μm or more and 10 μm or less. Examples of the formation method include a physical vapor deposition method such as a sputtering method and a vacuum deposition method, and a wet plating method.

Further, the conductive layer is formed of, for example, Ag, Al, Au, or the like to have a thickness of approximately 0.1 μm or more and 10 μm or less. Examples of the formation method include a physical vapor deposition method such as a sputtering method and a vacuum deposition method, and a wet plating method.

The metallization layer of any of the single layer and the buildup layer can form a fine pattern by photolithography.

Further, the metallization layer can also be formed by a thick film method (Au, Cu, etc.). Further, it is also possible to form a film by plating Ni or Ni/Au on a pattern formed by a thick film method.

Further, the metallized layer may be formed by patterning on the surface of the substrate by a screen printing method adjusted to a paste suitable for screen printing.

The thickness of the metallized layer by the method can be arbitrarily changed by, for example, about 5 μm to 100 μm by adjusting the viscosity of the paste for screen printing. Among them, it is generally about 20 μm, and may be set to 100 μm or more when a large current is applied.

Further, the metallization layer formed by the method may be further patterned by polishing or chemical etching as needed. Further, a film may be formed on the metallization layer by Ni or Ni/Au plating.

A resistive film such as NiCr or TaN may be formed on or near the metallization layer formed by the method as needed.

Further, depending on the structure of the semiconductor device or the like, the metallization layer may be formed without a pattern surface without performing the pattern formation as described above.

Further, in order to mount a semiconductor element on at least one surface of the metallization layer as described above, it is preferable to form a pattern of a solder layer such as AuSn.

Usually, a plurality of semiconductor device regions are formed on one substrate, and after the formation of the metallization layer and the solder layer is completed, the regions are cut into various regions by a well-known method such as dicing or laser irradiation, and then mounted at a predetermined position. Semiconductor component. However, it can also be cut into various regions after the semiconductor device is mounted.

When a semiconductor element is mounted, various conventionally known methods such as a die bonding method using AuSn solder can be employed.

(semiconductor component)

The semiconductor element is not particularly limited, and for example, Si, GaAs, InP, or the like can be mounted. Various semiconductor elements such as GaN and SiC. The size of the semiconductor element is also not particularly limited.

<Example> <Example 1> (formation of upper and lower vias)

The substrate of the commercially available AlN sintering system was cut and polished to a length of 100 mm × a width of 100 mm × a thickness of 0.5 mm.

Then, a Y-, Yttrium Aluminum Garnet laser is used to form a length of 35 x 80 wide, for a total of 2,800 Lower via hole above 0.3mm. The distance between the centers of the adjacent upper and lower via holes is set to 2.5 mm in the longitudinal direction and 1.0 mm in the lateral direction. The positional accuracy of the upper and lower via holes formed was measured using a tool microscope, and the result was ±20 μm.

(Preparation of paste for porous structure)

To 100 parts by mass of the W particles as the high-melting-point metal, 2 parts by mass of the acrylic binder as a resin binder and 5 parts by mass of butyl carbitol as a solvent were blended, and the paste was adjusted to adjust the paste.

In addition, as W particles, 24 parts by mass of W particles (B10 manufactured by ALMT Co., Ltd.) having an average particle diameter of 1.2 μm and W particles having an average particle diameter of 3.1 μm (C50 manufactured by ALMT Co., Ltd.) of 51 parts by mass are used. And W particles having an average particle diameter of 6.0 μm [Manufactured by ALMT Co., Ltd. D20] 25 parts by mass

Three kinds (a total of 100 parts by mass) of mixed particles.

(formation of porous structure)

The substrate on which the upper and lower via holes were formed was immersed in isopropyl alcohol (IPA), ultrasonically cleaned, and the IPA was scattered by air blowing, and then heated in an oven at 100 ° C for 10 minutes to dry.

Then, the previously prepared paste is filled in the lower via hole of the substrate by screen printing, and then subjected to debonding treatment by heating at 600 ° C for 3 hours in a nitrogen atmosphere, and then borrowed in a hydrogen atmosphere. The W particles were sintered by heating at 1000 ° C for 1 hour to form a porous structure.

(melting of low resistance metal)

The substrate is sandwiched by a Cu plate having a thickness of 0.3 mm, and is immersed in a porous structure in the upper and lower via holes as a low-resistance metal by heating at 1200 ° C for 0.5 hours in a hydrogen atmosphere. Cu forms a lower conductive body having a composite structure of Cu and W.

Then, both surfaces of the substrate were polished so that the thickness of the substrate was 0.4 mm, and the surface roughness Ra of both surfaces was 0.5 μm, thereby manufacturing a ceramic wiring substrate.

(Measurement of residual stress)

The residual stress of the ceramic wiring board produced by the X-ray stress measurement method was found to be 68 MPa, and the X-ray stress measurement method was used. The result of X-ray diffraction of a 0.3 mm collimator on a portion 0.3 mm away from the upper and lower conductors in the plane direction of the substrate, and the Young's modulus (=280 GPa) and Poisson's ratio (=0.24) of the ceramic forming the substrate. Calculate the stress.

(section observation 1)

The lower conductive body of the ceramic wiring substrate was ground to expose the cross section, and then the SEM was used to observe the cross-section polishing (CP) processed by the dry etching using Ar plasma at a magnification of 1000 times the field of view of 90 μm × 130 μm. Any 10 places.

Further, all the high-melting-point metal particles exposed in the above-mentioned field of view are classified into the A-C particles described above, and the number of each of them is counted, and based on the result, the total number of the A-C particles is determined by the A-particles. The following results were obtained by taking the ratio N _A (%), the ratio of the number of C particles N _C (%), the sum of the two N _A + N _C , and the ratio N _A / N _C .

N _A :37

N _C : 32%

N _A +N _C :69

N _A / N _C : 1.16

(section observation 2)

The lower conductive body of the ceramic wiring substrate was ground to expose the cross section, and then the SEM was used to observe the cross-section polishing (CP) processed by dry etching using Ar plasma at a magnification of 250 times 350 μm × 500 μm. at arbitrary 10 points, the measurement area of the porous structure are exposed in the field of view of S _1, area _2, and the porosity of the unfilled areas of low resistance metal of low resistance metal S S _3, (1) the request in accordance with the above formula The area ratio of the low-resistance metal was 46%. Further, the void ratio was determined according to the above formula (2), and as a result, it was less than 1%.

(Production of semiconductor device)

On both surfaces of the ceramic wiring board to be manufactured, a metallization layer constituting the circuit pattern was formed by the following method.

First, the ceramic wiring board was immersed in IPA, ultrasonically cleaned, and the air was scattered by the blast, and then heated in an oven oven at 100 ° C for 10 minutes to dry.

Then, on the both surfaces of the ceramic wiring board, a Ti film of 0.05 μm as an adhesion layer, 0.2 μm of a Pt film as a diffusion prevention layer, and 0.2 μm of an Au film as a conductive layer were sequentially formed by using a sputtering apparatus to form three layers. The metallization layer of the structure.

The film formation is performed in an environment of a vacuum of 1 × 10 ^-4 Pa in a sputtering apparatus, and the ceramic wiring board is heated at 200 ° C for 5 minutes by a halogen heater, and then dry cleaning by Ar plasma is performed as usual. Implementation of the law.

Then, a Si element having a length of 1 mm, a width of 1 mm, and a thickness of 0.3 mm was mounted on the formed metallization layer through a solder foil having a thickness of 20 μm to fabricate a semiconductor device.

(reliability test 1)

The fabricated semiconductor device was kept at a low temperature of -40 ° C for 30 minutes, and then held at a high temperature of 120 ° C for 30 minutes. This operation was performed as one cycle, and a temperature cycle test of 1000 cycles was repeated for one cycle. It is kept for 1000 hours in a high temperature and high humidity environment at 85 ° C and a relative humidity of 85%.

And, on the ceramic wiring substrate of the semiconductor device after the polishing is maintained The lower via was exposed to expose the cross section, and then SEM was used to obtain a field of view of 1000 μm × 130 μm at a magnification of 1000 μm × 130 μm, and any 10 sections of the cross section after dry etching by dry etching using Ar plasma were observed, and evaluated by the following criteria. The usual reliability, the result is level A.

Level A: No cracks at all.

Grade B: Cracks are visible on the substrate side, but only cracks having a crack length of 10 μm or less which have no influence on mechanical properties.

Grade C: Cracks having a crack length of more than 10 μm and a thickness of 100 μm or less which have an influence on joint characteristics or electrical and thermal characteristics are observed.

Grade D: Large cracks with crack lengths greater than 100 μm are visible.

(Reliability test 2)

The following reliability test was carried out under conditions more stringent than the reliability test 1 described above.

That is, the fabricated semiconductor device was held in a low temperature environment of -65 ° C for 30 minutes, and then held in a high temperature environment of 150 ° C for 30 minutes, and this operation was performed as one cycle, and after repeating the temperature cycle test of 1000 cycles, It was kept at a temperature of 130 ° C and a relative humidity of 85% in a high temperature and high humidity environment for 1,000 hours.

Then, the upper and lower conductive bodies of the ceramic wiring substrate of the semiconductor device after polishing were polished to expose the cross section, and then the SEM was used to observe the cross-section polishing (CP) by dry etching using Ar plasma at a magnification of 1000 times the field of view of 90 μm × 130 μm. At any 10 points of the processed profile, the reliability was evaluated on the same basis as the reliability test 1, and the result was grade A.

<Examples 2 to 29, Comparative Examples 1 to 12>

A paste was prepared in the same manner as in Example 1 except that the average particle diameter and the mixing ratio of the three types of W particles were changed, and a ceramic wiring board was produced to produce a semiconductor device, and each of the above tests was carried out.

<Example 30>

As the particles of the high-melting-point metal, 25 parts by mass of Mo particles (TMO-10 manufactured by ALMT Co., Ltd.) and Mo particles having an average particle diameter of 3.3 μm (TMO-30 manufactured by ALMT Co., Ltd.) are used. 49 parts by mass, and Mo particles having an average particle diameter of 5.4 μm [TMO-50 manufactured by ALMT Co., Ltd.] 26 parts by mass

A paste was prepared in the same manner as in Example 1 except that the mixed particles of three types of Mo particles (total of 100 parts by mass) were used in place of the W particles, and a ceramic wiring board was produced to produce a semiconductor device, and each of the above tests was carried out.

<Example 31>

A paste was prepared in the same manner as in Example 1 except that Ag was used instead of Cu as a low-resistance metal, a ceramic wiring board was produced, a semiconductor device was produced, and each test described above was carried out.

<Example 32>

A paste was prepared in the same manner as in Example 30 except that Ag was used instead of Cu as a low-resistance metal, and a ceramic wiring substrate was produced to fabricate a semiconductor device. And the above tests were carried out.

<Primary Example 1>

A paste was prepared in the same manner as in Example 1 except that 100 parts by weight of W particles (C50 manufactured by ALMT Co., Ltd.) having an average particle diameter of 3.1 μm was used as the W particles, and a ceramic wiring board was produced. A semiconductor device, and each of the above tests was carried out.

The results are shown in Tables 1 to 3.

According to the results of Examples 1 to 32 and Comparative Examples 1 to 12 and the conventional example 1 of Tables 1 to 3, it is understood that the usual reliability is set by setting the residual stress of the ceramic wiring board to be manufactured to 100 MPa or less. For the A grade, the reliability under more severe conditions is set to A to B grade, which improves the reliability of the semiconductor device.

In addition, according to the results of the examples 1 to 32, it is understood that the reliability of the ceramic wiring board is 80 MPa or less in the above range, and the reliability under more severe conditions is also set to A level, thereby further improving the semiconductor device. reliability.

Further, according to the results of Examples 1 to 32, Comparative Examples 1 to 12, and Conventional Example 1, it was found that the upper and lower conductive bodies were made into a porous structure in which a low-resistance metal was immersed in a sintered body containing high-melting-point metal particles. In the case of the composite structure, in order to set the residual stress of the ceramic wiring board to a range of 100 MPa or less, the ratio N _A (%) of the A particles having a maximum major axis of 1.0 μm or less and the maximum long diameter of 5.0 μm or more are used. C ratio of the number of particles N _C (%) and the N _A + N _C is 50 or more and 90 or less, and than N _A / N _C is set to 2/3 or more and 2 or less.

Further, in the case of the above-described composite structure, in order to set the residual stress of the ceramic wiring board to 80 MPa or less, the above-mentioned N _A + N _C is preferably 60 or more, preferably 80 or less, in the above range. N _A /N _C is preferably 1 or more, and preferably 1.5 or less in the above range.

Further, according to the results of Examples 1 and 30 to 32, it is understood that even if Mo is used instead of W as the high melting point metal which is a raw material of the porous structure, or Ag is used instead of Cu as the low resistance metal, the above and N _A + are The same result can be obtained by setting N _C and the ratio N _A /N _C in the above range.

Claims (11)

A ceramic wiring board comprising: a ceramic substrate formed in a plate shape and having a vertical via hole penetrating through the thickness direction thereof; and a vertical conductive body filled in the upper and lower via holes and containing a selected from the group consisting of Cu, Ag, and A composite material of at least one of a low-resistance metal selected from the group consisting of Au and at least one high-melting-point metal selected from the group consisting of W and Mo; and a residual stress of 100 MPa or less. The ceramic wiring board of claim 1, wherein the residual stress is 80 MPa or less. The ceramic wiring board according to claim 1 or 2, wherein the upper and lower conductive bodies have a composite structure in which the low-resistance metal is immersed in a porous structure including a sintered body of particles of the high-melting-point metal, The ratio of the number of particles having a maximum long diameter of 1.0 μm or less among all the high melting point metal particles exposed in the predetermined field of view of the cross section of the upper and lower conductive bodies is N _A (%), and the particles having a maximum long diameter of 5.0 μm or more When the number ratio is N _C (%), the sum of N _A and N _C and N _A + N _C is 50 or more and 90 or less, and the ratio N _A /N _C is 2/3 or more and 2 or less. The ceramic wiring board of claim 3, wherein the sum of N _A + N _C is 60 or more and 80 or less. The ceramic wiring board of claim 3, wherein the ratio N _A /N _C is 1 or more and 1.5 or less. The ceramic wiring board according to any one of claims 3 to 5, wherein the area S ₁ of the porous structure exposed in a predetermined field of view of the cross section of the upper and lower conductive bodies, and the low resistance metal The area S _{2 is} an area ratio of the low-resistance metal obtained by the formula (1): area ratio (%) = S ₂ /(S ₁ + S ₂ ) × 100 (1) of 3% or more and 88% or less. The ceramic wiring board of claim 6, wherein the area S ₃ of the pores which are not filled in the predetermined field of view and which are not filled with the low-resistance metal, and the areas S ₁ and S _{2 are} according to the formula (2): void Rate (%) = S ₃ / (S ₁ + S ₂ + S ₃ ) × 100 (2) The void ratio determined was 10% or less. The ceramic wiring board according to any one of claims 1 to 7, wherein the upper and lower via holes are formed after the sintered substrate. The ceramic wiring board according to any one of claims 1 to 8, wherein the substrate comprises at least one selected from the group consisting of AlN, Al ₂ O ₃ , Si ₃ N ₄ , and SiC. The ceramic wiring board according to any one of the items 1 to 9, wherein the inner diameter of the upper and lower via holes is 0.1mm or more and 0.3mm or less. A semiconductor device in which a semiconductor element is mounted on a ceramic wiring board according to any one of the above claims.