WO2015141344A1 - Ceramic wiring board and semiconductor device - Google Patents

Abstract

[Problem] To provide a ceramic wiring board having a high degree of reliability with low susceptibility to cracking due to heat load and temperature cycles and peeling of a metalization layer and a solder layer, and to provide a semiconductor device. [Solution] In the present invention, a ceramic wiring board is obtained by filling an up/down conduction hole formed through a ceramic board in the direction of thickness thereof with an up/down conductor comprising a composite material containing at least one low resistance metal selected from the group consisting of Cu, Ag, and Au, and at least one high melting point metal selected from the group consisting of W and Mo, the residual stress being 100 MPa or less. In a semiconductor device of the present invention, a semiconductor element is installed on the ceramic wiring board.

Description

Ceramic wiring board and semiconductor device

The present invention relates to a ceramic wiring board including a substrate formed in a plate shape with ceramic and a vertical conductive body penetrating in the thickness direction of the substrate, and a semiconductor device using the ceramic wiring substrate.

For example, a vertical conduction hole (via) is formed by forming a vertical conduction hole penetrating in the thickness direction at a predetermined position of a substrate formed in a plate shape by a ceramic such as AlN, Al ₂ O ₃ , Si ₃ N ₄ , or SiC. Is used for mounting semiconductor elements.

However, if the entire upper and lower conductors are made of a low-resistance metal such as Cu, Ag, or Au as a conductive material, the coefficient of thermal expansion between the low-resistance metal and the ceramic is greatly different. In addition, local stress is applied to the solder layer and the metallized layer and the solder layer are liable to crack, and the crack causes a problem that the reliability of mounting the semiconductor element is remarkably lowered. Moreover, there is a possibility that a large thermal stress is applied to the substrate itself or the mounted semiconductor element.

Therefore, it has been studied that the vertical conductor is formed of a composite material containing a low resistance metal such as Cu and a high melting point metal such as W or Mo, and has a thermal expansion coefficient close to that of a ceramic substrate.

For example, in Patent Document 1, an upper and lower conduction hole penetrating in the thickness direction of a substrate is formed in advance on a plate body (ceramic green sheet) of a precursor that becomes a ceramic material before sintering, and a high melting point is formed there. The ceramic substrate and the vertical conductive body made of the composite material filled in the vertical conductive hole of the substrate are integrated by filling the paste containing the metal and the low resistance metal and then sintering the whole. Is formed.

Further, in Patent Document 2, the upper and lower conductive holes are formed in the ceramic green sheet before sintering, and the paste containing the high melting point metal particles is filled therein, and then the whole is sintered, After integrally forming a porous structure made of a sintered body of a large number of high melting point metal particles filled in the vertical conduction holes of the substrate, the low resistance metal is infiltrated into the formed porous structure. Thus, a vertical conductor having a composite structure in which a low-resistance metal is filled in a porous structure made of a refractory metal is formed.

In Patent Document 3, a vertical conduction hole is formed at a predetermined position of a substrate formed by previously sintering a ceramic green sheet, and then a paste containing particles of a high melting point metal such as W or Mo is formed in the vertical conduction hole. After filling and sintering to form a porous structure made of a sintered body of a large number of high melting point metal particles, a low resistance metal is infiltrated into the formed porous structure, and the same as above A vertical conductor having a composite structure is formed. According to this forming method, the positional accuracy of the upper and lower conductive bodies can be improved compared to the previous two methods.

However, as described in each of the above patent documents, all of the conventional ceramic wiring boards provided with the upper and lower conductive bodies made of the composite material of the refractory metal and the low resistance metal have metallized layers for mounting semiconductor elements on the surface thereof. Cracks especially near the surface of the substrate due to thermal load and temperature cycle such as when forming a solder layer, mounting a semiconductor element on the formed metallized layer, solder layer, or operating the mounted semiconductor element There is a problem that the reliability is low because the metallized layer or the solder layer is easily peeled off.

JP 2000-22338 A JP-A-5-267849 Japanese Examined Patent Publication No. 7-101724

An object of the present invention is to provide a highly reliable ceramic wiring board which is hard to cause cracks due to heat load or temperature cycle, or to peel off a metallized layer or a solder layer.

Another object of the present invention is to provide a highly reliable semiconductor device in which a semiconductor element is mounted on such a ceramic wiring board.

The present invention is selected from the group consisting of a ceramic substrate formed in the shape of a plate and having vertical conduction holes formed through the thickness direction, and Cu, Ag, and Au filled in the vertical conduction holes Ceramic comprising a vertical conductor made of a composite material comprising at least one low-resistance metal selected from the group consisting of W and Mo, and having a residual stress of 100 MPa or less It is a wiring board.

Further, the present invention is a semiconductor device in which a semiconductor element is mounted on the ceramic wiring board of the present invention.

According to the present invention, it is possible to provide a highly reliable ceramic wiring board which is difficult to crack due to a thermal load or a temperature cycle, or to peel off a metallized layer or a solder layer.

Further, according to the present invention, a semiconductor device having a high reliability can be provided by mounting a semiconductor element on such a ceramic wiring board.

<Ceramic wiring board>
The present invention includes a ceramic substrate formed in a plate shape and having vertical conduction holes formed through the thickness direction, and a group consisting of Cu, Ag, and Au filled in the vertical conduction holes of the substrate. A vertical conductor made of a composite material including at least one low-resistance metal selected from the group consisting of W and Mo, and a residual stress of 100 MPa or less It is a certain ceramic wiring board.

According to the present invention, by adjusting the residual stress of the ceramic wiring substrate to a range of 100 MPa or less as described above, a crack is generated near the surface of the substrate when a thermal load or a temperature cycle is applied, or a metallized layer Further, the reliability of the ceramic wiring board can be improved by suppressing the peeling of the solder layer. This is due to the following reasons.

That is, even if the upper and lower conductors are formed of a composite material of a refractory metal and a low resistance metal, the difference in coefficient of thermal expansion from the substrate is not only reduced, but not completely eliminated. It causes the residual stress of the wiring board.

In particular, in the method of forming the vertical conductor described in Patent Documents 2 and 3, when infiltrating a low-resistance metal into the porous structure, it must be heated to a high temperature of 1000 ° C. or higher. Based on the difference, a relatively large stress is generated in both the substrate and the upper and lower conductors, and remains as a residual stress in the ceramic wiring substrate.

According to the inventor's study, when the residual stress exceeds 100 MPa, the thermal load and temperature cycle described above are applied to the ceramic wiring board, causing cracks in the vicinity of the surface of the board, the metallized layer, The solder layer is easily peeled off.

When these problems occur, it is natural that the semiconductor element cannot be operated normally.

On the other hand, if the residual stress of the ceramic wiring board is adjusted to a range of 100 MPa or less, cracks may occur near the surface of the board even if the thermal load or temperature cycle is applied, or the metallized layer or solder layer may be peeled off. It becomes possible to make it difficult.

In addition, the effect of suppressing cracking near the surface of the board when a thermal load or temperature cycle is applied, or the metallized layer or solder layer from peeling off is further improved, and the reliability of the ceramic wiring board is improved. In view of further improving the properties, the residual stress is preferably 80 MPa or less even in the above range.

Needless to say, the lower limit of the residual stress is 0 MPa. Ideally, no residual stress remains.

In the present invention, the residual stress of such a ceramic wiring board is obtained by X-ray diffraction using a φ0.3 mm collimator at a position 0.3 mm away from the vertical conductor in the plane direction of the board, and the ceramic forming the board. It is expressed by the value obtained by the X-ray stress measurement method for calculating the stress from the Young's modulus and Poisson's ratio.

The ceramic wiring board of the present invention, for example, a step of forming a vertical conduction hole by penetrating in a thickness direction after sintering at a predetermined position of a substrate formed by sintering a precursor such as a ceramic green sheet,
Filling the formed upper and lower conductive holes with paste containing refractory metal particles, sintering a number of refractory metal particles by sintering to form a porous structure, and in the formed porous structure A step of infiltrating a low resistance metal to form a vertical conductor,
It is preferable to manufacture through this.

<substrate>
As the ceramic for forming the substrate, various ceramics having high heat dissipation properties that can cope with high output of the semiconductor element can be used. In particular, in order to improve heat dissipation, the thermal conductivity of the ceramic forming the substrate is preferably 80 W / mK or more. The upper limit of the thermal conductivity is not particularly limited, but is preferably 400 W / mK or less.

Also to minimize the difference in thermal expansion coefficient between the semiconductor element to be mounted, it is preferred thermal expansion coefficient of the ceramic forming the substrate is 2.5 × 10 ^-6 / ℃ above, 7.0 × 10 ^{- It} is preferably ⁶ / ° C or lower.

Examples of such ceramic include AlN, Al ₂ O ₃ , Si ₃ N ₄ , and SiC. These ceramic substrates can be formed in the same manner as before.

That is, as described above, after sintering the ceramic green sheet as a precursor, the substrate is formed by polishing the surface as necessary. The sintering conditions, temperature, polishing method, and the like can be the same as in the prior art. For example, examples of the polishing method include mechanical polishing (fixed abrasive grains, loose abrasive grains), chemical mechanical polishing, and the like.

<Vertical conduction hole>
The hole diameter of the vertical conduction hole is preferably φ0.1 mm or more, and preferably φ0.3 mm or less.

If the pore diameter is less than this range, it may be difficult to fill the upper and lower conductive holes with a paste containing refractory metal particles that are the basis of the porous structure. On the other hand, when the pore diameter exceeds the above range, a porous structure formed by filling and sintering the paste, and a vertical conductive body formed by infiltrating a low-resistance metal into the porous structure. However, there is a possibility that it will easily fall off the substrate in the subsequent process.

However, although it is necessary to devise the viscosity of the paste, etc., the hole diameter may be smaller than φ0.1 mm depending on the wiring arrangement in the substrate, for example, in order to improve electrical characteristics, thermal characteristics, etc. The hole diameter may be larger than φ0.3 mm.

The upper and lower conductive holes are preferably formed later on a substrate that has been previously sintered and formed into a plate shape as described above. Thereby, the positional accuracy can be improved as compared with the method of drilling before sintering. For example, the positional accuracy is not limited to this, but can be about ± 50 μm or less.

In order to form the upper and lower conductive holes later on the previously sintered substrate, various methods such as a method using a laser, a method using a micro drill, and a method using a micro blast can be employed.

Among these, in the method using a laser or a micro drill, the vertical conduction hole can be automatically formed at a predetermined formation position by programming the formation position of the vertical conduction hole in the processing machine.

On the other hand, in the method using microblasting, for example, a resist pattern having a desired pattern is formed by a photolithographic method using a photoresist agent for blasting made of, for example, a urethane-based resin, and then blasting is performed on the resist pattern. After selectively perforating the uncovered portion, the resist is peeled off and removed to form a vertical conduction hole at a predetermined formation position.

<Vertical conductor>
As described above, the vertical conductor is formed by first sintering a large number of particles of at least one refractory metal selected from the group consisting of W and Mo in the vertical conduction hole to form a porous structure. Then, it is preferable that at least one low-resistance metal selected from the group consisting of Cu, Ag, and Au is infiltrated into the porous structure to form a composite structure. The porous structure may further contain C.

In order to adjust the residual stress of the ceramic wiring board provided with the upper and lower conductive bodies having such a composite structure to the above-described range of 100 MPa or less, the distribution of the particle size of the particles of the refractory metal is adjusted to obtain a stronger porous material. A structure may be formed.

Specifically, the number ratio N _A (%) of particles having a maximum major axis of 1.0 μm or less (referred to as “A particles”) in a cross section of a vertical conductor formed by infiltrating a low-resistance metal into a porous structure. ) And the number ratio N _C (%) of particles having a maximum major diameter of 5.0 μm or more (referred to as “C particles”) N _A + N _C is 50 or more and 90 or less, and the ratio N _A / N _C is 2 / It is preferable to adjust the structure of the porous structure so as to be 3 or more and 2 or less.

In the present invention, the sum N _A + N _C and the ratio N _A / N _C are determined by the following method.

That is, the upper and lower conductive bodies formed are polished to expose the cross section, and then subjected to cross section polishing (CP) processing that is dry-etched with Ar plasma, and any 10 positions in the cross section are scanned using a scanning electron microscope (SEM). When observing in a field of view of 1000 μm and 90 μm × 130 μm, all the high melting point metal particles exposed in the field of view are the above A particles and C particles, and the maximum major axis between them exceeds 1.0 μm. The particles are classified into particles of less than 5.0 μm (referred to as “B particles”) and the number of each is counted.

At this time, what was originally a plurality of particles was grown by the sintering process and the grain boundary disappeared, and the major axis was measured as one particle and any of A particle to C particle. Classify and count.

Next, the number ratio N _A (%) of the _A particles and the number ratio N _C (%) of the C particles in the total number of A particles to C particles are calculated, and the sum N _A + N _C and the ratio N _A / N are calculated from the results. _{Find C.}

By setting the sum N _A + N _C and ratio N _A / N _C within the above ranges, neck growth is sufficiently generated between particles of the refractory metal forming the porous structure, and the porous structure is strong. A structure can be formed, and the residual stress of the ceramic wiring board can be adjusted to a range of 100 MPa or less.

That is, the C particles function to secure a large space for low resistance metal infiltration between the particles by contact between adjacent C particles.

Also, the B particles having a smaller particle diameter than the C particles function to enter the space formed by the C particles and adjust the size of the space. That is, it functions to adjust the ratio of the porous structure and the low resistance metal infiltrated into the porous structure.

The A particles having the smallest particle size enter the gap near the contact point between the C particles and function to promote neck growth between the C particles. That is, it functions to increase the neck growth location between the C particles, improve the sinterability, and form a strong porous structure.

The fact that the sum N _A + N _C and the ratio N _A / N _C both satisfy the above range means that the mixing ratio of the three types of particles A to C is defined within a predetermined range.

If the sum N _A + N _C is less than 50, there will be an excessive amount of B particles having an intermediate particle size, and many B particles will enter the space formed by the C particles, thereby narrowing the space more than necessary. There is a fear.

For this reason, a sufficient amount of low resistance metal cannot be infiltrated into the space, resulting in voids, and the ratio of low resistance metal having high thermal conductivity is reduced, so that the heat of the upper and lower conductors is reduced. There is a risk of problems such as a decrease in conductivity.

On the other hand, when the sum N _A + N _C exceeds 90, the B particles are insufficient, and the space formed by the C particles may not be appropriately filled with the B particles.

Therefore, excessive low-resistance metal is infiltrated in the space, and the difference in thermal expansion coefficient between the upper and lower conductive bodies and the substrate becomes large, and the residual stress of the ceramic wiring board may not be adjusted to a range of 100 MPa or less. .

In addition, when the ratio N _A / N _C is less than 2/3, the A particles are insufficient, so that the A particles can improve the sinterability and increase the neck growth location between the C particles to form a strong porous structure. The effect of forming may be insufficient.

For this reason, a part or the whole of the porous structure is destroyed at the time of infiltration of the low resistance metal, and the expansion and contraction of the low resistance metal, and hence the upper and lower conductive bodies, are expanded based on the high strength of the porous structure. The suppression effect cannot be obtained sufficiently, and the residual stress of the ceramic wiring board may not be adjusted to a range of 100 MPa or less.

Further, when the ratio N _A / N _C is much smaller even in the range of less than 2/3, the number of neck growth points between the C particles is greatly reduced, and one of the high melting point metal particles is infiltrated with the low resistance metal. The part may be pushed out of the vertical conduction hole.

For this reason, the ratio of the low-resistance metal is excessively increased, and the difference in the coefficient of thermal expansion between the upper and lower conductive bodies and the substrate is increased, so that a porous structure having sufficient strength formed integrally cannot be formed. In combination, the residual stress of the ceramic wiring board may not be adjusted to a range of 100 MPa or less.

On the other hand, when the ratio N _A / N _C exceeds 2, the number of C particles is insufficient and the number of A particles is too large, so that the space formed by the C particles is reduced and a space formed by the A particles is formed. There is a possibility that the neck growth which is difficult to increase and the shrinkage of the porous structure due to the sintering will increase.

For this reason, a large gap (void) may be formed between the inner surface of the vertical conduction hole of the substrate and the porous structure, or the porous structure and the vertical conduction body may easily fall off the substrate.

On the other hand, by defining both the sum N _A + N _C and the ratio N _A / N _C within the above-described range, the refractory metal having a thermal expansion coefficient close to that of a ceramic substrate is stronger and less likely to be deformed. A porous structure can be formed.

Therefore, after infiltrating a low-resistance metal having a large thermal expansion coefficient, the thermal expansion of the low-resistance metal is suppressed by the porous structure, and the thermal expansion coefficient of the upper and lower conductive bodies is as close as possible to the thermal expansion coefficient of the substrate. Therefore, it is possible to adjust the residual stress of the ceramic wiring board to a range of 100 MPa or less.

In addition, it is possible to suppress the shrinkage of the porous structure to prevent voids and dropouts, and to maintain the thermal conductivity of the upper and lower conductive bodies in a favorable range.

In consideration of further improving this effect, the sum N _A + N _C is preferably 60 or more, and more preferably 80 or less, even in the above range. Further, the ratio N _A / N _C is preferably 1 or more in the above range, and is preferably 1.5 or less.

(Formation of porous structure)
In order to form the porous structure, the substrate after forming the vertical conduction holes is washed and dried as necessary, and then the refractory metal particles, the resin binder, and the solvent are contained in the vertical conduction holes. Fill with paste containing etc. As a filling method, a known coating method such as screen printing, dispenser, brush coating, spin roller coating or the like can be employed.

As the high melting point metal particles, the sum N _A + N _C and the ratio N _A / N _C of the number ratio N _A of the A particles exposed in the cross section and the number ratio N _C of the C particles are adjusted to the ranges described above. In order to form the upper and lower conductive bodies, it is preferable to use, for example, a plurality of types of particles having different average particle sizes, for example.

Specifically, as the particles of the refractory metal, the particles having a small average particle size that is the basis of the A particles described above, the particles having a medium average particle size that is the basis of the B particles, A combination of particles having a large average particle size is used. Then, the sum N _A + N _C and the ratio N _A / N _C may be adjusted to be in the ranges described above by adjusting the average particle size and the blending ratio of each particle.

In the present invention, the average particle diameter of the refractory metal particles is determined by allowing the air to permeate in a state where the sample tube is filled with the particles, and calculating the average particle diameter by obtaining the specific surface area from the measurement results of the flow velocity and the pressure drop. Among the methods, it is expressed by a value measured by the Fisher method (FSSS).

That is, in the Fischer method, a calculator is calculated from the porosity determined by measuring the sample height in a state where a powder sample of a predetermined true density is filled in the sample tube, and the manometer water level measured by passing constant pressure air therethrough. The numerical value read on the chart is defined as the average particle diameter.

Examples of the resin binder include one or more of acrylic binder, ethyl cellulose, nitrocellulose, wax and the like.

Further, as the solvent, various solvents that can dissolve or disperse the resin binder well and can disperse the high melting point metal particles to form a paste can be used.

Examples of such a solvent include at least one kind such as butyl carbitol and terpineol.

The blending ratio of the resin binder and the solvent is usually 1 to 3 parts by mass of the resin binder and 3 to 15 parts by mass of the solvent per 100 parts by mass of the high melting point metal particles. However, it is possible to make the blending ratio of both components out of these ranges in consideration of the filling property of the paste into the upper and lower conductive holes, the amount of remaining carbon during the binder removal treatment, and the like.

The composition of the paste is preferably adjusted so that a porous structure is formed in the vertical conduction holes by sintering. In addition, in order to avoid unevenness in the distribution of the low resistance metal and the high melting point metal after the infiltration, the above composition is adjusted or the coating method is optimized in order to form a porous structure having a uniform spatial distribution as much as possible. It is preferable to do this.

After filling the prepared paste into the upper and lower conductive holes, it is preferable to remove the resin in the paste by heating in a non-oxidizing atmosphere such as nitrogen, hydrogen or vacuum prior to sintering. . The temperature of the binder removal treatment is preferably 300 ° C. or more and 1000 ° C. or less, and the time is preferably 0.5 hours or more and 40 hours or less.

Next, the refractory metal is sintered in a non-oxidizing atmosphere such as nitrogen, hydrogen or vacuum. In general, the sintering temperature is preferably 600 ° C. or more and 1300 ° C. or less, and the sintering time is preferably 0.5 hours or more and 10 hours or less.

The resin component in the paste is removed by the above binder removal and sintering, and the particles of the high melting point metal are connected to each other by the grain growth during sintering, that is, the particles are neck-grown. In addition, a space in which the resin component is removed and a low-resistance metal is infiltrated is formed in the interior, and a porous structure having a three-dimensional network structure is formed.

Note that a metal layer made of, for example, Ti, W, Mo, or the like may be formed on the inner surface of the vertical conduction hole prior to the formation of the porous structure. When the metal layer is formed, neck paste growth occurs between the metal layer and the refractory metal particles during sintering of the paste, so that the bonding strength of the porous structure to the substrate can be improved. It is possible to more reliably prevent the vertical conductor from falling off the substrate.

The metal layer can be formed by physical vapor deposition such as sputtering or vacuum vapor deposition.

By the way, the whole is formed by a bulk composite material having the same composite structure as the vertical conductor, that is, a composite material formed by infiltrating a low resistance metal into a porous structure made of particles of a high melting point metal. In such a substrate, there is no possibility that various problems will occur even if the above-mentioned sum N _A + N _C and ratio N _A / N _C are not specified within a predetermined range.

This is because the high melting point metal particles are pressed at a high pressure of about 10 GPa to form a press body as a precursor of the porous structure, and then sintered to form the porous structure. This is because the adhesiveness is high and neck growth is likely to occur during sintering.

On the other hand, in the step of forming the porous structure in the fine vertical conduction hole in the present invention, as described above, the paste containing the particles of the refractory metal is applied to the screen printing, the dispenser, the brush coating, the spin roller. Since it is filled by a coating method such as coating, the pressure can hardly be applied, or even if it can be applied, it is only about several tens of MPa, and the particles cannot be strongly adhered to each other.

In addition, the porous structure in the vertical conduction hole is formed by sintering high-melting point metal particles to form the porous structure or infiltrating the low-resistance metal into the formed porous structure. It is easily broken because it receives tensile stress or compressive stress from the surrounding substrate due to the change in temperature. Moreover, the residual stress of the manufactured ceramic wiring board tends to increase.

Therefore, in the present invention, unlike the production of the bulk composite material, it is necessary to adjust the particle size distribution of the refractory metal particles as described above in order to promote neck growth. That is, the subject of this invention is a subject peculiar when forming a porous structure and by extension, a vertical conduction body in a fine vertical conduction hole.

(Low resistance metal infiltration)
For example, nitrogen, hydrogen, vacuum, etc. with a plate made of a low resistance metal that infiltrates the upper and lower sides of the substrate on which the porous structure is formed in the vertical conduction hole, or a plate that overlaps only one side of the substrate Heat in a non-oxidizing atmosphere above the melting temperature of the low resistance metal.

Then, the melted low-resistance metal is infiltrated into the porous structure by wetting and spreading through the communicating space in the porous structure by a capillary phenomenon, thereby forming a vertical conductive body.

In general, the infiltration temperature is preferably 900 ° C. or more and 1500 ° C. or less, and the infiltration time is preferably 0.1 hours or more and 3 hours or less.

(Area ratio of low resistance metal and porosity)
The coefficient of thermal expansion of the vertical conductor is determined by the abundance ratio of the low resistance metal infiltrated into the porous structure made of the high melting point metal.

In such an abundance ratio, in the present invention, the formed vertical conductor is polished to expose the cross section, and then subjected to cross section polish (CP) processing in which dry etching is performed with Ar plasma. When observed in a field of view having a magnification of 250 times and 350 μm × 500 μm, the area S ₁ of the porous structure exposed in the field of view and the area S ₂ of the low-resistance metal are measured, and both areas S ₁ , S _{From 2} , formula (1):
Area ratio (%) = S ₂ / (S ₁ + S ₂ ) × 100 (1)
It will be expressed by the area ratio obtained by.

The area ratio is preferably 3% or more, and preferably 88% or less.

If the area ratio of the low-resistance metal is less than this range, the space formed in the porous structure cannot be completely filled with the low-resistance metal, and voids may remain.

Therefore, there is a possibility that the thermal conductivity of the upper and lower conductors may be lowered in combination with the decrease in the ratio of the low resistance metal having a high thermal conductivity.

On the other hand, when the area ratio of the low-resistance metal exceeds the above range, the ratio of the refractory metal is relatively reduced, so that a strong porous structure cannot be maintained by the refractory metal, Based on the high strength of the porous structure, there is a tendency that the effect of suppressing the expansion and contraction of the low-resistance metal and the vertical conductor is not sufficiently obtained.

Also, the ratio of the low resistance metal having a large coefficient of thermal expansion tends to be excessive, and the difference in coefficient of thermal expansion between the vertical conductor and the substrate tends to increase.

Therefore, there is a possibility that the residual stress of the ceramic wiring board cannot be adjusted to a range of 100 MPa or less due to these two tendencies.

On the other hand, by setting the area ratio of the low-resistance metal in the above range, the residual stress of the ceramic wiring board can be made as small as possible even in the range of 100 MPa or less while maintaining the thermal conductivity of the upper and lower conductive bodies in a favorable range. .

In consideration of imparting a high thermal conductivity of, for example, 180 W / mK or more to the vertical conductor, the area ratio of the low-resistance metal is preferably 10% or more, particularly 20% or more even in the above range. In consideration of further reducing the residual stress of the ceramic wiring board even in the range of 100 MPa or less, the area ratio of the low resistance metal is preferably 80% or less, particularly 75% or less even in the above range.

The area ratio of the low-resistance metal can be adjusted by adjusting the particle size distribution of the refractory metal particles that form the porous structure, the viscosity of the paste, the amount of the resin binder, and the like. The particle size distribution is as described above.

Also, when the viscosity of the paste is reduced or the amount of the resin binder is increased to reduce the ratio of the refractory metal contained in the paste, the vertical conduction formed through the steps described above using the paste. The abundance ratio of the low resistance metal contained in the body can be increased.

Further, from the area S _{3 of the} void that is exposed in the same field of view as the area ratio of the low-resistance metal and is not filled with the low-resistance metal, and the areas S ₁ and S ₂ , the formula (2):
Porosity (%) = S ₃ / (S ₁ + S ₂ + S ₃ ) × 100 (2)
Is preferably 10% or less.

When the porosity exceeds this range, the infiltrated low-resistance metal does not sufficiently enter the porous structure, and many voids are generated in the upper and lower conductive bodies. For example, when the metallized layer is formed on the surface of the substrate including the upper and lower conductors, the metallized layer and its metallization layer are not peeled off due to the generation of gas from the void. There is a risk of cracking the upper solder layer.

Note that the porosity is preferably 5% or less even in the above range. When the porosity exceeds this range, when the thickness of the metallized layer is smaller than, for example, 0.5 μm, the metallized layer directly above the upper and lower conductors or the solder layer thereon is strongly affected by the voids described above. May cause cracks.

Note that the void may be generated as a gap in the vertical conductor, or may be generated as a gap at the interface between the vertical conductor and the substrate. Here, not only the gap but also the area ratio of the gap generated at the interface is included in the void ratio.

Needless to say, the lower limit of the porosity is 0%. Ideally, there should be no voids.

(Polishing)
The ceramic wiring substrate of the present invention is manufactured by polishing the surface of the substrate after infiltrating the low-resistance metal as necessary.

The polishing method is the same as described above. That is, examples of the polishing method include the above-described mechanical polishing (fixed abrasive grains, loose abrasive grains), chemical mechanical polishing, and the like.

The surface roughness (arithmetic mean roughness of the roughness curve) Ra after polishing is preferably 0.01 μm or more, particularly 0.02 μm or more, and preferably 1 μm or less, particularly 0.5 μm or less.

If the surface roughness Ra after polishing is less than this range, the effect of improving the adhesion of the metallized layer by the so-called anchor effect may be insufficient. On the other hand, when the surface roughness Ra after polishing exceeds the above range, it may be difficult to form a metallized layer having a uniform thickness.

The thickness of the substrate after polishing is preferably 0.1 mm or more, particularly 0.15 mm or more, preferably 1 mm or less, particularly 0.5 mm or less, considering the balance between practical strength and volume reduction of the semiconductor device. Preferably there is.

<Semiconductor device>
The present invention is a semiconductor device in which a semiconductor element is mounted on the ceramic wiring board of the present invention.

Specifically, for example, a metallized layer is formed on both surfaces of the ceramic wiring board of the present invention on both the upper and lower sides including the upper and lower conductive bodies, and a semiconductor element is mounted on the metallized layer on at least one surface via a solder layer. Thus, a semiconductor device is configured.

(Metalized layer)
As described above, the metallized layer is formed on the surface of the substrate on which the upper and lower conductive bodies are formed, and further polished to have the above-described predetermined surface roughness Ra as necessary.

The metallized layer may have a single-layer structure including only the conductive layer described below, but is usually formed in a laminated structure of at least two layers of an adhesion layer for securing adhesion to the substrate and a conductive layer for external connection. It is preferable to do this. Further, a diffusion preventing layer may be interposed between these two layers.

The adhesion layer is formed to have a thickness of about 0.05 μm or more and 1.0 μm or less using, for example, Ti, Cr, NiCr, Ta, Nb, TiW, and compounds thereof. Examples of the forming method include physical vapor deposition such as sputtering and vacuum vapor deposition, and wet plating.

Further, the diffusion preventing layer is formed with a thickness of about 0.1 μm or more and 10 μm or less by, for example, Pt, Pd, Cu, Ni, Mo, NiCr or the like. Examples of the forming method include physical vapor deposition such as sputtering and vacuum vapor deposition, and wet plating.

Further, the conductive layer is formed with a thickness of about 0.1 μm or more and 10 μm or less, for example, with Ag, Al, Au or the like. Examples of the forming method include physical vapor deposition such as sputtering and vacuum vapor deposition, and wet plating.

A fine pattern can be formed by a photolithographic method on a metallized layer having a single layer structure or a stacked structure.

The metallized layer can also be formed by a thick film method (Au, Cu, etc.). Moreover, it can also form into a film by Ni or Ni / Au plating on the pattern formed by the thick film method.

Further, the metallized layer may be formed by patterning on the surface of the substrate by a screen printing method using a paste adjusted to a viscosity suitable for screen printing.

The thickness of the metallized layer by this method can be arbitrarily changed from, for example, about 5 μm to 100 μm or more by adjusting the viscosity of the paste used for screen printing. Of these, about 20 μm is common, but when a large current is applied, it may be 100 μm or more.

Further, the metallized layer formed by this method may be further patterned by polishing or chemical etching as necessary. Further, a film may be formed on the metallized layer by Ni or Ni / Au plating.

A resistance film such as NiCr or TaN may be formed on or near the metallized layer formed by these methods, if necessary.

The metallized layer may be a solid surface without the pattern formation described above depending on the structure of the semiconductor device.

Further, as described above, it is preferable to pattern a solder layer such as AuSn on the metallized layer on at least one surface for mounting a semiconductor element.

Usually, a plurality of regions to be a semiconductor device are formed on a single substrate, and after the formation of the metallized layer and the solder layer is completed, each region is separated by a well-known method such as dicing or laser, and then predetermined. A semiconductor element is mounted at the position. However, it may be divided for each region after mounting the semiconductor element.

For mounting the semiconductor element, any of various conventionally known methods such as a die bonding method using AuSn solder can be employed.

(Semiconductor element)
The semiconductor element is not particularly limited, and various semiconductor elements made of, for example, Si, GaAs, InP, GaN, SiC, or the like can be mounted. The size of the semiconductor element is not particularly limited.

<Example 1>
(Formation of vertical conduction holes)
A substrate made of a commercially available AlN sintered body was cut, polished, and processed into a length of 100 mm × width of 100 mm × thickness of 0.5 mm.

Next, a total of 2800 vertical and vertical conduction holes of φ0.3 mm were formed on this substrate using a YAG laser, 35 vertical x 80 horizontal. The distance between the centers of adjacent upper and lower conduction holes was 2.5 mm in the vertical direction and 1.0 mm in the horizontal direction. When the positional accuracy of the formed vertical conduction hole was measured using a tool microscope, it was ± 20 μm.

(Preparation of paste for porous structure)
A paste was prepared by blending 100 parts by mass of W particles as a refractory metal with 2 parts by mass of an acrylic binder as a resin binder and 5 parts by mass of butyl carbitol as a solvent and dispersing them.

As W particles,
24 parts by mass of W particles having an average particle diameter of 1.2 μm [B10 manufactured by Allied Material Co., Ltd.]
Three types of W particles having an average particle diameter of 3.1 μm (C50 manufactured by Allied Material Co., Ltd.) and 51 parts by mass of W particles having an average particle diameter of 6.0 μm [D20 manufactured by Allied Material Co., Ltd.] Mixed particles in which a total of 100 parts by mass) was mixed were used.

(Formation of porous structure)
The substrate having the upper and lower conductive holes formed therein was immersed in isopropanol (IPA), ultrasonically cleaned, air blown to scatter IPA, and then dried by heating at 100 ° C. for 10 minutes in an oven furnace.

Next, the paste prepared above was filled in the upper and lower conductive holes of the substrate by screen printing, and then the binder was removed by heating at 600 ° C. for 3 hours in a nitrogen atmosphere, and then 1000 ° C. in a hydrogen atmosphere. The porous particles were formed by sintering the W particles by heating for 1 hour.

(Low resistance metal infiltration)
In a state where the upper and lower sides of the substrate are sandwiched between Cu plates having a thickness of 0.3 mm, Cu as a low resistance metal is put into the porous structure in the vertical conduction hole by heating at 1200 ° C. for 0.5 hour in a hydrogen atmosphere. Infiltration was performed to form a vertical conductor having a composite structure of Cu and W.

Next, both surfaces of the substrate were polished so that the thickness of the substrate was 0.4 mm and the surface roughness Ra of both surfaces was 0.5 μm to produce a ceramic wiring substrate.

(Measurement of residual stress)
The results of X-ray diffraction of the residual stress of the manufactured ceramic wiring board using a φ0.3 mm collimator at a part 0.3 mm away from the vertical conductor in the plane direction of the board, and the Young's modulus of the ceramic forming the board It was 68 MPa when calculated | required by the X-ray-stress measuring method which calculates stress from (= 280GPa) and Poisson's ratio (= 0.24).

(Cross-section observation 1)
The upper and lower conductors of the manufactured ceramic wiring substrate are polished to expose the cross section, and then subjected to cross section polishing (CP) processing that is dry-etched with Ar plasma. It was observed in a field of view of 90 μm × 130 μm.

Then, all refractory metal particles exposed in the field of view are classified into A particles to C particles described above, and the number of each is counted. From the results, A particles occupy the total number of A particles to C particles. The number ratio N _A (%) of C, the number ratio N _C (%) of C particles, the sum N _A + N _{C of} both, and the ratio N _A / N _C were obtained, and the following results were obtained.

N _A : 37%
N _C : 32%
N _A + N _C : 69
N _A / N _C : 1.16
(Cross-section observation 2)
The vertical conductor of the manufactured ceramic wiring board is polished to expose the cross section, and then subjected to cross section polish (CP) processing that is dry-etched with Ar plasma, and at a magnification of 250 using SEM. When observed in the field of view of 350 μm × 500 μm, the area S ₁ of the porous structure exposed in the field of view, the area S _{2 of} the low-resistance metal, and the area S _{3 of the} void not filled with the low-resistance metal Was measured and the area ratio of the low-resistance metal was determined by the previous equation (1) to be 46%. Moreover, when the porosity was calculated | required by previous Formula (2), it was less than 1%.

(Fabrication of semiconductor devices)
A metallized layer constituting a circuit pattern was formed on both surfaces of the manufactured ceramic wiring substrate by the following method.

First, the ceramic wiring board was immersed in IPA, ultrasonically cleaned, air blown to scatter IPA, and then dried by heating at 100 ° C. for 10 minutes in an oven furnace.

Next, on both surfaces of the ceramic wiring substrate, using a sputtering apparatus, a Ti film as an adhesion layer is 0.05 μm, then a Pt film as a diffusion prevention layer is 0.2 μm, and an Au film as a conductive layer is 0.1 μm. A film having a thickness of 2 μm was formed in this order to form a metallized layer having a three-layer structure.

Film formation is carried out in accordance with a conventional method after heating the ceramic wiring substrate at 200 ° C. for 5 minutes with a halogen heater in an atmosphere of ultimate vacuum of 1 × 10 ⁻⁴ Pa in a sputtering apparatus and further performing dry cleaning with Ar plasma. did.

Next, on the metallized layer thus formed, a Si device having a length of 1 mm, a width of 1 mm, and a thickness of 0.3 mm was mounted via a solder foil having a thickness of 20 μm to produce a semiconductor device.

(Reliability test 1)
The fabricated semiconductor device was held for 30 minutes in a low temperature environment of −40 ° C. for 30 minutes and then held for 30 minutes in a high temperature environment of 120 ° C., followed by a temperature cycle test repeated 1000 cycles, followed by a relative temperature of 85 ° C. It was kept for 1000 hours in a high temperature and high humidity environment with a humidity of 85%.

And in any 10 places of the cross section after the cross section polish (CP) processing of polishing the upper and lower conductors of the ceramic wiring board of the held semiconductor device to expose the cross section and then performing dry etching with Ar plasma, When the general reliability was evaluated according to the following criteria when observed with a SEM in a field of view of a magnification of 1000 times and 90 μm × 130 μm, it was ranked A.

Rank A: No cracks were seen.

Rank B: Although cracks were observed on the substrate side, only cracks having a crack length of 10 μm or less and having no influence on mechanical properties were found.

Rank C: Cracks having a crack length exceeding 10 μm and not more than 100 μm that may affect the bonding characteristics and electrical / thermal characteristics were observed.

Rank D: A large crack with a crack length exceeding 100 μm was observed.

(Reliability test 2)
The following reliability test was performed under conditions severer than the reliability test 1 described above.

That is, after the temperature cycle test was repeated for 1000 cycles, the operation of holding the manufactured semiconductor device in a low temperature environment of −65 ° C. for 30 minutes and then holding in a high temperature environment of 150 ° C. for 30 minutes, It was kept for 1000 hours in a high temperature and high humidity environment with a relative humidity of 85%.

And in any 10 places of the cross section after the cross section polish (CP) processing of polishing the upper and lower conductors of the ceramic wiring board of the held semiconductor device to expose the cross section and then performing dry etching with Ar plasma, When the reliability was evaluated using the same standard as the reliability test 1 by observing in a field of view of 90 μm × 130 μm with a magnification of 1000 times using an SEM, it was ranked A.

<Examples 2 to 29, Comparative Examples 1 to 12>
A paste was prepared in the same manner as in Example 1 except that the average particle size and mixing ratio of the three types of W particles used in combination were changed, a ceramic wiring board was manufactured, a semiconductor device was manufactured, and each of the above-mentioned The test was conducted.

<Example 30>
As refractory metal particles, instead of W particles,
25 parts by mass of Mo particles having an average particle size of 1.3 μm [TMO-10 manufactured by Allied Material Co., Ltd.]
49 parts by mass of Mo particles having an average particle size of 3.3 μm [TMO-30 manufactured by Allied Material Co., Ltd.] and 26 parts by mass of Mo particles having an average particle size of 5.4 μm [TMO-50 manufactured by Allied Material Co., Ltd.] A paste was prepared in the same manner as in Example 1 except that mixed particles obtained by mixing the three types of Mo particles (100 parts by mass in total) were used, a ceramic wiring board was manufactured, a semiconductor device was manufactured, and the above-mentioned Each test of was conducted.

<Example 31>
A paste was prepared in the same manner as in Example 1 except that Ag was used instead of Cu as the low-resistance metal, a ceramic wiring board was manufactured, a semiconductor device was manufactured, and the above tests were performed.

<Example 32>
A paste was prepared in the same manner as in Example 30 except that Ag was used as the low-resistance metal instead of Cu, and a ceramic wiring board was manufactured, a semiconductor device was manufactured, and the above tests were performed.

<Conventional example 1>
A paste was prepared in the same manner as in Example 1 except that 100 parts by weight of W particles having an average particle diameter of 3.1 μm (C50 manufactured by Allied Material Co., Ltd.) alone were used as W particles. Were manufactured, and a semiconductor device was manufactured, and each of the above tests was performed.

The results are shown in Tables 1 to 3.

From the results of Examples 1 to 32, Comparative Examples 1 to 12, and Conventional Example 1 of Tables 1 to 3, the general reliability is ranked A by setting the residual stress of the manufactured ceramic wiring board to 100 MPa or less. It has been found that the reliability of the semiconductor device can be improved by setting the reliability under more severe conditions as A to B ranks.

Further, from the results of Examples 1 to 32, it was found that by setting the residual stress of the ceramic wiring board to 80 MPa or less even in the above range, the reliability under more severe conditions is also ranked A, and the reliability of the semiconductor device can be further improved. It was.

In addition, from the results of Examples 1 to 32, Comparative Examples 1 to 12, and Conventional Example 1, a low resistance metal was infiltrated into a porous structure made of a sintered body of high melting point metal particles. In the case of a composite structure, in order to make the residual stress of the ceramic wiring board within a range of 100 MPa or less, the number ratio N _A (%) of A particles having a maximum major axis of 1.0 μm or less and C having a maximum major axis of 5.0 μm or more. It was found that the sum N _A + N _C with the number ratio N _C (%) of the particles should be 50 or more and 90 or less, and the ratio N _A / N _C should be 2/3 or more and 2 or less.

Further, in the case of the above composite structure, in order to make the residual stress of the ceramic wiring board 80 MPa or less, the sum N _A + N _C is preferably 60 or more in the above range, and 80 or less. It was found that the ratio N _A / N _C is preferably 1 or more in the above range, and preferably 1.5 or less.

In addition, from the results of Examples 1 and 30 to 32, Mo was used instead of W as the high melting point metal that is the basis of the porous structure, and Ag was used instead of Cu as the low resistance metal. It was also found that the same result can be obtained by setting the above sum N _A + N _C and the ratio N _A / N _C within the above ranges.

Claims (11)

1. At least one selected from the group consisting of a ceramic substrate formed in the shape of a plate and having vertical conduction holes formed through the thickness direction, and Cu, Ag, and Au filled in the vertical conduction holes A ceramic wiring board comprising a vertical conductor made of a composite material including a kind of low-resistance metal and at least one refractory metal selected from the group consisting of W and Mo, and having a residual stress of 100 MPa or less.
2. The ceramic wiring board according to claim 1, wherein the residual stress is 80 MPa or less.
3. The vertical conductor has a composite structure in which the low-resistance metal is infiltrated into a porous structure made of a sintered body of particles of the refractory metal, and within a predetermined field of view of a cross section of the vertical conductor Of all the refractory metal particles exposed to N, the number ratio of particles having a maximum major axis of 1.0 μm or less was defined as N _A (%), and the number ratio of particles having a maximum major axis of 5.0 μm or greater was defined as N _C (%). when the N _a, the sum N _a + N _C of N _C is 50 or more and 90 or less, the ratio N _a / N _C is 2/3 or more, the ceramic wiring according the to claim 1 or claim 2 2 or less substrate.
4. The ceramic wiring board according to claim 3, wherein the sum N _A + N _C is 60 or more and 80 or less.
5. 5. The ceramic wiring board according to claim 3, wherein the ratio N _A / N _C is 1 or more and 1.5 or less.
6. From the area S ₁ of the porous structure exposed within a predetermined field of view of the cross section of the upper and lower conductive bodies and the area S _{2 of the} low-resistance metal, the formula (1):
   Area ratio (%) = S ₂ / (S ₁ + S ₂ ) × 100 (1)
   The ceramic wiring board according to any one of claims 3 to 5, wherein the area ratio of the low-resistance metal obtained by the above is 3% or more and 88% or less.
7. From the area S _{3 of the} void exposed in the predetermined visual field and not filled with the low-resistance metal, and the areas S ₁ and S ₂ , the formula (2):
   Porosity (%) = S ₃ / (S ₁ + S ₂ + S ₃ ) × 100 (2)
   The ceramic wiring board according to claim 6, wherein the porosity obtained by the above is 10% or less.
8. The ceramic wiring board according to any one of claims 1 to 7, wherein the vertical conduction hole is formed later in the sintered board.
9. The ceramic wiring board according to any one of claims 1 to 8, wherein the substrate is made of at least one ceramic selected from the group consisting of AlN, Al ₂ O ₃ , Si ₃ N ₄ , and SiC.
10. The ceramic wiring board according to any one of claims 1 to 9, wherein an inner diameter of the vertical conduction hole is not less than φ0.1 mm and not more than φ0.3 mm.
11. A semiconductor device in which a semiconductor element is mounted on the ceramic wiring substrate according to any one of claims 1 to 10.