TW201539145A - Overlay metrology method - Google Patents

Abstract

A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies.

Description

Overlap metric

The present invention relates to a method of overlay pair measurement, and more particularly to a method for calculating a virtual overlay pair metric.

The semiconductor integrated circuit industry is experiencing exponential growth. During the development of the integrated circuit industry, the reduction in component size has led to a significant increase in component density on a single wafer. Therefore, it is possible to manufacture a circuit that is smaller and more complicated than the previous generation. This reduction process increases production efficiency and reduces manufacturing costs, while also complicating the manufacturing process of integrated circuits.

These integrated circuits are manufactured in a number of processes in a semiconductor fab, each of which forms a patterned layer on the wafer. In order for the components to function properly, such patterned layers must be precisely aligned. If there is a stacking error between the pattern layers, it will lead to short circuit or connection failure, which will greatly reduce the fab's yield and profit.

Therefore, in the manufacturing process of integrated circuit components, it is very important to measure the overlap error values between pattern layers, which is also commonly referred to as a stack pair metric. The alignment accuracy between one of the pattern layers and the next pattern layer can be known by the overlay pair metric. Therefore, as the density and complexity of integrated circuits increase, stacked pairs Metrics are becoming more and more important, and it is more difficult to perform overlapping pairs of measurements.

In view of this, one aspect of the present invention is a method of measuring a stack metric of a plurality of wafers, wherein each wafer has a plurality of pattern layers thereon. The method first takes a historical overlay pair metric in a database and measures the true overlay metric for a first set of wafers. On the other hand, the virtual overlay metric of a second set of wafers is calculated by taking the historical overlay pair metrics. The true overlay metric for the first set of wafers and the virtual overlay metric for the second set of wafers are stored in the database and used as historical overlay metrics.

Another aspect of the present invention is a device for measuring a wafer stack metric value, comprising: a database in which a historical overlay metric value is stored; and a stack metric device configured to be taken out of the database The history overlays the metric and measures the overlay metric of the wafer. The overlay pair metric device includes a real overlay metric device and a virtual overlay metric device, wherein the virtual overlay metric device is configured to retrieve historical overlay metric values within the database.

Another aspect of the present invention is a method of forming a plurality of pattern layers on a plurality of wafers, comprising taking a historical overlay pair metric in a database and a process recipe in an exposure apparatus to an advanced process controller in. Then, the stacking parameters in the process recipe are determined according to the historical stacking metric value, the process recipe is returned to the exposure apparatus, and a plurality of pattern layers are formed on the wafers according to the process recipe. A true overlay metric for a first set of wafers is measured, and a virtual overlay metric for a second set of wafers is calculated. Among them Calculating the virtual overlay metric of the second set of wafers by selecting a first pattern layer from one of the second set of wafers and searching for a first reference wafer having a second pattern layer, wherein The time during which the second pattern layer is formed to the first reference wafer is closest to the time at which the first pattern layer is formed to the wafer. A standard wafer having a first pattern layer is further searched, wherein the time at which the first pattern layer is formed to the standard wafer is earlier than the time at which the first pattern layer is formed to the wafer. Finally, a second reference wafer having a second pattern layer is formed, wherein the time when the second pattern layer is formed to the second reference wafer is closest to the time when the first pattern layer is formed to the standard wafer. Extracting a stack metric value of the first pattern layer on the standard wafer, the second pattern layer on the first reference wafer, and the second pattern layer on the second reference wafer in the database, and calculating the second on the first reference wafer The overlay metric difference between the pattern layer and the second pattern layer on the second reference wafer. Further extracting the overlay metric values of one or more pattern layers on the wafer in the database, wherein the pattern layers are formed on the wafer earlier than the first pattern layer, and the total overlap metric difference, standard wafer The overlay metric of the first patterned layer and the overlay metric of the plurality of patterned layers on the wafer prior to the formation of the first patterned layer to obtain a virtual overlay metric of the first patterned layer on the wafer. Finally, the true overlay pair metric and the virtual overlay metric are stored in the database.

110‧‧‧Database

120‧‧‧Exposure device

130‧‧‧Adaptive device

140‧‧‧Real stacking metric device

150‧‧‧Virtual Overlap Measurer

160‧‧‧Advanced Process Controller

210~260‧‧‧Steps

310‧‧‧ wafer

320‧‧‧First reference wafer

330‧‧‧Standard Wafer

340‧‧‧second reference wafer

312A, 312B‧‧‧ first pattern layer

322A, 322B‧‧‧ second pattern layer

410~440‧‧‧Steps

510, 521~526, 531~532, 540‧‧ steps

314‧‧‧ Third pattern layer

316‧‧‧Four pattern layer

The above and other objects, features, advantages and embodiments of the present invention will become more <RTIgt; Value measuring device.

2 is a flow chart of a method for measuring a wafer stack metric according to some embodiments of the present invention.

3 is a schematic view showing the formation of a pattern layer in a exposure apparatus of a wafer according to some embodiments of the present invention.

4 is a flow chart of a method for measuring a true stack pair metric of a first set of wafers in accordance with some embodiments of the present invention.

5 is a flow chart of a method for calculating a second set of wafer virtual overlay metrics in accordance with some embodiments of the present invention.

Figure 6 is a diagram showing a wafer exploded view in accordance with some embodiments of the present invention.

The spirit and scope of the present invention will be apparent from the following description of the preferred embodiments of the invention. The spirit and scope of the invention are not departed. For the sake of clarity, many of the practical details will be explained in the following description. However, it should be understood by those skilled in the art that the details of the invention are not essential to the details of the invention. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

In the prior art, the overlay error between the layers of the wafer pattern is known by a real measurement, which is also commonly referred to as a true overlay metric. However, if all the wafers are actually measured, it will cause a huge negative impact on the measurement system. Lotus. Therefore, a method of calculating the overlapping pair metrics must be used, and a highly reliable virtual overlay metric can be obtained accordingly. The virtual overlay pair metric can replace part of the true overlay metric to reduce the system load during real measurements. The present invention provides a mechanism for calculating virtual overlay metrics to mitigate the load of a true overlay metric system.

1 is a wafer stack metric measurement device in accordance with some embodiments of the present invention, wherein each wafer has a plurality of pattern layers. The wafer stack metric measuring apparatus 100 includes a database 110, an exposure device 120, an adaptive device 130, a real overlay metric device 140, and a virtual overlay metric device 150. In Fig. 1, the solid line indicates the traveling route of the wafer, and the broken line indicates the transmission route of the data stream.

Referring to FIG. 1, when the wafers enter the real overlay metric device 140 and the virtual overlay metric device 150, the overlay metric of the wafer can be known. These overlay pairs of metrics are stored in the repository 110 and used as historical overlay metrics. Historical overlay metrics in database 110 can be used as feedback information to increase the efficiency of run-to-run. The inter-process control can be between batch-to-lot control or wafer-to-wafer control.

In the exposure device 120, the pattern layers are formed on the wafer according to a process recipe, and the pattern layers on the same wafer are not identical to each other.

The process recipe in exposure device 120 includes an in-exposure region parameter and an inter-exposure region parameter. The parameters in the exposure area include a wafer horizontal displacement parameter, a wafer vertical displacement parameter, a wafer horizontal amplification parameter, a wafer vertical amplification parameter, a wafer horizontal rotation parameter, and a wafer sag Rotate the parameters directly. The inter-exposure zone parameters include a reticle horizontal displacement parameter, a reticle vertical displacement parameter, a reticle horizontal magnification parameter, a reticle vertical magnification parameter, a reticle horizontal rotation parameter, and a reticle vertical rotation parameter.

Apparatus 100 further includes an advanced process controller 160 that can retrieve process recipes from exposure apparatus 120 and retrieve historical overlay metrics from database 110. The advanced process controller 160 can analyze the historical overlay metrics and determine the overlay parameters in the process recipe, and then transfer the changed process recipes to the exposure device 120.

After the wafer forms a pattern layer in the exposure device 120, the adaptive device 130 first obtains the historical overlay metric from the database 110, and assigns a first set of wafers into the real overlay metric device 140 and a second group. The wafer enters the virtual overlay metric device 150. The adaptive device 130 determines the number of first and second sets of wafers based on the stability of the historical overlay metric.

In the true overlay pair metric device 140, the true overlay metric values for the first set of wafers will be measured realistically. In the virtual overlay metric device 150, the virtual overlay metric of the second set of wafers is calculated based on the historical overlay metric in the database 110. Applying the virtual overlay pair metric device 150 can substantially reduce the system load of the true overlay pair metric device 140.

Since both the real overlay pair metric device 140 and the virtual overlay metric device 150 are coupled to the database 110, the measured true overlay metrics and the calculated virtual overlay metrics are stored in the repository 110. Take the metric as a historical overlay.

2 is a wafer stack pair metric according to some embodiments of the present invention. Value measurement method. Figure 2 provides a flow chart of a wafer overlay metric measurement method that is run on device 100 of Figure 1.

First, step 210 is performed to retrieve the historical overlay metric value in the database 110. The overlay metric values for the pattern layers on the wafer have been stored in the database 110. These overlay metric values will be used as historical overlay metrics and used in the following steps.

Continuing with step 220, the exposure device 120 forms a pattern layer on each of the wafers according to the process recipe. See Figure 3 for a further understanding of step 220. FIG. 3 is a schematic view showing the formation of a pattern layer in the exposure device 120 by the wafer. In FIG. 3, exposure devices 120 respectively form different types of pattern layers on each of the wafers. In order to confirm the accuracy of the pattern layer stacking on the wafer, the overlay metric values of the pattern layers formed in the exposure device 120 must be measured or calculated.

Next, step 230 is performed to allocate the first set of wafers into the real overlay pair metric device 140 and the second set of wafers into the virtual overlay metric device 150. The adaptive device 130 determines the number of the first set of wafers and the second set of wafers after analyzing the historical overlay metrics in the database 110.

Continuing with step 240, a true overlay pair metric for the first set of wafers is measured in the real overlay pair metric device 140. On the other hand, step 250 is tied to virtual overlay metric device 150 to calculate a virtual overlay metric for the second set of wafers from the retrieved historical overlay metric.

Finally, step 260 is performed to store the true overlay metric of the first set of wafers and the virtual overlay metric of the second set of wafers into the repository 110. The true stack pair metric and the first set of wafers stored in the database 110 The virtual overlay metric of the two sets of wafers is the historical overlay metric and can be used as feedback information for the next stage of the process.

Figure 4 is a flow chart showing the method of measuring the true overlay metric of the first set of wafers, see Figure 4 for a further understanding of step 240. First, step 410 is performed to provide a plurality of fields on the first set of wafer surfaces, wherein the fields include a plurality of internal fields in a central region of the wafer surface, and the plurality of external fields are adjacent to a peripheral edge of the wafer surface.

Continuing to step 420, a first number of stacked pairs in one of the inner fields is measured and a first number of stacked pairs are obtained.

Next, step 430 is performed to measure a second number of overlapping pairs in one of the outer fields and obtain a second number of overlapping pairs. Wherein the second quantity is greater than the first quantity.

Finally, step 440 is performed to determine a true overlay metric of the pattern layer on the wafer by the first number of overlay states and the second number of overlay states.

Step 250 calculates the virtual overlay metric for the second set of wafers, see FIG. 3 and FIG. 5 for further understanding of step 250. Figure 5 is a flow chart showing the method of calculating the virtual overlay metric of the second set of wafers. First, step 510 is performed to select a first pattern layer 312A from a plurality of pattern layers on a wafer 310 of the second set of wafers. Referring to FIG. 3 together, the wafer 310 has a plurality of pattern layers on the wafer 310, and a first pattern layer 312A is formed in the exposure device 120. The first pattern layer 312A calculates its virtual overlay metric value with the virtual overlay pair metric device 150. The virtual overlay metric of the first pattern layer 312A is determined by the first virtual overlay metric and the second virtual overlay metric In total, they are calculated by different mechanisms.

Steps 521 through 525 are used to calculate a first virtual overlay metric of the first pattern layer 312A on the wafer 310. Referring to step 521, a first reference wafer 320 having a second pattern layer 322A is formed. The second pattern layer 322A is formed to the first reference wafer 320 at a time closest to the first pattern layer 312A. 310 hours. Referring to FIG. 3, in the exposure device 120, a different type of pattern layer from the first pattern layer 312A will be formed on the first reference wafer 320. Also, the time from the formation of the second pattern layer 322A to the first reference wafer 320 is closest to the time at which the first pattern layer 312A to the wafer 310 are formed.

Continuing to step 522, a standard wafer 330 having a first pattern layer 312B is searched for, wherein the first pattern layer 312B is formed to the standard wafer 330 earlier than the first pattern layer 312A is formed to the wafer 310. Referring to FIG. 3, the first pattern layer 312B and the first pattern layer 312A are the same type of pattern layer. Moreover, the time from the formation of the first pattern layer 312B to the standard wafer 330 is earlier than the time from the formation of the first pattern layer 312A to the wafer 310.

Next, step 523 is performed to search for a second reference wafer 340 having a second pattern layer 322B. The second pattern layer 322B is formed to the second reference wafer 340 at a time closest to the first pattern layer 312B to form a standard wafer. 330 hours. Referring to FIG. 3, the second pattern layer 322B and the second pattern layer 322A are the same type of pattern layer. Also, the time from the formation of the second pattern layer 322B to the second reference wafer 340 is closest to the time when the first pattern layer 312B is formed to the standard wafer 330.

In some embodiments of the present invention, the first pattern layer 312B is formed The time to the standard wafer 330, the time to form the second pattern layer 322A to the first reference wafer 320, and the time to form the second pattern layer 322B to the second reference wafer 340 are both earlier than the formation of the first pattern layer 312A The time of wafer 310.

Proceed to step 524, the first pattern layer 312B on the standard wafer 330, the second pattern layer 322A on the first reference wafer 320, and the second pattern layer 322B on the second reference wafer 340 are taken out from the database 110. metric. Since the formation time of the first pattern layer 312B and the second pattern layers 322A and 322B is earlier than the first pattern layer 312A, the virtual overlay metric values of the pattern layers are stored in the database 110 as historical overlay metric values. The first virtual overlay metric value of the first pattern layer 312A on the wafer 310 can be calculated by the historical overlay metrics.

Next, step 525 is performed to calculate a stack of metric difference values between the second pattern layer 322A on the first reference wafer 320 and the second pattern layer 322B on the second reference wafer 340. The overlapping metric values of the second pattern layers 322A and 322B have been previously taken out in step 524, and the difference between the two pairs of metric values is calculated accordingly, which is also referred to as device calibration. The device is calibrated to the overlay metric bias produced in exposure device 120, and the first virtual overlay metric value of first pattern layer 312A on wafer 310 can be accurately calculated by device calibration.

Finally, step 526 is performed to add the overlay metric difference value of the first pattern layer 312B on the standard wafer 330 to obtain the first virtual overlay metric value of the first pattern layer 312A on the wafer 310. The overlay metric value of the first pattern layer 312A has been taken out in step 524, followed by the difference in the overlay metric The value is corrected to calculate a first virtual overlay metric for the first pattern layer 312A on the wafer 310. The reliability of the first virtual overlay metric of the first pattern layer 312A on the wafer 310 will be substantially increased by considering the effect of the exposure device 120 on the overlay metric values in the process.

On the other hand, the virtual overlay metric device 150 also calibrates the features of the wafer 310 itself. Exposure device 120 will form first pattern layer 312A onto wafer 310 and form first pattern layer 312B onto standard wafer 330. However, there are characteristic differences between the wafer 310 and the standard wafer 330, for example, wafer size, wafer displacement or rotation. There is also a difference in characteristics between the reticle forming the first pattern layers 312A and 312B, for example, the size of the reticle, the displacement of the reticle or the rotation.

Differences in such wafer or reticle features will result in a bias value for the calculated virtual overlay metric. If these differences are ignored, the previously calculated first virtual overlay pair metric must be difficult to approximate to the true overlay metric. Therefore, to further enhance the reliability of the virtual overlay metric, steps 531 and 532 will be used to calibrate differences in features between different wafers or between different reticle.

As previously mentioned, the wafer 310 has a plurality of patterned layers thereon. Please refer to FIG. 6 , which illustrates an exploded view of the wafer 310 . Before the first pattern layer 312A is formed in the exposure device 120, a third pattern layer 314 and a fourth pattern layer 316 are formed on the wafer 310. Since the formation time of the third pattern layer 314 and the fourth pattern layer 316 is earlier than the first pattern layer 312A, the overlapping metric values of the third pattern layer 314 and the fourth pattern layer 316 have been stored in the database 110 as a historical overlay. metric. The overlay metric values of the third pattern layer 314 and the fourth pattern layer 316 represent features of the wafer 310 in size, displacement, or rotation.

Referring to step 531, the overlay metric values of one or more pattern layers on the wafer 310 in the database 110 are taken out, wherein the pattern layers are formed to the wafer 310 earlier than the first pattern layer 312A. Since the formation time of the third pattern layer 314 and the fourth pattern layer 316 is earlier than the first pattern layer 312A, the overlapping metric values of the pattern layers 314 and 316 have been stored in the database 110, and the stacks may be stacked in step 531. The metrics are taken for use in subsequent calculations.

Next, step 532 is performed to add a stack metric value of the pattern layers earlier than the first pattern layer 312A to calculate a second virtual overlay metric value of the first pattern layer 312A on the wafer 310. The second virtual overlay pair metric is also referred to as wafer feature calibration, and the overlay error feature of the third pattern layer 314 and the fourth pattern layer 316 will remain in the second virtual overlay metric and substantially increase the virtual overlay metric. The reliability of the magnitude.

Proceeding to step 540, the first virtual overlay pair metric and the second virtual overlay metric are summed to obtain a virtual overlay metric of the first pattern layer 312A on the wafer 310. The virtual overlay metric can be calculated by correcting the effect of the exposure device 120 on the overlay metrics in the process, and by correcting differences in features between wafers or reticle. This virtual overlay pair metric has high reliability and can partially or completely replace the true overlay metric to reduce the system load of the true overlay metric device 140.

In some embodiments of the present invention, the first virtual overlay pair metric and the second virtual overlay metric are summed to obtain a virtual overlay metric. The first virtual overlay pair metric and the second virtual overlay metric are calculated by the above mechanism or algorithm, but are not limited by the methods. Any step or method can be used to calculate the approximate true and effective The virtual overlay metric of the metric value is actually stacked to reduce the system load of the overlay metric device.

In addition, the process recipes in exposure device 120 and the historical overlay metrics in database 110 are communicated to advanced process controller 160. The advanced process controller 160 analyzes the historical overlay metrics, re-determines the overlay parameters in the process recipe, and then transmits the new process recipe back to the exposure device 120. Using the advanced process controller 160, it is possible to achieve better alignment between the pattern layers formed in the exposure device 120.

Please continue to Figure 6 to learn more about how the advanced process controller 160 enhances the alignment between the pattern layers. As previously described, the fourth pattern layer 316 on the wafer 310 is formed earlier than the third pattern layer 314. After the third pattern layer 314 is formed, the overlay metric values of the third pattern layer 314 are obtained by a true overlay pair metric measurement or a virtual overlay metric calculation.

The overlay metric of the third pattern layer 314 represents the overlay error between the third pattern layer 314 and the fourth pattern layer 316, and then the first pattern layer 312A is formed over the third pattern layer 314. In order to reduce the overlay error between the first pattern layer 312A and the third pattern layer 314, the advanced process controller 160 is applied for arithmetic control before the first pattern layer 312A is formed on the wafer 310.

The overlay error is calibrated by changing the overlay parameters within the recipe recipe in exposure apparatus 120. The process recipe in the exposure device 120 includes an intra-exposure region parameter and an exposure inter-region parameter. The parameters in the exposure area include a wafer horizontal displacement parameter, a wafer vertical displacement parameter, a wafer horizontal amplification parameter, a wafer vertical amplification parameter, and a wafer horizontal rotation parameter. And a wafer vertical rotation parameter. The inter-exposure zone parameters include a reticle horizontal displacement parameter, a reticle vertical displacement parameter, a reticle horizontal magnification parameter, a reticle vertical magnification parameter, a reticle horizontal rotation parameter, and a reticle vertical rotation parameter.

The advanced process controller 160 first analyzes the overlay metric values of the third pattern layer 314, thereby redetermining the values of the overlay parameters in the process recipe. The process recipe with the new overlay parameters will be transferred back to the exposure device 120 and the first pattern layer 312A formed thereon on the wafer 310. The stacking error between the first pattern layer 312A formed with the new stacking parameters and the third pattern layer 314 will be greatly reduced.

It will be apparent from the above-disclosed embodiments of the present invention that the present invention has the following advantages. In some embodiments, the virtual overlay pair metric can partially replace the true overlay pair metric and substantially reduce the system load of the true overlay pair metric device 140. The virtual overlay metric calculated by device calibration and wafer feature calibration can closely approximate the true overlay metric obtained by real measurement. Therefore, the virtual overlay metric has very high reliability.

In addition, the true overlay metric and the virtual overlay metric are stored in the database 110 as historical overlay metrics, which are used as feedback information for the next phase of the process, while increasing the efficiency of the inter-process control. . By calculating the virtual overlay metrics, the advanced process controller 160 can quickly obtain overlay information between the pattern layers and immediately change the recipe recipe to reduce stacking errors between subsequently formed pattern layers. Summarizing the above points, the calculation of the virtual overlay metric can reduce the system load of the true overlay pair metric device 140 and reduce the overlay error between the pattern layers.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and retouched without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.

210~260‧‧‧Steps

Claims (10)

A method of measuring a stack metric of a plurality of wafers, wherein each wafer has a plurality of pattern layers, the method comprising: taking a historical overlay metric in a database; measuring a first set of wafers a true overlay pair metric; calculating a virtual overlay metric of the second set of wafers by taking the historical overlay pair metric; and storing the true overlay metric and the virtual overlay metric into the database. The method of claim 1, wherein the stack metric values of the pattern layers on the wafers are stored to the database as the historical overlay metric. The method of claim 1, wherein measuring the true overlay metric of the first set of wafers comprises: providing a plurality of fields on a surface of the first set of wafers, wherein the fields comprise a plurality of infields Located in a central region of the surface and a plurality of outer fields adjacent to a peripheral edge of the surface; measuring a first number of overlapping structures in one of the inner fields and obtaining the first number of overlapping pairs; measuring one of a second number of stacked pairs in the outer field and obtaining the second number of stacked pairs, wherein the second quantity is greater than the first quantity; The true overlay metric of one of the pattern layers on the wafer is determined by the first number of overlay states and the second number of overlay states. The method of claim 1, wherein calculating the virtual overlay metric of the second set of wafers comprises: selecting a first pattern layer from one of the second set of wafers; Calculating a first virtual overlay metric value and a second virtual overlay metric value of the first pattern layer for the metric value; and summing the first virtual overlay metric value and the second virtual overlay metric value to obtain One of the first pattern layers on the wafer is a virtual overlay metric. The method of claim 4, wherein calculating the first virtual overlay metric of the first pattern layer on the wafer comprises: searching for a first reference wafer having a second pattern layer, wherein the second Forming the pattern layer to the first reference wafer at a time closest to the time at which the first pattern layer is formed to the wafer; searching for a standard wafer having the first pattern layer, wherein the first pattern layer is formed to the standard The time of the wafer is earlier than the time when the first pattern layer is formed to the wafer; searching for a second reference wafer having the second pattern layer, wherein the second pattern layer is formed to the second reference wafer The time when the first pattern layer is formed to the standard wafer; the first pattern layer on the standard wafer, the second pattern layer on the first reference wafer, and the second reference crystal are taken out from the database The second picture on the circle a stack metric of the layer; calculating a stack metric difference between the second pattern layer on the first reference wafer and the second pattern layer on the second reference wafer; and summing the standard wafer The stack metric value of the first pattern layer and the overlay metric difference value are used to obtain the first virtual overlay metric value of the first pattern layer on the wafer. The method of claim 5, wherein calculating the second virtual overlay metric of the first pattern layer on the wafer comprises: extracting a stack metric of one or more pattern layers on the wafer in the database a value, wherein the pattern layers are formed to the wafer earlier than the first pattern layer; and the overlap metric values of the pattern layers are added to calculate the first pattern layer on the wafer The second virtual overlay pair metric. A wafer overlay metric measurement device includes: a database storing historical overlay metrics; and a stack metric device configured to extract the historical overlay metrics in the database And measuring a stack metric of the plurality of wafers, the overlay metric device comprising: a true overlay metric device; and a virtual overlay metric device configured to retrieve the historical overlay metric within the database value. The measuring device of claim 7, wherein the virtual overlay metric device calculates the virtual overlay metric of the wafers by using the historical overlay metric, by selecting one of the wafers a first pattern layer; searching for a first reference wafer having a second pattern layer, wherein the second pattern layer is formed to the first reference wafer at a time closest to the time at which the first pattern layer is formed to the wafer Searching for a standard wafer having the first pattern layer, wherein the first pattern layer is formed to the standard wafer earlier than the first pattern layer is formed to the wafer; the search has the second pattern layer a second reference wafer, wherein the second pattern layer is formed to the second reference wafer at a time closest to the time when the first pattern layer is formed to the standard wafer; and the standard wafer is taken out of the database Calculating a stack metric of the first pattern layer, the second pattern layer on the first reference wafer, and the second pattern layer on the second reference wafer; calculating the second pattern layer on the first reference wafer And the second pattern layer on the second reference wafer a stacking metric difference between the stacks; taking out a stack metric of the one or more pattern layers on the wafer in the database, wherein the pattern layers are formed on the wafer earlier than the first pattern layer; And summing the stack metric difference, the stack metric of the first pattern layer on the standard wafer, and the stacked pairs of the pattern layers on the wafer earlier than the first pattern layer Measured to obtain the first pattern on the wafer One of the layers is a virtual overlay pair metric. A method for forming a plurality of pattern layers on a plurality of wafers, comprising: taking out a historical overlay pair metric in a database and a process recipe in an exposure device to an advanced process controller; The metric determines a stacking parameter in the process recipe; the process recipe is returned to the exposure apparatus and the pattern layer is formed on the wafers according to the process recipe; and the true overlay metric of the first set of wafers is measured Calculating a virtual overlay metric of a second set of wafers, comprising: selecting a first pattern layer from one of the second set of wafers; searching for a first reference having a second pattern layer a wafer, wherein the second pattern layer is formed to the first reference wafer at a time closest to the time at which the first pattern layer is formed to the wafer; searching for a standard wafer having the first pattern layer, wherein the Forming a pattern layer to the standard wafer earlier than a time at which the first pattern layer is formed to the wafer; searching for a second reference wafer having the second pattern layer, wherein the second pattern layer is formed to Second reference wafer Between the first pattern layer is formed closest to the standard time of the wafer; the first pattern layer on the wafer taken out of the standard database, the Calculating a stack metric of the second pattern layer on the second reference layer and the second pattern layer on the second reference wafer; calculating the second pattern layer and the second reference wafer on the first reference wafer a stacking metric difference between the second pattern layers; taking out a stack metric of the one or more pattern layers on the wafer of the database, wherein the pattern layers are formed on the wafer earlier than the a first pattern layer; and a total of the overlay metric difference, a stack metric of the first pattern layer on the standard wafer, and the pattern layer on the wafer prior to the first pattern layer The stacked pairs of metrics to obtain a virtual overlay metric of the first pattern layer on the wafer; and storing the true overlay metric and the virtual overlay metric into the database. The method of claim 9, wherein measuring the true overlay metric of the first set of wafers comprises: providing a plurality of fields on a surface of the first set of wafers, wherein the fields comprise a plurality of infields One of the central regions of the surface and the plurality of outer fields are adjacent to a peripheral edge of one of the surfaces. A first number of stacked pairs in one of the inner fields is measured and the first number of stacked pairs is obtained. Measuring a second number of stacked pairs in one of the outer fields and obtaining the second number of stacked pairs, wherein the second amount is greater than the first number. By the first number of stacked pairs and the second number of stacked pairs The condition determines the true overlay metric for the pattern layer on the wafer.