TW201537304A - Exposure method, photomask, and chip substrate - Google Patents

Abstract

An exposure method is provided, which includes: providing a substrate; forming a photoresist layer on the substrate; and forming an image on the photoresist layer corresponding to patterns on a photomask by an image-forming lens, so as to expose the photoresist layer. The photomask has a plurality of chip areas. Each of the chip areas includes the pattern. The patterns of the chip areas are substantially the same. The line widths of the patterns of the chip areas have an increasing tendency from the edge of the photomask to the middle of the photomask. A photomask and a chip substrate are also provided.

Description

Exposure method, photomask and wafer substrate

The present invention relates to a chip substrate, an exposure method, and a photomask.

In semiconductor manufacturing, photolithography is one of the decisive factors influencing the quality of the resulting wafer. In the lithography process, the pattern on the reticle cannot be copied into the photoresist pattern with no error, which is affected by optical factors and factors such as rounding of the corners during development of the photoresist.

Embodiments of the present invention provide an exposure method, a photomask, and a wafer substrate, which can make the line widths of the line layouts of the respective crystal grains relatively uniform.

An exposure method according to an embodiment of the present invention includes: providing a substrate; forming a photoresist layer on the substrate; and imaging a plurality of patterns on the photomask on the photoresist layer by an imaging lens to The resist layer is exposed. Wherein the photomask has a plurality of wafer regions, each of the wafer regions including the pattern, and the patterns of the wafer regions are mutually Substantially the same, and the line width of these patterns of these wafer regions tends to increase from being located at the edge of the reticle towards the center of the reticle.

A reticle according to an embodiment of the invention includes a plurality of wafer regions, each wafer region including a pattern, and the patterns of the wafer regions are substantially identical to each other. The line width of these patterns of these wafer regions tends to increase from being located at the edge of the reticle towards the center of the reticle.

An exposure method according to an embodiment of the present invention includes: providing a substrate; forming a photoresist layer on the substrate; and imaging a pattern on the photomask on the photoresist layer by an imaging lens to face the photoresist layer Exposure is performed wherein the reticle has a plurality of wafer regions and at least two of the wafer regions have substantially the same pattern, but the substantially identical patterns each have a different line width.

A wafer substrate according to an embodiment of the invention includes a plurality of dies arranged in an array, and each of the dies includes a line layout. These line layouts of these grains are substantially identical to each other, and the difference in line width of these line layouts of these grains is less than 2%.

The above described features and advantages of the invention will be apparent from the following description.

110‧‧‧Substrate

112‧‧‧ grain area

120‧‧‧ photoresist layer

130‧‧‧ imaging lens

140‧‧‧Photomask

142‧‧•Image beam

144‧‧‧ wafer area

145‧‧‧ patterns

150‧‧‧Light source

152‧‧‧ illumination beam

212‧‧‧ grain

245‧‧‧Line layout

A, A1, R1, R2, R3, R4‧‧‧ areas

V, W, W1, W2‧‧‧ line width

1A and 1B are schematic views showing the flow of an exposure method according to an embodiment of the present invention.

2A is a front elevational view of the reticle of FIG. 1B.

2B is a front elevational view of the substrate of FIG. 1B.

2C is a front elevational view of the region of the substrate of FIG. 2B subjected to one exposure.

3A is a partial front elevational view of the pattern in the wafer region of the edge of the reticle of FIG. 2A.

Figure 3B is a partial front elevational view of the pattern in the centrally located wafer region of the reticle of Figure 2A.

4A is a front elevational view of a portion of the wafer substrate of FIG. 2B after being fabricated through a semiconductor process, wherein the portion corresponds to region A of the substrate.

4B is a front elevational view of a portion of the line layout in the die of FIG. 4A.

1A and FIG. 1B are schematic diagrams showing a flow of an exposure method according to an embodiment of the present invention, FIG. 2A is a front view of the photomask of FIG. 1B, and FIG. 2B is a front view of the substrate of FIG. 1B, and FIG. 2C is a front elevational view of a portion of the substrate of FIG. 2B subjected to one exposure. Referring to FIG. 1A, FIG. 1B and FIG. 2A to FIG. 2C, the exposure method of this embodiment includes the following steps. First, referring to FIG. 1A, a substrate 110 is provided. The substrate 110 is, for example, a germanium substrate, another semiconductor substrate, a glass substrate, a plastic substrate, or other suitable substrate. Then, a photoresist layer 120 is formed on the substrate 110. The above-mentioned formation of a photoresist layer 120 on the substrate 110 may be performed by directly forming a photoresist layer 120 on the substrate 110 and forming on other material layers on the substrate. The photoresist layer 120 is formed in other ways. The way to form the photoresist layer 120 is, for example, A coating (e.g., spin coating) process applies the photoresist layer 120 to the substrate 110, or the photoresist layer 120 is formed on the substrate 110 in other suitable manners (e.g., a printing process).

Then, referring to FIG. 1B, a mask 140 is imaged on the photoresist layer 120 by an imaging lens 130, for example, a pattern on the mask 140 is formed on the photoresist layer 120 to the photoresist layer 120. Exposure. In this embodiment, an illumination beam 152 can be provided by a light source 150. The illumination beam 152 passes through the reticle 140 to form an image beam 142 that carries pattern information on the reticle 140. In the present embodiment, the light source 150 is, for example, an ultraviolet light source, and the illumination beam 152 is, for example, an ultraviolet light beam. However, in other embodiments, light sources of other wavelengths or bands that expose the photoresist layer 120 may also be employed.

When a mask is used to expose an area on a substrate once, this area will typically form a plurality of arrayed die regions in the future. That is to say, there are corresponding patterns on the reticle that are arranged in an array and substantially identical to each other. For an imaging lens of an exposure machine, light rays close to the optical axis of the imaging lens are more likely to be concentrated, so that when these substantially identical patterns arranged in an array on the photomask are imaged on the substrate, the closer to the optical axis is the photoresist The line width of the pattern will be smaller. As a result, the line widths of the patterns in the plurality of die regions formed by one exposure may be inconsistent, which may cause inconsistencies in the electrical quality of the manufactured die or chip.

Referring to FIG. 1B and FIG. 2A to FIG. 2C , in the embodiment, the reticle 140 may have a plurality of wafer regions 144 , and the reticle 140 may be imaged by the imaging lens 130 on the substrate 110 respectively in a plurality of different times. A different area A. Wherein the substrate 110 For example, wafers, and the wafer regions 144 of the reticle 140 can be imaged onto a plurality of die regions 112 on the substrate 110, respectively, and the die regions 112 will be fabricated and cut into a plurality of substantially identical ones. The grains, and thus the patterns in the wafer regions 144 of the reticle 140 are substantially identical to each other. However, as mentioned above, the imaging lens 130 produces some aberrations in optical imaging such that the imaging size near the center in the region A is small, and the imaging size in the region A near the edge is large. Therefore, if the line widths of the patterns in the wafer regions 144 on the mask 140 are the same, the line widths of the photoresist layers 120 in the die regions 112 on the substrate 110 will be inconsistent after development, and the regions A will be generated. The line width in the grain region 112 near the center is small, and the line width in the grain region 112 near the edge in the region A is large. Therefore, the line widths of the patterns of the wafer regions 144 of the present embodiment are subject to a fixed change (for example, an increasing tendency) from the edge of the reticle 140 to the center of the reticle 140, so that the substrate 110 can be The photoresist layer 120 in the die region 112 has a uniform line width after development. In this way, the line widths of the conductive lines in the crystal grains cut out from the substrate 110 can be made uniform, and the electrical qualities of the crystal grains can be made uniform. In other words, at least two of the wafer regions 144 in the reticle 140 may have substantially the same pattern, but these substantially identical patterns each have a different line width. In more detail, reference can be made to the description of FIGS. 3A and 3B to further understand the variation of the pattern on the photomask 140.

3A is a partial front elevational view of the pattern in the wafer region of the edge of the mask of FIG. 2A, and FIG. 3B is a partial front elevational view of the pattern in the central wafer region of the mask of FIG. 2A. Referring to FIGS. 2A, 3A and 3B, each wafer region 144 may include a pattern, such as pattern 145, of these wafer regions 144. The patterns 145 are substantially identical to one another, and the line widths W of the patterns 145 of the wafer regions 144 tend to increase from being located at the edge of the reticle 140 toward the center of the reticle 140. For example, the line width W1 of the pattern 145 of the wafer region 144 at the edge of the reticle 140 is less than the line width W2 of the pattern 145 of the wafer region 144 at the center of the reticle 140.

In some embodiments, techniques such as phase shift and optical proximity correction (OPC) can be used to bring the developed photoresist pattern closer to the reticle pattern. The phase shifting technique is mainly used to solve the problem that the resolution of the linear pattern on the reticle is too close, and the optical proximity repair is mainly used to solve the problem of rounding the corner of the photoresist pattern. The aforementioned phase shifting and optical proximity repair techniques can be used to repair the distortion of a pattern in a die, and the mask 140 and the exposure method of the present embodiment can be used to narrow the difference between different crystal grains, further In this case, it can be used to compensate for the imaging difference between the grain region near the center and the grain region near the edge due to optical imaging. In the conventional lithography process, the difference in line width between different crystal grains can generally be as large as about 7%, and the mask 140 and the exposure method of the present embodiment can reduce the difference in line width between different crystal grains to Less than 2%, even less than 1%.

4A is a front elevational view of a portion of the wafer substrate of FIG. 2B after being fabricated through a semiconductor process, and FIG. 4B is a front elevational view of a portion of the wiring layout of the die of FIG. 4A. Referring to FIG. 1B, FIG. 2B, FIG. 4A and FIG. 4B, the substrate 110 of FIG. 2B can form a wafer substrate after the exposure process and other semiconductor processes of FIGS. 1A and 1B, and FIG. 4A illustrates the wafer substrate. Front view of the part, The middle region A1 corresponds to the region A of the substrate 110 of FIG. 2B, and the above semiconductor process may be other steps in the lithography process (such as development), etching, ion implantation, removing photoresist, forming a conductive layer, forming Insulation or other semiconductor process. The plurality of regions A1 are connected to each other like the region A of FIG. 2B to constitute a wafer substrate. In the present embodiment, the wafer substrate includes a plurality of dies 212 that are arranged in an array, and each die 212 can include a line layout, such as a line layout 245. These line layouts 245 of the dies 212 are substantially identical to each other, and the difference between the line widths V of the line layouts 245 of the dies 212 is less than 2%. Along the boundary between the die 212 and the die 212, the wafer substrate can be cut into a plurality of wafers, and since the line width V of the wiring layouts 245 of these wafers is not much different, the electrical quality of the wafers is relatively uniform. As a result, the manufacturing yield of the wafer can be improved.

Referring to FIG. 1B, FIG. 2A, FIG. 3A, FIG. 3B, FIG. 4A and FIG. 4B, in the embodiment, the line width W of the patterns 145 of the wafer regions 144 in the mask 140 is located at the edge of the mask 140. The increased tendency to the center of the reticle 140 compensates for the aberrations formed by the imaging lens, so that the line width V of the line layout 254 between the dies 212 of the formed wafer substrate can be relatively uniform. In the present embodiment, the tendency of the increase in the line width W of these patterns 145 of these wafer regions 144 may be stepwise increment. For example, the line widths W of the wafer regions 144 in the region R1 in FIG. 2A are not increased, and the line widths W of the wafer regions 144 in the region R2 are each increased by, for example, 0.005 μm with respect to the line width in the region R1. The line widths W of the wafer regions 144 in the region R3 are each increased by, for example, 0.010 μm with respect to the line width in the region R1, and the line widths W of the wafer regions 144 in the region R4 are all relative to the region R1. The line width is increased by, for example, 0.015 micrometers. However, in other embodiments, the increasing trend of the line width W of the patterns 145 of the wafer regions 144 may also be continuously increasing, that is, from the wafer area 144 located at the edge of the reticle 140 to the center of the reticle 140. When a wafer area 144 is reached, the line width in the number of wafer areas 144 that is counted is increased by a little wider than the line width of the wafer area 144 which was last counted.

In this embodiment, the photoresist layer 120 is a positive photoresist layer, and the patterns 145 are respectively a plurality of light shielding patterns, and the line widths W of the light shielding patterns of the wafer regions 144 are located at the edge of the mask 140. The person is presenting an increasing trend toward the center of the reticle 140. However, in other embodiments, the photoresist layer 120 may also be a negative photoresist layer, and the patterns 145 are respectively a plurality of transparent patterns, and the line widths W of the transparent patterns of the wafer regions 144 are located in the mask. The edge of the 140 presents an increasing trend toward the center of the reticle 140.

In summary, in the wafer substrate of the embodiment of the present invention, since the difference in line width of the line layouts of the crystal grains is less than 2%, that is, the difference in line width of the line layout between different crystal grains is small. Therefore, the wafers cut by the wafer substrate of the embodiment of the present invention have relatively uniform electrical qualities. In the exposure method and the reticle of the embodiment of the present invention, since the line width of the patterns of the wafer regions on the reticle is increased from the edge of the reticle to the center of the reticle, the imaging lens The resulting linewidth distortion problem can be compensated for, thereby providing a relatively uniform electrical quality between the plurality of dies corresponding to the wafer regions, respectively.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art without departing from the invention. In the spirit and scope, the scope of protection of the present invention is subject to the definition of the appended patent application.

140‧‧‧Photomask

144‧‧‧ wafer area

R1, R2, R3, R4‧‧‧ areas

Claims (11)

An exposure method includes: providing a substrate; forming a photoresist layer on the substrate; and imaging a plurality of patterns on a photomask on the photoresist layer by an imaging lens to perform the photoresist layer Exposure, wherein the reticle has a plurality of wafer regions, each of the wafer regions including the pattern, the patterns of the wafer regions being substantially identical to each other, and the line widths of the patterns of the wafer regions are located at the light The edge of the cover presents an increasing tendency towards the center of the reticle. The exposure method of claim 1, wherein the increasing trend of the line width of the patterns compensates for aberrations formed by the imaging lens. The exposure method of claim 1, wherein the photoresist layer is a positive photoresist layer, the patterns are respectively a plurality of light shielding patterns, and the line widths of the light shielding patterns of the wafer regions are located at the light The edge of the cover presents an increasing tendency towards the center of the reticle. The exposure method of claim 1, wherein the photoresist layer is a negative photoresist layer, the patterns are respectively a plurality of light transmissive patterns, and the line widths of the light transmissive patterns of the wafer regions are The edge of the reticle appears to be increasing toward the center of the reticle. The exposure method of claim 1, wherein the increasing trend of the line widths of the patterns of the wafer regions is a stepwise increment or a continuous increment. A reticle comprising: a plurality of wafer regions, each of the wafer regions including a pattern, the patterns of the wafer regions being substantially identical to each other, and the line widths of the patterns of the wafer regions being located at an edge of the mask The centrality of the mask is showing an increasing trend. The photomask of claim 6, wherein the patterns are respectively a plurality of light shielding patterns, and the line widths of the light shielding patterns of the wafer regions are located at the edge of the light mask. The central players are showing an increasing trend. The reticle of claim 6, wherein the increasing trend of the line widths of the patterns of the plurality of wafer regions is a stepwise increment or a continuous increment. An exposure method includes: providing a substrate; forming a photoresist layer on the substrate; and imaging a plurality of patterns on a photomask on the photoresist layer by an imaging lens to perform the photoresist layer Exposure wherein the reticle has a plurality of wafer regions, and at least two of the wafer regions have substantially the same pattern, but the substantially identical patterns each have a different line width. The exposure method of claim 9, wherein each of the wafer regions has substantially the same pattern, and the line widths of the patterns of the wafer regions exhibit a fixed trend. A wafer substrate comprising: a plurality of dies arranged in an array, each dies comprising a line layout, the line layouts of the dies being substantially identical to each other, and line widths of the line layouts of the dies The difference between them is less than 2%.