CN104950588A - Exposure method, mask and chip substrate - Google Patents
Exposure method, mask and chip substrate Download PDFInfo
- Publication number
- CN104950588A CN104950588A CN201410209488.9A CN201410209488A CN104950588A CN 104950588 A CN104950588 A CN 104950588A CN 201410209488 A CN201410209488 A CN 201410209488A CN 104950588 A CN104950588 A CN 104950588A
- Authority
- CN
- China
- Prior art keywords
- mask
- pattern
- chip region
- photoresist layer
- live width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 32
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 40
- 238000003384 imaging method Methods 0.000 claims abstract description 18
- 239000013078 crystal Substances 0.000 claims description 31
- 230000004075 alteration Effects 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 9
- 230000003287 optical effect Effects 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 239000003795 chemical substances by application Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000010363 phase shift Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Abstract
The embodiment of the invention provides an exposure method, a mask and a chip substrate, wherein the method comprises the following steps: providing a substrate; forming a photoresist layer on the substrate; and imaging a plurality of patterns on a mask on the photoresist layer through an imaging lens so as to expose the photoresist layer. The mask has a plurality of chip regions, each chip region includes the pattern, the patterns of the chip regions are substantially the same, and the line widths of the patterns of the chip regions tend to increase from the edge of the mask to the center of the mask. A mask and a chip substrate are also provided.
Description
Technical field
The invention relates to a kind of chip substrate, exposure method and mask.
Background technology
In semiconductor processing, photoetching process (photolithography) account for one of conclusive influence factor for the quality of produced chip.In a lithographic process, the pattern on mask also absolutely free from errors cannot be duplicated into photoetching agent pattern, and this is the impact such as factor being subject to optic factor and photoresist developing hour angle edge sphering.
Summary of the invention
The embodiment of the present invention provides a kind of exposure method, mask and chip substrate (chip substrate), and the live width of the configuration of each crystal grain can be made more consistent.
One embodiment of the invention provide a kind of exposure method, and it comprises: provide a substrate; Substrate is formed a photoresist layer; And by an imaging lens, the multiple patterns on one mask are imaged on photoresist layer, to expose photoresist layer.Wherein, mask has multiple chip region, and each chip region comprises this pattern, and these patterns of these chip region are essentially the same as each other, and the live width of these patterns of these chip region presents the trend of increase from the edge being positioned at mask toward the central authorities being positioned at mask.
One embodiment of the invention also provide a kind of mask, and it comprises multiple chip region, and each chip region comprises a pattern, and these patterns of these chip region are essentially the same as each other.The live width of these patterns of these chip region presents the trend of increase from the edge being positioned at mask toward the central authorities being positioned at mask.
One embodiment of the invention also provide a kind of exposure method, and it comprises: provide a substrate; Substrate is formed a photoresist layer; And by an imaging lens, the pattern on one mask is imaged on photoresist layer, to expose photoresist layer, wherein mask has multiple chip region, and has at least two chip region to have the identical pattern of essence, but the identical pattern of these essence has different live widths respectively.
One embodiment of the invention reoffer a kind of chip substrate, and it comprises multiple crystal grain, and these crystal grain are arranged in array, and each crystal grain comprises a configuration.These configurations of these crystal grain are essentially the same as each other, and the difference between the live width of these configurations of these crystal grain is less than 2%.
Accompanying drawing explanation
Figure 1A and Figure 1B is the schematic diagram of the flow process of the exposure method illustrating one embodiment of the invention.
Fig. 2 A is the front elevational schematic of the mask in Figure 1B.
Fig. 2 B is the front elevational schematic of the substrate in Figure 1B.
Fig. 2 C is the front elevational schematic that substrate in Fig. 2 B is subject to the region of single exposure.
Fig. 3 A is the partial elevational schematic diagram being arranged in the pattern of the chip region at edge in the mask of Fig. 2 A.
Fig. 3 B is the partial elevational schematic diagram being arranged in the pattern of the chip region of central authorities in the mask of Fig. 2 A.
Fig. 4 A is the front elevation of substrate in the part of chip substrate made after semiconductor technology of Fig. 2 B, and wherein this part corresponds to the region A of substrate.
Fig. 4 B is the front elevation of the part configuration in the crystal grain in Fig. 4 A.
Main element symbol description
110: substrate
112: die region
120: photoresist layer
130: imaging lens
140: mask
142: image strip
144: chip region
145: pattern
150: light source
152: illuminating bundle
212: crystal grain
245: configuration
A, A1, R1, R2, R3, R4: region
V, W, W1, W2: live width
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Figure 1A and Figure 1B is the schematic diagram of the flow process of the exposure method illustrating one embodiment of the invention, Fig. 2 A is the front elevational schematic of the mask in Figure 1B, Fig. 2 B is the front elevational schematic of the substrate in Figure 1B, and Fig. 2 C is substrate in Fig. 2 B is subject to the front elevational schematic of the subregion of single exposure.Please refer to Figure 1A, Figure 1B and Fig. 2 A to Fig. 2 C, the exposure method of the present embodiment comprises the following steps.First, please refer to Figure 1A, provide a substrate 110, substrate 110 is such as silicon substrate, other semiconductor substrates, glass substrate, plastic substrate or other suitable substrates.Afterwards, substrate 110 is formed a photoresist layer 120, aforementionedly mention that on substrate 110, form a photoresist layer 120 can be, directly formed on substrate 110 on a photoresist layer 120, other materials layer on substrate and form photoresist layer 120, or other generation types.The mode forming photoresist layer 120 is such as be coated with (as rotary coating) technique to be coated on substrate 110 by photoresist layer 120, or is formed on substrate 110 by photoresist layer 120 in other suitable modes (such as jet printing technique).
Then, referring again to Figure 1B, imaging on photoresist layer 120 by an imaging lens 130 by a mask 140, such as, is image on photoresist layer 120 by the pattern on mask 140, to expose photoresist layer 120.In the present embodiment, provide an illuminating bundle 152 by a light source 150, illuminating bundle 152 forms the image strip 142 that carries the pattern information on mask 140 after mask 140.In the present embodiment, light source 150 is such as a ultraviolet source, and illuminating bundle 152 is such as ultraviolet light beam.But, in other embodiments, the light source that the made photoresist layer 120 of other wavelength or wave band exposes also can be adopted.
When utilizing mask to make single exposure to the region of on substrate, this region can form multiple crystal grain (die) district lining up array in the future usually.That is, on mask corresponding have multiplely line up array and the pattern that essence is identical each other.For the imaging lens of exposure machine, the light near the optical axis of imaging lens is easier to optically focused, and therefore when the pattern that these essence mask being lined up array are identical is imaged on substrate, the live width the closer to the photoetching agent pattern of optical axis can be less.Thus, the live width of the pattern in multiple die region that single exposure is formed will be inconsistent, and then the electrical quality of manufactured crystal grain or chip (chip) may be caused inconsistent.
Please refer to Figure 1B and Fig. 2 A to Fig. 2 C, in the present embodiment, mask 140 can have multiple chip region 144, and mask 140 can be imaged camera lens 130 respectively and image on the multiple different region A of substrate 110 in multiple different time.Wherein substrate 110 is such as wafer (wafer), and these chip region 144 of mask 140 can be imaged on the multiple die region 112 on substrate 110 respectively, and these die region 112 are by manufactured and cut into multiple crystal grain be essentially the same as each other, the pattern in these chip region 144 of therefore mask 140 is essentially the same as each other.But as previously suggested, imaging lens 130 can produce the aberration on some optical imageries, and make in the A of region less by ectocentral imaging size, and make submarginal imaging size in the A of region larger.Therefore, if when the live width of the pattern in these chip region 144 on mask 140 is all identical, by inconsistent for photoresist layer 120 live width after development in the die region 112 that makes on substrate 110, and produce in the A of region little by the live width in ectocentral die region 112, the situation that the live width in the A of region in submarginal die region 112 is large.So the trend (such as presenting the trend of increase) that the live width of these patterns of these chip region 144 of the present embodiment presents fixing change from the edge being arranged in mask 140 toward the central authorities being positioned at mask 140 can make photoresist layer 120 live width after development of the die region 112 on substrate 110 more consistent.Thus, the live width of the conducting wire the crystal grain cut out from substrate 110 just can be made more consistent, and then make the electrical quality of these crystal grain more consistent.In other words, two chip region 144 can be had at least in mask 140 to have the identical pattern of essence, but the identical pattern of these essence have different live widths respectively.In more detail, can refer to describing with the change understanding the pattern on mask 140 further of Fig. 3 A and Fig. 3 B.
Fig. 3 A is the partial elevational schematic diagram being arranged in the pattern of the chip region at edge in the mask of Fig. 2 A, and Fig. 3 B is the partial elevational schematic diagram being arranged in the pattern of the chip region of central authorities in the mask of Fig. 2 A.Please refer to Fig. 2 A, Fig. 3 A and Fig. 3 B, each chip region 144 can comprise a pattern, such as pattern 145, these patterns 145 of these chip region 144 are essentially the same as each other, and the live width W of these patterns 145 of these chip region 144 presents the trend of increase from the edge being positioned at mask 140 toward the central authorities being positioned at mask 140.For example, the live width W1 being positioned at the pattern 145 of the chip region 144 at the edge of mask 140 is less than the live width W2 of the pattern 145 of the chip region 144 of the central authorities being positioned at mask 140.
In embodiments of the present invention, phase shift (phase shift) and optical nearing repair technology such as (optical proximity correction, OPC) can in order to make the photoetching agent pattern after development more close to mask pattern.Phase-shifting technique mainly in order to solve linear pattern on mask too close to time the resolution that the produces problem that declines, optical nearing is repaired then mainly in order to solve the problem of the angle edge sphering of photoetching agent pattern.The aforementioned technology such as phase shift and optical nearing repairing mentioned is the distortion of the pattern that can be used in repairing crystal grain, the mask 140 of the present embodiment and exposure method then can be used to reduce the difference between different crystal grain, further, can in order to make up the imaging difference caused because of optical imagery by ectocentral die region and submarginal die region.In existing photoetching process, the live width difference between different crystal grain can be as big as about 7% usually, and the live width difference between different crystal grain then can be reduced to and be less than 2% by the mask 140 of the present embodiment and exposure method, or even is less than 1%.
Fig. 4 A is the front elevation of substrate in a part for chip substrate made after semiconductor technology of Fig. 2 B, and Fig. 4 B is the front elevation of the part configuration in crystal grain in Fig. 4 A.Please refer to Figure 1B, Fig. 2 B, Fig. 4 A and Fig. 4 B, the substrate 110 of Fig. 2 B is after the exposure technology and other semiconductor technologies of such as Figure 1A and Figure 1B, a chip substrate can be formed, and Fig. 4 A illustrates the front elevation of the part of this chip substrate, wherein A1 system in region corresponds to the region A of substrate 110 of Fig. 2 B, and above-mentioned semiconductor technology can be other steps (as development), etching, ion implantation in photoetching process, remove photoresist, form conductive layer, formation insulation course or other semiconductor technologies.Multiple region A1 just connects and forms chip substrate as the region A of Fig. 2 B.In the present embodiment, chip substrate comprises multiple crystal grain 212, and these crystal grain 212 are arranged in array, and each crystal grain 212 can comprise a configuration, such as configuration 245.These configurations 245 of these crystal grain 212 are essentially the same as each other, and the difference between the live width V of these configurations 245 of these crystal grain 212 is less than 2%.Border between crystal grain 212 and crystal grain 212, chip substrate can be cut to multiple chip, and due to the live width V difference of the configuration 245 of these chips little, therefore the electrical quality of these chips is more consistent.Thus, the fine ratio of product of chip can just be promoted.
Referring again to Figure 1B, Fig. 2 A, Fig. 3 A, Fig. 3 B, Fig. 4 A and Fig. 4 B, in the present embodiment, the trend that in mask 140, the live width W of these patterns 145 of these chip region 144 is presented increase from the edge being positioned at mask 140 toward the central authorities being positioned at mask 140 compensate for the aberration that imaging lens is formed, and the live width V of the configuration 254 between each crystal grain 212 of therefore formed chip substrate can be more consistent.In the present embodiment, the trend of the increase of the live width W of these patterns 145 of these chip region 144 can be segment increasing.For example, the live width W of these chip region 144 of the region R1 among Fig. 2 A does not all increase, the live width W of these chip region 144 in the R2 of region is all relative to the live width increase in the R1 of region such as 0.005 micron, the live width W of these chip region 144 in the R3 of region is all relative to the live width increase in the R1 of region such as 0.010 micron, and the live width W of these chip region 144 in the R4 of region is all relative to the live width increase in the R1 of region such as 0.015 micron.But, in other embodiments, the trend of the increase of the live width W of these patterns 145 of these chip region 144 can also be increase progressively continuously, that is when often coming a chip region 144 toward the central number of mask 140 from the chip region 144 being positioned at mask 140 edge, increased some width compared with compared to the last time by chip region 144 live width counted to by the live width in this chip region 144 of counting to.
In the present embodiment, photoresist layer 120 is positive photoresist layer (positive photoresist layer), these patterns 145 are respectively multiple light-shielding pattern, and the live width W of these light-shielding patterns of these chip region 144 presents the trend of increase from the edge being positioned at mask 140 toward the central authorities being positioned at mask 140.But, in other embodiments, photoresist layer 120 also can be negative photoresist layer, then these patterns 145 are respectively multiple light-transparent pattern, and the live width W of these light-transparent patterns of these chip region 144 presents the trend of increase from the edge being positioned at mask 140 toward the central authorities being positioned at mask 140.
In sum, in the chip substrate of embodiments of the invention, because the difference of the live width of these configurations of these crystal grain is less than 2%, the difference of the live width of namely different intercrystalline configurations is less, therefore embodiments of the invention chip substrate the chip chamber that cuts there is more consistent electrical quality.In the exposure method and mask of embodiments of the invention, because the live width of these patterns of these chip region on mask to present the trend of increase from the edge being positioned at mask toward the central authorities being positioned at mask, therefore the live width problem of dtmf distortion DTMF that imaging lens produces can obtain compensation, and then makes the multiple intercrystallines corresponding respectively to these chip region have more consistent electrical quality.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the claim person of defining.
Claims (11)
1. an exposure method, is characterized in that, described exposure method comprises:
One substrate is provided;
Form a photoresist layer on the substrate; And
By an imaging lens, the multiple patterns on one mask are imaged on this photoresist layer, to expose this photoresist layer, wherein this mask has multiple chip region, each this chip region comprises this pattern, the described pattern of described chip region is mutually the same, and the live width of the described pattern of described chip region presents the trend of increase from the edge being positioned at this mask toward the central authorities being positioned at this mask.
2. exposure method as claimed in claim 1, is characterized in that, the trend of this increase of the live width of described pattern compensate for the aberration that this imaging lens is formed.
3. exposure method as claimed in claim 1, it is characterized in that, this photoresist layer is positive photoresist layer, and described pattern is respectively multiple light-shielding pattern, and the live width of the described light-shielding pattern of described chip region presents the trend of increase from the edge being positioned at this mask toward the central authorities being positioned at this mask.
4. exposure method as claimed in claim 1, it is characterized in that, this photoresist layer is negative photoresist layer, and described pattern is respectively multiple light-transparent pattern, and the live width of the described light-transparent pattern of described chip region presents the trend of increase from the edge being positioned at this mask toward the central authorities being positioned at this mask.
5. exposure method as claimed in claim 1, it is characterized in that, the trend of this increase of the live width of the described pattern of described chip region is segment increasing or increases progressively continuously.
6. a mask, is characterized in that, described mask comprises:
Multiple chip region, each this chip region comprises a pattern, and the described pattern of described chip region is mutually the same, and the live width of the described pattern of described chip region presents the trend of increase from the edge being positioned at this mask toward the central authorities being positioned at this mask.
7. mask as claimed in claim 6, it is characterized in that, described pattern is respectively multiple light-shielding pattern, and the live width of the described light-shielding pattern of described chip region presents the trend of increase from the edge being positioned at this mask toward the central authorities being positioned at this mask.
8. mask as claimed in claim 6, it is characterized in that, the trend of this increase of the live width of the described pattern of described chip region is segment increasing or increases progressively continuously.
9. an exposure method, is characterized in that, described exposure method comprises:
One substrate is provided;
Form a photoresist layer on the substrate; And
By an imaging lens, the multiple patterns on one mask are imaged on this photoresist layer, to expose this photoresist layer, wherein this mask has multiple chip region, and has at least two chip region to have identical described pattern, but described identical pattern has different live widths respectively.
10. exposure method as claimed in claim 9, it is characterized in that, chip region described in each has identical pattern, and the live width of the described pattern of described chip region presents a fixing variation tendency.
11. 1 kinds of chip substrates, is characterized in that, described chip substrate comprises:
Multiple crystal grain, is arranged in array, and each crystal grain comprises a configuration, and the described configuration of described crystal grain is mutually the same, and the difference between the live width of the described configuration of described crystal grain is less than 2%.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103111792 | 2014-03-28 | ||
| TW103111792A TW201537304A (en) | 2014-03-28 | 2014-03-28 | Exposure method, photomask, and chip substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104950588A true CN104950588A (en) | 2015-09-30 |
Family
ID=54165349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410209488.9A Pending CN104950588A (en) | 2014-03-28 | 2014-05-16 | Exposure method, mask and chip substrate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104950588A (en) |
| TW (1) | TW201537304A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109491197A (en) * | 2018-11-30 | 2019-03-19 | 上海华力微电子有限公司 | A kind of detection method of mask plate and camera lens lightening homogeneity |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129852A (en) * | 1994-12-29 | 1996-08-28 | 现代电子产业株式会社 | Light exposure mask for semiconductor devices |
| TW462078B (en) * | 2001-01-17 | 2001-11-01 | United Microelectronics Corp | Optical proximity correction method based on contact hole model |
| KR20060024628A (en) * | 2004-09-14 | 2006-03-17 | 주식회사 하이닉스반도체 | Exposure mask |
| US20060246362A1 (en) * | 2005-05-02 | 2006-11-02 | Elpida Memory, Inc. | Mask data creation method |
| TW200639578A (en) * | 2005-05-03 | 2006-11-16 | Nanya Technology Corp | Lithographic process and the mask used in the same |
| CN101042527A (en) * | 2006-03-20 | 2007-09-26 | 中芯国际集成电路制造(上海)有限公司 | Compensation process for critical dimension homogeneity |
| CN101364047A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting light intensity distribution of gradient filter and method for enhancing consistency of line width |
| CN101464625A (en) * | 2007-12-20 | 2009-06-24 | 上海光刻电子科技有限公司 | Precompensation technology for photo-etching mask plate characteristic line width equality |
| CN102466982A (en) * | 2010-11-16 | 2012-05-23 | 无锡华润上华半导体有限公司 | Test method for line width uniformity |
-
2014
- 2014-03-28 TW TW103111792A patent/TW201537304A/en unknown
- 2014-05-16 CN CN201410209488.9A patent/CN104950588A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1129852A (en) * | 1994-12-29 | 1996-08-28 | 现代电子产业株式会社 | Light exposure mask for semiconductor devices |
| TW462078B (en) * | 2001-01-17 | 2001-11-01 | United Microelectronics Corp | Optical proximity correction method based on contact hole model |
| KR20060024628A (en) * | 2004-09-14 | 2006-03-17 | 주식회사 하이닉스반도체 | Exposure mask |
| US20060246362A1 (en) * | 2005-05-02 | 2006-11-02 | Elpida Memory, Inc. | Mask data creation method |
| TW200639578A (en) * | 2005-05-03 | 2006-11-16 | Nanya Technology Corp | Lithographic process and the mask used in the same |
| CN101042527A (en) * | 2006-03-20 | 2007-09-26 | 中芯国际集成电路制造(上海)有限公司 | Compensation process for critical dimension homogeneity |
| CN101364047A (en) * | 2007-08-09 | 2009-02-11 | 中芯国际集成电路制造(上海)有限公司 | Method for detecting light intensity distribution of gradient filter and method for enhancing consistency of line width |
| CN101464625A (en) * | 2007-12-20 | 2009-06-24 | 上海光刻电子科技有限公司 | Precompensation technology for photo-etching mask plate characteristic line width equality |
| CN102466982A (en) * | 2010-11-16 | 2012-05-23 | 无锡华润上华半导体有限公司 | Test method for line width uniformity |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109491197A (en) * | 2018-11-30 | 2019-03-19 | 上海华力微电子有限公司 | A kind of detection method of mask plate and camera lens lightening homogeneity |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201537304A (en) | 2015-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8728713B2 (en) | Stitching methods using multiple microlithographic expose tools | |
| JP3556591B2 (en) | Defect repair method of gray tone part in gray tone mask | |
| TW200933289A (en) | Photomask, method of manufacturing the photomask, and method of transferring a pattern | |
| US7745072B2 (en) | Method of correcting critical dimension in photomask and photomask having corrected critical dimension using the method | |
| US20090142675A1 (en) | Reticle for optical proximity correction test pattern and method of manufacturing the same | |
| CN110095946B (en) | Projection optical system, exposure apparatus, and method for manufacturing article | |
| CN104950588A (en) | Exposure method, mask and chip substrate | |
| CN101989039B (en) | Method for fabricating photomask | |
| JP4794408B2 (en) | Photomask and semiconductor device manufacturing method | |
| JP2013055197A (en) | Exposure method and exposure mask | |
| CN114256209A (en) | Large-size chip design layout structure | |
| CN112965349A (en) | Wafer alignment method and wafer double-side measurement system | |
| KR101952990B1 (en) | Mask for evaluation, evaluating method, exposure apparatus and method of manufacturing an article | |
| CN113050367A (en) | Optical proximity effect correction method and system, mask and preparation method thereof | |
| JP2009237289A (en) | Halftone phase shift mask and method for manufacturing the same | |
| US7312020B2 (en) | Lithography method | |
| US20070072128A1 (en) | Method of manufacturing an integrated circuit to obtain uniform exposure in a photolithographic process | |
| JP2005031287A (en) | Projection aligner, reticle used in projection aligner, projection exposure method and method for manufacturing semiconductor device | |
| JP2018072690A (en) | Photomask and method for manufacturing electronic device | |
| US9366969B2 (en) | Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication | |
| US8472005B2 (en) | Methodology for implementing enhanced optical lithography for hole patterning in semiconductor fabrication | |
| JP2011257614A (en) | Photo mask, method for reprocessing the same and method for forming resist pattern | |
| CN101644889B (en) | Photoetching scattering strip for improving focal depth and manufacturing method thereof | |
| JPH10256126A (en) | Exposing method | |
| JP2009010122A (en) | Mask for microlens formation, and solid-state imaging element formed therewith |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150930 |
|
| WD01 | Invention patent application deemed withdrawn after publication |