TW201530125A - Method for measuring and analyzing surface structure of chip or wafer - Google Patents

Abstract

A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip or wafer by an instrument, and then performing an image extraction on the image to convert into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at last one target in the image are compared to get a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected form one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect.

Description

Method for measuring and analyzing wafer or wafer surface structures

The present invention relates to a surface structure analysis technique for a wafer, and more particularly to a method of measuring and analyzing a wafer or wafer surface structure.

As the line width of the IC process continues to shrink, the control and monitoring of the critical dimension (CD) of the process is also more important. From the perspective of nanometer semiconductor technology, it is even more difficult to accurately obtain the surface structure on a wafer such as a line width.

Traditionally, a critical dimension scanning electron microscope (CD-SEM) has been used as a wafer line width measurement surface structure analysis. However, because the measurement speed is quite slow, and a photo only outputs a small amount of measurement information, it is impossible to obtain a large amount of measurement values in real time.

For nano generation semiconductor wafers, CD-SEM can only obtain data of one-dimensional images, such as line edge roughness (LER), line width roughness (LWR) and other linear pattern roughness. Measure. As for the measurement of the two-dimensional image, the contact edge roughness (CER) of the circular contact can only be calculated by the specific software.

Therefore, there is a need to find a measurement method capable of obtaining surface structures of all types on a wafer, and more even a method for quickly obtaining defect information such as critical dimension uniformity (CDU) of an entire chip.

The present invention provides a method of measuring the surface structure of a wafer or wafer, which can instantly and accurately obtain a two-dimensional structural pattern of the surface of the wafer.

The invention further provides a method for analyzing the surface structure of a wafer or a wafer, which can quickly and quickly obtain defect information of the surface structure of the entire wafer.

The invention further provides a method for supplementing the yellow light exposure, and the complementary value can be performed without establishing a model.

A method for measuring a surface structure of a wafer or a wafer according to an embodiment of the present invention includes obtaining an image of a surface structure of the wafer by using an instrument, and performing image extraction on the image and converting the image into a first circuit design file. Another standard image is selected and converted into a second circuit design file, and then at least one target and the standard image in the image are compared to obtain a difference between the target and the standard image. Line edge roughness (LER), line width roughness (LWR), contact window edge roughness (CER), critical dimension (CD), critical dimension deviation (Bias) of the surface structure are generated according to the gap ), 3igma, maximum, minimum, etc., and at least one of repetitive defects.

In an embodiment of the invention, the method may further include obtaining, by the data, a critical dimension uniformity (CDU) and a Bias difference of the entire wafer or wafer.

In an embodiment of the invention, the method may further derive the performance and trend of the wafer or wafer by the data of the surface structure.

In an embodiment of the invention, the surface structure of the wafer includes a surface structure within a range of a single yellow light shot in the wafer.

A method for analyzing a surface structure of a wafer or a wafer according to another embodiment of the present invention includes obtaining a plurality of defective regions in a chip on a wafer, and then using the instrument to obtain an image of at least one defective region, and then The image is image extracted and converted into a first circuit design file. Another standard image is selected and converted into a second circuit design file, and then the image is compared with the standard image to obtain a difference between the image and the standard image. Line edge roughness (LER), line width roughness (LWR), contact window edge roughness (CER), critical dimension (CD), critical dimension deviation (Bias), and repetition of the defect region are generated according to the gap At least one of the data of a sexual defect.

In another embodiment of the invention, the method of obtaining the defect region includes performing a wafer mapping of the entire wafer.

In another embodiment of the present invention, the method of obtaining the defective area includes marking an area where defects are likely to occur according to a rule of thumb.

In another embodiment of the present invention, the method of obtaining the defective area includes setting an area exceeding or lower than a set value as the defective area according to design rule data.

In another embodiment of the present invention, the above method may further include deriving the performance and trend of the entire wafer after obtaining data of all defective regions.

In another embodiment of the invention, the measurement magnitude difference mapping is color coded based on the severity of the defect measurement size difference associated with each of the defect regions.

A method for supplementing the yellow light exposure according to still another embodiment of the present invention comprises: obtaining an image of the surface structure of the exposed wafer by using an E-Beam inspection tool, and performing image extraction and conversion on the image. Design the file for the first circuit. Another standard image is selected and converted to the second circuit design file, and then the complement calculation is performed.

In still another embodiment of the present invention, the image includes an image of a defect area of each of the wafers in a wafer or a single yellow light exposure in the wafer.

In various embodiments of the present invention, the apparatus for obtaining an image includes a key size scanning electron microscope (CD-SEM), an electron beam inspection tool (E-Beam inspection tool), and a scanning electron microscope detection camera table (SEM). Review tool), Bright field inspection equipment with a wavelength of 150nm ~ 800nm light source or laser light source with Dark field inspection equipment.

In various embodiments of the present invention, the first circuit design file and the second circuit design file are graphical data system files.

In various embodiments of the invention, the standard image is derived, for example, from a design database, post optical proximity effect correction (post-OPC), or converted by a simulated tool.

In various embodiments of the invention, the image extraction includes adjusting a grayscale of the background or a grayscale of the foreground to extract contours of the two-dimensional (2D) image of the image.

In various embodiments of the present invention, the image extraction may further include performing gray scale equalization when the contrast difference of the image is greater than a preset value; and when the grayscale difference of the image is greater than another preset value , separate the images.

In various embodiments of the present invention, the image extraction may further include supplementing the image in which the difference is made.

Based on the above, according to the method of the embodiment of the present invention, the two-dimensional structure pattern of the wafer surface can be accurately obtained, and the wafer or the wafer can be measured by the wafer mapping method. All defect areas on the wafer change trend, and the defect information of the surface structure of the entire wafer is accelerated.

The above described features and advantages of the invention will be apparent from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a timing chart showing the surface structure of a wafer in accordance with a first embodiment of the present invention. The so-called surface structure is a structure formed on a chip by which an image can be obtained by an optical or electron microscope, such as a structure of a photoresist layer, a structure of an insulating layer, a structure of a conductor layer, and the like. Similarly, the structure formed on the entire wafer can also be measured by the same method.

First, step 100 is performed to obtain an image of the surface structure of the wafer by using an instrument, wherein the instrument can be a key size scanning electron microscope (CD-SEM), an electron beam inspection tool (E-Beam inspection tool), and an SEM detection camera machine. (SEM review tool), Bright field inspection equipment with a wavelength of 150 nm ~ 800 nm light source or a laser light source with Dark field inspection equipment. If an electron beam inspection tool is used, an electron beam inspection tool with a high resolution (for example, a resolution of 5 nm or less) can be used, and the coordinates can be marked at the time of image output; or under a known coordinate (for example, directly converted by Klarf coordinates) Take a photo.

Then, in step 102, the image is image extracted and converted into a first circuit design file. The above image extraction extracts contours of two-dimensional (2D) images. Methods for image extraction may include Edge contour extraction, Self-Affine mapping system, Self-Affine snake model, Active contour model. , expectation-maximisation algorithm, principal component analysis, level sets algorithm or Monte Carlo techniques. Moreover, the above-mentioned image extraction type may include off-line extraction or on-line extraction, wherein off-line extraction can accurately obtain the contour of the structure, and on-line extraction can achieve immediate treatment by rapid calculation. And can mark the coordinates. As for the circuit design file in this embodiment, it generally refers to a circuit design file for a semiconductor circuit design (ie, a wafer), such as a graphic data system file, such as a GDSII file or another graphic data system OASIS format. Can also be used.

In addition, for the image extraction step, different results can be obtained by adjusting the formulation to conform to the CD-SEM results, such as adjusting the gray scale of the background or the gray scale of the foreground, as shown in FIG. 2A and FIG. 2B. Figure 2A shows a statistical chart with a background grayscale of 20 and a foreground grayscale of 14 with an average linewidth of about 32 nm. Figure 2B shows a line width distribution graph with a background gray scale of 20 and a foreground gray scale of 94 with an average linewidth of about 40 nm. Therefore, the CDU can be made to meet the CD-SEM target or a standard by changing the extraction recipe. In addition, when the contrast of the image is too large (ie, greater than a certain preset value), image gray level equalization may be performed; when the grayscale difference is too large (ie, greater than a preset value), the image may be separated. The subsequent extraction operation is performed on the image with normal gray scale, and the image group with excessive difference is first corrected and then image extracted.

Step 104 is to select a standard image and convert it into a second circuit design file, wherein the first circuit design file and the second circuit design file are the same type of file. Moreover, the standard image can be defined by a design database, post-OPC, or converted by a simulated tool. There is no absolute sequence between step 104 and step 102.

Then in step 106, the target and the standard image in the image are compared to obtain the difference between the two. Since the information has been converted to the same file in both step 102 and step 104, it is possible to quickly compare the specific target area of the surface structure in which the information is desired to be compared with the standard image. Moreover, if the data of steps 102 and 104 are both marked with coordinates, a more accurate comparison can be performed.

Then, step 108 is performed to generate line edge roughness (LER), line width roughness (LWR), contact window edge roughness (CER), critical dimension (CD), and critical dimension deviation value (Bias) of the surface structure according to the above difference. At least one of a 3igma, a maximum, a minimum, and the like, and a repeating defect of the wafer. For example, by means of post-OPC comparison, it is possible to compare and find some repetitive defects and morphologies that are different from the target.

After obtaining the above data, step 110 can be selected, and the performance and trend of the wafer are derived by the above data.

The present invention is also applicable to a method of yellow light exposure correction. The so-called yellow light exposure compensation is usually an action that optimizes the yellow light process parameters for defects caused by the yellow light process. In general, the CDU collected by the yellow light complement or yellow light exposure map is less than 20 points CD-SEM measurement in one chip or one shot (shot), on a wafer. Medium is a CD-SEM measurement of less than 150 points, so it is necessary to establish a model and then perform a supplementary action. However, in the present invention, it is possible to measure thousands to tens of thousands of points in one wafer or one exposure, so that it is possible to directly perform a supplementary value operation or recalculate OPC data (re-tape out mask). There is no need to establish a model.

Steps 100-106 of the present embodiment are used for the defect detection process of the yellow light exposure compensation value, instead of the complicated and lengthy test analysis establishment mode step.

Since an instrument such as a high-resolution (for example, a resolution of 0.1 nm to 5 nm) electron beam detecting tool is used, an image of the exposed wafer can be obtained immediately. In this embodiment, an image of a defect area of each chip in the entire wafer or an image of only a range of yellow light (which may include a defect area of 2 to 3 wafers) may be obtained. Then, when the image of the entire wafer is image-extracted and then complemented, the CDU value for improving the yellow exposure can be achieved.

In the first embodiment, one or more of the following actions can be performed in the processor by the software according to different appeals: 1. Take a SEM photograph with a coordinate position or a known position to directly take a photographing action. 1-1. Image coordinate position decoding. 2. Instant image contour extraction. 3. Instantly compare and check the difference with the standard target database layout database, and then output the results. 4. Instantly output the difference between each image and the standard target database layout. 5. After collecting all the images, compare the target with the target to find the weakness of the system. 6. Collect the difference between all the images and output the Process window. 7. Collect all image or image extraction and output the CD uniformity of the entire wafer. 8. Collect all image or image extraction and output the LER and LWR trend of the entire wafer. 9. The CER of the entire wafer can be output after collecting all the images of the contact window or the connection window. 10. Output deviation value (difference between line width or spacing and standard target database layout), 3 sigma, maximum (maximum), minimum (minimum), etc. 11. Instant CD measurements and LER/LWR/CER measurements.

When the surface structure is a circular contact window, the CD-SEM image obtained through the step 100 of the first embodiment can be subjected to image extraction to obtain a contour view as shown in FIG. 3A or FIG. 3B. Figure 3A shows a larger circular contact window 300, so its spacing is smaller than the target 302; conversely, if the image extracted contour is smaller than the circular contact window 304 as shown in Figure 3B, the spacing is Will be larger than target 302. In other words, the CD value of the circular contact window can be monitored by the critical dimension (CD) of the wafer or wafer surface structure, and the results are displayed across the wafer's key size difference map. It can also directly compare the size of the contact window.

In addition to measuring the circular contact window, when the surface structure of the wafer is the circuit layout design shown in FIG. 4, the outline 400 of the surface structure can be obtained by the image extraction step 102 of the first embodiment, and the circuit layout Design (ie, standard image) 402 comparison, can produce maximum and minimum critical dimensions (CD) by the difference between the two and thus obtain critical dimension uniformity (CDU), critical dimension deviation (Bias), deviation percentage (Bias%) , 3 sigma, maximum, minimum and other data, as well as LER, LWR, CER and other line width defect information. Since the method of the first embodiment can obtain a clear outline of the two-dimensional image, the portion 404 where the defect occurs can be accurately obtained, and thereby the circuit layout and the process parameters thereof can be corrected or changed to prevent problems such as circuit breaking.

Figure 5 is a step diagram showing the analysis of the surface structure of a wafer in accordance with a second embodiment of the present invention. The so-called surface structure is a structure formed on a wafer by which an image can be obtained by an optical or electron microscope, such as a structure of a photoresist layer, a structure of an insulating layer, a structure of a conductor layer, etc., and the above structure is distributed on a wafer. The structure is repeated on each chip (chip, die).

First, step 500 is performed to obtain a plurality of defective regions in a chip to be measured on a wafer. The implementation of this step is, for example, performing a wafer mapping on the entire wafer, marking an area susceptible to defects according to an empirical rule, or setting a value above or below a certain value according to design rule data. The area of the value is used as the defect area. Moreover, these defective areas can be color coded according to the defects (line width or spacing) associated with each part.

Then, step 502 is performed to obtain an image of the defective area using the instrument, wherein the apparatus used is as described in the first embodiment. Moreover, in this step, image acquisition can be performed only on a single defect area, or only the defect area in the target area can be selected for image acquisition. Of course, image acquisition can be performed on all defect areas according to requirements.

Then, in step 504, the image is image extracted and converted into a first circuit design file, wherein the circuit design file refers to a circuit design file for a semiconductor circuit design, such as a circuit design file such as a GDS file. The image extraction can extract the outline of the two-dimensional (2D) image, and the extracted outline size can be extracted in the manner shown in step 102 of the first embodiment or FIGS. 2A-2B. As for the method and type of image extraction, reference can be made to the first embodiment.

Step 506 is to select a standard image and convert it into a second circuit design file, wherein the first and second circuit design files can be the same type of file. The standard image is for example converted by a design database, post optical proximity correction (post-OPC), or converted by a simulated tool. There is no absolute sequence between step 504 and step 506.

Then in step 508, the image and the standard image are compared to obtain a difference between the two. Since the information has been converted to the same file in both step 504 and step 508, the defect area and the standard image in the surface structure can be compared instantly and quickly.

Then, step 510 is performed to generate line edge roughness (LER), line width roughness (LWR), contact window edge roughness (CER), critical dimension uniformity (CD), and critical dimension deviation value of the defect region according to the above difference ( Bias), 3 sigma, maximum, minimum, etc., and at least one of the repetitive defects.

After obtaining the above data, step 512 can be selected to derive the performance and trend of the entire wafer by the data of the defect area. Because the embodiment can select the measurement difference difference of the whole wafer first, that is, the coarse step scanning is performed first to obtain all the defect regions on the wafer, thereby speeding up the defect information of obtaining the surface structure of the entire wafer or a specific target area. .

6 is a diagram of a method for measuring a critical dimension of a wafer in accordance with a third embodiment of the present invention. The so-called critical dimension uniformity may be the critical dimension uniformity of the line width and width formed on the wafer, the critical dimension uniformity of the contact, or the line width and spacing or area of the irregular pattern. Wait.

First, step 600 is performed to obtain a plurality of defect areas in the chip to be measured on the entire wafer, wherein the "defect area" means an area where the critical dimension uniformity may be poor or a region to be measured. As for how to obtain this defect area, the wafer mapping of the key size uniformity difference in the entire wafer can be performed, and color coding is performed according to the size of each part to visualize the line width distribution and the pitch distribution in the wafer. In addition, it is also possible to mark several areas where the critical dimension uniformity may be unfavorable according to the rule of thumb; or, according to the design rule data, set a region exceeding a certain value or below a certain value as a defective area, for example, All of the line widths below 0.8 μm are regarded as defect areas to be tested. In addition, it is also possible to partition the entire wafer and set each area as a "defect area" for measurement.

Then, step 602 is performed, and an image of the defect area is obtained instantaneously by using an electron beam detecting tool such as a high resolution (resolution below 5 nm); or a Klarf file is converted into a Klarf file by a known design point to detect the camera machine by SEM (SEM review) Tool) Get an image of the defective area. In this step, image acquisition of the above defect area can be performed comprehensively.

For example, if the wafer has a plurality of wires as shown in FIG. 7A, the region having a small line width is prone to poor uniformity of key dimensions according to the rule of thumb, so that four regions 701 to 704 are marked as the defect regions to be tested. As a result, after the image was taken by the electron beam detecting tool, the test points as shown in Fig. 7B can be collected. As can be seen from Fig. 7B, even a small area 704 can collect hundreds of points, and only two to five points in the die can be viewed with the CD-SEM, and accurate and immediate results can be obtained. However, the present invention is not limited thereto, and may not mark the measurement area, but set a region exceeding a certain value or lower than a certain value as a defect area according to design rule data, and the measurement range is all of the image extraction. The position, in which the line width and space (width/space) range that meets the above settings can be quickly collected.

Then, in step 604, image extraction is performed and converted into a first circuit design file, wherein the circuit design file refers to a circuit design file for a semiconductor circuit design, such as a circuit design file such as a GDS or an OASIS file. As for the method and type of image extraction, reference can be made to the first embodiment.

Step 606 is to select a standard image and convert it into a second circuit design file, wherein the first and second circuit design files can be the same type of file. There is no absolute sequence between step 604 and step 606, and step 606 is not required if only the first circuit design file size is to be measured. Typically, the second circuit design file described above is the original circuit design file or the post OPC simulation result or the original circuit layout design.

Then, in step 608, the results of the image extraction are analyzed and measured at intervals of 0.0001 μm to 0.01 μm to obtain critical dimension uniformity (CDU). The data of several thousand points obtained in Fig. 7B can be converted by software to obtain a space distribution as shown in Fig. 7C and a line width distribution shown in Fig. 7D. Further, according to the results of FIG. 7D, the different regions 701 to 704 are respectively displayed, whereby the distribution curve 7E can be obtained, so that the CDU can be acquired instantaneously and quickly, and the difference of the difference (Bias difference) can be obtained.

8A and 8B are schematic views of another application of the third embodiment. FIG. 8A shows a region 800 in a single die in which two lines 802 and three spaced spaces 804 are included. If the key size uniform measurement is performed on the area 800 by using the steps of FIG. 5, the test points as shown in FIG. 8B can be collected, wherein the interval can measure 507 points and the line width can measure 303 points, far more than before. Using CD-SEM can only see 2 to 5 points in the die to get more accurate and immediate results.

9A to 9C are still another application diagram of the third embodiment. FIG. 9A is a diagram showing the difference in the size uniformity of the wafers obtained by the software conversion after image extraction and the image of the defective area of each chip in a wafer after the high-resolution electron beam detecting tool is obtained. (wafer mapping). In Fig. 9A, the data difference is displayed in gray scale, but it is actually marked by a diffuse color, so that the difference point can be easily observed. At the same time, the linewidth distribution of the entire wafer can be converted into a statistical chart, as shown in FIG. 9B. It can be seen from FIG. 9B that the line width does not conform to the value of the design database, and the portion circled on the right side of FIG. 9B is a portion showing more than 46, which can correspond to the key size uniformity map in the entire wafer as shown in FIG. 9C. And by the above steps, the line width of the wafer at the center and the edge becomes larger. Similarly, the space distribution and trend of the entire wafer can be obtained in the same way.

Fig. 10 is a schematic view showing still another application of the third embodiment. In the case of FIG. 10, after obtaining the image by using step 502 of FIG. 5, in steps 504-508, the width of the circular contact hole is obtained by image extraction, and according to the data, the CDU or the contact window of the circular contact hole is obtained. Area; or direct contact with the diameter and spacing of the window.

In summary, according to the embodiment of the present invention, the surface structure of the nano generation semiconductor can be obtained not only by the high-resolution image capturing instrument, but also the two-dimensional image such as the circular contact window can be obtained by combining various algorithms. profile. In addition, according to the embodiment of the present invention, the defect area of the entire wafer can be obtained by the preliminary scanning, and the surface structure of the specific area of the wafer or the entire wafer can be analyzed, so that the image can be obtained only by CD-SEM. The way to get the structural analysis of the entire wafer is faster. In addition, the present invention can quickly collect a large number of detection points, so that accurate and immediate results can be obtained. Moreover, the present invention can also be applied to a defect detection process for yellow light exposure compensation, thereby replacing the current complicated and lengthy test analysis establishment mode step.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100~110, 500~512, 600~608‧‧‧ steps
300, 304‧‧‧ circular contact windows
302‧‧‧ Target
400‧‧‧ contour
402‧‧‧Circuit layout design
404‧‧‧ parts
701~704, 800‧‧‧ areas
802‧‧‧ line
804‧‧‧ spacing area

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a timing chart showing the surface structure of a wafer in accordance with a first embodiment of the present invention. 2A and 2B are respectively a statistical chart of line widths in which the background gray levels are the same but the foreground gray levels are different. Figure 3A shows a profile of the distance between the contact window and the hole that is smaller than the standard design file (with a larger contact window). Figure 3B represents a contour view of the distance between the contact window and the hole being greater than the standard design (with smaller contact holes). 4 is a comparison diagram of a circuit layout design and an image profile obtained through the first embodiment. Figure 5 is a step diagram showing the analysis of the surface structure of a wafer in accordance with a second embodiment of the present invention. 6 is a diagram of a method for measuring a critical dimension of a wafer in accordance with a third embodiment of the present invention. Figure 7A is a partial wafer layout of a third embodiment, labeled with different areas 701, 702, 703, and 704. Figure 7B shows a bar graph of test points in different defect areas. Fig. 7C is a distribution diagram of the pitch of the defective area. Fig. 7D is a line width distribution map of the defect area. Fig. 7E is a line width distribution diagram indicating different defect regions. Fig. 8A is another portion of the wafer layout of the third embodiment and the area to be measured. Figure 8B shows a bar graph of test points in the defect area of Figure 8A. Figure 9A is a wafer mapping of the entire wafer for measurement size difference. Figure 9B shows a line width profile of the wafer of Figure 9A. Fig. 9C is a wafer difference size map of an area where the line width is too large in the entire wafer. Figure 10 shows a circular contact window.

100~110‧‧‧Steps

Claims (31)

A method for measuring a surface structure of a wafer or a wafer, comprising: obtaining an image of a surface structure of the wafer by using an instrument; performing image extraction on the image and converting the image into a first circuit design file; selecting a standard image and converting the image into a second circuit design Comparing at least one target in the image with the standard image to obtain a difference between the target and the standard image; and generating a line edge roughness (LER) of the surface structure according to the gap ), line width roughness (LWR), contact window edge roughness (CER), critical dimension (CD), critical dimension deviation (Bias), 3 sigma, maximum (maximum), minimum (minimum) and repeatability At least one of the defects. The method for measuring a surface structure of a wafer or a wafer according to claim 1, further comprising obtaining, by using the data, a difference in critical dimension uniformity (CDU) and deviation value of the entire wafer or wafer. The method of measuring a wafer or wafer surface structure as described in claim 1, further comprising deriving performance and trends of the wafer or wafer by the data of the surface structure. The method for measuring a surface structure of a wafer or a wafer according to claim 1, wherein the apparatus for obtaining the image comprises a key size scanning electron microscope (CD-SEM) and an electron beam detecting tool (E). -Beam inspection tool), scanning electron microscope inspection camera (SEM review tool), bright field inspection equipment with wavelength 150nm~800nm light source or dark field detection with laser light source (laser light source with Dark field inspection equipment. The method of measuring a wafer or wafer surface structure according to claim 1, wherein the first circuit design file and the second circuit design file are graphic data system files. The method of measuring a wafer or wafer surface structure as described in claim 1, wherein the standard image is from a design database, post optical proximity correction (post-OPC), or by a simulated tool. Converted. The method of measuring a wafer or wafer surface structure according to claim 1, wherein the image extraction comprises adjusting a gray scale of a background or a gray scale of a foreground to extract a two-dimensional (2D) image of the image. The outline of the image. The method for measuring a surface structure of a wafer or a wafer according to claim 1, wherein the image extraction further comprises: performing grayscale equalization of the image when a contrast difference of the image is greater than a first preset value. And separating the images when the grayscale difference of the image is greater than a second preset value. The method for measuring a surface structure of a wafer or a wafer according to claim 1, wherein the image extraction further comprises: complementing the image in which the difference is made. A method of measuring a wafer or wafer surface structure as described in claim 1, wherein the surface structure of the wafer comprises a surface structure within a range of a single yellow light shot in the wafer. A method for analyzing a surface structure of a wafer or a wafer, comprising: obtaining a plurality of defect regions in a chip on a wafer; obtaining an image of at least one of the defect regions by using an instrument; and imaging the image Extracting and converting into a first circuit design file; selecting a standard image and converting it into a second circuit design file; comparing the image with the standard image to obtain a difference between the image and the standard image; and according to the gap Producing at least a line edge roughness (LER), line width roughness (LWR), contact window edge roughness (CER), critical dimension (CD), critical dimension deviation (Bias), and repeatability defects of the defect region A type of data. A method of analyzing a wafer or wafer surface structure as described in claim 11, wherein the method of obtaining the defect region comprises performing a wafer mapping of the entire wafer. The method of analyzing a wafer or wafer surface structure according to claim 11, wherein the method of obtaining the defect region comprises marking a region susceptible to defects according to a rule of thumb. The method for analyzing a wafer or wafer surface structure according to claim 11, wherein the method of obtaining the defect region comprises setting an area exceeding or lower than a set value according to design rule data. Defect area. The method of analyzing a wafer or wafer surface structure as described in claim 11 further includes, after obtaining the data of all of the defect regions, deriving performance and trends of the entire wafer. The method for analyzing a wafer or wafer surface structure according to claim 12, wherein the measurement size difference mapping is colored according to a severity difference of a defect measurement size associated with each of the defect regions. coding. The method of analyzing a wafer or wafer surface structure according to claim 11, wherein the apparatus for obtaining the image comprises a key size scanning electron microscope (CD-SEM) and an electron beam detecting tool (E- Beam inspection tool), scanning electron microscope inspection camera (SEM review tool), bright field inspection equipment with wavelength 150nm~800nm light source or dark field detection with laser light source (laser light source with dark) Field inspection equipment. The method of analyzing a wafer or wafer surface structure according to claim 11, wherein the first circuit design file and the second circuit design file are graphic data system files. The method of analyzing a wafer or wafer surface structure as described in claim 11, wherein the standard image is from a design database, post optical proximity correction (post-OPC), or by a simulated tool. Converted. The method of analyzing a wafer or wafer surface structure according to claim 11, wherein the image extraction comprises adjusting a gray scale of a background or a gray scale of a foreground to extract a two-dimensional (2D) image of the image. Outline. The method for analyzing a surface structure of a wafer or a wafer according to claim 11, wherein the image extraction further comprises: performing grayscale homogenization of the image when a contrast difference of the image is greater than a first preset value; And separating the images when the grayscale difference of the image is greater than a second preset value. The method of analyzing a wafer or wafer surface structure according to claim 11, wherein the image extraction further comprises: complementing the image in which the difference is made. The method for analyzing a wafer or wafer surface structure as described in claim 11 further includes obtaining, by the data, a critical dimension uniformity (CDU) and a deviation value difference of the entire wafer. A method for complementing a yellow light exposure, comprising: obtaining an image of a surface structure of the exposed wafer by using an E-Beam inspection tool; performing image extraction on the image and converting the image into a first circuit design file; Select a standard image and convert it to a second circuit design file; and perform a complement calculation. The method of supplementing the yellow light exposure according to claim 24, wherein the resolution of the electron beam detecting tool is between 0.1 nm and 5 nm. The method of claim 1 , wherein the image comprises an image of a defect area of each of the wafers in a wafer or a single yellow light exposure in the wafer. Within the scope of. The method of yellow light exposure compensation according to claim 24, wherein the first circuit design file and the second circuit design file are graphic data system files. A method of yellow light exposure compensation as described in claim 24, wherein the standard image is from post-optical proximity effect correction (post-OPC). The method of refilling a yellow light exposure according to claim 24, wherein the image extraction comprises adjusting a gray scale of a background or a gray scale of a foreground to extract a contour of a two-dimensional (2D) image of the image. . The method of claim 1 , wherein the image extraction further comprises: performing image grayscale equalization when the contrast difference of the image is greater than a first preset value; The grayscale difference of the image is greater than a second preset value to separate the images. The method for supplementing the yellow light exposure according to claim 24, wherein the image extraction further comprises: complementing the image in which the difference is performed.