TW201528457A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A manufacturing method of semiconductor structure is provided, including firstly enabling a first semiconductor substrate that has a plurality of first conductive vias and a second semiconductor substrate that has a plurality of second conductive vias, which are attached to each other, so as to enable the first and the second conductive vias to be electrically connnected to each other, and further setting at least one electronic component on the first semiconductor substrate to be electrically connected to the first conductive vias. By using the second semiconductor substrate as carrier member and package substrate at the same time, the removal of the second semiconductor substrate becomes unnecessary, the extensional setting of package substrate in the subsequent manufacturing becomes unnecessary, and the repeated process of binding/removing carrier member can be omitted, and therefore, the process can be simplified and the production costs can be reduced. This invention further includes the semiconductor structure.

Description

Semiconductor structure and its manufacturing method

The present invention relates to a semiconductor process, and more particularly to a semiconductor structure having a load carrying function and a method of fabricating the same.

Due to the increasing importance of the variety of portable electronic products and their peripheral products such as communication, networking, and computers, and the development of these electronic products in the direction of versatility and high performance, semiconductor manufacturing processes It is constantly evolving toward a higher process evolution, and the high-density structure is the goal pursued by the industry. As a result, semiconductor and package manufacturers are turning to the development of semiconductor packaging to three-dimensional packaging technology to further realize the high-density packaging system required to support these thinner and lighter electronic products.

The three-dimensional packaging technology, the so-called 3D integrated circuit (3D IC), integrates a plurality of layers of wafers or circuit substrates having active components into a single integrated circuit by various means. Specifically, the 3D integrated circuit technology collectively sets a plurality of wafers on a single integrated circuit in a three-dimensional or three-dimensional configuration. Therefore, high-density electrical interconnect technology is required in 3D integrated circuit technology to provide electrical contacts on the active surface and/or back side of the wafer to provide a three-dimensional stack and/or a high-density package.

The technique of an interposer with a through silicon via (TSV) is one of the key technologies currently used to implement a 3D integrated circuit, which is a via hole provided as a vertical electrical connection in a wafer or a substrate. , stack more wafers on a given area to increase stack density. Moreover, the 矽 puncturing design can provide more efficient integration, for example, can integrate different processes or reduce the transfer delay, and at the same time, because of the shorter interconnect length, thereby reducing power consumption, improving performance, and increasing transmission bandwidth. Therefore, the helium perforation technology enables the technology of wafer stack assembly construction to further move toward the trend of low power, high density and miniaturization processes.

As shown in FIGS. 1A to 1F, it is a schematic cross-sectional view of a conventional semiconductor structure 1.

As shown in FIG. 1A, an interposer 10 is provided having opposite crystallizing sides 10a and back sides 13, and a plurality of conductive vias 100 communicating with the crystallizing sides 10a, and having electrical connections on the crystallizing sides 10a. The conductive via 100 has a redistribution layer (RDL) 11 and a glass plate 12 is bonded to the crystallized side 10a by the bonding layer 120.

As shown in FIG. 1B, the back side 13 is ground to thin the interposer 10 and form an intermediate side 10b opposite to the crystallizing side 10a, and the conductive via 100 is connected to the interposing side 10b.

As shown in FIG. 1C, an insulating layer 14 exposing the conductive via 100 is formed on the intermediate side 10b, and an under bump metallurgy (UBM) 15 is formed on the exposed end of the conductive via 100. The under bump metal layer 15 is electrically connected to the conductive via 100.

As shown in FIG. 1D, the composite layer 15 is laminated on the metal layer 15 under the bumps. After the conductive elements 16 of the solder balls are counted, the conductive elements 16 are covered with a glue 17 on the other glass plate 12'.

As shown in FIG. 1E, the glass sheet 12 and the bonding layer 120 are removed, and then a singulation process is performed.

As shown in FIG. 1F, a semiconductor element 18 is flip-chip bonded to the circuit redistribution structure 11 by a plurality of conductive bumps 180, and the other glass plate 12' and the glue 17 are removed to form the semiconductor. Structure 1.

In the subsequent process, the semiconductor structure 1 can connect the intermediate side 10b of the interposer 10 to the package substrate 9 by the conductive elements 16.

However, in the manufacturing method of the conventional semiconductor structure 1, the interposer 10 is used to implement the 3D integrated circuit, and the process on the interposer 10 needs to use the crystallized side 10a and the back side 13 for the double-sided circuit conduction design (such as Since the conductive element 16 and the semiconductor element 18 are manufactured and transported by the thinned interposer 10, the work is performed by a temporary bonding technique, that is, a hard, high temperature resistant material such as the glass is used. The plate 12, 12' or the crucible wafer is used as a carrier, so that the steps of bonding/removing the glass plate 12, 12' are required to be repeated in the process, and the glass plates 12, 12' cannot be reused, resulting in Production costs are difficult to reduce.

Therefore, how to solve the above-mentioned shortcomings of the prior art is a technical problem that various circles are currently trying to solve.

In order to solve the above problems of the prior art, the present invention discloses a semiconductor structure including: a first semiconductor substrate having a first side and a second side opposite thereto, and a plurality of first and second sides connected to each other First conductive The second semiconductor substrate has a plurality of second conductive vias opposite to the third side and the fourth side, and the third side and the fourth side, and the first side of the first semiconductor substrate is bonded to the first side The third conductive substrate is electrically connected to the first conductive via and the second conductive via; and the at least one electronic component is disposed on the second side of the first semiconductor substrate and electrically connected to the first Conductive perforation.

The invention further provides a method for fabricating a semiconductor structure, comprising: providing a first semiconductor substrate and a second semiconductor substrate, wherein the first semiconductor substrate has opposite first and second sides, and is located therein and exposed to the first a plurality of first conductive vias on one side, and the second semiconductor substrate has opposite third and fourth sides, and a plurality of second conductive vias located therein and exposed on the third side; combined with the first semiconductor substrate The first side and the third side of the second semiconductor substrate electrically interconnect the first conductive via and the second conductive via; and the at least one electronic component is disposed on the second side of the first semiconductor substrate, and The electronic component is electrically connected to the first conductive via.

In the above manufacturing method, after the electronic component is disposed, the cutting process is performed.

In the foregoing semiconductor structure and method of fabricating the same, the first side of the first semiconductor substrate has an oxide layer to bond the third side of the second semiconductor substrate. Alternatively, the third side of the second semiconductor substrate has an oxide layer to bond the first side of the first semiconductor substrate. Or the first side of the first semiconductor substrate has a first oxide layer, and the third side of the second semiconductor substrate has a second oxide layer, such that the first oxide layer combines the second oxide a layer to bond the first and second semiconductor substrates.

In the foregoing semiconductor structure and method of fabricating the same, the first side of the first semiconductor substrate has a circuit redistribution layer to bond the third side of the second semiconductor substrate with the second conductive via. For example, the third side of the second semiconductor substrate has an oxide layer to bond the line redistribution layer.

In the foregoing semiconductor structure and method of manufacturing the same, the electronic component is a semiconductor component.

In the foregoing semiconductor structure and method of fabricating the same, the method further comprises forming an encapsulation layer on the second side of the first semiconductor substrate to encapsulate the electronic component, and the encapsulation layer exposes a portion of the surface of the electronic component. For example, prior to forming the encapsulation layer, a primer is formed between the second side of the first semiconductor substrate and the electronic component.

In the foregoing semiconductor structure and method of fabricating the same, the plurality of conductive elements are formed on the fourth side of the second semiconductor substrate, and the conductive elements are electrically connected to the second conductive via.

In the foregoing semiconductor structure and manufacturing method thereof, before the electronic component is disposed, a first line redistribution structure is formed on the second side of the first semiconductor substrate, and the first circuit redistribution structure is electrically connected to the first A conductive via is disposed on the first line redistribution structure and electrically connected to the first line redistribution structure.

In addition, in the foregoing semiconductor structure and the manufacturing method thereof, the second circuit redistribution structure is formed on the fourth side of the second semiconductor substrate, and the second circuit redistribution structure is electrically connected to the second conductive via.

It can be seen from the above that the semiconductor structure of the present invention and its manufacturing method are mainly The second semiconductor substrate serves as the carrier and the package substrate at the same time, so that the second semiconductor substrate does not need to be removed, and there is no need to add a conventional package substrate in the subsequent process, so the method of the present invention does not need to be repeated compared with the prior art. The process of bonding/removing the carrier is performed, thereby simplifying the process and at the same time reducing the manufacturing cost.

Furthermore, the first and second semiconductor substrates can be bonded by using an oxide layer and the first and second conductive vias can be used to form a fusion butt joint to improve the bonding.

1, 2, 2', 2", 3, 3' ‧ ‧ semiconductor structures

10‧‧‧Intermediary board

10a‧‧‧The crystal side

10b‧‧‧Intermediary side

100‧‧‧Electrical perforation

11‧‧‧Line redistribution structure

12, 12'‧‧‧ glass plate

120‧‧‧bonding layer

13‧‧‧ Back side

14‧‧‧Insulation

15‧‧‧ Metal layer under the bump

16, 25‧‧‧ conductive elements

17‧‧‧Stained materials

18‧‧‧Semiconductor components

180, 230‧‧‧ conductive bumps

20‧‧‧First semiconductor substrate

20a‧‧‧ first side

20b‧‧‧ second side

200‧‧‧First conductive perforation

201‧‧‧First oxide layer

202‧‧‧Line redistribution

202a‧‧‧Insulation

202b‧‧‧ lines

203‧‧‧ Passivation layer

22‧‧‧Second semiconductor substrate

22a‧‧‧ third side

22b‧‧‧ fourth side

220‧‧‧Second conductive perforation

221‧‧‧Second oxide layer

21‧‧‧First line redistribution structure

210, 260‧‧‧ dielectric layer

211, 261‧‧‧ circuit layer

212, 262‧‧‧ conductive blind holes

23‧‧‧Electronic components

23a‧‧‧Action surface

23b‧‧‧Non-active surface

24, 24'‧‧‧ encapsulation layer

26‧‧‧Second line redistribution structure

27‧‧‧Bottom glue

9‧‧‧Package substrate

S‧‧‧ cutting path

1A to 1F are schematic cross-sectional views showing a method of fabricating a conventional semiconductor structure; and 2A to 2F are schematic cross-sectional views showing a method of fabricating the first embodiment of the semiconductor structure of the present invention; wherein the 2A' pattern is 2A In another mode, the 2F' and 2F" diagrams are other different aspects of the 2Fth diagram; and the 3rd is a schematic cross-sectional view of the second embodiment of the semiconductor structure of the present invention; wherein the 3' diagram is Another aspect of Figure 3.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The qualifications are not technically meaningful, the modification or proportion of any structure Changes in the relationship or the size of the relationship should be within the scope of the technical contents disclosed in the present invention without affecting the effects and the achievable effects of the present invention. In the meantime, the terms "upper", "first", "second", "one" and "the" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes.

2A to 2F are schematic cross-sectional views showing the process of the first embodiment of the semiconductor structure 2 of the present invention.

As shown in FIG. 2A, a first semiconductor substrate 20 and a second semiconductor substrate 22 are provided. The first semiconductor substrate 20 has a first side 20a and a second side 20b opposite thereto, and is located therein and exposed to the first The plurality of first conductive vias 200 of the side 20a, and the second semiconductor substrate 22 has a third side 22a and a fourth side 22b opposite thereto, and a plurality of second conductive vias 220 located therein and exposed on the third side 22a.

In the embodiment, the first semiconductor substrate 20 is a tantalum interposer, and the second semiconductor substrate 22 is a glass plate.

Furthermore, the first side 20a of the first semiconductor substrate 20 and the first conductive via 200 are surrounded by a first oxide layer 201 such as yttrium oxide (SiO ₂ ), and the third side 22a of the second semiconductor substrate 22 A second oxide layer 221 such as one of yttrium oxide (SiO ₂ ) is disposed around the second conductive via 220. Specifically, the thickness of the first oxide layer 201 and the thickness of the second oxide layer 221 are about 1.0 um.

Further, as shown in FIG. 2A', the first side of the first semiconductor substrate 20 20a (or on the first oxide layer 201) may also have a line redistribution layer 202. Specifically, the circuit redistribution layer 202 has an insulating portion 202a on the first side 20a (or the first oxide layer 201) and a line 202b on the first conductive via 200. The insulating portion 202a The oxidized material is electrically connected to the line 202b.

In addition, the conductive via process first etches the semiconductor substrate to form a via, and then forms an oxide layer in the via, and then forms a conductive material (such as copper) in the via to form the conductive via.

As shown in FIG. 2B, in connection with the process of FIG. 2A, the first conductive via 200 and the second conductive via 200 are combined with the first side 20a of the first semiconductor substrate 20 and the third side 22a of the second semiconductor substrate 22. The conductive vias 220 are electrically connected to each other.

In the embodiment, the first semiconductor substrate 20 is bonded to the second oxide layer 221 of the second semiconductor substrate 22 by the first oxide layer 201. Specifically, the bonding process conditions of the first oxide layer 201 and the second oxide layer 221 are a temperature of 800 to 1000 ° C, a bonding pressure of 5 to 10 KN at 1 to 2 MPa, and a vacuum pressure of less than 4 to 10 Torr.

Moreover, the end surface of the first conductive via 200 is in direct contact with the end surface of the second conductive via 220.

As shown in FIG. 2C, a first line redistribution structure (RDL) 21 is formed on the second side 20b of the first semiconductor substrate 20, and the first circuit redistribution structure 21 is electrically connected to the first conductive via 200. .

In this embodiment, the first circuit redistribution structure 21 has at least one dielectric layer 210, a circuit layer 211 combined with the dielectric layer 210, and the dielectric layer. The conductive vias 212 of the layer 210 are electrically connected to the first conductive vias 200 by the conductive vias 212.

Furthermore, before the first line redistribution structure 21 is formed, the second side 20b of the first semiconductor substrate 20 is thinned by polishing, and then thinned by a reactive ion etching (RIE) method. The second side 20b of the first semiconductor substrate 20 causes the first conductive via 200 to protrude from the second side 20b, and then a passivation layer 203 such as hafnium oxide or tantalum nitride (SiN _X ) is formed on the first semiconductor On the second side 20b of the substrate 20, the end surface of the first conductive via 200 is flush with the surface of the passivation layer 203, and the end surface of the first conductive via 200 is exposed, and then the first line redistribution structure 21 is formed. The passivation layer 203 is on.

Moreover, in other embodiments, the passivation layer 203 may not be formed on the second side 20b of the first semiconductor substrate 20, so that the end surface of the first conductive via 200 is flush with the surface of the second side 20b.

As shown in FIG. 2D, a plurality of electronic components 23 are disposed on the first circuit redistribution structure 21, and the electronic components 23 are electrically connected to the circuit layer 211 of the first circuit redistribution structure 21. Next, an encapsulation layer 24 is formed between the first circuit redistribution structure 21 and the electronic component 23 and covers the electronic components 23.

In this embodiment, the electronic component 23 is a semiconductor component. Therefore, the electronic component 23 has an opposite active surface 23a and an inactive surface 23b, and the active surface 23a is electrically flipped by the plurality of conductive bumps 230. The circuit layer 211 of the first line redistribution structure 21 is connected.

Furthermore, the encapsulation layer 24 is formed by a molding process, a dry film or other insulating material. For example, if the encapsulation layer 24 is an encapsulant, it first forms a colloid having a thickness of 300 to 500 um, and then removes a colloid of up to 300 um thick so that the encapsulation layer 24 has a thickness of 100 to 200 um.

In addition, a primer 27 may be formed between the first circuit redistribution structure 21 and the active surface 23a of the electronic component 23 to cover the conductive bumps 230, and then the package layer 24' is formed to cover the primer. The electronic components 23 and the primer 27 are as shown in FIG. 2F.

In addition, the encapsulating layer 24 does not expose the inactive surface 23b of the electronic component 23. In other embodiments, as shown in the 2Fth diagram, the encapsulating layer 24' exposes the inactive surface 23b of the electronic component 23.

As shown in FIG. 2E, the fourth side 22b of the second semiconductor substrate 22 is thinned, and the end surface of the second conductive via 220 is flush with the surface of the fourth side 22b, and the second conductive via 220 is exposed. On the surface of the fourth side 22b.

In the present embodiment, the fourth side 22b of the second semiconductor substrate 22 is thinned by polishing.

As shown in FIG. 2F, a dicing process is performed along the dicing path S shown in FIG. 2E to obtain a plurality of semiconductor structures 2, and a plurality of conductive elements such as solder balls are formed on the fourth side 22b of the second semiconductor substrate 22. The second conductive vias 220 are electrically connected to the second conductive vias 220.

In this embodiment, the second semiconductor substrate 22 can serve as both a carrier and a package substrate, so that the second semiconductor substrate 22 does not need to be removed.

In another embodiment, a plurality of conductive elements 25 such as solder balls may be first bonded to the second conductive vias 220 to perform a dicing process.

The method of the present invention uses the second semiconductor substrate 22 as a carrier and also serves as a package substrate, so that there is no need to remove the second semiconductor substrate 22, and there is no need to add a conventional package substrate, so compared with the prior art, the present invention The manufacturing method of the invention does not need to repeatedly carry out the process of bonding/removing the carrier, thereby greatly reducing the process steps and material costs.

Further, the first oxide layer 201 is bonded to the second oxide layer 221, and the end faces of the first conductive vias 200 and the end faces of the second conductive vias 220 are butted to each other to make the first and second semiconductor substrates 20, 22 forming a Fusion Bonding to improve the bonding of the first and second semiconductor substrates 20, 22.

Further, if the process of FIG. 2A is continued, the semiconductor structure 2' shown in FIG. 2F' is obtained, that is, the second semiconductor substrate 20 is bonded to the second semiconductor substrate 22 by the insulating portion 202a. The layer 221 is connected to the end surface of the second conductive via 220, so that the first and second semiconductor substrates 20, 22 are fused to each other to enhance the combination of the first and second semiconductor substrates 20, 22. Sex.

In addition, in other embodiments, as shown in FIG. 2F, a second line redistribution structure 26 may be formed on the fourth side 22b of the second semiconductor substrate 22, and the second line redistribution structure 26 is electrically The second conductive via 220 is connected to the second conductive via.

Specifically, the second circuit redistribution structure 26 has at least one dielectric layer 260 , a circuit layer 261 coupled to the dielectric layer 260 , and the dielectric layer 260 . The conductive via 262 is electrically connected to the conductive via 262 and the circuit layer 261 of the second circuit redistribution structure 26 .

The third and third views are schematic cross-sectional views of different aspects of the second embodiment of the semiconductor structure 3, 3' of the present invention. The difference between this embodiment and the first embodiment is that the first line redistribution structure 21 is not formed, and other processes are substantially the same.

As shown in FIG. 3, the electronic component 23 is disposed on the second side 20b of the first semiconductor substrate 20, and the conductive bumps 230 are directly bonded to the end faces of the first conductive vias 200 to make the electronic components. 23 electrically connecting the first conductive via 200.

As shown in FIG. 3', the second line redistribution structure 26 may be formed on the fourth side 22b of the second semiconductor substrate 22 in the step of FIG. 2C, and the second line redistribution structure 26 may be formed. The second conductive via 220 is electrically connected. Then, the electronic component 23 is disposed on the second side 20b of the first semiconductor substrate 20, and the conductive bumps 230 are directly bonded to the end faces of the first conductive vias 200 to electrically connect the electronic components 23. The first conductive via 200.

The present invention further provides a semiconductor structure 2, 2', 2", 3, 3' comprising: a first semiconductor substrate 20 and a second semiconductor substrate 22 stacked on each other, and at least a first semiconductor substrate 20 disposed on the first semiconductor substrate 20 An electronic component 23.

The first semiconductor substrate 20 has a first side 20a and a second side 20b opposite to each other, and a plurality of first conductive vias 200 communicating with the first side 20a and the second side 20b.

The second semiconductor substrate 22 has a third side 22a and a fourth side 22b opposite thereto, and a plurality of second sides 22a and a fourth side 22b. The first side 20a of the first semiconductor substrate 20 is bonded to the third side 22a of the second semiconductor substrate 22, so that the first conductive via 200 and the second conductive via 220 are electrically connected to each other.

In one embodiment, the first side 20a of the first semiconductor substrate 20 has a first oxide layer 201 to bond the third side 22a of the second semiconductor substrate 22.

In one embodiment, the third side 22a of the second semiconductor substrate 22 has a second oxide layer 221 to bond the first side 20a of the first semiconductor substrate 20.

In one embodiment, the first side 20a of the first semiconductor substrate 20 has a first oxide layer 201, and the third side 22a of the second semiconductor substrate 22 has a second oxide layer 221 for the first oxidation. The layer 201 is bonded to the second oxide layer 221 to bond the first and second semiconductor substrates 20, 22.

In one embodiment, the first side 20a of the first semiconductor substrate 20 has a line redistribution layer 202 for bonding the third side 22a of the second semiconductor substrate 22 and the second conductive via 220. Preferably, the third side 22a of the second semiconductor substrate 22 has a second oxide layer 221 to bond the circuit redistribution layer 202.

The electronic component 23 is a semiconductor component and is disposed on the second side 20b of the first semiconductor substrate 20 and electrically connected to the first conductive via 200.

In one embodiment, the semiconductor structure 2, 2', 2", 3, 3' includes an encapsulation layer 24, 24' disposed on the second side 20b of the first semiconductor substrate 20 to package Overlying the electronic component 23 and exposing or not exposing the electronic component The top surface of 23 (i.e., the non-active surface 23b). In one aspect, the semiconductor structure 2 ′′ includes a primer 27 disposed between the second side 20 b of the first semiconductor substrate 20 and the electronic component 23 to package the package layer 24 ′. The primer 27 is covered.

In one embodiment, the semiconductor structure 2, 2', 2", 3, 3' includes a plurality of conductive elements 25 disposed on the fourth side 22b of the second semiconductor substrate 22 and electrically connected thereto. The second conductive via 220.

In one embodiment, the semiconductor structure 2, 2', 2" includes a first line redistribution structure 21, which is disposed on the second side 20b of the first semiconductor substrate 20 and electrically connected to the first conductive The electronic component 23 is disposed on the first circuit redistribution structure 21 and electrically connected to the first circuit redistribution structure 21 .

In one embodiment, the semiconductor structure 2", 3' includes a second line redistribution structure 26, which is disposed on the fourth side 22b of the second semiconductor substrate 22 and electrically connected to the second conductive via. 220.

In summary, the semiconductor structure of the present invention and the method for manufacturing the same are used as the carrier and the package substrate by the second semiconductor substrate, so that there is no need to remove the second semiconductor substrate, and there is no need to add a conventional package substrate, so The process of bonding/removing the carrier is repeated, thereby greatly reducing the process steps and material costs.

Furthermore, the first and second semiconductor substrates use an oxide layer as a bonding component and the conductive vias are butted to form a fusion butt joint to enhance the bonding between the two.

The above embodiments are merely illustrative of the effects of the present invention, rather than Modifications and variations of the embodiments described above can be made by those skilled in the art without departing from the spirit and scope of the invention. In addition, the number of elements in the above-described embodiments is merely illustrative and is not intended to limit the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

3‧‧‧Semiconductor structure

20‧‧‧First semiconductor substrate

20a‧‧‧ first side

20b‧‧‧ second side

200‧‧‧First conductive perforation

201‧‧‧First oxide layer

203‧‧‧ Passivation layer

22‧‧‧Second semiconductor substrate

22a‧‧‧ third side

22b‧‧‧ fourth side

220‧‧‧Second conductive perforation

221‧‧‧Second oxide layer

23‧‧‧Electronic components

24‧‧‧Encapsulation layer

25‧‧‧Conductive components

Claims (27)

A semiconductor structure comprising: a first semiconductor substrate having a first side and a second side opposite to each other; and a plurality of first conductive vias communicating with the first side and the second side; the second semiconductor substrate having a relative a third side and a fourth side, and a plurality of second conductive vias connecting the third side and the fourth side, and the first side of the first semiconductor substrate is bonded to the third side of the second semiconductor substrate, so that the first side A conductive via is electrically connected to the second conductive via; and at least one electronic component is disposed on the second side of the first semiconductor substrate and electrically connected to the first conductive via. The semiconductor structure of claim 1, wherein the first side of the first semiconductor substrate has an oxide layer to bond the third side of the second semiconductor substrate. The semiconductor structure of claim 1, wherein the third side of the second semiconductor substrate has an oxide layer to bond the first side of the first semiconductor substrate. The semiconductor structure of claim 1, wherein the first side of the first semiconductor substrate has a first oxide layer, and the third side of the second semiconductor substrate has a second oxide layer. The first oxide layer is bonded to the second oxide layer to bond the first and second semiconductor substrates. The semiconductor structure of claim 1, wherein the first side of the first semiconductor substrate has a line redistribution layer for bonding The third side of the second semiconductor substrate and the second conductive via. The semiconductor structure of claim 5, wherein the third side of the second semiconductor substrate has an oxide layer to bond the line redistribution layer. The semiconductor structure of claim 1, wherein the electronic component is a semiconductor component. The semiconductor structure of claim 1, further comprising an encapsulation layer disposed on the second side of the first semiconductor substrate to encapsulate the electronic component. The semiconductor structure of claim 8 further comprising a primer disposed between the second side of the first semiconductor substrate and the electronic component. The semiconductor structure of claim 8, wherein the encapsulation layer exposes a portion of the surface of the electronic component. The semiconductor structure of claim 1, further comprising a plurality of conductive elements disposed on the fourth side of the second semiconductor substrate and electrically connected to the second conductive via. The semiconductor structure of claim 1, further comprising a first line redistribution structure disposed on the second side of the first semiconductor substrate and electrically connected to the first conductive via, such that the electronic component is disposed on The first line is re-wired and electrically connected to the first line redistribution structure. The semiconductor structure of claim 1, further comprising a second line redistribution structure disposed on the fourth side of the second semiconductor substrate and electrically connected to the second conductive via. A method of fabricating a semiconductor structure, comprising: providing a first semiconductor substrate and a second semiconductor substrate, the first semiconductor substrate having a first side and a second side opposite thereto, and a plurality of opposite sides and exposed on the first side a first conductive via, and the second semiconductor substrate has opposite third and fourth sides, and a plurality of second conductive vias located therein and exposed on the third side; bonding the first side of the first semiconductor substrate with a third side of the second semiconductor substrate, the first conductive via is electrically connected to the second conductive via; and at least one electronic component is disposed on the second side of the first semiconductor substrate, and the electronic component is electrically The first conductive via is connected sexually. The method of fabricating a semiconductor structure according to claim 14, wherein the first side of the first semiconductor substrate has an oxide layer to bond the third side of the second semiconductor substrate. The method of fabricating a semiconductor structure according to claim 14, wherein the third side of the second semiconductor substrate has an oxide layer to bond the first side of the first semiconductor substrate. The method of manufacturing the semiconductor structure of claim 14, wherein the first side of the first semiconductor substrate has a first oxide layer, and the third side of the second semiconductor substrate has a second oxide layer. The first oxide layer is bonded to the second oxide layer to bond the first and second semiconductor substrates. The method of fabricating a semiconductor structure according to claim 14, wherein the first side of the first semiconductor substrate has a line redistribution layer. The third side of the second semiconductor substrate is bonded to the second conductive via. The method of fabricating a semiconductor structure according to claim 18, wherein the third side of the second semiconductor substrate has an oxide layer to bond the line redistribution layer. The method of fabricating a semiconductor structure according to claim 14, wherein the electronic component is a semiconductor component. The method of fabricating the semiconductor structure of claim 14, further comprising forming an encapsulation layer on the second side of the first semiconductor substrate to encapsulate the electronic component. The method of fabricating a semiconductor structure according to claim 21, further comprising forming a primer between the second side of the first semiconductor substrate and the electronic component before forming the encapsulation layer. The method of fabricating a semiconductor structure according to claim 21, wherein the encapsulation layer exposes a portion of the surface of the electronic component. The method for fabricating a semiconductor structure according to claim 14, wherein the method further comprises: after the electronic component is disposed, performing a cutting process. The method of fabricating the semiconductor structure of claim 14, further comprising forming a plurality of conductive elements on the fourth side of the second semiconductor substrate, and the conductive elements are electrically connected to the second conductive via. The method of fabricating the semiconductor structure of claim 14, further comprising forming a first line redistribution structure on the second side of the first semiconductor substrate before the electronic component is disposed, and the first line is redistributed The structure electrically connects the first conductive via, so that the electronic component is disposed on the The first line is re-wired and electrically connected to the first line redistribution structure. The method of fabricating the semiconductor structure of claim 14, further comprising forming a second line redistribution structure on the fourth side of the second semiconductor substrate, and the second circuit redistribution structure is electrically connected to the second Conductive perforation.