TW201515171A - Chip packaging structure and process - Google Patents

Abstract

The present invention discloses a chip packaging structure and process. The structure includes a chip and a nanometer deposition layer. The chip has electrical wiring, a photosensitive area and a plurality of electrical connection pads in which the photosensitive area and the electrical connection pads are disposed on the upper surface of the chip while the nanometer deposition layer covers the surface of the photosensitive area and exposes the electrical connection pads. The photosensitive area has a photosensitive function; and the electrical connection pads are connected with the electrical wiring to allow the connection to an external circuit or an electrical component. The nanometer deposition layer has the characteristic of electrical insulation and transparency, and provides the effects of electrical insulation and isolation protection. The process includes washing chips; forming a nanometer deposition layer; and cutting a wafer to separate the chips. The present invention straightly adopts nanometer deposition layer encapsulation instead of mold injection, and thereby simplifies processing steps, lowers processing cost, makes production easier, and further miniaturizes packaging scale.

Description

Chip package structure and process

The invention relates to a chip package structure and a process, in particular to a chip package method which has one or more layers of atomic deposition layers instead of being injection molded, thereby achieving a lighter, thinner, shorter process, a lower processing cost, a lower processing cost, and a convenient production. To improve yield, and to enhance functions such as EMI prevention, heat dissipation, re-layout (RDL), anti-reflection, anti-ultraviolet (UV), and IR cut as needed.

With the advancement of semiconductor technology, the integrated circuit (IC) has become more powerful, not only the higher the circuit density, but also the greater the power consumption, which makes it possible to enhance the heat dissipation efficiency and improve the electromagnetic interference (EMI). The ability to improve electrical conductivity has become more important, which has led to the evolution of packaging technology to place, secure, and seal semiconductor chips for use in printed circuit boards (PCBs) or other circuits. The substrate and the carrier further provide protection, enhance heat conduction, prevent the wafer from overheating, and affect electrical performance or failure to meet the above practical requirements.

In conventional technology, packaging technology can include dual In-line Package (DIP), Quad Flat Package (QFP), Thin Small Outline Package (TSOP), ball Ball Grid Array (BGA), etc., mainly uses a package made of plastic material to cover the wafer by Mold Filling, providing electrical insulation protection and heat dissipation, and electrically connecting to the wafer by using the pins. The connection is made to achieve electrical signal conduction. Crystal with a small number of pins The chip can be used in a DIP package, in which the pins are arranged on two sides, and the number of pins is usually up to several tens, and the QFP package is configured with four pins on the four sides, so the number of pins is more than 256. However, for a chip with hundreds of pins or more, a BGA package must be used because the solder balls are used as pins and are arranged in an array on the bottom surface of the carrier.

However, for applications that are lighter, thinner, shorter, smaller, and more complex, and powerful for mobile phones, mobile or handheld electronic devices, the BGA package has a large carrier area and requires a certain solder ball. The size of the package makes it impossible to further shrink the overall package size, driving the industry to develop a chip scale package (CSP) with a smaller package size, usually only 20% larger than the original chip.

However, the disadvantage of the above conventional technology is that whether it is a DIP package, a QFP package, a BGA package, or a CSP package, the wafer is first placed in a mold, and then the package material is injected to surround the wafer, and is heated and cured to form a package, so that finally The longitudinal height (thickness) and lateral size (area) of the product can no longer be reduced due to the limitations of mold forming, such as the fluidity of the packaging material and the mechanical strength of the package.

In addition, for wafers with light transmissive functions, such as optical image wafers, an additional process is required, one piece of glass element is added at a time, and during the process of loading, the wafer is easily contaminated or the overall structure is offset. Etc.

Therefore, there is a need for a chip package structure and process that does not require injection molding to form a package, but directly utilizes one or more layers of functional atomic deposition layers instead of injection molding to cover the chip package, thereby making the package lighter, thinner and shorter. And simplify the processing process, reduce the processing cost, facilitate the production, improve the yield, and especially strengthen the functions of preventing EMI, heat dissipation, re-layout, anti-reflection, anti-ultraviolet light, infrared light cutoff, etc. as needed, so as to effectively solve the above-mentioned conventional use. Technical issues.

The main object of the present invention is to provide a chip package structure including a wafer and a nano-deposited layer, wherein the wafer has an electrical circuit, a photosensitive region, and a plurality of electrical connection pads, and the photosensitive region and the electrical connection pad are disposed on the upper surface of the wafer. The nano-deposited layer covers the surface of the photosensitive region and exposes the electrical connection pads.

The photosensitive area has a photosensitive function, and the electrical connection pads are connected to electrical lines and provide connection to external circuits or electrical components such as circuit boards or other integrated circuit chips. In particular, the photosensitive region can be disposed in a central region of the wafer, and the electrical connection pads can be located around the outer edge of the wafer, surrounding the outer edge of the photosensitive region.

The nano-deposited layer is electrically insulating and light-transmitting and can be composed of oxide, silicone, phenolic resin, polycarbonate, acrylic resin, polyamido resin, polytetrafluoroethylene, BT resin or epoxy resin.

Another object of the present invention is to provide a wafer package structure including a wafer, a nano-deposited layer, a wiring layer, and a plurality of connection bumps, wherein a portion of the lower surface of the wiring layer covers the outer edge of the nano-deposited layer, and the rest of the wiring layer The lower surface contacts the wafer and is electrically connected to the electrical connection pads. The connection bumps are disposed on the upper surface of the circuit layer and can be connected to external circuits or electrical components. Therefore, the main purpose of the connection bumps is to provide a large connection area, extend the connection function of the electrical connection pads, and facilitate connection of external circuits or electrical components.

Another object of the present invention is to provide a chip package structure including a wafer, a nano-deposited layer, a wiring layer, a plurality of connection bumps, and at least one electronic component, and the wafer is an integrated circuit (IC) semiconductor wafer having electrical wiring And a plurality of electrical connection pads, and the nano deposited layer can be light transmissive or opaque. The nanodeposited layer covers a portion of the surface of the wafer and does not cover the electrical connection pads. The circuit layer has a circuit pattern and covers the nano-deposited layer and the wafer to contact the electrical connection pads, and the connection bumps are disposed on the circuit layer.

Therefore, the electrical connection pads are electrically connected to the connection bumps, and electronic components such as surface mount components (SMD) are disposed on the circuit pattern of the circuit layer, including passive RC components. Therefore, the nano-deposited layer can be directly used as a carrier electron element. The substrate of the piece simplifies the overall structure.

Another object of the present invention is to provide a wafer packaging process comprising: cleaning a plurality of wafers on a wafer, each wafer having a photosensitive region and a plurality of electrical connection pads; forming a nano-deposited layer on the wafer, covering the electrical insulation Bonding a surface area other than the pad and covering the photosensitive area; and dicing the wafer to separate the wafer to form a chip scale package (CSP) package having a wafer and a nano deposited layer.

Another object of the present invention is to provide a wafer packaging process comprising: cleaning a plurality of wafers on a wafer, each wafer having a photosensitive region and a plurality of electrical connection pads; forming a nano-deposited layer on the wafer to cover the sensitization of the wafer Forming a circuit layer covering the outer edge of the wafer; forming a connection bump disposed on the circuit layer; and dicing the wafer to separate the wafer to form a wafer, a nano-deposited layer, a wiring layer, and a plurality of connecting bumps Wafer level package.

Another object of the present invention is to provide a wafer packaging process comprising: cleaning a plurality of wafers on a wafer, each wafer having a photosensitive region and a plurality of electrical connection pads; forming a nano-deposited layer on the wafer to cover the sensitization of the wafer a circuit layer and a connection bump, and the circuit layer covers the outer edge of the wafer, and the connection bump is disposed on the circuit layer; the electronic component is attached to the circuit layer to connect the bump; and the wafer is etched to separate The wafer is formed into a wafer level package having a wafer, a nano deposited layer, a wiring layer, a plurality of connecting bumps, and electronic components.

The invention replaces the traditional injection molding method with a nano-deposited layer coating method, which can greatly reduce the package size and realize a true wafer-level package. In addition, masks and different nano-deposit materials can be used to achieve light transmission, waterproof and EMI prevention in multiple deposition methods.

10‧‧‧ wafer

11‧‧‧Photosensitive area

14‧‧‧Electrical connection pads

20‧‧‧ nano-sediment

30‧‧‧ boards

31‧‧‧Connected solder joints

40‧‧‧Line layer

42‧‧‧Connecting bumps

50‧‧‧Electronic components

60‧‧‧ mirror base

61‧‧‧ Cover

63‧‧‧ lenses

L‧‧‧Light

S10~S30‧‧‧Steps

The first figure shows a schematic diagram of a chip package structure in accordance with a first example of the present invention.

The second figure is a top view of the first wafer package structure.

The third figure shows a schematic diagram of an application example of the chip package structure of the present invention.

The fourth figure shows a schematic diagram of a chip package structure in accordance with a second embodiment of the present invention.

Figure 5 is a schematic view showing a chip package structure according to a third example of the present invention.

Figure 6 is a flow chart showing the operation of the wafer packaging process of the present invention.

Figure 7 is a flow chart showing the operation of another chip packaging process of the present invention.

Figure 8 is a flow chart showing the operation of still another wafer packaging process of the present invention.

The embodiments of the present invention will be described in more detail below with reference to the drawings and the reference numerals, which can be implemented by those skilled in the art after having studied this specification.

Referring to the first figure, a schematic diagram of a wafer package structure of the present invention. As shown in the first figure, the chip package structure of the present invention mainly comprises a wafer 10 and a nano-deposited layer 20, wherein the wafer 10 is, for example, an optical sensing wafer, having an electrical line (not shown), a photosensitive region 11 and a plurality of The electrical connection pad 14 is disposed, and the photosensitive region 11 and the plurality of electrical connection pads 14 are disposed on the upper surface of the wafer 10, and the nano-deposited layer 20 covers the surface of the photosensitive region 11 in a semiconductor process, that is, the nano-deposited layer 20 The lateral dimension is greater than or equal to the lateral dimension of the photosensitive zone 11 for coverage purposes.

The photosensitive region 11 has a photosensitive function, and further a plurality of microlenses (not shown) may be further disposed on the surface thereof to enhance the photosensitive efficiency, and the electrical connection pads 14 are connected to the electrical circuit and provide connection to an external circuit or an electrical component such as a circuit. Board or other integrated circuit chip. Specifically, as shown in the second figure, that is, a top view of the first chip package structure, the photosensitive region 11 can be disposed in a central region of the wafer 10, and the electrical connection pads 14 are located around the outer periphery of the wafer 10, that is, around The outer edge of the photosensitive region 11.

The nano-deposited layer 20 is electrically insulating and translucent, and can be composed of a light-transmissive hydrophobic plastic material, such as a thermoplastic or thermoplastic, and may include an oxide (Oxide), a silicone, or a phenolic resin (Phenolic). , polycarbonate, acrylic resin, polyimide, polytetrafluorethylene, BT resin (Bismaleimide Triazine) or epoxy resin (Epoxy). Since the nano-deposited layer 20 is hydrophobic, it prevents a large amount of water droplets from sticking and can be used simply. A single blowing method removes water droplets. At the same time, the nano-deposited layer 20 has a function of protecting the photosensitive region 11, and it is possible to prevent particles or dust from contaminating the photosensitive region 11. In particular, when the photosensitive region 11 has a microlens, since the microlens does not have a scratch-proof function, and the depressed region between the microlenses easily collects contaminating particles or dust, and is not easily removed, the nano-deposited layer 20 can be solved. This type of problem.

In order to clearly illustrate the features of the present invention, please refer to the third figure to show an application example of the chip package structure of the present invention. In the third figure, a circuit board 30, such as a printed circuit board, may be disposed on the upper surface of the wafer 10 that is not covered by the nanodeposited layer 20 to contact the electrical connection pads 14 and expose the photosensitive region 11 of the wafer 10, or The electrical connection pads 14 can be connected to the bottom surface of the circuit board 30 via bond wires. The front side of the circuit board 30 has a plurality of connection pads 31, preferably disposed on the outer edge of the circuit board 30.

In addition, the lens holder 60 is disposed on the circuit board 30, and a cavity is formed between the wafer 10 and the lens holder 60. The lens holder 60 includes a cover body 61 and at least one lens 63, and the cover body 61 and the lens 63 are integrated into one body. . The lens 63 is aligned with the photosensitive region 11 of the wafer 10, and the cover 61 is fixed to the circuit board 30 by a fixing glue. Therefore, the external light L can penetrate the lens 63 to reach the nano-deposited layer 20 and further penetrate the nano-deposited layer 20 to reach the photosensitive region 11.

In addition to providing a barrier protection, the nano-deposited layer 20 can also have low reflectivity as an anti-reflective layer, reducing or eliminating reflections so that light projected onto the nano-deposited layer 20 can reach the underlying photosensitive region as much as possible. 11, in order to improve the overall efficiency. Preferably, the nano-deposited layer 20 as an anti-reflection layer may have a thickness of 120 to 260 nm. Therefore, it is not necessary to additionally use an anti-reflection film or an anti-reflection sheet of a conventional technique, and the lens 63 does not need to be plated with a general anti-reflection film, which simplifies the manufacturing process, reduces the manufacturing cost, and improves the reliability of the product.

However, it should be noted that the application examples of the third embodiment are merely for convenience of explaining the features of the present invention, and are not intended to limit the scope of the present invention, that is, the chip package structure of the present invention can be applied to other fields.

In addition, referring to the fourth figure, a schematic diagram of a chip package structure according to a second example of the present invention, wherein the wafer package structure of the present example includes a wafer 10, a nano-deposited layer 20, a wiring layer 40, and a plurality of connection bumps 42, and the wafer 10 And the technical features of the nano-deposited layer 20 are similar to the embodiment of the first figure, that is, the wafer 10 has electrical lines (not shown), a photosensitive region 11 and a plurality of electrical connection pads 14, and the nano-deposited layer 20 The surface of the photosensitive region 11 is covered, and therefore will not be described again.

The wiring layer 40 of the second example wafer package structure is a metal conductive layer having a circuit pattern (not shown), and a portion of the lower surface of the wiring layer 40 covers the outer edge of the nano-deposited layer 20, while the remaining portion of the wiring layer 40 The surface contacts the wafer 10 and is electrically connected to the electrical connection pads 14. The connection bumps 42 are disposed on the upper surface of the circuit layer 40 for connecting external circuits or electrical components. Therefore, the connection bumps 42 mainly extend the connection function of the electrical connection pads 14, that is, external circuits or electrical components. The gas connection pad 14 is not directly connected, and is electrically connected to the gas connection pad 14 via the connection bump 42.

Due to the limited size of the outer edge region of the wafer 10, the maximum size of the electrical connection pads 14 is about 80 x 80 um. For soldering certain electrical components, the contact area is insufficient to affect the electrical function, and the connection bumps 42 are on the wiring layer 40. Formed, so the size of the connecting bumps 42 can reach 120x120um, or even 150x150um, which can greatly improve the yield of the subsequent welding process. Similarly, the chip package structure of the second embodiment can be further applied to the connection lens holder as in the first embodiment to form an optical sensing module, thereby improving the overall structure and improving the photosensitive efficiency.

Please refer to the fifth figure for a schematic view of the chip package structure of the third example of the present invention. As shown in the fifth figure, the chip package structure of the third example includes a wafer 10, a nano-deposited layer 20, a wiring layer 40, a plurality of connection bumps 42 and at least one electronic component 50, wherein the wafer 10 is an integrated circuit (IC). A semiconductor wafer, and the nano-deposited layer 20 may have light transmissivity or opacity. in particular. The wafer 10 has electrical wiring (not shown) and a plurality of electrical connection pads 14. The nanodeposited layer 20 covers a portion of the surface of the wafer 10 and exposes the electrical connection pads 14. The wiring layer 40 has a circuit pattern and covers the nanodeposited layer 20 and the wafer 10 to contact the electrical connection pads 14. The connection bumps 42 are disposed on the wiring layer 40, so that the electrical connection pads 14 and the connection bumps 42 form an electrical connection. In addition, the electronic component 50 is disposed on a circuit pattern of the wiring layer 40, such as a surface mount component (SMD), including a passive RC component.

Therefore, the main purpose of the nano-deposited layer 20 is to provide isolation protection and electrical insulation of the wafer 10 to prevent the wafer 10 from being contaminated by particles or dust, and other technical features of the nano-deposited layer 20 are similar to the embodiment of the first figure described above. No longer. Since the electronic component 50 of the application field is directly soldered to the wiring layer 40 on the nano-deposited layer 20, the overall structure of the application device can be greatly simplified and the size can be reduced.

In addition, the present invention further provides a wafer packaging process, as shown in the sixth figure, wherein the operation flow of the chip packaging process of the present invention starts from step S10, mainly cleaning a plurality of wafers on the wafer, and each wafer has electrical The circuit, the photosensitive region and the plurality of electrical connection pads, wherein the photosensitive region and the electrical connection pad are disposed on the upper surface of the wafer.

Next, in step S20, a nano-deposited layer is formed on the surface of each wafer to cover the area of the wafer other than the electrical connection pads, and also covers the photosensitive area and exposes the electrical connection pads. The composition of the nano-deposited layer may include an oxide, a phenolic resin, an epoxy resin, a polyamidene resin, a polytetrafluoroethylene or a BT resin, and may be subjected to chemical vapor deposition (CVD), or spin coating and curing. The treatment is deposited on the wafer, especially at a lower temperature, such as 50 to 70 ° C, to avoid affecting the photoelectric characteristics of the photosensitive region 11, and to provide electrical insulation.

Finally, proceeding to step S30, the wafer is diced to separate each wafer.

In addition, referring to the seventh figure, the operation flow of another chip packaging process of the present invention. As shown in the seventh figure, the chip packaging process of the present invention includes steps performed in sequence. Steps S10, S20, S22, S24, and S30, wherein steps S10, S20, and S30 are like the chip packaging process of the sixth figure, and are not described herein again. The difference from the sixth figure process is that the wafer packaging process of the seventh figure additionally includes steps S22 and S24. Specifically, the step S22 is performed after the step S20, mainly to form a circuit layer on the nano-deposited layer and the wafer to cover the outer edge of the nano-deposited layer and contact the electrical connection pad to complete the arrangement of the line. Next, in step S24, a plurality of connection bumps are formed on the circuit layer for connecting external circuits or electrical components.

In addition, referring to the eighth figure, the operational flowchart of the chip packaging process of the present invention includes steps S10, S20, S26, S28, and S30, which are sequentially performed, wherein steps S10, S20, and S30 are the same as the chip packaging process of the sixth figure. However, the wafer of the present embodiment does not include a photosensitive wafer, that is, does not have a photosensitive region, and the rest of the techniques are similar, and thus will not be described again.

The difference from the sixth figure process is that the chip packaging process of the eighth figure additionally includes steps S26 and S28. Specifically, a wiring layer and a plurality of connection bumps are formed in step S26, and the wiring layer covers the outer edge of the nano-deposited layer and contacts the electrical connection pads, and the connection bumps are formed on the wiring layer. Next, in step S28, surface mount components (SMD) electronic components, such as passive RC components, are planarly soldered to the connection bumps using Surface Mount Technology (SMT) to form the desired circuitry.

In summary, the main feature of the present invention is that the nano-deposition method is used to replace the injection molding process, and the nano-deposited layer is directly coated with the wafer to provide electrical insulation and isolation protection, so that the package size can be greatly reduced, and the ratio can be reduced. The true wafer-level package (CSP) size of hundreds of wafers (250nm) nanometers, especially the thickness of the package is only the thickness of the wafer itself plus the thickness of the nano-deposited layer, so as to achieve light transmission, waterproof and electromagnetic interference (EMI). Features. Therefore, the present invention has the advantages of simpler process, higher yield, and lower cost, and indeed has industrial applicability.

The above is only a preferred embodiment for explaining the present invention, and is not an attempt. It is intended that the present invention be construed as being limited by the scope of the invention.

10‧‧‧ wafer

11‧‧‧Photosensitive area

14‧‧‧Electrical connection pads

20‧‧‧ nano-sediment

Claims (12)

A chip package structure comprising: a wafer, an optical sensing chip, having an electrical circuit, a photosensitive region and a plurality of electrical connection pads, wherein the photosensitive region and the electrical connection pads are disposed on the wafer An upper surface, wherein the photosensitive region has a photosensitive function, and the electrical connection pads are used to connect external circuits or electrical components; and a nano-deposited layer, electrically insulating and translucent, covers the photosensitive region, and The electrical connection pads are exposed, and the nano deposited layer is composed of a light transmissive hydrophobic plastic material. The wafer package structure of claim 1, wherein the photosensitive region is disposed in a central region of the wafer, and the electrical connection pads are located around an outer periphery of the wafer, and the plastic material comprises an oxide (Oxide) , silicone, phenolic resin, polycarbonate, acrylic resin, polyimide, polytetrafluorethylene, BT resin (Bismaleimide Triazine) ) or epoxy resin (Epoxy). The wafer package structure according to claim 1, wherein the surface of the photosensitive region is provided with a plurality of microlenses, and the nano-deposited layer has low reflectivity as an anti-reflection layer, and the nano-deposited layer The thickness is from 120 to 260 nm. The chip package structure of claim 1, further comprising: a circuit layer, which is a metal conductive layer having a circuit pattern, and a portion of the lower surface of the circuit layer covers the outer edge of the nano-deposited layer, and The remaining lower surface of the circuit layer contacts the wafer and is electrically connected to the electrical connection pads; A plurality of connection bumps are disposed on an upper surface of the circuit layer for connecting the external circuit or the electrical component. A chip package structure comprising: a wafer, an integrated circuit (IC) semiconductor chip having an electrical circuit and a plurality of electrical connection pads, wherein the electrical connection pads are disposed on an upper surface of the wafer, wherein To connect an external circuit or an electrical component; a nano-deposited layer having a light transmissive or opaque property covering a portion of the surface of the wafer and exposing the electrical connection pads, and the nano-deposited layer is electrically insulated And consisting of a hydrophobic plastic material; a circuit layer is a metal conductive layer having a circuit pattern, and a portion of the lower surface of the circuit layer covers the outer edge of the nano-deposited layer, and the rest of the circuit layer a lower surface contacting the wafer and electrically connected to the electrical connection pads; a plurality of connection bumps disposed on an upper surface of the circuit layer for connecting the external circuit or the electrical component; and at least one electronic component A surface mount component (SMD) is disposed on the circuit pattern of the circuit layer. The chip package structure according to claim 5, wherein the plastic material comprises an oxide, a silicone, a phenolic resin, a polycarbonate, an acrylic resin, a polyamidene resin, a polytetrafluoroethylene, a BT resin or an epoxy. Resin. A wafer packaging process includes: a cleaning step of cleaning a plurality of wafers on a wafer, each wafer having an electrical circuit, a photosensitive region, and a plurality of electrical connection pads, wherein the photosensitive region and the electrical connections The pad is disposed on the upper surface of the wafer; a nano-deposited layer forming step is formed by chemical vapor deposition (CVD), or spin coating and curing to form a nanometer on the surface of each wafer. Depositing a layer covering the photosensitive region and exposing the electrical connection pads, and the nano-deposited layer is electrically insulating and transmissive; and a cutting step of dicing the wafer to separate each wafer. According to the wafer packaging process of claim 7, wherein the wafer is an integrated circuit semiconductor wafer, the electrical connection pads are located around the outer periphery of the wafer, and the plastic material comprises an oxide, a silicone, a phenolic resin, Polycarbonate, acrylic resin, polyamido resin, polytetrafluoroethylene, BT resin or epoxy resin. According to the wafer packaging process of claim 7, further comprising, after the step of forming the nano-deposition layer, a circuit layer forming step of forming a circuit layer on the nano-deposited layer and the wafer to cover the The outer edge of the nano-deposited layer contacts the electrical connection pads; and a connection bump forming step is formed on the circuit layer to form a plurality of connection bumps for connecting the external circuit or the electrical component. A chip packaging process includes: a cleaning step of cleaning a plurality of wafers on a wafer, each wafer having an electrical circuit and a plurality of electrical connection pads, wherein the electrical connection pads are disposed on the wafer a nano-deposited layer forming step of forming a nano-deposited layer on the surface of each wafer by chemical vapor deposition or spin coating and aging, and exposing the electrical connection pads, And the nano-deposited layer is electrically insulating; In a cutting step, the wafer is etched to separate each wafer. According to the wafer packaging process of claim 10, wherein the wafer is an optical sensing wafer, the photosensitive region is disposed in a central region of the wafer, and the electrical connection pads are located at an outer periphery of the wafer, and The plastic material comprises an oxide, a silicone, a phenolic resin, a polycarbonate, an acrylic resin, a polyamidene resin, a polytetrafluoroethylene, a BT resin or an epoxy resin. According to the wafer packaging process of claim 10, after the step of forming the nano-deposited layer, a step of forming a circuit layer and connecting bumps is formed, and a circuit layer is formed on the nano-deposit layer to cover The outer edge of the nano-deposited layer contacts the electrical connection pads, and a plurality of connection bumps are formed on the circuit layer; and an electronic component connection step utilizes Surface Mount Technology (SMT), The electronic components of at least one surface-adhesive component are flat-bonded to the connecting bumps.