TW201511228A - Semiconductor device - Google Patents

Abstract

When using a diffusion layer with a high resistance in a source terminal, there had been a possibility that high speed operations become difficult by the current required to write to a memory cell not flowing. A semiconductor device according to the present invention comprises: memory cells which are located near the intersections of local bit lines and word lines, each memory cell being electrically connected between a corresponding local bit line and a shared source line and being selected by a corresponding word line; first transistors that are electrically connected between the shared source line and the local bit lines; second transistors that are electrically connected between a global bit line and the local bit lines; and a control circuit that controls each of the first transistors and the second transistors. The control circuit places a second transistor that corresponds to a selected local bit line into a conducting state and the first transistor into a non-conducting state, and places the second transistors corresponding to non-selected local bit lines into a non-conducting state and the first transistors into a conducting state.

Description

Semiconductor device [For the record of related applications]

The present invention is based on the constitutional claim of Japanese Patent Application No. 2013-085423 (filed on Apr. 16, 2013), the entire contents of which are incorporated herein by reference. .

The present invention relates to a semiconductor device having a memory element.

In a semiconductor device having a memory element, there is known a semiconductor device having a bipolar switching type impedance varying element that applies a voltage in a reverse direction to a memory element when information of logics 0 and 1 is written. As such an impedance change element, it is known to use a Schottky barrier as a memory element (for example, refer to Patent Document 1), using a tunneling magneto-resistance (TMR) element and using spin injection. For magnetization reversal phenomenon, use metal oxides, etc. Such an impedance changing element is used as a memory unit combined with a selection element. Use a vertical MOSFET (metal- as a selection component) For example, in the case of the NMOS transistor of the gate structure of Patent Document 2, the area of the memory cell can be made 4F2 in size, and the degree of integration can be improved. In such a vertical MOSFET, the source terminal is electrically connected to a bit line constructed using a wide-area bit line and a local bit line.

[Previous Technical Literature] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2005-183570

[Patent Document 2] Japanese Patent Laid-Open Publication No. 2010-55696

The following analysis was obtained by the inventors of the present application.

However, the diffusion layer of the lower MOSFET has a higher impedance, and the lower diffusion layer is used for the source terminal, and there is no current necessary for writing to the memory cell. High-speed operation becomes a difficult possibility. However, Patent Document 1, 2 is a relationship between a local bit line and a wide-area bit line in the case where a plurality of local bit lines are provided in plural, or is not described in terms of control thereof.

In one aspect of the present invention, in a semiconductor device, there are: a wide-area bit line, a common source line, and a plurality of local bit lines, a plurality of word lines intersecting the plurality of local bit lines, and a plurality of word lines arranged in the vicinity of the intersection of the plurality of local bit lines and the plurality of word lines, electrically connected to the corresponding a plurality of memory cells selected between the local bit lines and the common source lines, and the plurality of memory cells selected by the corresponding word lines, and electrically connected to each of the common source lines and the plurality of local bits a first transistor having a plurality of lines between the lines, and a second transistor electrically connected between the plurality of bit lines and the plurality of local bit lines, and a first transistor for controlling each of the plurality a control circuit for the crystal and the second plurality of transistors, wherein the control circuit is configured to be in a conductive state corresponding to the second transistor corresponding to one local bit line of the plurality of local bit lines; The first transistor of the one local bit line has a non-conduction state, and the second transistor corresponding to another local bit line included in the plurality of local bit lines is in a non-conduction state. Corresponding to the other local bit line of the first transistor, a conduction state.

According to the present invention, even if the bit line of the layer structure is used, appropriate control can be performed with respect to precharging, and a semiconductor device having a high speed and highly integrated memory cell array can be provided.

1‧‧‧Semiconductor device

10‧‧‧Control circuit

11‧‧‧ address input circuit

12‧‧‧ address latch circuit

13‧‧‧Command input circuit

14‧‧‧Instruction Decoding Circuit

15‧‧‧ mode register

16,16a‧‧ line decoder

17,17a‧‧‧ column decoder

20‧‧‧Memory cell array

20a‧‧‧ pads

20b‧‧‧Sub-character line driver. Secondary pad control circuit

20c‧‧‧Sense Amplifier Circuit

20d‧‧‧Subpad

21‧‧‧clock input circuit

22‧‧‧DLL circuit

23‧‧‧ FIFO circuit

24‧‧‧Output and input circuit

25‧‧‧Internal power generation circuit

31‧‧‧Activating the sense amplifier

32‧‧‧Activation segmentation

Section 33‧‧

40‧‧‧矽 substrate

41‧‧‧p-type well

42‧‧‧Cylinder

43‧‧‧Diffusion layer separation range

44a, 44b‧‧‧n+ diffusion layer (2nd wiring layer)

45‧‧‧n+ diffusion layer

46‧‧‧gate electrode

47‧‧‧Contact plug

48‧‧‧ lower electrode

49‧‧‧ impedance change film

50‧‧‧Upper electrode

52a~g‧‧‧Contact plug

53a~f‧‧‧ wiring (3rd wiring layer)

54, 54a~c‧‧‧ contact plug

55, 55a~c‧‧‧ Wiring (1st wiring layer)

56‧‧‧buried metal (metal layer)

BANK0~7‧‧‧ memory group 0~7

ARRAY0~3‧‧‧Array 0~3

BLOCK0~8‧‧‧Unit 0~8

CK, /CK‧‧‧ external clock signal

ICLK‧‧‧ internal clock signal

LCLK‧‧‧ internal clock signal

GBL, GBL0~n/2-1‧‧‧ wide-area bit line

LBL, LBL0~n-1‧‧‧ local bit line

DLBL‧‧‧virtual local bit line

GCS‧‧‧ Wide-area common source line

CS‧‧‧Common source line

LCS‧‧‧Local Common Source Line

PC0~n-1‧‧‧Precharge control signal line

SW0~n-1‧‧‧Connected control signal line

SEL‧‧‧ segment selection signal line

SELB‧‧‧Reverse segmentation selection signal line

WL0~m-1‧‧‧ character line

SWD‧‧‧Sub-character line driver

MC‧‧‧ memory unit

M‧‧‧ impedance change component (memory component)

SA‧‧‧Sense Amplifier

PCA‧‧‧Precharge range

SWA‧‧‧Switching range

CSA‧‧‧Common source supply range

LCSA‧‧‧Local Common Source Supply Range

Tr1~7‧‧‧Optocrystal (select component)

DTr‧‧‧Virtual Crystal

VPP‧‧‧ boost voltage (line)

VDD‧‧‧Power supply voltage

VSS‧‧‧ Grounding voltage

VCS‧‧‧Precharge voltage (line)

Vreset‧‧‧Logic 0 write voltage

Vset‧‧‧Logic 1 write voltage

Vread‧‧‧ read voltage

Iread0, Iread1‧‧‧ read current

figure 1

A block diagram showing the circuit configuration of the semiconductor device according to the first embodiment of the present invention is schematically shown.

figure 2

A layout of the configuration of the semiconductor device according to the first embodiment of the present invention is schematically shown.

image 3

A layout of a configuration of one memory cell of the semiconductor device according to the first embodiment of the present invention is schematically shown.

Figure 4

A layout of a configuration of one array of the semiconductor device according to the first embodiment of the present invention is schematically shown.

Figure 5

A layout of a configuration of one spacer of the semiconductor device according to the first embodiment of the present invention is schematically shown.

Figure 6

A layout view of the configuration of the sub-pad and the periphery of the semiconductor device according to the first embodiment of the present invention is schematically shown.

Figure 7

A circuit diagram showing a configuration of a sub-pad and a periphery of the semiconductor device according to the first embodiment of the present invention is schematically shown.

Figure 8

A plan view showing a configuration of a sub-pad and a peripheral portion of the semiconductor device according to the first embodiment of the present invention is schematically shown.

Figure 9

A cross-sectional view taken along line X-X' of Fig. 8 in which a sub-pad of the semiconductor device according to the first embodiment of the present invention and a peripheral portion thereof are configured is schematically shown.

Figure 10

A pattern diagram showing the hysteresis characteristics of the impedance varying elements.

Figure 11

A sequence diagram showing an operation waveform of each signal line of the complex pad of the semiconductor device according to the first embodiment of the present invention is schematically shown.

Figure 12

A plan view showing a partial configuration of a sub-pad of the semiconductor device according to the second embodiment of the present invention is schematically shown.

Figure 13

A cross-sectional view taken along line X-X' of Fig. 12, which is a partial configuration of a sub-pad of the semiconductor device according to the second embodiment of the present invention, is schematically shown.

Figure 14

A plan view showing a partial configuration of a sub-pad of the semiconductor device according to the third embodiment of the present invention is schematically shown.

Figure 15

A cross-sectional view taken along line X-X' of Fig. 14 in which one of the sub-pads of the semiconductor device according to the third embodiment of the present invention is configured is schematically shown.

Figure 16

A cross-sectional view taken along line Y-Y' of Fig. 14 in which a part of the sub-pad of the semiconductor device according to the third embodiment of the present invention is configured is schematically shown.

Figure 17

A circuit diagram showing a configuration of a sub-pad of the semiconductor device according to the fourth embodiment of the present invention is schematically shown.

Figure 18

A cross-sectional view showing a part of a sub-pad of the semiconductor device according to the fourth embodiment of the present invention is schematically shown.

Figure 19

A sequence diagram showing an operation waveform of each signal line of the sub-pad of the semiconductor device according to the fourth embodiment of the present invention is schematically shown.

Figure 20

A layout of the configuration of the sub-pad of the semiconductor device according to the fifth embodiment of the present invention is schematically shown.

Figure 21

A circuit diagram showing a configuration of a sub-pad of the semiconductor device according to the fifth embodiment of the present invention is schematically shown.

Figure 22

An enlarged plan view of the range R of Fig. 20 showing the configuration of the sub-pad of the semiconductor device according to the fifth embodiment of the present invention is schematically shown.

Figure 23

A cross-sectional view taken along line X-X' of Fig. 22, which is a partial configuration of a sub-pad of the semiconductor device according to the fifth embodiment of the present invention, is schematically shown.

[Embodiment 1]

The semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. Fig. 1 is a block diagram schematically showing a circuit configuration of a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a layout diagram schematically showing the configuration of a semiconductor device according to the first embodiment of the present invention. Fig. 3 is a layout diagram schematically showing the configuration of one storage unit of the semiconductor device according to the first embodiment of the present invention. Fig. 4 is a layout diagram schematically showing the configuration of one array of the semiconductor device according to the first embodiment of the present invention. Fig. 5 is a layout diagram schematically showing the configuration of one spacer of the semiconductor device according to the first embodiment of the present invention.

Referring to Fig. 1, a semiconductor device 1 is a semiconductor memory device having a memory element (memory). The semiconductor device 1 is an internal circuit having a control circuit 10, a memory cell array 20, and a clock input circuit 21, and a DLL circuit 22, and a FIFO circuit 23, an input/output circuit 24, and an internal power supply circuit 25. However, the internal circuit is formed on all of the same semiconductor wafers formed of a single crystal germanium, for example, a plurality of transistors having PMOS, NMOS, or the like.

The control circuit 10 is a circuit that controls the operation of the memory cell array 20. The control circuit 10 is a main circuit unit having an address input circuit 11, and an address latch circuit 12, and an instruction input circuit 13, and an instruction decoding circuit 14, and a mode register 15, and a row decoder 16, And column decoder 17.

The address input circuit 11 is a circuit that outputs an address signal ADD input by a plurality of external terminals (address terminals) toward the address latch circuit 12.

The address latch circuit 12 is a circuit that latches the address signal ADD from the address input circuit 11. The address latch circuit 12 is among the latched address signals ADD, outputs the row address to the row decoder 16, and outputs the column address to the column decoder 17. The address latch circuit 12 outputs the latched address signal ADD toward the mode register 15.

The command input circuit 13 is directed to a command signal CMD (row address strobe signal /RAS, column address strobe signal /CAS, write enable signal /WE) input by a plurality of external terminals (command terminals), A circuit that instructs the decoding circuit 14 to output. The command input circuit 13 outputs a reset signal /RESET input by an external terminal (reset terminal) toward the DLL circuit 22. However, in the present specification, the signal with the "/" attached to the signal name means the inverted signal of the corresponding signal or the signal of low activity.

The command decoding circuit 14 holds a command signal CMD from the command input circuit 13, decodes and holds the command signal CMD, and generates various internal command signals. The command decoding circuit 14 outputs the generated various internal command signals to the mode register 15, the row decoder 16, and the column decoder 17.

The mode register 15 is a circuit for generating the mode information MRS for the internal circuit based on the internal command signal from the instruction decode circuit 14 and the address signal from the address latch circuit 12. The mode register 15 outputs the generated mode information MRS toward the internal circuit.

The row decoder 16 corresponds to the internal command signal from the instruction decode circuit 14, and is selected according to the row address of the address latch circuit 12. A circuit of any one of the word lines (corresponding to the word line WL0 to m-1 of FIG. 7) in the memory cell array 20.

The column decoder 17 corresponds to the internal command signal from the instruction decoding circuit 14, and selects any sense amplifier in the memory cell array 20 according to the column address of the address latch circuit 12 (corresponding to FIG. 5, The circuit of sense amplifier SA) of Figure 6.

The clock input circuit 21 is a circuit that inputs an external clock signal CK, /CK by an external terminal (clock terminal). The clock input circuit 21 generates a single-phase internal clock signal ICLK based on the external clock signals CK and /CK, and outputs the generated internal clock signal ICLK to the DLL circuit 22. Here, the external clock signal CK and the external clock signal / CK system have signals that complement each other.

The DLL (Delay Locked Loop) circuit 22 is a circuit that generates an internal clock signal LCLK that controls the delay amount of the internal clock signal ICLK. The DLL circuit 22 generates an internal clock signal LCLK for controlling the delay amount of the internal clock signal ICLK in response to the reset signal /RESET, and outputs the generated internal clock signal LCLK toward the FIFO circuit 23 and the input/output circuit 24.

The FIFO (first-in first-out) circuit 23 is a circuit that performs the exchange of data between the memory cell array 20 and the input/output circuit 24 in the same manner as the internal clock signal LCLK. The FIFO circuit 23 outputs the read data DQ from the memory cell array 20 toward the input/output circuit 24 in synchronization with the internal clock signal LCLK during the read operation. The FIFO circuit 23 is synchronized with the internal clock signal LCLK during the write operation. The write data DQ from the input/output circuit 24 is output toward the memory cell array 20.

The input/output circuit 24 is a circuit that controls the input and output of the data DQ at a plurality of external terminals (data input/output terminals). The input/output circuit 24 reads the data from the FIFO circuit 23 in synchronization with the internal clock signal LCLK during the read operation, and outputs the data to the terminal as the read data DQ. The input/output circuit 24 outputs the self-data to the write data DQ of the terminal in synchronization with the internal clock signal LCLK during the write operation, and outputs it to the FIFO circuit 23.

The internal power generating circuit 25 generates a plurality of internal voltages (boost voltage VPP, precharge voltage VCS, etc.) in response to the voltage applied to the internal circuit based on the power supply voltage VDD and the ground voltage VSS input from the external terminal (power supply terminal). A circuit that reads out the voltage Vread, etc.). The internal power generating circuit 25 outputs the generated internal voltages to the respective internal circuits.

Here, the semiconductor device 1 includes a row decoder 16, a column decoder 17, and a memory bank BANK of the memory cell array 20, and has a plurality of (eight memory banks BANK0 to 7 in FIG. 2). However, in FIG. 2, eight memory banks are provided, but the number of memory banks is not limited to eight, but may be, for example, four.

Referring to Fig. 2, in each of the memory banks BANK0 to S7, the vertical direction row decoder 16a (one part of the row decoder 16 of Fig. 1) extending in the center portion is arranged in two columns. Further, a column decoder 17a extending in the lateral direction of the central portion is disposed (FIG. 1) One of the columns of the decoder 17). The arrays ARRAY0 to 3 are arranged in four ranges divided by the row decoder 16a and the column decoder 17a.

Referring to Fig. 3, each of the arrays ARRAY0 to 3 is divided into eight in the horizontal direction and 16 in the vertical direction, and is divided into spacers 20a of a total of 128. For the lower end of each pad 20a, a sub-word line driver is arranged. The subpad control circuit 20b is provided with a sense amplifier circuit 20c for the left and right end portions. Although there is no special restriction, but the sub-character line driver. The subpad control circuit 20b is shared by the spacer 20a adjacent to the upper and lower sides. Further, the sense amplifier circuit 20c is shared by the pads 20a adjacent to the left and right. Secondary character line driver. The subpad control circuit 20b is selected via the corresponding row decoder 16a. The sense amplifier circuit 20c is selected in the corresponding column and is selected via the column decoder 17a.

In the array ARRAY0~3, the complex word line (the character line WL0~m-1 of Fig. 7) and the partial bit line of the complex number (LBL0~n-1 of Fig. 7) are set at the intersections. The memory unit (the MC of FIG. 7) in the vicinity of the (stereoscopically intersecting portion) is plurally arranged, and the read operation, the write operation, the reproduction (sensing and re-processing) for the memory unit (MC of FIG. 7) It is possible to write an independent action such as an action. For example, the memory bank BANK0 is activated when an input activity command is input to the command input circuit (13 of FIG. 1), and an operation corresponding to the active command (sensing operation) is performed. After receiving the activity command, the memory bank BANK0 accepts a read command corresponding to the data read operation, or corresponds to The memory bank BANK1 is activated when a regenerative command is input to the command input circuit 13 during the period in which the data is written to the write command, or after the command is received, and the regenerative command operation can be performed ( The action of sensing and writing action). However, the reproducing operation is also an unnecessary memory unit, and the present invention is also applicable to the semiconductor device 1 using such a memory unit.

Referring to Fig. 4, each array (ARRAY 0 to 3 in Fig. 3) is divided into eight cells BLOCK0 to 7 in which 16 blocks 20a are arranged in the vertical direction. When accessing a specific memory unit (equivalent to the memory unit MC of Figure 7), via the sub-word line driver. The subpad control circuit 20b adds one segment of one of the cells BLOCK0 to 7 (for example, the activation segment 32 of the reference cell BLOCK5), and activates the sense of being located on both sides in the lateral direction. The amplifier is calibrated (for example, with reference to the activated sense amplifier 31 located on either side of the unit BLOCK5). Secondary character line driver. The subpad control circuit 20b selects a specific segment by the control of the row decoder 16a.

Referring to Fig. 5, each of the spacers (Fig. 4, 20a) is divided into, for example, 16 in the lateral direction and 32 in the vertical direction, and is divided into a total of 512 sub-pads 20d. The 32 sub-pads 20d arranged in a row in the longitudinal direction constitute one segment 33. Arranged in a row of 16 sub-pads 20d in the horizontal direction, via a sub-word line driver. The one segment activated by the subpad control circuit 20b is selectively connected to the sensing at the left and right ends by one wide-area bit line GBL and one wide-area common source line GCS. Amplifier SA (a part of the sense amplifier circuit 20c) Minute). The sense amplifier SA is selected via a column decoder (17a of Fig. 3). The sense amplifier SA amplifies the read data from the wide-area bit line GBL during the read operation, and outputs the amplified read data toward the FIFO circuit (23 of FIG. 1). On the other hand, the sense amplifier SA latches the write data from the FIFO circuit (23 of FIG. 1) during the write operation, and outputs the latched write data toward the wide-area bit line GBL.

Next, the sub-pad of the semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. Fig. 6 is a plan view schematically showing a configuration of a sub-pad and a peripheral portion of the semiconductor device according to the first embodiment of the present invention. Fig. 7 is a circuit diagram schematically showing a configuration of a sub-pad and a periphery of the semiconductor device according to the first embodiment of the present invention. Fig. 8 is a plan view schematically showing a configuration of a sub-pad of the semiconductor device according to the first embodiment of the present invention and a peripheral portion thereof. Fig. 9 is a cross-sectional view taken along the line X-X' of Fig. 8 showing a configuration of a sub-pad of the semiconductor device according to the first embodiment of the present invention and a peripheral portion thereof. Fig. 10 is a schematic view showing the hysteresis characteristic of the impedance varying element.

Referring to Fig. 6, the sub-pad 20d (corresponding to 20d of Fig. 5, but in Fig. 5, 20d is arranged 36 in the vertical direction, but in the first embodiment of the present invention, 32 such On the both sides in the horizontal direction of the figure in which one sub-pad is formed, a precharge range PCA and a switching range SWA are arranged. A sub-word line driver SWD is disposed on both sides in the longitudinal direction of the sub-pad 20d. The sub-word line driver SWD is the sub-word line driver of Figure 5. Secondary pad control circuit 20b portion. For the sub-pad 20d including the switching range SWA and the pre-charging range PCA, a wide-numbered bit line GBL0~ extending in the horizontal direction (n/2 in FIG. 6) extending in the horizontal direction of the figure is disposed. n/2-1. The wide-area bit line GBL0~n/2-1 is continuously extended in the horizontal direction of the figure in a horizontal direction of one pad 20a of FIG. The wide-area bit line GBL0~n/2-1 is electrically connected to the source/汲 terminal of the transistor (corresponding to Tr2 of FIG. 7) of the switching range SWA, and the sense amplifier SA. The signals from the wide-area bit lines GBL0~n/2-1 are amplified by the sense amplifier SA. However, in FIG. 5, the sense amplifier circuit 20c is disposed on both sides of the spacer 20a, but FIG. 6 is an example in which only the left side is disposed.

Referring to Fig. 7, on the sub-pad 20d including the precharge range PCA and the switching range SWA, n local bit lines LBL0 to n-1 extending in the lateral direction of the figure are disposed. The local bit line LBL0~n-1 is different from the wide-area bit line GBL0~n/2-1, and is disposed on one sub-pad 20d and its pre-charging range PCA and switching range SWA on both sides in the lateral direction. The scope. However, although not particularly limited, in one sub-pad 20d, one local bit line LBL0~n is disposed for each of the two sides of the wide-area bit line GBL0~n/2-1. -1, and the number of wide-area bit lines becomes n/2. The sub-pad 20d is provided with m word lines WL0 to m-1 extending in the longitudinal direction of the drawing. The word lines WL0 to m-1 are controlled via the sub word line driver SWD of FIG. The memory cell MC is disposed in the vicinity of a portion where the word line WL0 to m-1 and the local bit line LBL0 to n-1 intersect. The memory cells MC are arranged in a matrix, in one There are m × n in the sub-pad 20d. The memory cell MC is configured by connecting a transistor Tr3 (for example, an nMOSFET) and an impedance conversion element M in series. The transistor Tr3 system gate electrode is electrically connected to the corresponding word line WL0~m-1, and the source terminal is electrically connected to the common source line CS, and the 汲 terminal is electrically connected to the impedance conversion element M. connection. One end of the impedance converting element M is electrically connected to the first terminal of the transistor Tr3, and the other end is electrically connected to the corresponding local bit line LBL0~n-1. The precharge voltage VCS is supplied to the common source CS system.

For the precharge range PCA, two precharge control signal lines PC0, PC1 extending in the longitudinal direction of the drawing are disposed. Precharge control signal lines PC0, PC1 are via the sub-character line driver of Figure 5. The subpad control circuit 20b is controlled. For the local bit line LBL0, 2, 4 of the even number of the local bit line LBL0~n-1. . . A transistor Tr1 (for example, an nMOSFET) for precharging is disposed in the vicinity of a portion intersecting the precharge control signal line PC0. For the local bit line LBL1, 3, 5. of the odd number among the local bit lines LBL0~n-1. . . A transistor Tr1 for precharging is disposed in the vicinity of a portion intersecting the precharge control signal line PC1. The local bit line LBL0, 2, 4 of the even number in the transistor Tr1. . . The gate electrode of the corresponding electro-crystal system is electrically connected to the pre-charge control signal line PC0, and the source terminal is electrically connected to the common source line CS, and the 汲 terminal is corresponding to the local number of the corresponding even number. Yuan line 0, 2, 4. . . Connected to it electrically. In addition, the local bit line LBL1, 3, 5. of the odd number in the transistor Tr1. . . Corresponding transistor The gate electrode is electrically connected to the precharge control signal line PC1, and the source terminal is electrically connected to the common source line CS, and the 汲 terminal is connected to the corresponding odd number local bit line LBL1, 3 , 5. . . Connected to it electrically.

In the switching range SWA, two connection control signal lines SW0 and SW1 extending in the longitudinal direction of the drawing are disposed. Connect the control signal lines SW0, SW1 via the sub-word line driver of Figure 5. The subpad control circuit 20b is controlled. For the local bit line LBL0, 2, 4 of the even number of the local bit line LBL0~n-1. . . A transistor Tr2 (for example, an nMOSFET) for switching is disposed in the vicinity of a portion intersecting the connection control signal line SW0. In addition, for the partial bit line LBL1, 3, 5. of the odd number among the local bit lines LBL0~n-1. . . A transistor Tr2 for precharging is disposed in the vicinity of a portion intersecting the connection control signal line SW1. The local bit line LBL0, 2, 4 of the even number in the transistor Tr2. . . The gate electrode of the corresponding electro-crystal system is electrically connected to the connection control signal line SW0, and the source terminal is electrically connected to the wide-area bit line GBL0~n/2-1, and the 汲 terminal corresponds to The even bit number of the local bit line LBL0, 2, 4. . . Connected to it electrically. In addition, the local bit line LBL1, 3, 5. of the odd number in the transistor Tr2. . . And the corresponding gate electrode of the electro-crystal system is electrically connected to the connection control signal line SW1, and the source terminal is electrically connected to the corresponding wide-area bit line GBL0~n/2-1, and the 汲 terminal is Local bit line LBL1, 3, 5. with corresponding odd number. . . Connect electrically.

In the configuration of Figure 7, for example, for an even number Partial line LBL0, 2, 4. . . When it is connected to the corresponding wide-area bit line GBL0~n/2-1, the pre-charge control signal line PC0 is low, the pre-charge control signal line PC1 is high, and the connection control signal line SW0 is high. SW1 is controlled for low ground. At this time, the odd bit number local bit line LBL1, 3, 5. . . The voltage (potential) is the pre-charge voltage VCS, for the local bit line LBL1, 3, 5. connected to the selected word line and odd number. . . The impedance change element M of the non-selected memory cell MC is such that no current flows, and it is possible to prevent the memory information from being read and destroyed by interference. However, the wide-area bit line GBL0~n/2-1 is electrically connected to a sense amplifier (sense amplifier SA of FIG. 6) and a write circuit (not shown). The sense amplifier (the sense amplifier SA of FIG. 6) is amplified while being read from the read signal current read by the selected memory cell MC, and is applied at the time of writing and writing again. The voltage is applied to the selected memory cell MC.

When referring to FIG. 8 of the circuit of FIG. 7, the sub-word driver SWD is disposed on both sides in the longitudinal direction of the sub-pad 20d, and the lateral sides of the sub-pad 20d are disposed on the lateral side. Switching range SWA and pre-charging range PCA. In the sub-pad 20d, an n+ diffusion layer 44a serving as a common source line (common source line CS of FIG. 7) is disposed. The n+ diffusion layer 44a is also disposed over the entire range of the precharge range PCA. In the sub-pad 20d, a plurality of memory cells MC controlled by the word lines WL0 to m-1 are disposed between the n+ diffusion layer 44a and the local bit lines LBL0 to n-1.

In the precharge range PCA, the n+ diffusion layer 44a is used by The contact plug 52a is electrically connected to the common source line CS. In the precharge range PCA, a transistor Tr1 (for example, nMOSFET) controlled via the precharge control signal line PC0 or PC1 is disposed between the n+ diffusion layer 44a and the local bit lines LBL0 to n-1.

For the switching range SWA, an n+ diffusion layer 44b electrically separated from the n+ diffusion layer 44a is disposed. The n+ diffusion layer 44b is disposed in the switching range SWA in accordance with the wide-area bit lines GBL0 to n/2-1. The n+ diffusion layer 44b is electrically connected to the corresponding wide-area bit lines GBL0 to n/2-1 by wirings 53c, contact plugs 52e, and the like. In the switching range SWA, a transistor Tr2 (for example, an nMOSFET) controlled via the connection control signal line SW0 or SW1 is disposed between the n+ diffusion layer 44b and the corresponding local bit line LBL0 to n-1.

When referring to FIG. 9 which is a cross section between XX' in FIG. 8, the semiconductor device is formed in the sub-pad (2d of FIG. 8) and its periphery, and a p-type well 41 is formed on the germanium substrate 40 in the p-type. An n+ diffusion layer 44a, 44b is formed on the well 41. A groove is formed in a range between the n+ diffusion layer 44a and the n+ diffusion layer 44b on the p-type well 41, and a diffusion layer separation range 43 in which an insulator is buried is formed in the groove. The diffusion layer separation range 43 is electrically separated between the n+ diffusion layer 44a and the n+ diffusion layer 44b, electrically separated between the adjacent n+ diffusion layers 44a, and electrically separated between the adjacent n+ diffusion layers 44b.

A specific position on the n+ diffusion layers 44a, 44b is formed by a column 42 made of a columnar p-type semiconductor to form an n+ diffusion layer 45. For the left and right sides of the cylinder 42, the specific interval is separated, and A gate electrode 46 is disposed (by a gate insulating film). The n+ diffusion layer 44a or 44b, the pillar 42, the n+ diffusion layer 45, and the gate electrode 46 constitute a vertical nMOSFET. A vertical nMOSFET which is a gate electrode 46 which is a part of the precharge control signal line PC0 (or PC1 of FIG. 8) is a transistor Tr1 for precharging. The vertical nMOSFET which is the gate electrode 46 which is one of the word lines WL0 to m-1 is a transistor Tr3 which is a selection element of the memory cell MC. The vertical nMOSFET which becomes the gate electrode 46 which is one part of the connection control signal line SW0 (or SW1 of FIG. 8) is the transistor Tr2 for switching.

On the n+ diffusion layer 45 of the transistor Tr3, the impedance change element M of the memory element of the memory cell MC is placed by the contact plug 47. The impedance changing element M has a configuration in which a lower electrode 48, an impedance change film 49, and an upper electrode 50 are laminated in this order from the contact plug 47 side. On the upper electrode 50, the wiring 53b of the local bit line LBL0 to n-1 is disposed by the contact plug 52c. The wiring 53b is electrically connected to the n+ diffusion layer 45 of the transistor Tr1 by the contact plug 52b. Further, the wiring 53b is electrically connected to the n+ diffusion layer 45 of the transistor Tr2 by the contact plug 52d.

Here, as the impedance change element M, for example, a spin torque transmission type TMR element can be used. In this case, a structure in which a thin film of magnesium dioxide is sandwiched between the magnetization fixed layer and the free layer formed of cobalt iron boron is generally used, but the configuration is not limited thereto (the semiconductor using the TMR element) The memory system is called STT-RAM). In addition, it is not limited to STT-RAM, but can also be applied to a semiconductor called so-called ReRAM. Memory. For the impedance change film 49, for example, any of a transition metal oxide, an aluminum oxide, a cerium oxide, or a mixed material thereof can be used. The transition metal oxide may further comprise any one of titanium oxide, nickel oxide, cerium oxide, zirconium oxide, cerium oxide, cerium oxide, cerium oxide, cerium oxide, tungsten oxide, or the like. Such as mixed materials. Among these memory cells, in the case of a non-destructive memory cell in which memory data is not destroyed by reading, the above-described reproducing operation system is unnecessary.

The wiring layer similar to the wiring 53b has the wiring 53a which becomes the common source line CS, and the wiring 53c. The wiring 53a is electrically connected to the n + diffusion layer 44a by the contact plug 52a. The wiring 53c is electrically connected to the n + diffusion layer 44b by the contact plug 52e. The wiring 53c is electrically connected to the wiring 55 which becomes the wide-area bit line GBL0 to n/2-1 by the contact plug 54.

For one of the local bit lines LBL0 to m-1, m memory cells MC are electrically connected. The local bit lines LBL0 to m-1 are electrically connected to the n+ diffusion layer 44b by the corresponding contact plug 52d and the transistor Tr2 in the vicinity of one end. The n+ diffusion layer 44b is electrically connected to the wiring 55 which becomes the wide-area bit lines GBL0 to n/2-1 by the contact plug 52e wiring 53c and the contact plug 54. The local bit lines LBL0 to m-1 are electrically connected to the corresponding wide-area bit lines GBL0 to n/2-1 of the upper layer when selected according to the corresponding transistor Tr2. The wide-area bit line GBL0~n/2-1 is electrically connected to the sense-sensing sense amplifier (sense amplifier SA of Fig. 6) and the circuit for writing (not shown). Sexual connection, which can be read and reflected in response to changes in impedance.

Further, the local bit lines LBL0 to m-1 are electrically connected to the n+ diffusion layer 44a by the corresponding contact plug 52b and the transistor Tr1 in the vicinity of the other end portion. The n+ diffusion layer 44a is electrically connected to the wiring 53a which becomes the common source line CS by the contact plug 52a. Further, the n+ diffusion layer 44a supplies a source voltage to the source terminal of the transistor Tr3 in each memory cell MC.

Fig. 10 is a diagram showing the hysteresis of the voltage-current characteristic of the impedance varying element M constructed by the circuit of Fig. 7 in a schematic manner. Both the high impedance state and the low impedance state show the characteristics of impedance. In the high-impedance state, when a voltage in the forward direction is applied with the precharge voltage VCS as a base point, the voltage is shifted to a low impedance state by a certain voltage or more. The voltage at which the voltage is higher than the voltage is set to the logic 1 write voltage Vset. Further, in the low-impedance state, when a voltage in the negative direction is applied with the precharge voltage VCS as a base point, the voltage is shifted to a high impedance state by a certain voltage or less. The voltage at which the voltage is lower than the voltage is set to the logic 0 write voltage Vreset. The reading is performed by applying the read voltage Vread and detecting the magnitude of the current flowing in the impedance varying element (corresponding to Iread1 of 1 data and Iread0 corresponding to 0 data).

Here, the logic 0 write voltage Vreset is set to the ground voltage VSS, and the logic 1 write voltage Vset is set to the power supply voltage VDD. The voltage at the above-mentioned base point corresponding to the characteristic of FIG. 10 is applied to the common source line (the precharge voltage VCS of the common source line CS of FIG. 8, FIG. 9), and the precharge voltage VCS and the ground voltage VSS. The read voltage Vread is set. However, for the gate electrode of the transistor Tr3 of Fig. 7, a boosting voltage VPP is applied, and this transistor is treated as an ideal switch. When the read voltage Vread is applied to the local bit line (LBL0 to n-1 in FIG. 7), the read current Iread0 or Iread1 flows in response to the impedance value of the impedance change element (M of FIG. 7). Further, a current value approximately between the Iread0 and the Iread1 is set to the reference current Iref, and is supplied to the sense amplifier (SA of FIG. 6) to be compared with the sense current.

Next, the operation of the sub-pad of the semiconductor device according to the first embodiment of the present invention will be described using the drawings. Fig. 11 is a sequence diagram showing an operation waveform of each signal line of the sub-pad of the semiconductor device according to the first embodiment of the present invention. However, in (A) of the left half of Figure 11, the 0 data read ~ write ~ 1 data write action is displayed, and in the right half (B), 1 data read ~ write again ~ 0 data write action. However, as described above, in the case of a memory cell that is not required to use the reproduction operation, the rewrite operation system may be omitted.

When referring to (A) of the left half of FIG. 11, during the precharge period, the precharge control signal line PC0 (or PC1) is controlled by the power supply voltage VDD, and the local bit line LBL is controlled to the precharge voltage VCS. The wide-area bit line GBL is controlled to a pre-charge voltage VCS via a precharge circuit (not shown). However, in the precharge period, the word line WL, the connection control signal line SW0 (or SW1) is simultaneously controlled by the ground voltage VSS.

After the precharge period, the even number of local bit lines LBL0, 2, 4. . . When the cell selection period is set to be connected to the address of the wide-area bit line GBL, the precharge control signal line PC0 is controlled to the ground voltage VSS, and the connection control signal line SW0 and the word line WL are controlled to be boosted. Voltage VPP. In addition, in the unit selection period, the odd number of local bit lines LBL1, 3, 5. . . The precharge voltage VCS is continuously maintained. The local bit line LBL and the wide field bit line GBL selected at the beginning of the sensing amplification period are set. The read voltage Vread is held, and the read current Iread0 flows in the memory cell MC.

After the cell selection period, when the sensing amplification period is reached, the read current Iread0 is smaller than the reference current Iref due to the small value corresponding to the high impedance state, and the current difference is sensed and amplified via the sense amplifier SA. . However, during the sense amplification period, the selected local bit line LBL and the wide field bit line GBL are slightly held as the read voltage Vread.

After the sensing amplification period, when the re-writing period is reached, the write circuit (not shown) controls the local bit line LBL and the wide-area bit line GBL selected corresponding to the read 0 data to the ground voltage. VSS. This is due to the logic 0 write voltage Vreset, and then write 0 data.

After the rewriting period, when the inversion write period is reached, the selected local bit line LBL and wide area bit line GBL are controlled by the power supply voltage VDD. This is because the logic 1 write voltage Vset is equivalent to the reverse writing of 1 data.

After the reverse write period, when the selection release period is reached, The connection control signal line SW0 and the word line WL are controlled to be the ground voltage VSS.

After the selection release period, when the precharge period is reached, the precharge control signal line PC0 is controlled by the power supply voltage VDD, and the local bit line LBL and the wide area bit line GBL are controlled to the precharge voltage VCS.

Next, when referring to the right half (B) of Fig. 11, the operation from the precharge period to the cell selection period is the same as that of Fig. 11(A). First, at the beginning of the sensing amplification period, the selected local bit line LBL and the wide field bit line GBL are set. The read voltage Vread is held, and the read current Iread1 flows in the memory cell MC.

After the cell selection period, when the sensing amplification period is reached, the read current Iread1 is larger than the reference current Iref due to the large value corresponding to the low impedance state, and the current difference is sensed and amplified via the sense amplifier SA. . However, during the sense amplification period, the selected local bit line LBL and the wide field bit line GBL are slightly held as the read voltage Vread.

After the sensing amplification period, when the re-writing period is reached, the write circuit (not shown) controls the local bit line LBL and the wide-area bit line GBL selected corresponding to the read 1 data to the power supply voltage. VDD. This is due to the logic 1 write voltage Vset, and then write 1 data.

After the rewriting period, when the inversion write period is reached, the selected local bit line LBL and the wide area bit line GBL are controlled to be grounded. Voltage VSS. This is due to the logic 0 write voltage Vreset, and the 0 data is inverted.

The operation from the selection release period to the precharge period after the reverse write period is the same as that of FIG. 11(A).

According to the first embodiment, a vertical MOSFET is used as a selection element of the memory cell, and even if a bit line (LBL, GBL) of a layer structure is used, appropriate control can be performed regarding precharging, and it is possible to provide A semiconductor device having a high speed and highly integrated memory cell array. Further, by shortening the length of the local bit line LBL, the width of the common source line CS can be narrowed, and the impedance of the common source line CS can be reduced. In addition, since only the memory cell MC connected to the local bit line LBL connected to the wide-bit bit line GBL has a write current flowing, the source line can be separated as in the case of the local bit line. In case of, reduce the source impedance. Moreover, the voltage of the common source line is set to be near the center of the power supply voltage VDD and the ground voltage VSS, and the logic 0 or logic 1 data is written to select the word line WL, and the bit line (LBL, GBL) When the voltage is set to the power supply voltage VDD or the ground voltage VSS, the polarity of the voltage applied to the impedance change element M can be inverted, and the current necessary for the flow can be performed.

[Embodiment 2]

The semiconductor device according to the second embodiment of the present invention will be described with reference to the drawings. Fig. 12 is a plan view schematically showing a partial configuration of a sub-pad of the semiconductor device according to the second embodiment of the present invention. Figure A cross-sectional view taken along line X-X' of Fig. 12 showing a partial configuration of a sub-pad of the semiconductor device according to the second embodiment of the present invention.

The second embodiment is a modification of the first embodiment. The common source line CS and the n+ diffusion layer 44a are electrically connected to each other, and are not in the precharge range PCA, but are formed in the range of the sub-pad 20d.

In the range of the sub-pad 20d, a common source supply range CSA is provided in a range between the word line WLf-1 and the word line WLf (for example, in the vicinity of the center of the range of the sub-pad 20d). In the common source supply range CSA, a p-type well 41 is formed on the germanium substrate 40, and an n+ diffusion layer 44a is formed on the p-type well 41. A specific position on the n+ diffusion layer 44a is formed by a column 42 made of a columnar p-type semiconductor to form an n+ diffusion layer 45. The gate electrodes 46 are disposed (with a gate insulating film) at a predetermined interval from the left and right sides of the column 42. The n+ diffusion layer 44a, the pillar 42, the n+ diffusion layer 45, and the gate electrode 46 constitute a vertical nMOSFET. The vertical nMOSFET which is the gate electrode 46 which is a part of the boost voltage line VPP is a transistor Tr4 for common source supply. The boost voltage line VPP word line WL0 to m-1 is fixed to a wiring which is a high boost voltage VPP, and is electrically connected to the sub word line driver SWD.

The wiring layer similar to the wirings 53a, 53b, and 53c has a wiring 53d. The wiring 53d is electrically connected to the n+ diffusion layer 45 of the transistor Tr4 by the contact plug 52e. The wiring 53d is electrically connected to the wiring 55b which becomes the common source line CS by the contact plug 54b. The precharge voltage VCS is supplied to the wiring 55b.

Among the wide-area bit lines GBL0 to n/2-1, the common source line CS is allocated to 10 pieces in a ratio of one degree. Accordingly, the local bit line assigned to the range of the common source line CS becomes the dummy local bit line DLBL, and the memory cell MC electrically connected to the dummy local bit line DLBL is also virtual.

The other configuration is the same as that of the first embodiment.

According to the second embodiment, the same effect as that of the first embodiment is obtained, and the precharge voltage VCS of the common source line CS is supplied to the central portion of the range of the sub-pad 20d, and is applied to each memory cell MC. The supply path of the precharge voltage VSC becomes a low impedance, and the operation margin can be ensured.

[Embodiment 3]

The semiconductor device according to the third embodiment of the present invention will be described with reference to the drawings. Fig. 14 is a plan view schematically showing a part of a configuration of a sub-pad of a semiconductor device according to a third embodiment of the present invention. Fig. 15 is a cross-sectional view taken along the line X-X' of Fig. 14 showing a partial configuration of a sub-pad of the semiconductor device according to the third embodiment of the present invention. Fig. 16 is a cross-sectional view schematically showing the configuration of a portion of a sub-pad of a semiconductor device according to a third embodiment of the present invention, taken along the line Y-Y' of Fig. 14.

The third embodiment is a modification of the first embodiment, and a structure in which the buried metal 56 (metal layer) is buried between the p-type well 41 and the n+ diffusion layer 44a is formed in order to reduce the low impedance of the common source line CS. By. For the buried metal 56, for example, W, TiN, or the like can be used. Buried metal The 56 series is wired at the same pitch as the local bit lines LBL0 to n-1, and the diffusion layer separation range 43 is disposed between the buried metals 56. The other configuration is the same as that of the first embodiment.

According to the third embodiment, the same effect as in the first embodiment is obtained, and the n+ diffusion layer 44a is reinforced by the buried metal 56 of the low-resistance material, and the operation margin can be improved.

[Embodiment 4]

The semiconductor device according to the fourth embodiment of the present invention will be described with reference to the drawings. Fig. 17 is a circuit diagram schematically showing the configuration of a sub-pad of the semiconductor device according to the fourth embodiment of the present invention. Fig. 18 is a cross-sectional view schematically showing a part of a configuration of a sub-pad of a semiconductor device according to a fourth embodiment of the present invention.

Embodiment 4 is a modification of the first embodiment, in which a lower diffusion layer (corresponding to the configuration of FIG. 5) is separated by SGI from a neighboring sub-pad, and a precharge range (PCA of FIG. 9) The common source line (CS of FIG. 9) and the n+ diffusion layer (44a of FIG. 9) replace the part electrically connected by the contact plug (Fig. 9, 52a), and reconfigure the local common source supply range LCSA. . In addition, in the precharge range PCA, precharging is controlled instead of two precharge control signal lines (PC0, PC1 of FIG. 7) as n precharge control signal lines PC0~n-1. Control pre-charge. Furthermore, in the switching range SWA, the bit line connection control is performed instead of the two connection control signal lines (SW0, SW1 of FIG. 7), and the connection control signal lines SW0~n-1 are provided as n pieces. Perform bit line connection control.

Referring to Fig. 17, a switching range SWA is disposed on the right side of the sub-pad 20d, and a pre-charging range PCA is disposed on the left side of the sub-pad 20d, and a local common source is disposed on the left side of the pre-charging range PCA. The pole supply range is LCSA.

The sub-pad 20d has m word lines WL0 to m-1, and n local bit lines LBL0 to n-1, and m × in the vicinity of the intersection (the portion where the three-dimensional intersection is arranged) n memory cells MC. The memory cell MC is configured by connecting a transistor Tr3 (for example, an nMOSFET) and an impedance conversion element M in series. The transistor Tr3 system gate electrode is electrically connected to the corresponding word line WL0~m-1, and the source terminal is electrically connected to the local common source line LCS, and the 汲 terminal is connected to the impedance conversion element M. Connect electrically. One end of the impedance converting element M is electrically connected to the first terminal of the transistor Tr3, and the other end is electrically connected to the corresponding local bit line LBL0~n-1.

In the switching range SWA, there are n connection control signal lines SW0 to n-1 corresponding to n pieces of local bit lines LBL0 to n-1, and have corresponding connection control signal lines SW0 to n-1. n transistors Tr2 for switching (for example, nMOSFET). The transistor Tr2 system gate electrode is connected to the corresponding connection control signal line SW0~n-1, and the source terminal is electrically connected to the wide field bit line GBL, and the 汲 terminal and the corresponding local bit element are electrically connected. The lines LBL0~n-1 are electrically connected.

In the switching range SWA, the precharge state, even The control signal lines SW0 to n-1 are controlled to be low, and each of the local bit lines LBL0 to n-1 is in a state of being separated from the wide-area bit line GBL. Further, in the switching range SWA, when the segmentation is activated, only the connection control signal lines SW0 to n-1 corresponding to the selected one of the local bit lines LBL0 to n-1 are controlled. To be high, only the selected local bit line LBL0~n-1 is connected to the wide-area bit line GBL.

In the precharge range PCA, there are n precharge signal lines PC0~n-1 corresponding to n local bit lines LBL0~n-1, and have corresponding precharge signal lines PC0~n-1. n of pre-charged transistors Tr1 (for example, nMOSFET). The gate electrode of the transistor Tr1 is electrically connected to the corresponding pre-charge signal line PC0~n-1, and the source terminal is electrically connected to the local common source line LCS, and the terminal is connected to the corresponding terminal. The part element lines LBL0~n-1 are electrically connected.

In the precharge range PCA, in the case of the precharge state, when the precharge signal lines PC0~n-1 are controlled to be high, the corresponding local bit lines LBL0~n-1 are connected to the local common bit line LCS. And supplying the precharge voltage VCS to the corresponding local bit line LBL0~n-1. Further, in the precharge range PCA, when the segmentation is activated, only the precharge signal lines PC0 to n-1 corresponding to the selected one of the local bit lines LBL0 to n-1 are added. The control is low, and only the selected local bit lines LBL0~n-1 are separated from the common source line LCS.

In the local common source supply range LCSA, there are a transistor Tr6 (for example, nMOSFET) corresponding to the segment selection signal line SEL, and an electric crystal corresponding to the inverted segment selection signal line SELB. Body Tr5 (eg, nMOSFET). The gate electrode of the transistor Tr6 is electrically connected to the segment selection signal line SEL, and the source terminal is electrically connected to the precharge voltage line VCS, and the gate terminal is electrically connected to the local common source line LCS. connection. The transistor Tr5-based gate electrode is electrically connected to the inverted segment selection signal line SELB, and the source terminal is electrically connected to the local common source line LCS, and the 汲 terminal is connected to the wide-area common source line. The GCS is electrically connected.

In the local common source supply range LCSA, the precharge state, and the segmentation are in the non-selected state, the segment selection signal line SEL is controlled to be low, and the inverted segment selection signal line SELB is controlled to be high. The local common source line LCS is controlled to be a precharge voltage VCS, and the local common source line LCS is separated from the wide area common source line GCS. Further, in the local common source supply range LCSA, when the segmentation is activated, the segment selection signal line SEL is controlled to be high, and the inverted segment selection signal line SELB is controlled to be low, local. The common source line LCS is disconnected from the precharge voltage VCS and connected to the wide area common source line GCS.

In the sub-pad 20d which is selected and activated, the local common source line LCS is disconnected from the precharge voltage VCS and connected to the wide-area common source line GCS. In addition, one character line WL0~n-1 and one local bit line LBL0~n-1 are selected, and the selected local bit line LBL0~n-1 is disconnected from the local common source line LCS. And connected to the wide-area bit line GBL, and the remaining non-selected local bit lines LBL0~n-1 are connected to the local common source line LCS. Connected to the election Selecting the word line WL0~n-1 and selecting the source terminal of the memory cell Tr3 of the memory cell MC of the local bit line LBL0~n-1 through the local common source line LCS and the wide-area common source The line GCS is connected to the sense amplifier SA and connected to the sense amplifier SA via the local bit line LBL0~n-1 and the wide area bit line GBL connected to the impedance change element M of the memory cell MC. . On the other hand, the source terminal of the transistor Tr3 connected to the remaining n-1 memory cells MC of the selected word line WL0~n-1 and the non-selected local bit line LBL0~n-1 is also The non-selected local bit lines LBL0 to n-1 connected to the impedance varying element M of the memory cell MC are simultaneously connected to the local common source line LCS, and even if the transistor Tr3 of the memory cell MC is turned on, Since the voltage is not applied to the impedance varying element M, and no current flows, even if the local common source line LCS is used as the power supply voltage VDD or the ground voltage VSS, the memory information is not destroyed.

Next, the operation of the sub-pad of the semiconductor device according to the fourth embodiment of the present invention will be described using the drawings. Fig. 19 is a sequence diagram showing an operation waveform of each signal line of the sub-pad of the semiconductor device according to the fourth embodiment of the present invention. However, Fig. 19 shows an operation waveform of each signal in the case where the word line WL0 and the local bit line LBL0 are selected in the selected segment. In addition, in (A) of the left half of Fig. 19, 0 data read ~ rewrite ~ 1 data write action is displayed, and in the right half (B), display 1 data read ~ rewrite ~ 0 data write action.

When referring to the left half of (A) of Figure 19, the precharge period The inversion reversal segment selection signal line SELB and the precharge control signal line PC0 are controlled to be the boost voltage VPP, and the segment selection signal line SEL is connected to the control signal line SW0, and the word line WL0 is simultaneously controlled to be grounded. The voltage VSS local bit line LBL0 and the local common source line LCS are controlled to be the precharge voltage VCS, and the wide field bit line GBL and the wide area common source line GCS are also controlled to the precharge voltage VCS.

After the precharge period, when the cell selection period is reached, the inverted segment selection signal line SELB and the precharge control signal line PC0 are controlled to the ground voltage VSS, and the segment selection signal line SEL is connected to the control signal line SW0 and the character. The line WL0 is controlled to be the boost voltage VPP, and the local bit line LBL0 is connected to the wide-area bit line GBL, and the local common source line LCS is connected to the wide-area common source line GCS. In the cell selection period, the wide-area bit line GBL and the local bit line LBL0 are set first before the beginning of the sensing amplification period. The read voltage Vread is maintained, and the read current Iread0 flows in the memory cell.

After the cell selection period, when the sensing amplification period is reached, the read current Iread0 is smaller than the reference current Iref due to the small value corresponding to the high impedance state, and the current difference is sensed and amplified via the sense amplifier SA. . In the meantime, the wide-area common source line GCS and the local common source line LCS are maintained as the pre-charge voltage VCS, and the wide-area bit line GBL and the local bit line LBL0 are slightly maintained as the read voltage Vread. .

When the re-writing period is reached after the sensing amplification period, the writing circuit (not shown) provided in the sense amplifier SA corresponds to the reading. The 0-data and the local bit line GBL and the local bit line LBL0 are controlled to the ground voltage VSS, and the wide-area common source line GCS and the local common source line LCS are controlled to the power supply voltage VDD, and then 0 data is written. . At this time, the voltage difference between the power supply voltage VDD and the ground voltage VSS is preferably larger than the absolute value of the logic 0 write voltage Vreset, compared to the necessity between the precharge voltage VCS and the ground voltage VSS. In the first embodiment (see FIG. 11(A)), the voltage difference is larger than the absolute value of the logical zero write voltage Vreset (see FIG. 11(A)), and the operating voltage is lowered, which has the advantage of low power consumption.

After the rewriting period, when the inversion write period is reached, the wide area bit line GBL and the local bit line LBL0 are controlled to the power supply voltage VDD corresponding to the 1 data, and the wide area common source line GCS and the local common are used. When the source line LCS is controlled to the ground voltage VSS, the 1 data is inverted.

After the reverse writing period, when the selection release period is reached, the word line WL0, the connection control signal line SW0, and the segment selection signal line SEL are controlled to be the ground voltage VSS.

After the selection release period, when the precharge period is reached, the inverted segment selection signal signal SELB and the precharge control signal line PC0 are controlled to be the boost voltage VPP, and the local common source line LCS and the local bit line LBL0 are applied. Control is the precharge voltage VCS. The wide-area common source line GCS and the wide-area bit line GBL are controlled to be pre-charge voltage VCS.

Next, when referring to the right half of (B) of Fig. 19, the operation from the precharge period to the cell selection period is the same as that of Fig. 19(A). First in the beginning of the sensing amplification period, the wide-area bit line GBL and local bits The line LBL0 is set. The read voltage Vread is held, and the read current Iread1 flows in the memory cell MC.

After the cell selection period, when the sensing amplification period is reached, the read current Iread1 is larger than the reference current Iref due to the large value corresponding to the low impedance state, and the current difference is sensed and amplified via the sense amplifier SA. . In the meantime, the wide-area common source line GCS and the local common source line LCS are maintained as the pre-charge voltage VCS, and the wide-area bit line GBL and the local bit line LBL0 are slightly maintained as Vread.

After the sensing amplification period, when the re-writing period is reached, the write circuit (not shown) provided in the sense amplifier SA corresponds to the read data 1 and the wide-bit bit line GBL and the local bit line LBL0. The voltage is controlled to the power supply voltage VDD, and the wide-area common source line GCS and the local common source line LCS are controlled to the power-on voltage VSS, and one data is written. At this time, the voltage difference between the power supply voltage VDD and the ground voltage VSS is preferably as large as the absolute value of the logic 1 write voltage Vset, compared to the necessity between the power supply voltage VDD and the precharge voltage VCS. In the first embodiment (see FIG. 11(B)), the voltage difference is larger than the absolute value of the logic 1 write voltage Vset, and the operating voltage is lowered, which has the advantage of low power consumption.

After the rewriting period, when the inversion write period is reached, the wide area bit line GBL and the local bit line LBL0 are controlled to the ground voltage VSS corresponding to the 0 data, and the wide area common source line GCS and the local common are used. When the source line LCS is controlled to the power supply voltage VDD, the 0 data is inverted.

After the reverse write period, from the selection release period to the precharge The operation during the electrical period is the same as that of Fig. 19(A).

According to the fourth embodiment, the same effect as in the first embodiment can be obtained, and the power consumption reduced by the low voltage is added, and only the sub-pads of the segment in which the wide-area common source line GCS is selected are connected. In the case of the local common source line LCS in 20d, the parasitic capacitance of the wide-area common source line GCS can be reduced, and even if the voltage is varied during writing, the increase in the current consumption can be suppressed.

[Embodiment 5]

The semiconductor device according to the fifth embodiment of the present invention will be described with reference to the drawings. Fig. 20 is a plan view schematically showing the configuration of a sub-pad of the semiconductor device according to the fifth embodiment of the present invention. Fig. 21 is a circuit diagram schematically showing the configuration of a sub-pad of the semiconductor device according to the fifth embodiment of the present invention. Fig. 22 is an enlarged plan view showing a range R of Fig. 20 showing a configuration of a sub-pad of the semiconductor device according to the fifth embodiment of the present invention. Fig. 23 is a cross-sectional view schematically showing the configuration of a portion of a sub-pad of the semiconductor device according to the fifth embodiment of the present invention, taken along line X-X' of Fig. 22.

Embodiment 5 is a modification of the fourth embodiment. In the switching range SWA, a transistor Tr7 (for example, a vertical nMOSFET) controllable via the segment selection signal line SEL is added as a relatively large controllable parasitic capacitance. The connection between the n+ diffusion layer 44b of the crystal Tr7 and the wide-area bit line (GBLi-1 to i+2) (see FIGS. 20 to 23). The transistor Tr7 system gate electrode is electrically connected to the segment selection signal line SEL. Connecting, and the source terminal is electrically connected to a source terminal corresponding to each of the switching transistors Tr2 (for example, nMOSFET) connected to the control signal lines SW0 to n-1, and the 汲 terminal is The wide-area bit line GBLi is electrically connected (refer to FIG. 21).

Further, since the sub-pads 20d are individually selected, it is necessary to separate the connected precharge voltage VCS between the sub-pads 20d. Therefore, electrical separation of the n+ diffusion layers 44a, 44b is necessary. Therefore, between the subpads 20d in which the extension of the word lines WL0 to m-1 exist, the continuity of the processing of the memory cells MC is considered, and the dummy transistor DTr (which may also be a memory cell) is disposed ( Refer to Figure 22). Similarly, for the switching range SWA of the extending direction of the word line WL0~m-1, between the pre-charging range PCA and the local common source supply range LCSA, the virtual transistor DTr is also disposed, and the adjacent n+ is electrically separated. Diffusion layers 44a, 44b. In addition, a separation range is also set for the lateral direction.

The other configuration is the same as that of the fourth embodiment.

According to the fifth embodiment, the same effects as those of the fourth embodiment are obtained, and the n+ diffusion layer 44b and the wide-area bit line (GBLi-1 to i+2) are provided via the segment selection signal line SEL. In the controllable transistor Tr7, the sub-pad 20d other than the selected segment controls the segment selection signal line SEL to be low, and the wide-area bit line (GBLi-1~i+2) is reduced. The parasitic capacitance can suppress an increase in current consumption even when the voltage is varied during writing.

Further, according to the fifth embodiment, between the n+ diffusion layer 44b and the wide-area bit line (GBLi-1 to i+2), the transistor Tr7 is provided. The contact plug of the n+ diffusion layer 44b is disposed in the switching range SWA, and the area of the sub-pad 20d can be reduced. That is, the contact plug layout area of the n+ diffusion layer 44b is larger than that of the vertical nMOSFET, and the vertical nMOSFET is used for the transistor Tr7, and the layout area can be reduced.

However, in the case where the drawing reference numerals are attached to the present application, these are specifically intended to be understood, and are not intended to be limited to the illustrated embodiments.

However, within the framework of the full disclosure of the present invention (including the scope and drawings of the patent application), according to the basic technical idea, the embodiment and the embodiment may be modified. Adjustment. In addition, within the framework of the full disclosure of the present invention, various combinations of elements (including various elements of each application, each embodiment, and various elements of the embodiments, elements of each drawing, etc.) can be made. select. That is, the present invention naturally includes the full disclosure of the scope of the patent application and the drawings, and various modifications and corrections that can be made with the technical idea of the company.

(attachment)

In one aspect of the present invention, in a semiconductor device, there are: a wide-area bit line, a common source line, and a plurality of local bit lines, and a plurality of words which are three-dimensionally intersected with the plurality of partial bit lines a plurality of lines, and are disposed between the local bit line of the plurality of complex lines and the intersection of the plurality of word lines, and electrically connected between the corresponding local bit line and the common source line, and The plural selected by the corresponding word line a memory cell, and a first transistor electrically connected between the common source line and the plurality of local bit lines, and electrically connected to the wide-area bit line and the foregoing plurality a second transistor having a plurality of local bit lines; and a control circuit for controlling each of the plurality of first transistors and the plurality of second transistors, wherein the control circuit is corresponding to a partial bit of the complex number The second transistor of one local bit line of the element line is in an on state, and the first transistor corresponding to the one of the local bit lines is in a non-conduction state, and is correspondingly included in the foregoing The second transistor of the other local bit line of the plurality of local bit lines is in a non-conduction state, and the first transistor corresponding to the other local bit line is turned on.

In the semiconductor device of the present invention, the multilayer wiring structure including the first wiring layer, the second wiring layer, and the third wiring layer disposed between the first wiring layer and the second wiring layer is provided. The wide-area bit line is disposed in the first interconnect layer, and the common source line is disposed in the second interconnect layer, and the plurality of local bit lines are disposed in the third interconnect layer.

In the semiconductor device of the present invention, the plurality of memory cells are disposed between the second wiring layer and the third wiring layer.

In the semiconductor device of the present invention, the memory cell is configured to electrically connect the third transistor and the memory element in series, and the third transistor system is formed by a gate electrode and a corresponding word line. Electrical connection.

In the semiconductor device of the present invention, the memory element is an impedance change element whose impedance value changes.

In the semiconductor device of the present invention, the second wiring layer is an n+ diffusion layer formed on the p-type well.

In the semiconductor device of the present invention, the second wiring layer has a metal layer formed between the p-type well and the n+ diffusion layer.

In the semiconductor device of the present invention, the common source line is supplied with a precharge voltage from a specific range other than a range in which the sub-pads of the plurality of memory cells are arranged.

In the semiconductor device of the present invention, the common source line is provided with a plurality of memory cells, and a fourth transistor of a specific range disposed within a range of the sub-pad is supplied to the precharge voltage. The fourth electro-crystalline system supplies a boosted voltage to the gate electrode.

In the above-described semiconductor device of the present invention, the common source line is provided with a plurality of memory cells, and a fifth transistor arranged in a specific range other than the range of the sub-pad is supplied to the precharge voltage. The control circuit controls the fifth transistor.

The semiconductor device of the present invention includes a wide-area common source line disposed in the first wiring layer, and a sixth electric source electrically connected between the common source line and the wide-area common source line In the crystal, the control circuit controls the sixth transistor.

In the foregoing semiconductor device of the present invention, the aforementioned precharging The voltage is set to the voltage between the supply voltage and the ground voltage.

In the semiconductor device of the present invention, the local bit line selected is supplied with a power supply voltage when the logic 0 data is written, and the ground voltage is supplied when the logic 1 data is written.

1‧‧‧Semiconductor device

10‧‧‧Control circuit

11‧‧‧ address input circuit

12‧‧‧ address latch circuit

13‧‧‧Command input circuit

14‧‧‧Instruction Decoding Circuit

15‧‧‧ mode register

16‧‧‧ line decoder

17‧‧‧ column decoder

20‧‧‧Memory cell array

21‧‧‧clock input circuit

22‧‧‧DLL circuit

23‧‧‧ FIFO circuit

24‧‧‧Output and input circuit

25‧‧‧Internal power generation circuit

ADD‧‧‧ address signal

BANK‧‧‧ memory group

CK, /CK‧‧‧ external clock signal

DQ‧‧‧Reading information

ICLK‧‧‧ internal clock signal

LCLK‧‧‧ internal clock signal

MRS‧‧‧ mode information

VCS‧‧‧Precharge voltage (line)

VDD‧‧‧Power supply voltage

VPP‧‧‧ boost voltage (line)

VSS‧‧‧ Grounding voltage

/RESET‧‧‧Reset signal

Claims (13)

A semiconductor device characterized by comprising: a wide-area bit line, a common source line, and a plurality of local bit lines, and a plurality of word lines intersecting the plurality of the local bit lines, and configured And electrically connecting the corresponding local bit line and the common source line to the vicinity of the intersection of the plurality of local bit lines and the complex word line, and corresponding to the character string a plurality of memory cells selected by the line, and a first transistor electrically connected between the plurality of common source lines and the plurality of local bit lines, and electrically connected to each of the foregoing wide areas a second transistor having a plurality of bit lines and a plurality of local bit lines; and a control circuit for controlling each of the plurality of first transistors and the plurality of second transistors, wherein the control circuit includes The second transistor of the one local bit line of the plurality of local bit lines is in an on state, and the first transistor corresponding to the one of the local bit lines is in a non-conduction state , The second transistor corresponding to the other local bit lines contained in the plurality of local bit line as a non-conductive state, and the other corresponding to the local bit line of the first transistor, a conduction state by. A semiconductor device according to claim 1, wherein A multilayer wiring structure including a first wiring layer, a second wiring layer, and a third wiring layer disposed between the first wiring layer and the second wiring layer, and the wide-area bit line system is disposed In the first wiring layer, the common source line is disposed in the second wiring layer, and the plurality of local bit lines are disposed in the third wiring layer. The semiconductor device according to claim 2, wherein the plurality of memory cells are disposed between the second wiring layer and the third wiring layer. The semiconductor device according to claim 3, wherein the memory cell is configured to electrically connect the third transistor and the memory device in series, and the third transistor system is composed of a gate electrode and a corresponding electrode. The aforementioned word lines are electrically connected. The semiconductor device according to claim 4, wherein the memory element is an impedance change element in which an impedance value changes. The semiconductor device according to claim 2, wherein the second wiring layer is an n+ diffusion layer formed on a p-type well. The semiconductor device according to claim 6, wherein the second wiring layer has a metal layer formed between the p-type well and the n+ diffusion layer. A semiconductor device according to claim 2, wherein In the common source line, a precharge voltage is supplied from a specific range other than the range in which the sub-pads of the plurality of memory cells are arranged. The semiconductor device according to claim 2, wherein the common source line is provided by a fourth transistor in a specific range in a range in which a plurality of sub-pads of the memory cell are disposed. The precharge voltage is supplied, and the fourth transistor system supplies a boosted voltage to the gate electrode. The semiconductor device according to the second aspect of the invention, wherein the common source line is provided by a fifth transistor arranged in a specific range other than a range of the sub-pads of the plurality of memory cells. The precharge voltage is supplied, and the control circuit controls the fifth transistor. The semiconductor device according to claim 9, comprising a wide-area common source line disposed in the first wiring layer, and electrically connected to the common source line and the wide-area common source line In the sixth transistor, the control circuit controls the sixth transistor. The semiconductor device according to claim 8 or 9, wherein the precharge voltage is set to a voltage between a power source voltage and a ground voltage. The semiconductor device according to claim 1, wherein the selected local bit line is supplied with a power supply voltage when the logic 0 data is written, and when the logic 1 data is written, The ground voltage is supplied.