TW201505178A - Semiconductor device and methods for forming the same - Google Patents

Abstract

A semiconductor device including a substrate having an active region is disclosed. A field plate region and a bulk region are in the active region, wherein the bulk region is at a first side of the field plate region. At least one trench gate structure is disposed in the substrate corresponding to the bulk region. At least one source doped region is in the substrate corresponding to the bulk region, wherein the source doped region surrounds the trench gate structure. A drain doped region is in the substrate at a second side opposite to the first side of the field plate region, wherein an extending direction of length of the trench gate structure is perpendicular to that of the drain doped region as viewed from a top view perspective.

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a trench gate and a method of fabricating the same.

The high-voltage component technology is applied to a high-voltage and high-power integrated circuit. In order to achieve high withstand voltage and high current, the flow of the drive current develops from a planar direction to a vertical direction. At present, a metal oxide semiconductor field effect transistor (MOSFET) having a trench gate is developed, which can effectively reduce the on-resistance and has a large current handling capability.

Figure 1 is a schematic plan view showing a conventional MOSFET with a trench gate. The metal oxide semiconductor field effect transistor includes a substrate 500, a gate doping region 510 located in the substrate 500, a trench gate structure 520, and a source doping region 530. The source doping regions 530 are located on both sides of the trench gate structure 520, and the source doping regions 530 and the trench gate structures 520 are connected to each other. The source doped region 530 and the trench gate structure 520 have the same length, and the trench gate structure 520 has a depth greater than the depth of the source doped region 530. The direction in which the lengths of the source doping region 530 and the trench gate structure 520 extend is parallel to the extending direction of the length of the drain doping region 510. The driving current of the metal oxide semiconductor field effect transistor flows from the drain doping region 510 toward the source doping region 530 and the trench gate structure 520, and along the sidewall of the trench gate structure 520. The source is doped to the source doping region 510, so that the gate channel width w of the MOSFET is the length of the trench gate structure 520 as viewed from above.

At a fixed gate channel length, the magnitude of the drive current is proportional to the width of the gate channel described above. However, if the gate channel width is increased, the length of the trench gate structure 520 is increased, thereby increasing the size of the semiconductor device.

Therefore, it is necessary to find a novel semiconductor device having a trench gate and a method of fabricating the same that can solve or ameliorate the above problems.

Embodiments of the present invention provide a semiconductor device including a substrate having an active region and a field region and a substrate region in the active region, wherein the substrate region is located on a first side of the field plate region. At least one trench gate structure is located within the substrate of the base region. At least one source doped region is located within the substrate of the base region, wherein the source doped region surrounds the trench gate structure. a drain doped region is located in the substrate of a second side of the field plate region, wherein the second side is opposite to the first side, and wherein the length of the trench gate structure extends from a top view direction An extension direction perpendicular to the length of the drain doping region.

Embodiments of the present invention provide a method of fabricating a semiconductor device, including providing a substrate having an active region and a field region and a substrate region in the active region, wherein the substrate region is located on a first side of the field plate region. At least one trench gate structure and at least one source doped region are formed in the substrate of the base region, wherein the source doped region surrounds the trench gate structure. a second in the field area Forming a drain doped region in the substrate, wherein the second side is opposite to the first side, and wherein the length of the trench gate structure extends perpendicular to the drain doping region from a top view direction The length of the extension direction.

10‧‧‧active area

20‧‧‧Field area

30‧‧‧basal area

50‧‧‧ drive current

100, 500‧‧‧ substrate

110‧‧‧ buried oxide layer

120‧‧‧矽

200, 520‧‧‧ trench gate structure

210‧‧‧ trench

220‧‧‧ dielectric layer

230‧‧‧ gate electrode layer

240‧‧ ‧ field oxide layer

250‧‧ ‧ field plate electrode

300, 530‧‧‧ source doped area

400, 510‧‧‧汲polar doped area

W, w‧‧‧ gate channel width

Figure 1 is a schematic plan view showing a conventional MOSFET with a trench gate.

2A and 3A are plan views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention.

Fig. 2B is a schematic cross-sectional view taken along line 2B-2B' in Fig. 2A.

Fig. 2C is a schematic cross-sectional view taken along line 2C-2C' in Fig. 2A.

Fig. 3B is a schematic cross-sectional view taken along line 3B-3B' in Fig. 3A.

Fig. 3C is a schematic cross-sectional view taken along line 3C-3C' in Fig. 3A.

Hereinafter, the fabrication and use of the semiconductor device and the method of manufacturing the same according to embodiments of the present invention will be described. However, it will be readily understood that the embodiments of the present invention are susceptible to many specific embodiments of the invention and can The specific embodiments disclosed are merely illustrative of the invention, and are not intended to limit the scope of the invention. In the drawings and the description of the embodiments of the present invention, the same reference numerals are used to refer to the same or similar parts.

The following description of the embodiments of the present invention with the 3A to 3C drawings A semiconductor device of a trench gate, wherein FIG. 3A is a schematic plan view showing a semiconductor device having a trench gate according to an embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line 3A A schematic cross-sectional view of line 3B-3B', and FIG. 3C is a cross-sectional view taken along line 3C-3C' of FIG. 3A.

A semiconductor device having a trench gate includes: a substrate 100, At least one trench gate structure 200, at least one source doped region 300, and a drain doped region 400. The substrate 100 has an active region 10 and a field plate region 20 located in the active region 10 and a base region 30, wherein the substrate region 30 is located on a first side of the field plate region 20. In this embodiment, the substrate 100 may be a silicon on insulator (SOI) substrate, and the substrate 100 includes a buried oxide (BOX) 110 and a germanium layer 120 thereon. As shown in Figures 3B and 3C. In other embodiments, the substrate 100 can be a single crystal germanium substrate, an epitaxial germanium substrate, a germanium substrate, a compound semiconductor substrate, or other conventional semiconductor substrates. In the present embodiment, the conductivity type of the substrate 100 is n-type, but is not limited thereto. In other embodiments, the conductivity type of the substrate 100 may also be p-type, and its conductivity type may be selected according to design requirements.

At least one trench gate structure 200 is located on the substrate of the base region 30 100, and includes a dielectric layer 220 and a gate electrode layer 230. The dielectric layer 220 is compliantly disposed within a trench 210 in the substrate 100, and the gate electrode layer 230 is disposed on the dielectric layer 220 and fills the trench 210 as shown in FIGS. 3B and 3C. Dielectric layer 220 can include an oxide, a nitride, an oxynitride, combinations thereof, or other suitable gate dielectric materials. The gate electrode layer 230 may comprise germanium, polysilicon or other conductive material. In this embodiment, the trench gate structure 200 is a long strip. The cylinder, and the bottom surface of the elongated cylinder has a rounded rectangular shape, as shown in Fig. 3A. In other embodiments, the bottom surface of the elongated column of the trench gate structure 200 may have an elliptical, rectangular or polygonal shape (not shown).

The source doping region 300 is located in the substrate 100 of the base region 30, wherein The source doped region 300 surrounds the trench gate structure 200 as shown in FIG. 3A. In the present embodiment, the conductivity type of the source doping region 300 is n-type, but is not limited thereto. In other embodiments, the conductivity type of the source doping region 300 may also be p-type, and the conductivity type may be selected according to design requirements. For example, the source doping region 300 may include a p-type dopant (eg, boron). Or boron fluoride) or an n-type dopant (for example, phosphorus or arsenic). In the present embodiment, the edge of the source doping region 300 has the same shape as the edge of the trench gate structure 200 as viewed from the top direction, as shown in FIG. 3A. In other embodiments, the edge of the source doped region 300 and the edge of the trench gate structure 200 may have different shapes (not shown).

In an embodiment, a semiconductor device having a trench gate can A plurality of trench gate structures 200 and corresponding complex source doped regions 300 are included, and the trench gate structures 200 are spaced apart from each other. For example, a semiconductor device having a trench gate includes two trench gate structures 200 and two corresponding source doped regions 300 spaced apart from each other, and the trench gate structures 200 may have the same as each other. The appearance is as shown in Figure 3A. In another embodiment, the two trench gate structures 200 can have different shapes (not shown) from each other. In other embodiments, two or more trench gate structures 200 may have the same or different outer shape of the trench gate structure 200, and adjacent trench gate structures 200 may have Same or different spacing. It can be understood that the number and appearance of the trench gate structure 200 and the corresponding source doping region 300 in FIGS. 3A to 3C are only examples. The description is not limited thereto, and the actual number and appearance of the trench gate structure 200 and the corresponding source doping region 300 depend on design requirements.

The drain doping region 400 is located on a substrate on a second side of the field plate region 20 100, wherein the second side is opposite to the first side, that is, the drain doping region 400 and the base region 30 having the trench gate structure 200 and the source doping region 300 are respectively located on opposite sides of the field plate region 20 . Each trench gate structure 200 has the same spacing from the drain doped region 400. In the present embodiment, the conductivity type of the drain doping region 400 is p-type, but is not limited thereto. In other embodiments, the conductivity type of the drain doping region 400 may also be n-type, and the conductivity type may be selected according to design requirements. For example, the gate doping region 400 may include a p-type dopant (eg, boron). Or boron fluoride) or an n-type dopant (for example, phosphorus or arsenic). In the present embodiment, the extending direction of the length of the trench gate structure 200 (i.e., the X direction) is substantially perpendicular to the extending direction of the length of the gate doping region 400 (i.e., Y) as viewed from the top direction. Direction), as shown in Figure 3A.

In this embodiment, the semiconductor device having the trench gate is more A field oxide layer 240 (eg, a local oxidation of silicon (LOCOS) structure) and a field plate electrode 250 are included. The field oxide layer 240 is located in the substrate 100 in the field plate region 20 and protrudes from the substrate 100. The field plate electrode 250 is disposed on the field oxide layer 240 and extends onto the substrate 100 as shown in FIGS. 3A and 3B.

Driving current 50 of a semiconductor device having a trench gate from 汲 The pole doped region 400 passes under the field oxide layer 240 and flows up along the sidewall of the at least one trench gate structure 200 to the corresponding at least one source doped region 300 (as indicated by the arrow in FIG. 3B). In this embodiment, a semiconductor package having a trench gate The width W of the gate channel is 1/2 of the bottom surface of the elongated cylinder of the trench gate structure 200, as shown in FIG. 3A.

Conventional metal oxide semiconductor field effect with trench gate The transistor has only one trench gate structure 500, and the length of the trench gate structure 500 extends parallel to the direction in which the length of the gate doped region 510 extends, as shown in FIG. The gate width w of the MOSFET having a trench gate is the length of the trench gate structure 500. If the gate width w is increased, the semiconductor device is proportionally increased. area.

Compared to conventional metal oxide semiconductors with trench gates The semiconductor device of the embodiment of the present invention has a single trench gate structure 200 or a plurality of trench gate structures 200 spaced apart from each other, and the length of the trench gate structure 200 extends in a general direction. The width of the gate channel perpendicular to the length of the drain doping region 400, the gate width W of the semiconductor device is 1/2 circumference or a plurality of grooves of the bottom surface of the elongated column of the single trench gate structure 200. The sum of the 1/2 circumferences of the bottom surface of the elongated cylinder of the slotted gate structure 200.

It can be seen that the direction of extension is parallel to the thickness of the drain The trench gate structure of the impurity region, in a fixed device area, the trench gate structure is configured such that the extending direction of the length thereof is substantially perpendicular to the extending direction of the length of the gate doping region, in the semiconductor device The plurality of trench gate structures arranged at intervals can be formed such that the width of the gate channel is increased to be 1/2 of the circumference of the bottom surface of the elongated column of the plurality of trench gate structures, thereby effectively utilizing the device area , thereby increasing the drive current.

According to an embodiment of the invention, when the length of the trench gate structure The extending direction is substantially perpendicular to the extending direction of the length of the drain doped region, and the semiconductor When the width W of the gate channel of the body device is 1/2 of the length of the bottom surface of the elongated column of the single trench gate structure, the gate area of the trench gate structure can be greatly improved by increasing the device area by a small portion. Channel width, which in turn increases drive current and improves on-resistance. In addition, since a plurality of trench gate structures spaced apart from each other can be formed in the semiconductor device, the driving current can be further improved and the on-resistance can be improved while increasing the device area, and the device area can be effectively increased. effectiveness. Furthermore, the trench gate structure according to the embodiment of the present invention can reduce the size of the gate structure and increase the use efficiency of the device area under the same required driving current, thereby reducing the size of the semiconductor device.

The following describes the implementation of the present invention in conjunction with FIGS. 2A to 2C and 3A to 3C. Example of a method of fabricating a semiconductor device having a trench gate, wherein FIGS. 2A and 3A are schematic plan views showing a method of fabricating a semiconductor device having a trench gate according to an embodiment of the present invention, and wherein 2B is a cross-sectional view taken along line 2B-2B' in FIG. 2A, and FIG. 2C is a cross-sectional view taken along line 2C-2C' in FIG. 2A, FIG. 3B A cross-sectional view along section line 3B-3B' in Fig. 3A is depicted, and a 3C diagram is a cross-sectional view along section line 3C-3C' in Fig. 3A.

Referring to FIGS. 2A to 2C, a substrate 100 having a main body is provided. The movable area 10 and a field area 20 and a base area 30 located in the active area 10, wherein the base area 30 is located on a first side of the field plate area 20. In this embodiment, the substrate 100 may be an insulating layer overlying the germanium substrate, and the substrate 100 includes a buried oxide layer 110 and a germanium layer 120 thereon, as shown in FIGS. 2B and 2C. In other embodiments, the substrate 100 can be a single crystal germanium substrate, an epitaxial germanium substrate, a germanium substrate, a compound semiconductor. Substrate or other conventional semiconductor substrate. In the present embodiment, the conductivity type of the substrate 100 is n-type, but is not limited thereto. In other embodiments, the conductivity type of the substrate 100 may also be p-type, and its conductivity type may be selected according to design requirements.

Formed on the substrate 100 through a deposition process and a photolithography process A patterned hard mask layer (not shown), such as a tantalum nitride layer, is patterned to expose the substrate 100 of the field plate region 20. Next, an oxidative growth process is performed to form a field oxide layer 240 (eg, a tantalum partial oxidation structure) in the substrate 100 of the field plate region 20, and protrudes from the substrate 100.

Then, after removing the hard mask layer, the deposition process can be And a lithography process, another patterned hard mask layer (not shown) is formed on the substrate 100 to expose the substrate 100 on the first side of the field plate region 20. Next, an etching process (eg, a dry etch process, a wet etch process, a plasma etch process, a reactive ion etch process, or other conventional etch process) is performed on the first side of the field plate region 20 (ie, the base region 30). At least one trench 210 is formed in the substrate 100. For example, two trenches 210 are formed within the substrate 100. Then, after removing the hard mask layer, the deposition process can be performed (for example, atomic layer deposition (ALD) process, chemical vapor deposition (CVD) process, physical vapor deposition (physical vapor deposition). , PVD) process, thermal oxidation process or other suitable process), a dielectric material is conformally deposited in each trench 210 to form a dielectric layer 220 as a gate dielectric layer. Dielectric layer 220 can include an oxide, a nitride, an oxynitride, combinations thereof, or other suitable gate dielectric materials.

Then, through a deposition process (for example, a physical vapor deposition process, Chemical vapor deposition process, atomic layer deposition process, sputtering process or coating process), Depositing a conductive material on each of the dielectric layers 220 and filling the corresponding trenches 210 to form the gate electrode layer 230, thereby forming two trench gate structures 200 in the substrate 100 of the base region 30, As shown in Figures 2B and 2C. Gate electrode layer 230 can include germanium, polysilicon or other conductive materials. Alternatively, a field plate electrode 250 may be formed on the field oxide layer 240 through the deposition process and extended onto the substrate 100 as shown in FIGS. 2A and 2B.

In this embodiment, the trench gate structure 200 is a long strip. The body, and the bottom surface of the elongated column has a rounded rectangular shape, as shown in Fig. 2A. In other embodiments, the bottom surface of the elongated column of the trench gate structure 200 may have an elliptical, rectangular or polygonal shape (not shown).

Semiconductor package with trench gate according to an embodiment of the invention The set may include a plurality of trench gate structures 200 that are spaced apart from one another. For example, a semiconductor device having a trench gate includes two trench gate structures 200 spaced apart from each other, and the trench gate structures 200 may have the same shape as each other, as shown in FIG. 2A. . In another embodiment, the two trench gate structures 200 can have different shapes (not shown) from each other. In other embodiments, two or more trench gate structures 200 may have the same or different outer shape of the trench gate structure 200, and adjacent trench gate structures 200 may have Same or different spacing. It can be understood that the number and shape of the trench gate structure 200 in FIGS. 2A to 2C are merely illustrative and not limited thereto, and the actual number and shape of the trench gate structure 200 depend on design requirements. .

Please refer to Figures 3A to 3C for pass through doping processes (eg, ions) The implantation process) forms a plurality of source doping regions 300 in the substrate 100 of the base region 30, wherein one source doping region 300 corresponds to a trench gate structure. 200, as shown in Figure 3A. In the present embodiment, the conductivity type of the source doping region 300 is n-type, but is not limited thereto. In other embodiments, the conductivity type of the source doping region 300 may also be p-type, and the conductivity type may be selected according to design requirements, for example, through a p-type dopant (eg, boron or boron fluoride), n A dopant (eg, phosphorus or arsenic) and/or combinations thereof are subjected to a doping process. In the present embodiment, the edge of the source doping region 300 has the same shape as the edge of the trench gate structure 200 as viewed from the top direction, as shown in FIG. 3A. In other embodiments, the edge of the source doped region 300 and the edge of the trench gate structure 200 may have different shapes (not shown).

Through the doping process (for example, ion implantation process), in the field plate area A drain doping region 400 is formed in the substrate 100 of a second side of the second side, wherein the second side is opposite to the first side, that is, the drain doping region 400 and the trench gate structure 200 and the source doping The base regions 30 of the zones 300 are located on opposite sides of the field plate region 20, respectively. In the present embodiment, the conductivity type of the drain doping region 400 is p-type, but is not limited thereto. In other embodiments, the conductivity type of the drain doping region 400 may also be n-type, and the conductivity type may be selected according to design requirements, for example, through a p-type dopant (eg, boron or boron fluoride), n A dopant (eg, phosphorus or arsenic) and/or combinations thereof are subjected to a doping process. Each trench gate structure 200 has the same spacing from the drain doped region 400. In the present embodiment, the extending direction of the length of the trench gate structure 200 (i.e., the X direction) is substantially perpendicular to the extending direction of the length of the gate doping region 400 (i.e., Y) as viewed from the top direction. Direction), as shown in Figure 3A.

Driving current 50 of a semiconductor device having a trench gate from 汲 The pole doped region 400 passes under the field oxide layer 240 and flows up along the sidewall of the at least one trench gate structure 200 to the corresponding at least one source doping region 300 (eg, 3B) The arrow of the figure is shown). In the present embodiment, the gate channel width W of the semiconductor device having the trench gate is 1/2 circumference or a plurality of trench gates of the bottom surface of the elongated column of the single trench gate structure 200. The sum of the 1/2 circumferences of the bottom surface of the elongated cylinder of the pole structure 200.

The trench is parallel to the trench of the drain doping region compared to the length extending direction a gate structure in which the trench gate structure is arranged such that the extending direction of the length thereof is substantially perpendicular to the extending direction of the length of the drain doped region, and the semiconductor device can be arranged to be spaced apart from each other The plurality of trench gate structures increase the width of the gate channel to the sum of 1/2 circumference of the bottom surface of the long column of the plurality of trench gate structures, thereby effectively utilizing the device area and thereby increasing the driving current .

According to an embodiment of the invention, when the length of the trench gate structure The extending direction is substantially perpendicular to the extending direction of the length of the drain doping region, and the gate channel width W of the semiconductor device is 1/2 of the bottom surface of the elongated column of the single trench gate structure, which is transparent A small part of the device area is increased, and the width of the gate channel of the trench gate structure is greatly increased, thereby increasing the driving current and improving the on-resistance. In addition, since a plurality of trench gate structures spaced apart from each other can be formed in the semiconductor device, the driving current can be further improved and the on-resistance can be improved while increasing the device area, and the device area can be effectively increased. effectiveness. Furthermore, the trench gate structure according to the embodiment of the present invention can reduce the size of the gate structure and increase the use efficiency of the device area under the same required driving current, thereby reducing the size of the semiconductor device.

The semiconductor device and the method of manufacturing the same according to embodiments of the present invention are applicable Various low voltage, high voltage and high voltage such as laterally diffused metal oxide semiconductor (LDMOS) and N-channel insulated gate bipolar transistor (NIGBT) The component of the voltage.

While the invention has been described above in terms of the preferred embodiments thereof, which are not intended to limit the invention, the invention may be modified and combined with the various embodiments described above without departing from the spirit and scope of the invention. example.

10‧‧‧active area

20‧‧‧Field area

30‧‧‧basal area

100‧‧‧Substrate

200‧‧‧ Trench gate structure

210‧‧‧ trench

220‧‧‧ dielectric layer

230‧‧‧ gate electrode layer

240‧‧ ‧ field oxide layer

250‧‧ ‧ field plate electrode

300‧‧‧ source doped area

400‧‧‧汲polar doped area

W‧‧‧ gate channel width

Claims (20)

A semiconductor device comprising: a substrate having an active region and a field region and a substrate region in the active region, wherein the substrate region is located on a first side of the field plate region; at least one trench gate a structure, located in the substrate of the substrate region; at least one source doped region, located in the substrate of the substrate region, wherein the at least one source doped region surrounds the at least one trench gate structure; a drain doped region in the substrate on a second side of the field plate region, wherein the second side is opposite to the first side, and wherein the at least one trench gate is viewed from a top view direction The length of the pole structure extends in a direction perpendicular to the direction in which the length of the drain doped region extends. The semiconductor device according to claim 1, wherein the at least one trench gate structure is an elongated column, and a bottom surface of the pillar has an elliptical shape, a rounded rectangle, a rectangle or a polygon. Appearance. The semiconductor device of claim 2, wherein the at least one trench gate structure comprises a gate electrode layer, and wherein the gate width of the semiconductor device is 1/2 circumference of the bottom surface. The semiconductor device of claim 1, wherein the semiconductor device comprises a plurality of trench gate structures and corresponding plurality of source doped regions, and the trench gate structures are spaced apart from each other. The semiconductor device of claim 4, wherein the trench gate structures have the same pitch therebetween, and each trench gate structure and the drain doped region have the same spacing. The semiconductor device of claim 4, wherein the trenches are The gate structures have different spacings between each other, and each trench gate structure has the same spacing from the gate doped regions. The semiconductor device of claim 4, wherein the trench gate structures have the same shape. The semiconductor device of claim 4, wherein the trench gate structures have different shapes. The semiconductor device of claim 1, wherein the at least one trench gate structure comprises: a dielectric layer in at least one trench in the substrate; and a gate electrode layer located at the And filling the at least one trench on the dielectric layer. The semiconductor device of claim 1, further comprising: a field oxide layer located in the field plate region; and a field plate electrode on the field oxide layer and extending onto the substrate of the substrate region. A method of fabricating a semiconductor device, comprising: providing a substrate having an active region and a field region and a substrate region in the active region, wherein the substrate region is located on a first side of the field plate region; Forming at least one trench gate structure and at least one source doped region in the substrate of the base region, wherein the at least one source doped region surrounds the at least one trench gate structure; and in the field plate Forming a drain doped region in the substrate on a second side of the region, wherein the second side is opposite to the first side, and wherein the at least one trench gate structure is viewed from a top view direction The extension of the length is perpendicular to the bungee The direction in which the length of the doped region extends. The method of manufacturing a semiconductor device according to claim 11, wherein the at least one trench gate structure is an elongated column, and a bottom surface of the pillar has an elliptical shape, a rounded rectangle, and a rectangular shape. Or a polygon type. The method of fabricating a semiconductor device according to claim 12, wherein the at least one trench gate structure comprises a gate electrode layer, and wherein a gate channel width of the semiconductor device is 1/2 of the bottom surface perimeter. The method of fabricating a semiconductor device according to claim 11, wherein the semiconductor device comprises a plurality of trench gate structures and corresponding complex source doped regions, and the trench gate structures are spaced apart from each other . The method of fabricating a semiconductor device according to claim 14, wherein the trench gate structures have the same pitch between each trench gate structure and the drain doped region. Have the same spacing. The method of fabricating a semiconductor device according to claim 14, wherein the trench gate structures have different pitches between each trench gate structure and the drain doped region. Have the same spacing. The method of fabricating a semiconductor device according to claim 14, wherein the trench gate structures have the same shape. The method of fabricating a semiconductor device according to claim 14, wherein the trench gate structures have different shapes. The method of fabricating a semiconductor device according to claim 11, wherein the forming the at least one trench gate structure comprises: forming at least one trench in the substrate on the first side of the field plate region Forming a dielectric layer in the at least one trench; A gate electrode layer is formed on the dielectric layer to fill the at least one trench. The method of fabricating a semiconductor device according to claim 11, further comprising: forming a field oxide layer in the field plate region; and forming a field plate electrode on the field oxide layer and extending to the substrate region On the substrate.