TW201505088A - 用於混合接合法的半導體晶圓清潔方法、半導體晶圓之混合接合法,以及用於混合接合法的整合系統 - Google Patents
用於混合接合法的半導體晶圓清潔方法、半導體晶圓之混合接合法,以及用於混合接合法的整合系統 Download PDFInfo
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- TW201505088A TW201505088A TW103115772A TW103115772A TW201505088A TW 201505088 A TW201505088 A TW 201505088A TW 103115772 A TW103115772 A TW 103115772A TW 103115772 A TW103115772 A TW 103115772A TW 201505088 A TW201505088 A TW 201505088A
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- semiconductor wafer
- cleaning
- hybrid bonding
- metal
- cavity
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 171
- 238000000034 method Methods 0.000 title claims abstract description 119
- 238000004140 cleaning Methods 0.000 title claims abstract description 76
- 235000012431 wafers Nutrition 0.000 title claims description 154
- 230000008569 process Effects 0.000 claims abstract description 79
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 34
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 34
- 239000001257 hydrogen Substances 0.000 claims abstract description 16
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 16
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 230000004888 barrier function Effects 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 15
- 229910052755 nonmetal Inorganic materials 0.000 claims description 12
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 4
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 claims description 3
- -1 tetramethyl hydroxide Chemical compound 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 238000005304 joining Methods 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- 230000007246 mechanism Effects 0.000 abstract description 5
- 238000006722 reduction reaction Methods 0.000 abstract description 2
- 239000011810 insulating material Substances 0.000 description 20
- 239000000758 substrate Substances 0.000 description 18
- 239000010949 copper Substances 0.000 description 14
- 239000000463 material Substances 0.000 description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010936 titanium Substances 0.000 description 8
- 239000000126 substance Substances 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000012774 insulation material Substances 0.000 description 4
- 238000007517 polishing process Methods 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000005751 Copper oxide Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 229910000431 copper oxide Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 229910016553 CuOx Inorganic materials 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910000420 cerium oxide Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910001392 phosphorus oxide Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- VSAISIQCTGDGPU-UHFFFAOYSA-N tetraphosphorus hexaoxide Chemical compound O1P(O2)OP3OP1OP2O3 VSAISIQCTGDGPU-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67196—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the construction of the transfer chamber
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68707—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a robot blade, or gripped by a gripper for conveyance
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02334—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment in-situ cleaning after layer formation, e.g. removing process residues
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/0361—Physical or chemical etching
- H01L2224/03616—Chemical mechanical polishing [CMP]
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/038—Post-treatment of the bonding area
- H01L2224/0381—Cleaning, e.g. oxide removal step, desmearing
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05547—Structure comprising a core and a coating
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- H01L2224/80053—Bonding environment
- H01L2224/80095—Temperature settings
- H01L2224/80096—Transient conditions
- H01L2224/80097—Heating
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- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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- H01L2224/808—Bonding techniques
- H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
- H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
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- H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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Abstract
本揭露提供一種用於混合接合法(hybrid bonding)的半導體晶圓的清潔方法,包括以下步驟:提供一半導體晶圓,其中該半導體晶圓具有埋設在一絕緣層中的一導電墊與形成在該導電墊上的一金屬氧化物層;對該半導體晶圓之一表面進行一電漿製程;在該電漿製程之後,使用一清潔溶液對該半導體晶圓之該表面進行一清潔製程,其中該金屬氧化物被還原且複數個金屬-氫鍵形成在該導電墊之表面上;以及在真空下,傳輸該半導體晶圓至一接合腔體。
Description
本揭露係有關於一種清潔方法,且特別有關於一種用於混合接合法的半導體晶圓清潔方法。
半導體裝置使用於各種電子應用中,舉例而言,諸如個人電腦、手機、數位相機以及其他電子設備。半導體裝置的製造通常是藉由在半導體基板上依序沉積絕緣或介電層材料、導電層材料以及半導體層材料,接著使用微影製程圖案化所形成的各種材料層,以形成電路組件和零件於此半導體基板之上。通常許多積體電路製作於單一半導體晶圓中,且沿著切割線(scribe line)切割相鄰的積體電路,以切割位在晶圓上的各晶粒。舉例而言,通常各自的晶粒被分別封裝在多種晶片模組(multi-chip modules)或其他類似的封裝結構中。
在半導體業界,不斷降低最小特徵尺寸,如此一來可允許更多的裝置集積於一個特定的區域中,藉此持續改善各種電子裝置(例如電晶體、二極體、電阻、電容等等)的集積密度。在某些應用中,相較於過去的產品,這些尺寸更小的電
子裝置需要利用較少區域及/或較低高度之更小的封裝。
因此,目前已經開始發展新的封裝技術,其中半導體晶粒堆疊於另一個半導體晶粒上,例如封裝體堆疊(package on package,PoP)與系統級封裝(system-in-package,SiP)技術。可藉由將晶粒放置在半導體晶圓上而完成一些三維積體電路堆疊(3DICs)結構。舉例而言,因為在堆疊晶粒之間的內連線結構具有降低的長度,三維積體電路堆疊(3DICs)結構提供較佳的積集密度(integration density)與其他優點,例如較快的速度與較高的帶寬(bandwidth)。然而,三維積體電路堆疊(3DICs)結構仍須面對其他挑戰。
本揭露提供一種用於混合接合法(hybrid bonding)的半導體晶圓的清潔方法,包括以下步驟:提供一半導體晶圓,其中該半導體晶圓具有埋設在一絕緣層中的一導電墊與形成在該導電墊上的一金屬氧化物層;對該半導體晶圓之一表面進行一電漿製程;在該電漿製程之後,使用一清潔溶液對該半導體晶圓之該表面進行一清潔製程,其中該金屬氧化物被還原且複數個金屬-氫鍵形成在該導電墊之表面上;以及在真空下,傳輸該半導體晶圓至一接合腔體。
本揭露另提供一種半導體晶圓之混合接合法,包括以下步驟:提供一第一半導體晶圓與一第二半導體晶圓,其中該第一半導體晶圓與該第二半導體晶圓各自具有一導電墊埋設在一絕緣層中;各自對該第一半導體晶圓之一表面與該第二半導體晶圓之一表面進行一電漿製程;使用一清潔溶液各自
對該第一半導體晶圓之該表面與該第二半導體晶圓之該表面進行一清潔製程;以及接合該第一半導體晶圓至該第二半導體晶圓。
本揭露亦提供用於混合接合法(hybrid bonding)的整合系統(integrated system),包括:一電漿腔體耦合至一傳輸腔體;一清潔腔體耦合至該傳輸腔體;以及一混合接合腔體耦合至該傳輸腔體,其中該混合接合腔體用於接合兩個半導體晶圓,以形成一金屬對金屬的鍵結(metal-to-metal bonding)與一非金屬對非金屬的鍵結(non-metal-to-non-metal bonding)。
10‧‧‧化學機械研磨製程法(CMP)
20‧‧‧電漿製程
30‧‧‧清潔溶液供應器(cleaning solution supplier)
35‧‧‧清潔溶液
100‧‧‧半導體晶圓
102‧‧‧基板
104‧‧‧裝置區域
105‧‧‧基板穿孔
106‧‧‧金屬化結構
108‧‧‧導電線
110‧‧‧導通孔
111‧‧‧開口
112‧‧‧導電墊(導電結構)
113‧‧‧擴散阻障層
114‧‧‧絕緣材料
115‧‧‧金屬氧化物層
130‧‧‧介面
132‧‧‧導電材料
140‧‧‧介面
150‧‧‧半導體晶圓
152‧‧‧導電墊
153‧‧‧擴散阻障層
154‧‧‧絕緣材料
155‧‧‧殘餘物
156‧‧‧導通孔
162‧‧‧導電材料
400‧‧‧整合系統
410‧‧‧電漿腔體
420‧‧‧傳輸腔體
430‧‧‧清潔腔體
440‧‧‧混合接合腔體
第1圖顯示依據本揭露實施例之半導體晶圓的一部分的剖面圖。
第2圖顯示依據本揭露實施例的接合結構的剖面圖。
第3A-3F圖顯示依據本揭露實施例的用於混合接合法的半導體晶圓的清潔方法在各個製程階段的剖面圖。
第4圖顯示依據本揭露實施例用於混合接合法的整合系統(integrated system)。
以下特舉出本揭露之實施例,並配合所附圖式作詳細說明。以下實施例的元件和設計係為了簡化所揭露之發明,並非用以限定本揭露。本揭露於各個實施例中可能使用重複的參考符號及/或用字。這些重複符號或用字係為了簡化與清晰的目的,並非用以限定各個實施例及/或所述結構之間的
關係。此外,說明書中提到在第二製程進行之前實施第一製程可包括第二製程於第一製程之後立即進行第二製程,也可包括有其他製程介於第一製程與第二製程之間的實施例。下述圖形並非依據尺寸繪製,該些圖式僅為了幫助說明。再者,說明書中提及形成第一特徵結構位於第二特徵結構之上,其包括第一特徵結構與第二特徵結構是直接接觸的實施例,另外也包括於第一特徵結構與第二特徵結構之間另外有其他特徵結構的實施例,亦即,第一特徵結構與第二特徵結構並非直接接觸。
為了形成三維積體電路(3DIC),混合接合法(hybrid bonding)是一種用於接合基板的接合製程。混合接合法牽涉到至少兩種鍵結,例如金屬對金屬鍵結(metal-to-metal bonding)與非金屬對非金屬鍵結(nonmetal-to-nonmetal bonding)。
第1圖顯示依據本揭露實施例之半導體晶圓的一部分的剖面圖。一或多個類似於半導體晶圓100的半導體晶圓可接合至半導體晶圓100,以形成三維積體電路(3DIC)。半導體晶圓100包括半導體基板102,其由矽或其半導體材料所組成。基板102可包括位於單晶矽上的氧化矽。也可以使用化合物半導體,例如砷化鎵(GaAs)、磷化銦(InP)、矽/鍺(Si/Ge)或碳化矽(SiC)。基板102可以是絕緣層上覆矽(silicon-on-insulator,SOI))或絕緣層上覆鍺(germanium-on-insulator,GOI)基板。
基板102包括裝置區域104形成在基板102鄰近於上表面的位置。裝置區域104可包括各種裝置元件。裝置元件
形成在基板102中,裝置元件的例子包括電晶體(例如金屬氧化物半導體場效電晶體metal oxide semiconductor field effect transistors,MOSFET)、互補金屬氧化物半導體(complementary metal-oxide semiconductor,CMOS)電晶體、雙極介面電晶體(bipolar junction transistors,BJT)、高壓電晶體(high voltage transistors)、高頻電晶體(high frequency transistors)、P通道及/或N通道場效電晶體(p-channel field effect transistor,PFETs)、二極體及/或其他應用元件。可進行各種製程以形成裝置元件,例如沉積、蝕刻、佈植、微影製程、退火及/或其他合適的製程。在一些實施例中,在前段製程(front-end-of-line(FEOL)process)中,裝置區域104形成在基板102中。在一些實施例中,基板102尚包括填滿導電材料的基板穿孔(through-substrate vias,TSVs)105,基板穿孔105用於提供基板102從底側到頂側的連接。
金屬化結構106形成在基板102上,例如位於裝置區域104上。在一些實施例中,金屬化結構106形成在後段製程(back-end-of-line(BEOL)process)中。金屬化結構106包括內連線結構,例如導電線(conductive lines)108、導通孔(vias)110與導電墊(導電結構)112。如第1圖所示,導電墊112為接觸墊(或接合墊),其形成在半導體晶圓100之上表面中。一些導通孔110耦合接觸墊112到金屬化結構106中的導電線108,且其他導通孔110隨著導電金屬線108,耦合導電墊112到基板102中的裝置區域104。導通孔110亦可連接不同金屬層的導電線108(圖中未顯示)。
在一些實施例中,導電線108、導通孔110與導電墊112各自包括導電材料,例如銅(copper,Cu)、鋁(aluminum,Al)、鎢(tungsten,W)、鈦(titanium,Ti)或鉭(tantalum,Ta)。
如第1圖所示,導電墊112形成在絕緣材料114中。絕緣材料114為介電材料,例如二氧化矽(silicon dioxide)、氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、未摻雜之矽玻璃(undoped silicon glass,USG)、摻雜磷之氧化物(phosphorus doped oxide,PSG)、摻雜硼之氧化物(boron doped oxide,BSG)或摻雜硼磷之氧化物(boron phosphorus doped oxide,BPSG)所組成。在一些實施例中,絕緣層114由電漿增強型化學氣相沉積法(plasma-enhanced chemical vapor deposition,PECVD)所形成。在一些實施例中,絕緣材料114包括多層介電材料的介電層。然而,顯示於圖中的金屬化結構106僅是舉例說明。另外,金屬化結構106可包括其他設計且可包括一或多個導電線與導通孔層。
依據本揭露之實施例,在後續的說明中,第1圖中的區域M用於說明使用混合接合法時,清潔半導體晶圓100的一表面的機制。如第1圖所示,區域M包括設置在導通孔110上的導電墊112。導電墊112與導通孔110被絕緣材料114所包圍。
第2圖顯示依據本揭露實施例的接合結構的剖面圖。在第2圖中,半導體晶圓100藉由混合接合法接合至半導體晶圓150。需注意的是,雖然第2圖只有顯示半導體晶圓100與150的一些元件(例如顯示在第1圖區域M中的這些元件),其他元件也可以包括在半導體晶圓100與150中。如上所述,晶圓100
包括導電墊112形成在導通孔110上。導電墊112與導通孔110被絕緣材料114所包圍。在一些實施例中,形成開口且填充導電材料132在開口中。在一些實施例中,導電材料132由銅(copper,Cu)、鋁(aluminum,Al)、鎢(tungsten,W)、鈦(titanium,Ti)、鉭(tantalum,Ta)或其他適合的材料所組成。在一些實施例中,導電材料132由銅或銅合金所組成。依據本揭露之實施例,因為考慮到金屬(例如銅)會在絕緣材料114中擴散,導電墊112可包括擴散阻障層113,用以阻擋銅的擴散。然而,當導電材料132不是銅時(例如是鋁),則可不需要設置擴散阻障層。在一些實施例中,擴散阻障層113由鈦(titanium,Ti)、鉭(tantalum,Ta)、氮化鈦(titanium nitride,TiN)、氮化鉭(tantalum nitride,TaN)或氮化鋁(aluminum nitride,AlN)或上述組合之多層材料所組成。在一些實施例中,擴散阻障層113由銅擴散阻障材料所組成。在一些實施例中,擴散阻障層113由高分子所組成,例如苯並環丁烯高分子(benzocyclobutene(BCB)polymer)。在一些實施例中,擴散阻障層113具有厚度範圍為約10埃至約1000埃。
半導體晶圓150類似於半導體晶圓100,且半導體晶圓150包括導電墊152、導通孔156與絕緣材料154。導電墊152類似於導電墊112,且導通孔156類似於導通孔110。絕緣材料154類似於絕緣材料114。導電墊152包括導電材料162與擴散阻障層153。導電材料162類似於導電材料132,且擴散阻障層153類似於擴散阻障層113。
在半導體晶圓100接合至半導體晶圓150之前,對
準半導體晶圓100與150,使得在後續混合接合時,導電墊112可接合至導電墊152,且絕緣材料114可接合至絕緣材料154。在一些實施例中,可使用光學感測方法對準半導體晶圓100與150。
在對準之後,半導體晶圓100與150被壓合在一起且提升至某溫度,使得在半導體晶圓100與150的導電層之間與絕緣層之間形成鍵結(bond)。如第2圖所示,接合結構具有介面130與介面140,介面130形成在具有金屬對金屬鍵結的兩個導電墊112與152之間,介面140形成在具有非金屬對非金屬鍵結的兩個絕緣材料114與154之間。在一些實施例中,非金屬對非金屬鍵結是一種介電對介電鍵結。
因為金屬表面清潔不完全及/或形成金屬氧化物在介面130上,可能會有一些裂縫(crack)形成在兩個導電墊112與152之間的介面130。因為在介面130產生裂縫可能會降低產率(yield),因此,需要清潔導電材料132與152的金屬表面的機制,以及移除在金屬表面上的金屬氧化物的機制。
第3A-3F圖顯示依據本揭露實施例的用於混合接合法的半導體晶圓的清潔方法在各個製程階段的剖面圖。為了簡化說明書,第3A圖只有顯示部分的半導體晶圓100。
如第3A圖所示,開口111形成在絕緣材料114之中。在一些實施例中,使用微影製程(photolithography process)圖案化絕緣材料114,以形成開口111。此外,依據本揭露之實施例,因為考慮到金屬(例如銅)會在絕緣材料114中擴散,擴散阻障層113沉積且襯於開口中。
如第3B圖所示,用導電材料132填充開口111。在一些實施例中,導電材料132由沉積法所形成。沉積法包括電鍍方法(例如電化學電鍍法(electrical chemical plating,ECP))。
如第3C圖所示,過量的導電材料132從絕緣材料114的上表面移除,以形成導電墊112。在一些實施例中,用化學機械研磨製程法(CMP)10移除在開口111外的導電材料132。在一些實施例中,在化學機械研磨製程法(CMP)10之後,金屬氧化物層115形成在導電墊112的表面上。在一些實施例中,金屬氧化物層115由氧化銅(copper oxide,CuOx))所組成。金屬氧化物可能會弱化金屬對金屬鍵結(metal-to-metal bonding)的鍵結強度,因此需要移除金屬氧化物。為了移除金屬氧化物層115,需要進行後化學機械研磨(post-CMP)清潔製程。在一些實施例中,使用於後化學機械研磨清潔製程包括去離子水(deionized(DI)water)、氨水(NH4OH)或各種酸與鹼。清潔製程可包括刷具清潔(brush clean)、超音波清潔(mega-sonic clean)或上述之組合。另外地,清潔製程可包括其他類型的化學與清潔步驟。在一些實施例中,在後化學機械研磨清潔製程之後,一部份的金屬氧化物層115仍然留在導電墊112的上表面上。
處理半導體晶圓100的上表面,以輔助後續混合接合製程。如第3D圖所示,使用電漿製程20處理半導體晶圓100之上表面。在電漿製程20期間,暴露出半導體晶圓100的上表面,使得在後續製程中,絕緣材料114可以接合到絕緣材料154(如第2圖所示)。在一些實施例中,絕緣材料114為二氧化矽(SiO2),在電漿製程20之後,形成矽-氧鍵結(Si-O bonds)在絕
緣材料114的上表面。在一些實施例中,在電漿製程20中使用氮氣(nitrogen,N2)或氬氣(argon,Ar)。在一些實施例中,電漿製程20包括使用體積範圍為約80%至約100%的氬氣(Ar),以及體積範圍為約0%至約20%的氫氣(H2)。在一些實施例中,電漿製程20包括使用體積範圍為約80%至約100%的氦氣(He),以及體積範圍為約0%至約20%的氫氣(H2)。當使用氫氣時,一部分的金屬氧化物會變成金屬。然而,仍然有一些金屬氧化物留在金屬墊112上。在另一些實施例中,用另外的處理方法處理半導體晶圓100之上表面。
如第3E圖所示,在電漿製程20之後,殘餘物155形成在半導體晶圓100之上表面上。如上所述,如第3F圖所示,一些金屬氧化物層115仍然殘留在導電墊112的上表面上。
請參見第3F圖,在電漿製程20之後,利用清潔製程清潔半導體晶圓100之上表面。第3F圖顯示清潔溶液供應器(cleaning solution supplier)30(例如噴嘴nozzle)設置在半導體晶圓100之上表面上,以供應清潔溶液35。清潔溶液35可包括檸檬酸(citric acid)、氫氟酸(hydrofluoric acid,HF)或氫氧化四甲基銨(tetramethylammonium hydroxide,TMAH)。在一些實施例中,利用清潔溶液35移除殘餘物155,且在清潔製程期間,將金屬氧化物層115還原成金屬-氫鍵(metal-hydrogen bonds)。
在一些實施例中,清潔溶液35包括檸檬酸(citric acid),且清潔製程包括下述反應。
2CuOx+2CA →2[Cu/CA]+xO2 (1)
[Cu/CA]+H →[Cu/H]+CA (2)
請參見反應式(1),金屬氧化物層115中的金屬氧化物(例如銅氧化物(CuOx))與檸檬酸反應,以形成錯合物(complex[Cu/CA])。在清潔溶液35中,檸檬酸被氫離子(H+)取代,以形成銅/氫錯合物[Cu/H],其中包含銅-氫鍵(copper-hydrogen bonds)(請參見反應式(2))。因此,在清潔製程期間,藉由還原反應,使金屬氧化物層115還原形成金屬-氫鍵(metal-hydrogen bonds)。此外,在進行混合接合法之前,這些金屬-氫鍵(metal-hydrogen bonds)保護導電墊112的表面免於氧化。再者,在進行混合接合法期間,容易破壞金屬-氫鍵,以形成金屬-金屬鍵(metal-to-metal bonding)。
在一些實施例中,檸檬酸的濃度範圍為約0.25%至約10%。在一些實施例中,氫氟酸(hydrofluoric acid,HF)的濃度範圍介於約0.1%至約0.5%。在一些其他實施例中,氫氧化四甲基銨(tetramethylammonium hydroxide,TMAH)的濃度範圍介於約0.25%至約0.5%。
上述第3A圖至第3F圖所敘述的製程步驟亦可執行在第2圖的半導體晶圓150上,詳細的製程步驟在此不再贅述。在清潔製程清潔半導體晶圓100與150兩者之後,對準半導體晶圓100與150,以使導電墊112對準於導電墊152,且絕緣層114對準於絕緣層154(如第2圖所示)。
當進行對準之後,藉由壓力與熱,將半導體晶圓100與150混合接合在一起。可在充滿鈍氣環境的條件下進行混合接合,例如充滿氮氣(nitrogen,N2)、氬氣(argon,Ar)、氦氣(He)或上述之組合。在一些實施例中,用於混合接合法的壓力範圍
為約10kPa至約200kPa。在一些實施例中,施加熱到半導體晶圓100與150以接合兩者,施加熱包括在溫度範圍為約300℃至約400℃的條件下進行退火步驟。另外地,可依照需要調整用於混合接合法的壓力與溫度。
既然半導體晶圓100與150的上表面已經被清潔,沒有阻礙半導體晶圓100與150接合的殘餘物155與金屬氧化物層115殘留在兩者之間。如此一來,增強介於導電墊112與150之間的鍵結強度(bonding strength),且解決或大幅改善介面裂縫問題(interfacial cracking)。
第4圖顯示依據本揭露實施例用於混合接合法的整合系統(integrated system)。整合系統400包括電漿腔體410、傳輸腔體420、清潔腔體430與混合接合腔體(hybrid bonding chamber)440。電漿腔體410、清潔腔體430與混合接合腔體(hybrid bonding chamber)440相鄰於傳輸腔體420。因為電漿腔體410、清潔腔體430與混合接合腔體(hybrid bonding chamber)440皆耦合到傳輸腔體420,因此,可以在真空條件下藉由傳輸腔體420將半導體晶圓100與150從一個腔體傳輸到另一個腔體。在一些實施例中,一個機械手臂(圖中未顯示)設置在傳輸腔體420中,且所設置的機械手臂用於將半導體晶圓100與150傳輸到想傳輸的腔體中。舉例而言,設置的機械手臂用於將半導體晶圓100與150從電漿腔體410(為了進行電漿處理)傳輸到清潔腔體430(為了進行清潔),且接著傳輸到混合接合腔體(hybrid bonding chamber)440(為了進行混合接合)。
舉例而言,半導體晶圓100首先放置在傳輸腔體
420中的機械手臂上。之後,如第3D圖所示,為了進行電漿製程20,藉由機械手臂將半導體晶圓100傳輸到電漿腔體410。在電漿製程20之後,如第3F圖所示,為了進行清潔製程,藉由機械手臂將半導體晶圓100傳輸到清潔腔體430。接著,半導體晶圓100傳輸到混合接合腔體440,且留在混合接合腔體440中,直到半導體晶圓150已經準備進行接合。半導體晶圓150亦可在整合系統400中進行上述提到的製程步驟。那就是,半導體晶圓150也放置在傳輸腔體420中且接著傳輸到電漿腔體410、清潔腔體430與混合接合腔體440。在半導體晶圓100與150兩者都傳輸到混合接合腔體440中,半導體晶圓100接合到半導體晶圓150上,以在混合接合腔體440中,藉由混合接合法形成鍵結結構。在一些實施例中,用於將半導體晶圓100與150從一腔體傳輸到另一腔體的製程皆在真空下進行,因而避免金屬氧化物的再次形成。
在上述討論的製程中,在混合接合之前,進行清潔製程以移除殘餘物155與金屬氧化物115。此外,既然在真空條件下藉由傳輸腔體420,將半導體晶圓100與150從一個腔體傳輸到另一個腔體,在製程過程中,半導體晶圓100與150並未離開整合系統400。因此,避免金屬氧化物(例如氧化銅CuOx)再次形成在導電墊112與152的上表面上,且提升兩個半導體晶圓100與150的混合接合強度。
本揭露提供用於混合接合法(hybrid bonding)的半導體晶圓的清潔方法的實施例。每一個半導體晶圓包括導電墊與金屬氧化物層,其中導電墊被絕緣層所包圍,且金屬氧化物
層形成在導電墊之上。半導體晶圓的表面首先被電漿處理,接著在電漿製程之後,使用清潔製程清潔半導體晶圓。在清潔製程期間,清潔溶液移除形成在半導體晶圓上表面的殘餘物。此外,清潔溶液中的酸還原形成在半導體晶圓的導電墊上的金屬氧化物層,且在導電墊上形成金屬-氫鍵,以保護導電墊。藉由混合接合法接合清潔過的半導體晶圓,以形成接合結構。製備與接合半導體晶圓的製程包括在整合系統中進行下述製程,包括:電漿製程,清潔製程以及混合接合法。在真空條件下,在整合系統中,將半導體晶圓從一腔體傳輸到另一腔體,以避免金屬發生氧化。因此,避免金屬再次被氧化,且大幅提升混合接合的品質。
在一些實施例中,本揭露提供一種用於混合接合法(hybrid bonding)的半導體晶圓的清潔方法,包括以下步驟:提供一半導體晶圓,其中該半導體晶圓具有埋設在一絕緣層中的一導電墊與形成在該導電墊上的一金屬氧化物層;對該半導體晶圓之一表面進行一電漿製程;在該電漿製程之後,使用一清潔溶液對該半導體晶圓之該表面進行一清潔製程,其中該金屬氧化物被還原且複數個金屬-氫鍵形成在該導電墊之表面上;以及在真空下,傳輸該半導體晶圓至一接合腔體。
在一些實施例中,本揭露另提供一種半導體晶圓之混合接合法,包括以下步驟:提供一第一半導體晶圓與一第二半導體晶圓,其中該第一半導體晶圓與該第二半導體晶圓各自具有一導電墊埋設在一絕緣層中;各自對該第一半導體晶圓之一表面與該第二半導體晶圓之一表面進行一電漿製程;使用
一清潔溶液各自對該第一半導體晶圓之該表面與該第二半導體晶圓之該表面進行一清潔製程;以及接合該第一半導體晶圓至該第二半導體晶圓。
在一些實施例中,本揭露又提供一種用於混合接合法(hybrid bonding)的整合系統(integrated system),包括:一電漿腔體耦合至一傳輸腔體;一清潔腔體耦合至該傳輸腔體;以及一混合接合腔體耦合至該傳輸腔體,其中該混合接合腔體用於接合兩個半導體晶圓,以形成一金屬對金屬的鍵結(metal-to-metal bonding)與一非金屬對非金屬的鍵結(non-metal-to-non-metal bonding)。
雖然本揭露已以數個較佳實施例揭露如上,然其並非用以限定本揭露,任何所屬技術領域中具有通常知識者,在不脫離本揭露之精神和範圍內,當可作任意之更動與潤飾,因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧半導體晶圓
110‧‧‧導通孔
112‧‧‧導電墊(導電結構)
113‧‧‧擴散阻障層
114‧‧‧絕緣材料
130‧‧‧介面
132‧‧‧導電材料
140‧‧‧介面
150‧‧‧半導體晶圓
152‧‧‧導電墊
153‧‧‧擴散阻障層
154‧‧‧絕緣材料
156‧‧‧導通孔
162‧‧‧導電材料
Claims (10)
- 一種用於混合接合法(hybrid bonding)的半導體晶圓的清潔方法,包括以下步驟:提供一半導體晶圓,其中該半導體晶圓具有埋設在一絕緣層中的一導電墊與形成在該導電墊上的一金屬氧化物層;對該半導體晶圓之一表面進行一電漿製程;在該電漿製程之後,使用一清潔溶液對該半導體晶圓之該表面進行一清潔製程,其中該金屬氧化物被還原且複數個金屬-氫鍵形成在該導電墊之表面上;以及在真空下,傳輸該半導體晶圓至一接合腔體。
- 如申請專利範圍第1項所述之用於混合接合法的半導體晶圓的清潔方法,其中該清潔溶液包括檸檬酸(citric acid)、氫氟酸(hydrofluoric acid,HF)或氫氧化四甲基銨(tetramethylammonium hydroxide,TMAH)。
- 如申請專利範圍第1項所述之用於混合接合法的半導體晶圓的清潔方法,其中提供該半導體晶圓尚包括:形成一開口在該絕緣層中;形成一擴散阻障層以襯於該開口;以及形成一導電材料在該擴散阻障層之上,以形成該導電墊。
- 如申請專利範圍第1項所述之用於混合接合法的半導體晶圓的清潔方法,其中該絕緣層由二氧化矽(silicon dioxide)、氧化矽(silicon oxide)、氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、未摻雜之矽玻璃(undoped silicon glass,USG)、摻雜磷之氧化物(phosphorus doped oxide,PSG)、摻 雜硼之氧化物(boron doped oxide,BSG)或摻雜硼磷之氧化物(boron phosphorus doped oxide,BPSG)所組成。
- 如申請專利範圍第1項所述之用於混合接合法的半導體晶圓的清潔方法,其中進行該電漿製程包括:將該半導體晶圓暴露到氬氣(argon,Ar)或氮氣(nitrogen,N2)中。
- 如申請專利範圍第1項所述之用於混合接合法的半導體晶圓的清潔方法,其中進行該電漿製程、進行該清潔製程與傳輸該半導體晶圓至該接合腔體皆在一整合系統(integrated system)中進行。
- 一種半導體晶圓之混合接合法,包括以下步驟:提供一第一半導體晶圓與一第二半導體晶圓,其中該第一半導體晶圓與該第二半導體晶圓各自具有一導電墊埋設在一絕緣層中;各自對該第一半導體晶圓之一表面與該第二半導體晶圓之一表面進行一電漿製程;使用一清潔溶液各自對該第一半導體晶圓之該表面與該第二半導體晶圓之該表面進行一清潔製程;以及接合該第一半導體晶圓至該第二半導體晶圓。
- 如申請專利範圍第7項所述之半導體晶圓之混合接合法,其中該混合接合法以下列步驟進行:對該第一半導體晶圓進行該電漿製程;在對該第一半導體晶圓進行該電漿製程之後,對該第一半導體晶圓進行該清潔製程; 在對該第一半導體晶圓進行該清潔製程之後,傳輸該第一半導體晶圓到一混合接合腔體(hybrid bonding chamber);在傳輸該第一半導體晶圓到該混合接合腔體之後,對該第二半導體晶圓進行該電漿製程;在該第二半導體晶圓進行該電漿製程之後,對該第二半導體晶圓進行該清潔製程;在對該第二半導體晶圓進行該清潔製程之後,傳輸該第二半導體晶圓到該混合接合腔體;以及在傳輸該第二半導體晶圓到該混合接合腔體之後,接合該第一半導體晶圓至該第二半導體晶圓。
- 一種用於混合接合法(hybrid bonding)的整合系統(integrated system),包括:一電漿腔體耦合至一傳輸腔體;一清潔腔體耦合至該傳輸腔體;以及一混合接合腔體耦合至該傳輸腔體,其中該混合接合腔體用於接合兩個半導體晶圓,以形成一金屬對金屬的鍵結(metal-to-metal bonding)與一非金屬對非金屬的鍵結(non-metal-to-non-metal bonding)。
- 如申請專利範圍第9項所述之用於混合接合法的整合系統,尚包括:一清潔供應器(cleaning supplier)設置在該清潔腔體中,其中該清潔供應器用於提供一清潔溶液,以還原位在該半導體晶圓之導電墊上的一金屬氧化物,以及在該半導體晶圓之一導電墊上形成金屬-氫鍵(metal-hydrogen bonds)。
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