TW201505027A - Semiconductor memory apparatus and method for erasing the same - Google Patents

Abstract

A flash memory with low power consumption and rapid operations is disclosed, including a memory array of memory cells, a word line selection circuit for selecting a row of cells, a current-type sensing circuit connected with each bit line of the array for sensing the current of a selected bit line, and an erase unit erasing the cells in a selected block of the array. The erase unit includes: an erase sequence that determines whether the current of each bit line in the erased block is larger than a first value and ends the erasure if the result is "yes", and a soft program sequence that performs a soft program verification, which applies a soft program voltage to all word lines in the erased block and determines whether the current of each bit line is less than a second value, and ends the soft programming if the result is "yes".

Description

Semiconductor memory device and erase method thereof

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for reading data of a (NAND) type flash memory in a current sensing manner, and a method of erasing the semiconductor memory device.

1 is a diagram showing an example of a bit line selection circuit and a page buffer/sense circuit of a flash memory of the prior art, in which a pair of bits including an even bit line GBL_e and an odd bit line GBL_o is illustrated. line. This bit line selection circuit 10 includes an even selection transistor SEL_e that connects the even bit line GBL_e, an odd selection transistor SEL_o that connects the odd bit line GBL_o, and an even number that is connected between the even bit line GBL_e and the virtual potential VIR. The bias selection transistor YSEL_e, the odd bias selection transistor YSEL_o connected between the odd bit line GBL_o and the dummy potential VIR, and the bit connected to the common node N1 of the even selection transistor SEL_e and the odd selection transistor SEL_o Line select transistor BLS.

The even bit line GBL_e and the odd bit line GBL_o are electrically connected to each other. NAND string NU. Each NAND string NU includes a plurality of memory cells connected in series in the row direction and a drain select transistor and a source select transistor electrically connected at both ends thereof, wherein the drain select transistor and the even bit line GBL_e or odd bit The element line GBL_o is electrically connected, and the source selection transistor is electrically connected to the common source line SL.

The sensing circuit 20 has: supplying a pre-charge potential to the bit line The precharged crystal BLPRE, the capacitor C electrically connected to the sense node SN formed between the precharge crystal BLPRE and the bit line selection transistor BLS, and the transfer of the potential of the sense node SN to the latch circuit 22 Power transmission crystal BLCD.

When the even bit line GBL_e is selected, the odd bit line GBL_o is not selected Alternatively, the even selection transistor SEL_e and the bit line selection transistor BLS are turned on, and the odd selection transistor SEL_o is turned off. When the odd bit line GBL_o is selected, the even bit line GBL_e is not selected, the odd selection transistor SEL_o and the bit line selection transistor BLS are turned on, and the even selection transistor SEL_e is turned off. Thus, one sensing circuit 20 is shared by two bit lines GBL_e and GBL_o.

Select the even bit line GBL_e in the read operation instead of the odd bit line In GBL_o, the even bias selection transistor YSEL_e is turned off, the odd bias selection transistor YSEL_o is turned on, and the odd bit line GBL_o is supplied with the ground potential by the dummy potential VIR. On the other hand, when the odd bit line GBL_e is not selected and the odd bit line GBL_o is selected, the even bias selection transistor YSEL_e is turned on, the odd bias selection transistor YSEL_o is turned off, and the even bit line GBL_e is supplied to the ground by the dummy potential VIR. Potential. Thus, when the even bit line is read, the ground potential is supplied to the odd bit line, and when the odd bit line is read, the ground potential is supplied to the even bit line, and the adjacent bit can be provided. The bit line-reducing effect of the noise reduction caused by the capacitive coupling between the lines is as described in Japanese Patent Laid-Open No. Hei 11-176177.

The sensing circuit 20 shown in FIG. 1 is a so-called voltage detecting type sensing circuit that supplies a precharge bit to the even bit line GBL_e or the odd bit line GBL_o by the precharge crystal BLPRE. Then, the bit line is discharged corresponding to the storage state of the selected memory cell, and the discharge state is detected by the sensing node SN. However, when the bit line width is decreased to increase the resistance, and the number of memory cells constituting the NAND string is increased to increase the capacitance of the bit line, the time constant of the voltage detecting type sensing circuit (time constant) ) will become larger, the time required for charging and discharging the bit line will become longer, and the time for reading the data will increase. Therefore, the voltage detection type sensing circuit is no longer suitable for a flash memory with an increased degree of accumulation.

Therefore, the current sensing circuit uses a current detecting type instead. The current detecting type sensing circuit detects the memory cell current corresponding to the storage state of the memory cell via the bit line, which enables high-speed sensing as compared with the voltage detecting type. The current detecting type sensing circuit is, for example, a cascode circuit or the like that performs current-voltage conversion.

However, the prior art current detecting type sensing circuit has the following problems. In flash memory, when accumulating, electrons are accumulated in the floating gate, and the starting voltage of the memory cell is changed positively. When erasing, the electrons are discharged from the floating gate, and the memory cell is activated. The starting voltage changes in a negative direction. However, in the case of such stylization and erasing, the starting voltage of the memory cell must be controlled within the distribution range of 0 or 1 storage state, or controlled at 00, 01, 10 in the case where the memory cell stores multiple bits. Or within 11 distributions of storage states. In order to accurately control the starting voltage of the memory cell, the Incremental Step Pulse Erase (ISPE) method has been used previously, which is the first The erasing pulse Vers0 is applied to the memory cell of the selected block, and when the erasing failure is confirmed by the erasing verification, the erasing pulse Vers1 which is higher than the erasing pulse Vers0 is applied, and the voltage of the erasing pulse is gradually increased. Until all the memory cells in the block are judged to be erased.

Due to the variation in process parameters due to the size or shape of each memory cell Variations, as well as factors such as deterioration of the tunneling oxide layer when the number of times of programming or erasing is large, make the difference between the memory cells easy to erase and difficult to erase. In particular, it is that the conductivity of some memory cells makes the current flow more easily, and the conductivity of some memory cells is smaller, making the current less difficult to flow. Since the erase verification does not check the erase state by memory, but judges whether the entire block is qualified by the bit line, when one bit line is connected to the memory cell with large conductivity and the memory with small conductivity. At the time of cell, a memory cell having a small conductivity becomes a criterion for judging whether or not the cell is highly qualified, so that a memory cell having a large conductivity is over-erased. Therefore, when reading data, the erased memory cells have a relatively large current, which increases the power consumption. At the same time, the sensing circuit must also supply a large current, which hinders the miniaturization of the sensing circuit.

In order to solve the above problems of the prior art, the present invention provides a semiconductor memory device which can reduce power consumption and can operate at high speed.

The present invention also provides an erase method for such a semiconductor memory device having a reverse (NAND) type non-volatile memory cell.

The semiconductor memory device of the present invention comprises a memory array including a plurality of memory cells, a word line selection circuit for selecting a column direction memory cell, and a bit element of the memory array A current detecting type sensing circuit electrically connected to detect a current of the selected bit line, and an erasing unit for erasing data of the memory cell of the selected block of the memory array. This erase unit contains an erase program and a soft program. The erase program includes an erase verify that determines whether the current of each of the bit lines of the erased block is greater than the first value, and if so, ends the erase. The soft programming program includes a soft stylized verification by applying a soft stylized voltage to all word lines of the erased block, and determining whether the current of each bit line is less than a second value smaller than the first value, and if so, the soft end Stylized.

In an embodiment of the invention, the soft stylization verifies the bias applied to the unselected word line when a read operation is applied to all of the word lines, and determines whether the current of each bit line is less than the second value. An anti-write voltage can be applied to the bit line having a current less than the second value, and the memory cell electrically connected to the bit line having a current greater than the second value can be soft-programmed.

In an embodiment of the invention, the semiconductor memory device further includes a plurality of precharge paths for supplying precharge voltage to the bit lines, and are disposed between the blocks. Each of the precharge paths can supply a precharge voltage to the bit line before supplying current to the bit line by the sense circuit. The sensing circuit may include a first sensing circuit that connects the even bit lines and a second sensing circuit that connects the odd bit lines, wherein the first sensing circuit is disposed at one end of the memory array, and the second sensing circuit is disposed at The other end of the memory array, and the precharge circuits are disposed between the first sensing circuit and the second sensing circuit. Each precharge path may include a wire extending from the word line selection circuit along the column direction of the memory array to be connected to the bit line.

The erasing method of the semiconductor memory device having the reverse (NAND) type non-volatile memory cell of the present invention includes an erase program and a soft program program. Erase program contains It is judged whether the current of each of the bit lines of the erased block is greater than the erase value of the first value, and if so, the erasing is ended. The soft programming program includes a soft stylized verification by applying a soft stylized voltage to all word lines of the erased block, and determining whether the current of each bit line is less than a second value smaller than the first value, and if so, the soft end Stylized.

According to the present invention, it is possible to provide a semiconductor memory device using a current detecting type sensing circuit which can reduce power consumption and can operate at high speed.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧ bit line selection circuit

20‧‧‧Sensor circuit

22‧‧‧Latch circuit

100‧‧‧flash memory

110‧‧‧ memory array

120‧‧‧Input and output buffers

130‧‧‧ address register

140‧‧‧data register

150‧‧‧ Controller

160‧‧‧Word line selection circuit

170‧‧‧Page Buffer/Sensor Circuit

180‧‧‧Precharge road

190‧‧‧ row selection circuit

200‧‧‧Internal voltage generation circuit

S110~S130, S200~S210‧‧‧ step label

Ax, Ay‧‧‧ address information, line address information

BL‧‧‧ bit line

BLCD‧‧‧Transfer transistor

BLK‧‧‧ Block

BLPRE‧‧‧Precharged crystal

BLS‧‧‧ bit line selection transistor

C‧‧‧ capacitor

C1, C2, C3‧‧‧ control signals

ERV‧‧‧Erasing verification

GBL_e, GBL_o‧‧‧ even bit lines, odd bit lines

IN‧‧‧ reverser

M1, M2‧‧‧P channel MOS semi-transistor, N-channel MOS semi-transistor

MC‧‧‧ memory cell

Common node of N1‧‧‧SEL_e and SEL_o

N2‧‧‧ node

NU‧‧‧NAND serial

Out‧‧‧Sense node SN output

PRE_e, PRE_o‧‧‧ even precharged crystal, odd precharged crystal

R‧‧‧Resistors

SEL_e, SEL_o‧‧‧ even choice transistor, odd selection transistor

SGD, SGS‧‧‧ select gate line

SL‧‧‧ source line

SN‧‧‧ sensing node

SPGM‧‧‧soft stylization

TR1, TR2‧‧‧ select transistor

VIR‧‧‧ virtual potential

WL‧‧‧ character line

WL_SEL‧‧‧Selected word line

WP_e, WP_o‧‧‧Metal wire

YSEL_e, YSEL_o‧‧‧ even bias transistor, odd bias transistor

FIG. 1 illustrates an example of a bit line selection circuit and a page buffer/sense circuit of a prior art flash memory.

Fig. 2 is a block diagram showing a configuration example of a flash memory according to an embodiment of the present invention.

3 is a circuit diagram showing the structure of a precharge circuit and a NAND string according to an embodiment of the present invention.

FIG. 4 illustrates an exemplary structure of a page buffer/sense circuit according to an embodiment of the present invention.

Figure 5 shows the voltage relationships of the various components of the flash memory in various modes of operation in accordance with an embodiment of the present invention.

FIG. 6 is a flowchart of an erase operation of a flash memory according to an embodiment of the present invention.

FIG. 7 is a timing chart of signals applied in an erase mode according to an embodiment of the present invention.

Figure 8 shows the distribution of the starting voltage during erase verification, soft stylization verification, and page stylization verification.

FIG. 9 is a flow chart showing the operation of soft stylization/verification according to an embodiment of the present invention.

FIG. 10 is a diagram showing another exemplary structure of a flash memory according to an embodiment of the present invention.

The flash memory of the present invention uses a current detecting type sensing circuit to determine the presence or absence of a memory cell current. In order to reduce the power consumption during reading, when the data of the memory cell is erased, an architecture that suppresses the negative starting voltage of the memory cell to a certain value or more is employed. When the current is read, the amount of current supplied from the current detecting type sensing circuit to the bit line can be suppressed to a certain value or less, thereby reducing the power consumption. Embodiments of the present invention will be described in detail below with reference to the drawings. It is also important to note that some of the components are emphasized in the drawings for ease of understanding, which differ from the actual component dimensions.

2 is a block diagram showing an exemplary structure of a flash memory according to an embodiment of the present invention. This illustrative structure is only an example and is not intended to limit the scope of the invention.

The flash memory 100 of the embodiment of the present invention includes: a memory array 110 having a plurality of memory cells arranged in a plurality of rows and columns; and an input/output buffer for electrically storing input and output data electrically connected to the external input/output terminal I/O 120. The address register 130 for obtaining address data from the input/output buffer 120, the data register 140 for storing the input and output data, the command data based on the input/output buffer 120, and the external control signal (not shown) Control of chip enable or address latch enable, etc., to supply control signals C1, C2, C3, etc. for controlling each component The controller 150 performs a word line selection circuit 160 for block selection, word line selection, and the like based on the decoding result of the column address information Ax from the address register 130, and saves the word line selection circuit 160 by the word line selection circuit 160. The data read by the selected page and the page buffer/sense circuit 170 for storing the written data of the selected page, the precharge path 180 for supplying the precharge voltage to the bit line, and the row based on the address from the address register 130 The decoding result of the address information Ay is used to select the row selection circuit 190 of the row data in the page buffer/sense circuit 170, and the voltage required to generate data reading, programming, and erasing (programming voltage Vpgm, The internal voltage generating circuit 200 is a pass voltage Vpass, a read pass voltage Vread, an erase voltage Vers, a soft programmed voltage Vsoft, and a non-selected read voltage VPASSR.

The memory array 110 has a plurality of blocks BLK(0) arranged in the row direction, BLK (1), ..., BLK (m). A page buffer/sense circuit 170 is disposed on both sides of the block, and a plurality of precharge paths 180 are arranged in the row direction of the block.

3 illustrates the structure of a NAND string formed in a memory block, and Configure the pre-charge path between the blocks. A plurality of NAND strings NU are formed in one memory block, each of which includes a plurality of memory cells connected in series in the row direction. In the example of FIG. 3, there are n+1 NAND strings NU arranged in the column direction in one memory area.

Each NAND string NU includes a plurality of memory cells MCi (i = 0, 1, ..., 31) connected in series in the row direction, and a selection transistor TR1 electrically connected to the drain side of the memory cell MC31 at one end thereof, And a selection transistor TR2 electrically connected to the source side of the memory cell MC0 at the other end. The drain of the transistor TR1 is electrically connected to the corresponding one bit line GBL, and the source of the selected transistor TR2 is electrically connected to the common source line SL.

The control gate of the memory cell MCi is electrically connected to the word line WLi, and the gates of the selection transistors TR1 and TR2 are electrically connected to the selection gate lines SGD and SGS parallel to the word line WL. When the memory block is selected based on the column address Ax, the word line selection circuit 160 selectively drives the selection transistors TR1, TR2 by the selection gate signals SGD, SGS of the memory block.

Generally, a P well is formed in a semiconductor substrate and a semiconductor layer, and one block is formed in one P well. Each memory cell has a MOS structure, including a source/drain for the N-type diffusion region, a tunnel oxide layer formed on the channel region between the source/drain, and a floating gate for charge accumulation formed on the tunnel oxide layer ( Or a charge accumulation layer), and a control gate formed on the floating gate via the dielectric layer. When the floating gate does not accumulate charge or is erased, that is, when it is in the "1" state, the starting voltage is a negative value, so that the memory cell is normally on. When the floating gate has accumulated charge or is programmed, it remains at the "0" state, and the starting voltage is positive, causing the memory cell to be normally off.

As shown in FIG. 3, a precharge path 180 is inserted between the block BLK(i) and the block BLK(i+1) to supply the precharge voltage to the bit line GBL. Although the insertion position and the number of the precharge paths 180 are arbitrary, the arrangement is preferably such that the number of blocks included between the precharge path 180 and the page buffer/sense circuit 170 is close to the precharge path 180. The number of blocks contained between them. By setting the precharge path 180, the time required to precharge the bit line can be shortened.

In a preferred embodiment, the precharge path 180 includes an even precharge crystal PRE_e electrically coupled to the even bit line GBL_e, and an odd precharge crystal PRE_o electrically coupled to the odd bit line GBL_o. Even precharged crystal Both PRE_e and odd precharge crystals PRE_o are formed within word line selection circuit 160 and operate based on control signals from controller 150. The metal wires WP_e and WP_o electrically connected to the even precharge crystals PRE_e and the odd precharge crystals PRE_o respectively extend in the column direction of the memory array 110, wherein the metal wires WP_e are electrically connected to the even bit lines GBL_e, and the metal wires WP_o It is electrically connected to the odd bit line GBL_o. The metal wires WP_e and WP_o preferably extend above the source line SL. When a read operation is performed, for example, the even precharge crystal PRE_e or the odd precharge crystal PRE_o is turned on, and the precharge bit Vpre is supplied to the even bit line GBL_e or the odd bit line GBL_o.

The bit lines GBL0, GBL1, ..., GBLn electrically connected to the NAND string NU are electrically connected to the page buffer/sense circuit 170 via a bit line selection circuit. The bit line selection circuit selects an even bit line or an odd bit line when reading or stylizing, etc., and electrically connects the selected even bit line or odd bit line to the page buffer/sense circuit 170. . For example, when an even bit line is selected, the even bit line is electrically connected to the page buffer/sense circuit 170 above the memory array 110 in the drawing; when the odd bit line is selected, the odd bit line is the same as the picture The page buffer/sense circuit 170 below the memory array 110 is electrically connected.

4 is a circuit diagram showing an exemplary structure of a page buffer/sense circuit according to an embodiment of the present invention, which is an example of a page buffer/sense circuit 170 electrically connected to one even bit line GBL_e. The page buffer/sense circuit 170 includes a sensing circuit that detects the current of the even bit line GBL_e at the time of reading, a latch circuit that holds the read data or the stylized data, and the like.

The sensing circuit of this embodiment is of a current detecting type, which can be constituted by a well-known circuit. Although FIG. 4 exemplifies a simplified splicing circuit, a circuit for accommodating a current-voltage converted signal based on a differential amplifier circuit of two splicing circuits may be used in addition to the configuration reference splicing circuit. The sensing circuit shown in FIG. 4 includes: a P-channel MOS transistor M1 electrically connected to the Vdd power source, a resistor R electrically connected to the PMOS half-crystal M1 in the row direction, and a resistor R in the row direction. A connected N-channel MOS transistor M2, and a CMOS inverter IN connected to the gate of the NMOS transistor M2.

The signal input for the sensing circuit is activated at the gate input of the transistor M1, so that the transistor M1 functions as a current source. The gate of the transistor M2 is coupled to the output of the inverter IN such that the inverter IN applies the inversion potential of the bit line GBL_e to the transistor M2. That is, the node N2 is electrically connected to the even bit line GBL_e via the bit line selection circuit to detect the current of the even bit line GBL_e. If the bit line GBL_e has a current, the potential of the node N2 is low and the transistor M2 is turned on, the detection current flowing through the transistor M1 is converted into a voltage by the resistor R, and the sensing node SN outputs a voltage corresponding to the detection current (resistance of the resistor R) Value × detection current flowing through the resistor R). If there is no current or current on the bit line GBL_e, the transistor M2 is turned off without passing the sense current through the resistor R, so the output Out of the sense node SN is zero. In addition, a shield reading operation in which an odd bit line has a reference potential and an even bit line has a reference potential when reading an odd bit line may be performed. The current detecting type sensing circuit of the present embodiment limits the maximum current to a certain value or less as described later to suppress the consumption of reading or verification. Electricity.

Next, the flash memory operation of this embodiment will be described. The table of Figure 5 is listed An example of a bias configuration of a voltage applied during erasing, writing, and reading operations, where F represents floating. The controller 150 interprets the instruction after receiving the relevant instruction for reading, programming or erasing, and then controls the word line driving circuit 160, the row selecting circuit 190, the internal voltage generating circuit 200, and the like to perform various operations.

The flash memory of this embodiment performs an erase operation including the flow shown in FIG. The controller 150 performs the erase operation shown in FIG. 6 after receiving the relevant instruction of the erase. The erasing operation includes: applying an erase pulse to the selected block to erase the memory cell data to the ISPE erase (S100), confirming whether the start voltage of the memory cell is below the erase verification voltage (S110), The soft programming (S120) for narrowing the distribution of the starting voltage of the memory cell, and the soft programming verification (S130).

Figure 7 illustrates the timing chart of the signal waveform applied during erase verification (ERV) and soft stylization (SPGM). The erase of the flash memory is to erase the data of all the memory cells in the selected block at a time, for example, by controlling the controller 150, applying 0V to all the bit lines of the selected block to select the gate signal. SGD and SGS are floating, and an erase voltage Vers of about 20 V is applied to the P well.

Next, the controller 150 performs an erase verify (ERV) under control, which applies 0V to all the word lines WL_SEL in the selected block as shown in FIG. 7, applies a power supply voltage Vdd to the selected gate lines SGD, SGS, and The sensing circuit applies a voltage (eg, 0.8 V) to all of the bit lines BL. During the erase verify, when the precharge voltage Vpre is supplied from the precharge path 180 to the bit line, and the bit line is coupled to the sensing circuit 170, The voltage of the bit line does not change. That is, the even precharge crystal PRE_e or the odd precharge crystal PRE_o shown in FIG. 3 is turned on for a certain period of time before the time when the sensing circuit 170 is coupled to the bit line. Since the voltage variation when the bit line is coupled to the sensing circuit 170 is minimized, it is expected that the precharge voltage Vpre is equal to the voltage supplied from the sensing circuit 170.

When the charge of the memory cell in the selected block is erased, the starting voltage changes in a negative direction, causing the memory cell to become "1". However, since the memory cells may differ due to deterioration of the tunneling oxide layer of the memory cell or other factors, there is a difference between the starting voltages of the respective memory cells. The erase verification is used to confirm whether the starting voltage of the memory cell in the selected block is below the verification limit voltage Vth. In the present embodiment, since the sensing circuit 170 is of a current detecting type, when the current of each of the bit lines is equal to or greater than a threshold current, for example, 1 μA or more, it is determined that the erasing is acceptable. The sensing circuit shown in FIG. 4, when the current of the transistor M1 is above a constant current, the sensing node exhibits a relatively high voltage corresponding to the limiting current; and when the memory cell of the corresponding bit line has no current or current, When the current is limited, the sensing node SN exhibits a relatively low voltage. Whether or not the erase is acceptable can be confirmed based on the voltage output from the sense node SN. If it is confirmed that the erasing is unqualified, the P well is applied with a certain value of the erase pulse higher than the previous applied erase pulse, so that the starting voltage of the memory cell is further changed in the negative direction. Thus, the erase-erase verification is repeated until the erase verification verifies that all the erases are acceptable, and the upper limit value Vmax of the start voltage distribution of the memory cells in the block is ensured to be below the threshold voltage Vth corresponding to the verification limit current. . FIG. 8A illustrates the initial voltage distribution of the memory cell at the end of the erase verification, where the upper limit of the initial voltage distribution is The value Vmax is smaller than the threshold voltage Vth corresponding to the erase verification limit current. Here, the current of the memory cell is a drain current Id which can be used to specify the memory cell starting voltage.

Then perform a soft stylization/test to narrow the initial voltage distribution of the memory cell. certificate. Although the previous data erase/erase verification operation causes the upper limit value Vmax of the distribution to be smaller than the threshold voltage Vth, the lower limit value Vmin of the distribution is not considered. Because the ISPE erase/erase verification is for the memory cell whose current is most difficult to flow, the erase pulse is applied to the entire block, so there will be erased memory cells in the block, that is, the initial voltage negatively changes too much. Memory cells exist. The soft programming here is to apply a soft stylized voltage Vsoft1 to the word line in the block which is smaller than the voltage Vpgm applied during the general stylization, and to provide a charge injection into the memory cell to change the starting voltage in the positive direction. Power.

FIG. 9 is a flow chart showing the soft stylization/verification of the embodiment. In the soft program During the process, a preset initial soft programming voltage Vsoft1 (S200) is set for the memory, and the soft programming voltage Vsoft1 is applied to all the word lines in the selected block as shown in FIG. 7 to select the gate line. The SGD, SGS apply the power supply voltage Vdd, and apply a programmable voltage of 0 V to all the bit lines (S202). At this time, the precharge path 180 is supplied with the precharge voltage Vpre to the bit line in the same manner as the erase verification. The soft stylized voltage Vsoft1 is lower than the normal stylized voltage, and it is relatively easy to inject the charge into the erased memory cell, and it is difficult to inject the charge into the memory cell near the upper limit of the initial voltage. Therefore, as shown in FIG. 8B, the starting voltage of the memory cell near the lower limit value of the distribution changes toward the positive direction, and the starting voltage distribution is narrowed.

In the soft stylization verification, the pass voltage VPASSR on the unselected word line is applied to all the word lines in the selected block (the example in the table of FIG. 5 is 4.5V). (S204). This verification is performed by the precharge path 180 as in the case of the erase verification, and the same bias voltage is applied to the selection gate lines SGD, SGS. Next, the sense circuit 170 detects whether the current of the bit line is less than the limit current (Id<1 μA?), and if so, confirms that the soft programming is acceptable (S206). That is to say, when the output of the sensing node SN of FIG. 4 is a lower voltage, it is confirmed to be acceptable. If it is confirmed that the soft stylization is unsatisfactory, the next soft stylization is performed (S208). At this time, the soft stylized voltage Vsoft2 higher than the previous soft-stylized voltage Vsoft1 is applied to the defective bit line. At the same time, for the bit line that has been confirmed to be soft-programmed, for example, an anti-writing voltage obtained by boosting a booster circuit or the like is supplied. In this way, the starting voltage of the memory cell corresponding to the unqualified bit line can be changed in the positive direction. This soft programming and verification is repeated until all of the bit lines are qualified (S210). Finally, the currents of the bits of the blocks that have ended the soft programming block converge to about 1 μA. In addition, FIG. 8C illustrates the initial voltage distribution at the time of stylized verification. For example, when 1.5V is applied to the selected word line, the current Id of the bit line is less than 0.15 μA.

With this embodiment, the lower limit value of the starting voltage distribution can be changed in the forward direction, and the starting voltage distribution of the memory cell is narrowed, so the current supplied by the sensing circuit via the bit line when reading data is used. The upper limit can be limited while suppressing power consumption. That is to say, since the pass voltage VPASSR of the unselected word line when reading is applied to all the word lines during the soft stylization verification, and the bit line whose current is less than the limit current is detected, the read can be suppressed. The maximum current supplied by the sensing circuit is taken. This matter is also related to the downsizing of the sensing circuit. Moreover, since the pre-charge voltage is supplied from any of the bits connecting the NAND string NU from the sensing circuit, the time required for the bit circuit to charge the bit line can be greatly shortened, and the read or Stylized High speed.

Although the above embodiment sets a pair of pages on the upper and lower sides of the memory array in the drawing Buffer/sense circuit, and each page buffer/sense circuit is electrically connected to even bit lines and odd bit lines, but one page buffer/sense circuit can also be even bit lines and odd bit lines Total. In this case, the page buffer/sense circuit 170 is selectively electrically connected to the even bit line GBL_e and the odd bit line GBL_o via the bit line selection circuit 10 as shown in FIG. Furthermore, in the case where the pair of page buffer/sense circuits are electrically connected to the even bit lines and the odd bit lines as in the embodiment, the bit line shielding operation can also be performed, which is in the read even The bit line makes the odd bit line have a reference potential such as GND, and makes the even bit line have a reference potential such as GND when reading the odd bit line.

Although the erase mode of the above embodiment includes the flow shown in FIG. 6, this The erase mode of the invention may also include processes other than the flow shown in FIG. 6. In addition, although the memory cell in the above embodiment stores data of one bit, the present invention can also be applied to a multi-bit memory cell. Moreover, the numerical values described in the above embodiments are obviously only examples.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧flash memory

110‧‧‧ memory array

120‧‧‧Input and output buffers

130‧‧‧ address register

140‧‧‧data register

150‧‧‧ Controller

160‧‧‧Word line selection circuit

170‧‧‧Page Buffer/Sensor Circuit

180‧‧‧Pre-charge circuit

190‧‧‧ row selection circuit

200‧‧‧Internal voltage generation circuit

Ax, Ay‧‧‧ address information, line address information

C1, C2, C3‧‧‧ control signals

Claims (10)

A semiconductor memory device comprising: a memory array comprising a plurality of memory cells; a word line selection circuit for selecting a memory cell in a column direction; and a current detection type sensing circuit coupled to each of the memory lines to detect The current of the selected bit line; the erasing unit is configured to erase the data of the memory cell in the selected block of the memory array, the erasing unit includes an erasing program and a soft programming program, wherein the erasing program includes Determining whether the current of each of the bit lines of the erased block is greater than the first value, if yes, ending the erasing; and the soft programming program includes applying a soft program to all the word lines of the erased block The voltage is determined, and it is judged whether or not the current of each bit line is less than the soft-form verification of the second value smaller than the first value, and if so, the soft programming is ended. The semiconductor memory device of claim 1, wherein the soft programming verifies a bias applied to the unselected word line when a read operation is applied to all of the word lines, and determines whether the current of each of the bit lines is Less than the second value. The semiconductor memory device of claim 2, wherein the soft programming program applies an anti-write voltage to a bit line having a current less than the second value, and a bit line with a current greater than the second value The connected memory cells are soft-programmed. The semiconductor memory device according to any one of claims 1 to 3, further comprising a plurality of precharge circuits for supplying precharge voltage to the bit line, disposed between the blocks. The semiconductor memory device of claim 4, wherein each of the precharge paths is supplied with precharge before the current is supplied to the bit line by the sensing circuit. Press the bit line. The semiconductor memory device of claim 4, wherein the sensing circuit comprises a first sensing circuit connected to the even bit line and a second sensing circuit connected to the odd bit line, wherein the first sensing The circuit is disposed at one end of the memory array, the second sensing circuit is disposed at the other end of the memory array, and the precharge circuits are disposed between the first sensing circuit and the second sensing circuit. The semiconductor memory device of claim 4, wherein each of the precharge paths comprises: a wire extending from the word line selection circuit in a column direction of the memory array and connected to the bit line. An erasing method for a semiconductor memory device having a non-volatile (NAND) type non-volatile memory cell, comprising: an erasing program, determining whether a current of each of the bit lines of the erased block is greater than a first value, and if so, ending the erasing And a soft programming program that applies a soft stylized voltage to all word lines of the erased block, and determines whether the current of each bit line is less than a second value smaller than the first value, and if so, ends the soft Stylized. An erasing method for a semiconductor memory device having a reverse-type non-volatile memory cell according to claim 8, wherein the soft programming program adds a non-selected character to a word when applying a read operation to all word lines. The bias of the line, and determine whether the current of each bit line is less than the second value. An erasing method for a semiconductor memory device having a reverse type non-volatile memory cell according to claim 9, wherein the soft programming program applies an anti-writing voltage to a bit line having a current less than the second value, The memory cell connected to the bit line having a current greater than the second value is soft-programmed.