TW201505015A - Temperature sensing circuit and driving circuit - Google Patents

Abstract

The present invention is related to a temperature sensing circuit and a driving circuit. The temperature sensing circuit comprises a switching circuit, a charging circuit, and a judging circuit. The switching circuit receives a supply voltage for generating a switching signal. The charging circuit is coupled to the switching circuit and receives the supply voltage. The switching signal controls the charging circuit for generating a voltage signal according to the supply voltage. The judging circuit is coupled to the charging circuit for generating a judging signal according to the level of the voltage signal. The levels of the switching signal and the voltage signal are related to a temperature state; and the judging signal represents the temperature state. The temperature sensing circuit can be applied to the driving circuit of a display panel for detecting the temperature state. Hence, the level of the driving signal of the driving circuit can be adjusted for improving the image quality.

Description

Temperature sensing circuit and driving circuit

The invention relates to a temperature sensing circuit, in particular to a temperature sensing circuit applicable to a driving circuit for sensing an ambient temperature to adjust a level of a driving signal for driving the liquid crystal display panel at different ambient temperatures. .

Thin film transistor liquid crystal display (TFT-LCD) is one of many liquid crystal displays, which uses Thin Film Transistor (TFT) technology to improve image quality.

As mentioned above, thin film transistors are one of the types of field effect transistors. The general fabrication method is to deposit various films on the substrate, such as semiconductor active layer, dielectric layer and metal electrode layer. The ruthenium layer used in the thin film transistor mainly uses an oxime gas to produce an amorphous silicon (a-Si) layer or a polycrystalline silicon layer (Poly-Si).

Compared with a polycrystalline germanium film transistor, a display made of an amorphous germanium film transistor can reduce the production cost and can be fabricated on a large-area glass substrate at a low temperature to increase the production rate. However, the characteristics of the amorphous germanium film transistor are easily affected by temperature. The higher the temperature of the gate at the same voltage, the higher the current flowing through the drain and the source; on the contrary, the lower the temperature, the flow through the drain The smaller the current with the source. Since the amorphous germanium thin film transistor is used as a driving switch of the display to control the display screen, the temperature affects the contrast of the display screen, the gamma curve, and the like.

A number of U.S. patents have proposed solutions for the lack of display characteristics due to temperature rise or fall in the characteristics of thin film transistors, as shown below.

A circuit architecture for temperature compensated drive voltage of a display is disclosed in U.S. Patent No. 7,696,977. The circuit architecture mainly includes a temperature sensor, a temperature sector register, a plurality of comparators, a voltage register, a voltage controller and a driver.

The circuit operation structure is: the comparator compares the temperature data output value sensed by the temperature sensor with the temperature zone data stored in the temperature zone register to output a predetermined bit Compare data. The voltage controller receives the comparison data and selects the voltage data corresponding to the comparison data to output the voltage control signal. The driver receives the voltage control signal to output a drive signal to the display panel. In other words, after the temperature sensor senses the temperature, the buffer, the comparator, and the voltage controller enable the driver to output different levels of driving voltage according to different temperatures to drive the display panel.

The circuit structure of the temperature-compensated driving voltage of this patent changes the ideal driving voltage value required for the liquid crystal for the characteristics of the liquid crystal at different temperatures. In order to detect the temperature of the panel, it is necessary to establish a plurality of temperature sensors around the panel, which will cost more to purchase the IC. The architecture proposed by this patent requires the circuit of the register, the comparator and the voltage controller. More complicated, if you want to save the cost of buying IC, the circuit and the panel together on the glass, the required circuit layout area will be too large, it is difficult to apply to the display of the narrow frame.

In addition, a display driving circuit with a temperature compensation circuit is disclosed in U.S. Patent No. 7,038,654 B2. The circuit structure mainly describes the temperature sensing circuit sensing the temperature, and the driving circuit can automatically adjust the driving voltage of the liquid crystal at different temperatures via the control circuit, the reference voltage circuit, the boosting circuit and the comparator.

However, the temperature detecting circuit in this patent uses an operational amplifier OP1 and two resistors (R1 and R2) to output a voltage to two diodes (D1 and D2) of a current source in series, due to the voltage of the diode. The drop will change with temperature, so the voltage output to the op amp OP2 will vary with temperature, but the DC current flowing through the two diodes will result in a large static power consumption. In addition, in order to save the cost of purchasing IC, the circuit of this patent is simultaneously fabricated on the glass together with the panel, and the required circuit layout area is too large and consumes power.

Accordingly, the present invention provides a temperature sensing circuit and a driving circuit to enable a liquid crystal display panel to obtain good picture quality at different ambient temperatures.

It is an object of the present invention to provide a temperature sensing circuit that can be integrated into a GOA (gate on array) to enable a liquid crystal display panel to obtain good picture quality at different ambient temperatures, and to drive the environment by sensing the ambient temperature. The circuit adjusts the level of the driving signal driving the liquid crystal display panel at different ambient temperatures to obtain good picture quality.

The invention provides a temperature sensing circuit comprising a switching circuit, a charging circuit and a determining circuit. The switching circuit receives a supply voltage to generate a switching signal. The charging circuit is coupled to the switching circuit and receives the supply voltage, and the switching signal controls the charging circuit to generate a voltage signal according to the supply voltage. The determining circuit is coupled to the charging circuit, and the determining circuit generates a determining signal according to the level of the voltage signal, wherein the level of the switching signal and the voltage signal is related to a temperature state, and the determining signal indicates the temperature state.

The invention provides a driving circuit comprising a switching circuit, a charging circuit, a determining circuit, a selector, a one-bit converter and a gate driving circuit. The switching circuit receives a supply voltage to generate a switching signal. The charging circuit is coupled to the switching circuit and receives the supply voltage, and the switching signal controls the charging circuit to generate a voltage signal according to the supply voltage. The determining circuit is coupled to the charging circuit, and the determining circuit generates a determining signal according to the level of the voltage signal, wherein the level of the switching signal and the voltage signal is related to a temperature state, and the determining signal indicates the temperature state. The selector is coupled to the determining circuit and receives the plurality of first voltage signals and the plurality of second voltage signals, and the level of each of the first voltage signals is greater than the level of each of the second voltage signals, and the selector selects the One of the first voltage signals and one of the second voltage signals are output. The level converter is coupled to the selector, and the level converter adjusts the voltage levels of the plurality of control signals according to the first voltage signal and the second voltage signal output by the selector. The gate driving circuit is coupled to the level converter, and the gate driving circuit generates a plurality of gate driving signals to drive a display panel according to the control signals that have been adjusted.

10‧‧‧ Temperature sensing circuit
101‧‧‧Switch circuit
102‧‧‧Charging circuit
1021‧‧‧First charging unit
1022‧‧‧Second charging unit
103‧‧‧Judgement circuit
1031‧‧‧Comparative circuit
15‧‧‧Data Drive Circuit
17‧‧‧ gate drive circuit
20‧‧‧Drive circuit
204‧‧‧Selector
2041‧‧‧First multiplexer
20411‧‧‧Selection circuit
20412‧‧‧ Charge pump circuit
20413‧‧‧Control circuit
2042‧‧‧Second multiplexer
205‧‧ ‧ level converter
30‧‧‧ display panel
C1‧‧‧first capacitor
C2‧‧‧second capacitor
C3‧‧‧ third capacitor
C4~C8‧‧‧ capacitor
CLK‧‧‧ first clock signal
CLK'‧‧‧ third clock signal
H _O ‧‧‧First voltage signal
INV1‧‧‧First Inverter
INV2‧‧‧Second inverter
INV3‧‧‧Inverter
L _O ‧‧‧second voltage signal
M1‧‧‧first transistor
M2‧‧‧second transistor
M3‧‧‧ third transistor
M4‧‧‧ fourth transistor
M5‧‧‧ fifth transistor
M6‧‧‧ sixth transistor
M7‧‧‧ seventh transistor
M8‧‧‧ eighth transistor
M9~M14‧‧‧O crystal
M15‧‧‧First protection transistor
M16~M21‧‧‧O crystal
M22‧‧‧Second protective transistor
M23‧‧‧O crystal
M24‧‧‧First choice transistor
M25‧‧‧Second choice transistor
M26‧‧‧ Third choice transistor
M27‧‧‧ fourth choice transistor
M28~M35‧‧‧O crystal
Mi‧‧‧judgment signal
Mi'‧‧‧judgment signal
VDD‧‧‧ supply voltage
V _det ‧‧‧Detection signal
V _G ‧‧‧ gate drive signal
V _GH1 ‧‧‧ voltage signal
V _GH2 ‧‧‧ voltage signal
V _GL1 ‧‧‧ voltage signal
V _GL2 ‧‧‧ voltage signal
V _out ‧‧‧ voltage signal
V _reset ‧‧‧Reset signal
VST‧‧‧ start signal
V _sample ‧‧‧Sampling signal
V _sample1 ‧‧‧first sampling signal
V _sample2 ‧‧‧Second sampling signal
V _sel1 ‧‧‧Selection signal
V _sel2 ‧‧‧Selection signal
V _sw ‧‧‧ switch signal
V _sw1 ‧‧‧first switching signal
V _sw2 ‧‧‧second switch signal
XCLK‧‧‧second clock signal
XCLK'‧‧‧ fourth clock signal

1 is a block diagram showing a temperature sensing circuit applied to a driving circuit of the present invention;
2 is a circuit diagram of an embodiment of a temperature sensing circuit of the present invention;
3A is a circuit diagram of another embodiment of a temperature sensing circuit of the present invention;
Figure 3B is a timing diagram of Figure 3A;
4 is a circuit diagram of an embodiment of a driving circuit of the present invention;
Figure 5 is a circuit diagram of a first multiplexer of a driving circuit of the present invention;
Figure 6 is a circuit diagram of a second multiplexer of the driving circuit of the present invention;
7A is a circuit diagram of a level converter of a driving circuit of the present invention; and FIG. 7B is a waveform diagram of a level converter of the driving circuit of the present invention.

For a better understanding and understanding of the structural features and the achievable effects of the present invention, the preferred embodiments and the detailed description are as follows:

As shown in FIG. 1, this figure is a block diagram of a temperature sensing circuit 10 applied to a driving circuit according to the present invention. As can be seen from the figure, the temperature sensing circuit 10 is built around the display panel 30, and the temperature sensing circuit 10 can push the associated driving circuit to adjust the level of the driving signal by detecting the temperature change around the display panel 30. Such as a data driver circuit (Source driver) 15 and a gate driver circuit (Gate driver) 17. The temperature sensing circuit 10 senses the ambient temperature of the display panel 30, thereby determining whether the temperature state around the display panel 30 is a first temperature state (also referred to as a high temperature state) or a second temperature state (also referred to as a low temperature state), A temperature state is higher than the second temperature state, and the operation principle of the temperature sensing circuit 10 is as follows.

Referring to FIG. 2, a circuit diagram of an embodiment of temperature sensing circuit 10 is shown. As shown in the figure, the temperature sensing circuit 10 includes a switching circuit 101, a charging circuit 102 coupled to the switching circuit 101, and a determining circuit 103 coupled to the charging circuit 102.

The switch circuit 101 includes a first transistor M1, a second transistor M2, and a first capacitor C1. One of the gates of the first transistor M1 receives a supply voltage VDD together with a drain, and one of the second transistors M2 is coupled to one of the sources of the first transistor M1, and one of the second transistors M2 The gate receives a reset signal V _reset , and one source of the second transistor M2 is coupled to a ground. The first end of the first capacitor C1 is coupled to the source of the first transistor M1 and the second transistor M2. The second end of the first capacitor C1 is coupled to the ground.

The charging circuit 102 includes a charging unit 1021. The charging unit 1021 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a second capacitor C2. One of the third transistors M3 receives the supply voltage VDD, one of the third transistors M3 receives a sampling signal V _sample , and one of the fourth transistors M4 is coupled to one of the third transistors M3 One of the fourth transistors M4 is coupled to the first capacitor C1, and one of the fifth transistors M5 is coupled to one of the fourth transistors M4, and one of the fifth transistors M5 is reset. a signal V _reset , a source of the fifth transistor M5 is coupled to the ground, and a first end of the second capacitor C2 is coupled to the source of the fourth transistor M4 and the drain of the fifth transistor M5, and The second end of one of the two capacitors C2 is coupled to the ground.

The determining circuit 103 includes a comparing circuit 1031 and a transistor M9. One of the transistors M9 is coupled to an input end of the comparing circuit 1031, and one of the gates of the transistor M9 receives a detecting signal V _det , the transistor M9 One source is coupled to the first end of the second capacitor C2.

When the supply voltage VDD is applied to the gate and drain of the first transistor M1, the first transistor M1 is turned on, and the second transistor M2 is turned off by receiving the reset signal V _{reset of the} logic low state. In the case where the first transistor M1 is turned on and the second transistor M2 is turned off, the supply voltage VDD charges the first capacitor C1 via the first transistor M1 to generate a switching signal _Vsw . Since the intensity of the current flowing through the first transistor M1 is affected by the temperature, the speed at which the first capacitor C1 is charged is affected by the temperature, so the level of the switching signal V _sw is related to the temperature state.

Thereafter, the third transistor M3 receives the sampling signal V _{sample of the} logic high state and is turned on. The fourth transistor M4 is turned on by receiving the switching signal V _{sw of the} logic high state. The fifth transistor M5 is turned off by receiving the reset signal V _{reset of the} logic low state.

When the third transistor M3 and the fourth transistor M4 are turned on and the fifth transistor M5 is turned off, the supply voltage VDD charges the second capacitor C2 via the third transistor M3 and the fourth transistor M4, and A voltage signal V _{out is} generated. Since the intensity of the current flowing through the third transistor M3 is affected by the temperature, and the degree of conduction of the fourth transistor M4 is determined by the level of the switching signal V _sw , and the level of the switching signal V _sw is related to the temperature state, the second capacitor C2 is charged i.e. velocity is temperature dependent, thus the bit signal voltage V _out at a temperature of the quasi-coherent state.

The transistor M9 in the determination circuit 103 receives the detection signal V _{det of the} logic high state and is turned on, and the voltage signal V _{out of the} charging circuit 102 is transmitted to the comparison circuit 1031 of the determination circuit 103. The comparison circuit 1031 compares the level of the voltage signal V _out with a reference level to generate a determination signal Mi, and the determination signal Mi represents the current temperature state.

In one embodiment of the present invention, the transistors used in the temperature sensing circuit 10 are all amorphous germanium film transistors, but other transistors having an N-type semiconductor type can also be used. The switching signal V _sw generated by the first capacitor C1 and the voltage signal V _out generated by the second capacitor C2 may differ depending on the ambient temperature. In other words, at high temperature surroundings panel display 30, and the switching signal V _sw bit signal voltage V _out of registration will be higher. On the other hand, when the display panel is low temperature surroundings 30 of the switching signal V _sw to the level of the voltage signal V _out will be relatively low.

In the above, when the temperature state around the display panel 30 is the first temperature state (high temperature state), the level of the voltage signal V _out will be higher, so the level of the voltage signal V _out will exceed the reference level, so the comparison circuit The level of the judgment signal Mi generated by 1031 is a high level, and the current temperature state is a first temperature state, that is, a high temperature state.

In contrast, when the temperature state around the display panel 30 is the second temperature state (low temperature state), the level of the voltage signal V _out will be lower, so the level of the voltage signal V _out will not exceed the reference level. Thus, the level of the determination signal Mi generated by the comparison circuit 1031 is a low level, and the current temperature state is a second temperature state, that is, a low temperature state.

Furthermore, since the comparison circuit 1031 of the present invention employs a digital logic circuit of four inverters, the determination signal Mi generated by the comparison circuit 1031 is a digital signal. The four inverters 1031 are composed of transistors, so that the four inverters 1031 provide a reference level and are compared with the voltage signal V _out . The use of an inverter as a comparison circuit is a well-known technique, so it will not be described in detail herein. The comparison circuit 1031 using the comparator invention can also be implemented, level comparator receives the reference voltage signal V _out, for comparison, to generate a determination signal Mi.

Please refer to FIG. 3A, which is a circuit diagram of another embodiment of the temperature sensing circuit 10 of the present invention. In addition to the first charging unit 1021, the charging circuit 102 further includes a second charging unit 1022, which includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a third capacitor. C3. One of the sixth transistors M6 receives the supply voltage VDD, one of the sixth transistors M6 receives a second sampling signal V _sample2 , and one of the seventh transistors M7 is coupled to one of the sixth transistors M6 a source, a gate of the seventh transistor M7 is coupled to the second capacitor C2, one of the eighth transistors M8 is coupled to one source of the seventh transistor M7, and one of the eighth transistors M8 is received by the gate. reset signal V _reset, one of the eighth transistor M8 source coupled to the ground, one end of the third capacitor C3 is coupled to a first power source transistor M7 of the seventh electrode and the eighth electrode electrically drain of M8 crystal, And a second end of the third capacitor C3 is coupled to the ground end.

Please refer to FIG. 3A and FIG. 3B together. FIG. 3B is a timing diagram of the temperature sensing circuit 10 of FIG. 3A detecting the temperature change around the display panel 30.

During T1, when the supply voltage VDD is applied to the gate and drain of the first transistor M1, the first transistor M1 is turned on, and the second transistor M2 is turned off by receiving the reset signal V _{reset of the} logic low state. .

In a case where the first transistor M1 is turned on and the second transistor M2 is turned off, the supply voltage VDD charges the first capacitor C1 via the first transistor M1 to generate a first switching signal V _sw1 , the first switch The level of the signal V _sw1 is related to the temperature state.

During T2, the third transistor M3 receives a first sampling signal V _sample1 in a logic high state and is turned on, and the fourth transistor M4 receives the first switching signal V _{sw1 in a} logic high state to be turned on, and the fifth transistor The crystal M5 is turned off by receiving the reset signal V _{reset of the} logic low state. At this time, the supply voltage VDD charges the second capacitor C2 via the third transistor M3 and the fourth transistor M4 to generate a second switching signal V _sw2 , and the level of the second switching signal V _sw2 is related to the temperature state.

During T3, the sixth transistor M6 receives the second sampling signal V _{sample2 of the} logic high state and is turned on, and the seventh transistor M7 receives the second switching signal V _sw2 of the logic high state generated by the second capacitor C2. And turned on, and the eighth transistor M8 receives the logic low state reset signal V _reset and is turned off. Therefore, the supply voltage VDD charges the third capacitor C3 via the sixth transistor M6 and the seventh transistor M7 to generate a voltage signal V _out , and the level of the voltage signal V _out is related to the temperature state.

During the period T4, the transistor M9 in the judging circuit 103 receives the detection signal V _{det of the} logic high state and is turned on, and the voltage signal V _{out of the} charging circuit 102 is transmitted to the comparison circuit 1031 of the judging circuit 103. The comparison circuit 1031 compares the level of the voltage signal V _out with the reference level to generate the determination signal Mi, so that the current temperature state can be known based on the determination signal Mi. During T5, transistors M2, M5, and M8 receive a logic high state reset signal V _reset and are turned on to discharge capacitors C1, C2, and C3 for the next temperature detection.

This embodiment uses the first charging unit 1021 and the second charging unit 1022 to generate a voltage signal V _out . The level of the voltage signal V _out is more affected by the temperature, so that the current temperature state can be accurately detected according to the level of the voltage signal V _out .

When the temperature sensing circuit 10 of the present invention is integrated with the GOA, the display panel 30 can obtain good picture quality at different ambient temperatures. FIG. 4 is a circuit diagram of an embodiment of the driving circuit 20 according to the present invention. The drive circuit 20 includes a switch circuit 101, a charge circuit 102, a determination circuit 103, a selector 204, a one-bit converter 205, and a gate drive circuit 17. The switching circuit 101, the charging circuit 102, and the determining circuit 103 of the driving circuit 20 are the temperature sensing circuit 10, so the connection and operation mode of the circuit are not described herein. The selector 204 and the level shifter 205 may be integrated in the temperature sensing circuit 10, or the selector 204 and the level converter 205 may be integrated in the gate driving circuit 17. The following is a description of the three circuits of the selector 204, the level converter 205 and the gate drive circuit 17:

The selector 204 is coupled to the determining circuit 103 and receives a plurality of first voltage signals V _GH1 and V _GH2 , and a plurality of second voltage signals V _GL1 and V _GL2 , wherein the level of the first voltage signal V _GH1 is greater than the first voltage signal V _GH2 of the level, the bit of the second voltage signal V _GL1 registration signal is less than the voltage level V _GL2 of the second, the plurality of first voltage signal V _GH1 and V _GH2 are greater than the level of the plurality of second signal voltage V _GL1 And the level of V _GL2 . In this embodiment, the level of the first voltage signal V _GH1 is 29V, the level of the first voltage signal V _GH2 is 25V, the level of the second voltage signal V _GL1 is -4V, and the second voltage signal V _GL2 The level is 0V. The selector 204 selects the first voltage signal V _GH1 or V _GH2 as a first voltage signal H _O according to the determination signal Mi, and selects the second voltage signal V _GL1 or V _GL2 as a second voltage signal L according to the determination signal _{Mi. O} and output.

The level converter 205 is coupled to the selector 204. The level converter 205 adjusts the voltage levels of the plurality of control signals according to the first voltage signal H _O and the second voltage signal L _O output by the selector 204. In this embodiment, the control signals are the first clock signal CLK and the second clock signal XCLK, which are used to provide to the gate driving circuit 17, and generate a plurality of gate driving signals V _G . In this embodiment, the level of the second clock signal XCLK is inverted to the first clock signal CLK, and the level of the two is 0V~25V. The level converter 205 adjusts the voltage levels of the first clock signal CLK and the second clock signal XCLK according to the first voltage signal H _O and the second voltage signal L _O to generate a third clock signal CLK′ and the first Four clock signal XCLK'.

The level converter 205 adjusts the high voltage level of the first clock signal CLK and the second clock signal XCLK to the first voltage signal H _O , and adjusts the low of the first clock signal CLK and the second clock signal XCLK. The voltage level is to the second voltage signal L _O . In other words, the high voltage level of the third clock signal CLK' and the fourth clock signal XCLK' is the first voltage signal H _O , and the low voltage bits of the third clock signal CLK′ and the fourth clock signal XCLK′ It is quasi-second voltage signal L _O . The gate driving circuit 17 is coupled to the level converter 205, and the gate driving circuit 17 receives the adjusted control signal, that is, the third clock signal CLK' and the fourth clock signal XCLK', to generate the gate driving signal V. _G to drive the display panel 30.

When the temperature state around the display panel 30 is the first temperature state (high temperature state), the selector 204 outputs the first voltage signal V _GH2 (25V) as the first voltage signal H _O and the output second voltage signal V _GL2 (0V) ) as the second voltage signal L _O . When the temperature state around the display panel 30 is the second temperature state (low temperature state), the selector 204 outputs the first voltage signal V _GH1 (29V) as the first voltage signal H _O and the output second voltage signal V _GL1 (- 4V) as the second voltage signal L _O .

As can be seen from the above, when the temperature state around the display panel 30 is the second temperature state (low temperature state), the level converter 205 raises the high voltage level of the first clock signal CLK and the second clock signal XCLK (25V). And to the first voltage signal H _O (29V), and to reduce the low voltage level (0V) of the first clock signal CLK and the second clock signal XCLK to the second voltage signal L _O (-4V). In other words, the level of the third clock signal CLK' and the fourth clock signal XCLK' is -4V~29V, that is, the potential voltage difference between the third clock signal CLK' and the fourth clock signal XCLK' is large. Thus, the gate driving circuit 17 has a larger potential difference between the gate driving signal V _G generated by the third clock signal CLK′ and the fourth clock signal XCLK′, which improves the driving capability to compensate for the low temperature. A good picture quality is obtained by the effect of lowering the mobility of the transistor.

The selector 204 includes a first multiplexer 2041 and a second multiplexer 2042. 5 is a circuit diagram of the first multiplexer 2041 of the driving circuit of the present invention. The first multiplexer 2041 includes a selection circuit 20411, a charge pump circuit 20412, and a control circuit 20413. The selection circuit 20411 is coupled to the first voltage signals V _GH1 and V _GH2 and selects one of the first voltage signals V _GH1 and V _GH2 for output. The charge pump circuit 20412 is coupled to the selection circuit 20411 and generates selection signals V _sel1 and V _sel2 . The selection circuit 20411 selects one of the first voltage signals V _GH1 and V _GH2 according to the selection signal V _sel1 or V _sel2 to output. The control circuit 20413 is coupled to the charge pump circuit 20412 and controls the charge pump circuit 20412 according to the determination signal Mi.

Further, the selection circuit 20411 includes a plurality of selection transistors M24 and M25, and one of the first selection transistors M24 is coupled to the first voltage signal V _GH1 (for example, 29V) and one of the second selection transistors M25. The pole is coupled to the first voltage signal V _GH2 (for example, 25V), and one gate of the first selection transistor M24 and one gate of the second selection transistor M25 are respectively coupled to the charge pump circuit 20412, and respectively Controlled by the selection signal V _sel1 or V _sel2 to control the first selection transistor M24 to output the first voltage signal V _GH1 to one of the sources, or to control the second selection transistor M25 to output the first voltage signal V _GH2 Source.

The charge pump circuit 20412 includes a plurality of transistors M10-M12 and M17-M19 and a plurality of capacitors C4-C7. Wherein, the transistor M17 to the transistor M19 are connected together in series, and the transistors M10 to M12 are also connected together in series. One of the gates of the transistor M10 receives a supply voltage VDD from a gate, and a source of the transistor M12 is coupled to the gate of the first selection transistor M24 and generates a selection signal V _sel1 . One of the gates of the transistor M17 receives a supply voltage VDD from a gate, and a source of the transistor M19 is coupled to the gate of the second selection transistor M25 and generates a selection signal V _sel2 . A first end of the capacitor C4 is coupled between a source of the transistor M10 and a drain of the transistor M11. A first end of the capacitor C5 is coupled between a source of the transistor M11 and one of the drains of the transistor M12. A first end of the capacitor C6 is coupled between a source of the transistor M17 and a drain of the transistor M18. A first end of the capacitor C7 is coupled between a source of the transistor M18 and a drain of the transistor M19.

The control circuit 20413 includes a plurality of transistors M13, M14, M16, M20, M21, and M23, and a first inverter INV1. One source of the transistor M14 and one source of the transistor M21 are used to receive the first clock signal CLK. One of the transistors M14 is coupled to one of the second ends of the capacitor C5, and one of the transistors M21 is coupled to the second end of the capacitor C7. One source of the transistor M13 and one source of the transistor M20 are used to receive the second clock signal XCLK. One of the transistors M13 is coupled to one of the second ends of the capacitor C4, and one of the transistors M20 is coupled to the second end of the capacitor C6. One of the gates of the transistor M20 and one of the gates of the transistor M21 receives the determination signal Mi.

An input terminal of the first inverter INV1 receives the determination signal Mi. An output of the first inverter INV1 is coupled to one of the gates of the transistor M13 and one of the gates of the transistor M14. One of the gates of the transistor M16 is coupled to the source of the transistor M12 of the charge pump circuit 20412 and the gate of the first selection transistor M24 of the selection circuit 20411. One source of the transistor M16 is coupled to the ground, and one of the gates of the transistor M16 receives the determination signal Mi. One of the gates of the transistor M23 is coupled to the source of the transistor M19 of the charge pump circuit 20412 and the gate of the second selection transistor M25 of the selection circuit 20411. One source of the transistor M23 is coupled to the ground, and one of the gates of the transistor M23 is coupled to the output of the first inverter INV1.

When the temperature state around the display panel 30 is the first temperature state (high temperature state), the state of the determination signal Mi generated by the temperature sensing circuit 10 (shown in FIG. 4) is a logic high state. The transistors M16, M20, and M21 receive the logic high state determination signal Mi and are turned on. The first inverter INV1 inverts the logic high state determination signal Mi and outputs a logic low state determination signal Mi'. The transistors M13, M14, and M23 are turned off by receiving the logic low state determination signal Mi'. At this time, since the transistor M16 is turned on, the gate of the first selection transistor M24 is coupled to the ground, so that the voltage of the gate of the first selection transistor M24 is discharged to the ground, that is, the first selection The crystal M24 is turned off, which means that the control circuit 20413 turns off the first selection transistor M24 in accordance with the determination signal Mi of the logic high state.

In contrast, the transistor M23 is turned off, so the gate of the second selection transistor M25 is not coupled to the ground, so that the second selection transistor M25 is controlled by the selection signal V _sel2 . When the transistors M20 and M21 of the control circuit 20413 are in an on state, the supply voltage VDD charges the capacitors C6 and C7 to generate a logic high state selection signal V _sel2 and is supplied to the gate of the second selection transistor M25, so that The second selection transistor M25 is turned on, thereby outputting the first voltage signal V _GH2 as the first voltage signal H _O to be supplied to the level converter 205 shown in FIG. As can be seen from the above description, when the temperature state around the display panel 30 is the first temperature state (high temperature state), the control circuit 20413 controls the selection circuit 20411 to output the first voltage signal V _{GH2 having a} lower level according to the determination signal Mi. The level of the first voltage signal V _GH2 (for example, 25V) is lower than the level of the first voltage signal V _GH1 (for example, 29V).

When the temperature state around the display panel 30 is the second temperature state (low temperature state), the state of the determination signal Mi generated by the temperature sensing circuit 10 (shown in FIG. 4) is a logic low state. The transistors M16, M20, and M21 receive the logic low state determination signal Mi and are turned off. The first inverter INV1 inverts the logic low state determination signal Mi and outputs a logic high state determination signal Mi'. The transistors M13, M14, and M23 are turned on by receiving the logic high state determination signal Mi'. Since the transistor M23 is turned on, the gate of the second selection transistor M25 is coupled to the ground, so that the second selection transistor M25 is turned off, which means that the control circuit 20413 is turned off according to the logic high state determination signal Mi. Second, choose transistor M25.

In contrast, the transistor M16 is turned off, so the gate of the first selection transistor M24 is not coupled to the ground, so that the first selection transistor M24 is controlled by the selection signal V _sel1 . When the transistors M13 and M14 of the control circuit 20413 are in an on state, the supply voltage VDD charges the capacitors C4 and C5 to generate a logic high state selection signal V _sel1 and is supplied to the gate of the first selection transistor M24, so that The first selection transistor M24 is turned on, thereby outputting the first voltage signal V _GH1 as the first voltage signal H _O to be supplied to the level converter 205 shown in FIG. As can be seen from the above description, when the temperature state around the display panel 30 is the second temperature state (low temperature state), the control circuit 20413 controls the selection circuit 20411 to output the first voltage signal V _{GH1 having a} higher level according to the determination signal Mi. The level of the first voltage signal V _GH1 (for example, 29V) is higher than the level of the first voltage signal V _GH2 (for example, 25V).

It can be seen from the above that when the determination signal Mi generated by the temperature sensing circuit 10 (shown in FIG. 4) indicates that the temperature state is the first temperature state (high temperature state), the first multiplexer 2041 is based on the determination signal Mi. The first voltage signal V _GH2 is selected, that is, the first voltage signal having the lowest voltage level is selected. When the determination signal Mi generated by the temperature sensing circuit 10 indicates that the temperature state is the second temperature state (low temperature state), the first multiplexer 2041 selects the first voltage signal V _GH1 according to the determination signal Mi, that is, selects the highest voltage. The first voltage signal of the level.

The determination signal Mi of the present invention can also directly control the selection circuit 20411 of the first multiplexer 2041 to output the first voltage signal V _GH1 or V _GH2 . However, if the level of the signal Mi is lower than the level of the first voltage signal V _GH1 or V _{GH2 ,} the level of the first voltage signal H _O output by the selection circuit 20411 is determined by the first selection transistor M24 of the selection circuit 20411. And falling with the threshold voltage of the second selection transistor M25, such that the level of the first voltage signal H _O is lower than the level of the first voltage signal V _GH1 or V _GH2 . By the charge pump circuit 20412 generates a selection signal having a V _sel2 V _sel1 and high level of the selection signal V _sel1 registration level equal to or above a first voltage signal V _GH1, the selection signal is equal to or a quasi V _sel2 It is higher than the level of the first voltage signal V _GH2 . Thus, the level of the first voltage signal H _O output by the first selection transistor M24 is equal to the level of the first voltage signal V _GH1 , and the level of the first voltage signal H _O output by the second selection transistor M25 is equal to The level of the first voltage signal V _GH2 .

In addition, since the levels of the selection signals V _sel1 and V _sel2 of the first selection transistor M24 and the second selection transistor M25 are controlled, the gate of the first selection transistor M24 and the second selection transistor M25 are coupled. The voltage difference between the drain and the source of the gate transistors M16 and M23 is large, so that the characteristics of the transistors M16 and M23 are easily deteriorated.

Therefore, the first multiplexer 2041 of the present invention further includes a first protection transistor M15 coupled between the first selection transistor M24 and the control circuit 20413. A second protection transistor M22 is coupled between the second selection transistor M25 and the control circuit 20413. The voltage received by the drains of the transistors M16 and M23 can be reduced by the first protection transistor M15 and the second protection transistor M22, thus reducing the voltage difference between the drain and the source of the transistors M16 and M23. One of the first protection transistors M15 is coupled to the gate of the first selection transistor M24 and the source of the transistor M12. One of the gates of the first protection transistor M15 receives the supply voltage VDD, and the first protection transistor M15 One source is coupled to the drain of the transistor M16. One of the second protection transistors M22 is coupled to the gate of the second selection transistor M25 and the source of the transistor M19, and one of the gates of the second protection transistor M22 receives the supply voltage VDD, and the second protection transistor M22 One source is coupled to the drain of the transistor M23.

Please refer to FIG. 6, which is a circuit diagram of the second multiplexer 2042. The second multiplexer 2042 includes a third selection transistor M26, a fourth selection transistor M27, a transistor M28, a transistor M29, and a second inverter INV2. Wherein, one of the third selection transistors M26 receives the second voltage signal V _GL1 (taking -4V as an example), and one of the third selection transistors M26 receives the supply voltage VDD, and one of the fourth selection transistors M27 The drain receives the second voltage signal V _GL2 (taking 0V as an example), one of the fourth selection transistors M27 receives the supply voltage VDD, and one of the third selection transistor M26 and one of the fourth selection transistors M27 The sources are coupled together for outputting the second voltage signal V _GL1 or V _GL2 as the second voltage signal L _O to be provided to the level converter 205 shown in FIG. One of the gates of the transistor M28 is coupled to the gate of the third selection transistor M26. One of the gates of the transistor M28 receives the determination signal Mi, and the transistor M28 is controlled by the determination signal Mi. One source of the transistor M28 is coupled. Connect to ground. One of the gates of the transistor M29 is coupled to the gate of the fourth selection transistor M27. One of the gates of the transistor M29 is coupled to one of the outputs of the second inverter INV2, and one of the sources of the transistor M29 is coupled to the ground. One of the inputs of the inverter INV2 receives the determination signal Mi, and the determination signal Mi is inverted, and a determination signal Mi' is generated to control the transistor M29.

When the temperature state around the display panel 30 is the first temperature state (high temperature state), the transistor M28 is turned on by receiving the logic high state determination signal Mi generated by the temperature sensing circuit 10 (shown in FIG. 4). At this time, the gate of the third selection transistor M26 is coupled to the ground, so the voltage of the gate of the third selection transistor M26 is discharged to the ground, so that the third selection transistor M26 is turned off.

On the other hand, the second inverter INV2 inverts the determination signal Mi of the logic high state, and outputs the determination signal Mi' of the logic low state. The transistor M29 receives the logic low state determination signal Mi' and is turned off, and the fourth selection transistor M27 is turned on by the supply voltage VDD, so that the source of the fourth selection transistor M27 outputs the second voltage signal V _GL2 as The second voltage signal L _O is provided to the level converter 205 shown in FIG. As can be seen from the above description, when the temperature state around the display panel 30 is the first temperature state (high temperature state), the second multiplexer 2042 turns on the fourth selection transistor M27 according to the determination signal Mi, and the output level is higher. Two voltage signals V _GL2 . The level of the second voltage signal V _GL2 (taking 0V as an example) is higher than the level of the second voltage signal V _GL1 (for example, -4V).

When the temperature state around the display panel 30 is the second temperature state (low temperature state), the transistor M28 receives the determination signal Mi of the logic low state generated by the temperature sensing circuit 10 and is turned off. Therefore, the third selection transistor M26 is turned on by the supply voltage VDD, and the source of the third selection transistor M26 outputs the second voltage signal V _GL1 as the second voltage signal L _O to be provided to the bit shown in FIG. Quasi-converter 205.

On the other hand, the second inverter INV2 inverts the determination signal Mi of the logic low state, and outputs the determination signal Mi' of the logic high state. The transistor M29 receives the determination signal Mi' of the logic high state and is turned on. At this time, the gate of the fourth selection transistor M27 is coupled to the ground, so the fourth selection transistor M27 is turned off. It can be seen from the above description that when the temperature state around the display panel 30 is the second temperature state (low temperature state), the second multiplexer 2042 turns on the third selection transistor M26 according to the determination signal Mi, and the output level is lower. Two voltage signals V _GL1 . The level of the second voltage signal V _GL1 (for example, -4V) is lower than the level of the second voltage signal V _GL2 (for example, 0V).

It can be seen from the above that when the determination signal Mi generated by the temperature sensing circuit 10 indicates that the temperature state is the first temperature state (high temperature state), the second multiplexer 2042 selects the second voltage signal V _GL2 according to the determination signal _Mi. That is, the second voltage signal having the highest voltage level is selected. When the determination signal Mi generated by the temperature sensing circuit 10 indicates that the temperature state is the second temperature state (low temperature state), the second multiplexer 2042 selects the second voltage signal V _GL1 according to the determination signal Mi, that is, the selection has the lowest The second voltage signal of the voltage level.

In short, as shown in the following Table 1, when the temperature state around the display panel 30 is the first temperature state (high temperature state), the first multiplexer 2041 of the selector 204 outputs the first voltage signal V _GH2 (25V). As the first voltage signal H _O , the second multiplexer 2042 of the selector 204 outputs the second voltage signal V _GL2 (0V) as the second voltage signal L _O . When the temperature state around the display panel 30 is the second temperature state (low temperature state), the first multiplexer 2041 outputs the first voltage signal V _GH1 (29V) as the first voltage signal H _O , and the second multiplexer 2042 The second voltage signal V _GL1 (-4V) is output as the second voltage signal L _O .
Table 1

The selector 204 outputs the first voltage signal H _O and the second voltage signal L _O to the level shifter 205, and the level converter 205 outputs the output according to the first multiplexer 2041 and the second multiplexer 2042 of the selector 204. The first voltage signal H _O and the second voltage signal L _O adjust the voltage level of the control signal, for example, the voltage level of the first clock signal CLK and the second clock signal XCLK, and the voltage level of the first clock signal CLK Quasi-inverted to the voltage level of the second clock signal XCLK.

Please refer to FIG. 7A, which is a circuit diagram of a level converter 205 of the driving circuit of the present invention. The level converter 205 includes a plurality of transistors M30 to M35 and a capacitor C8. The following is an example in which the temperature state around the display panel 30 is the second temperature state (low temperature state), and the level converter 205 adjusts the voltage level of the first clock signal CLK (0V~25V) and the second time. The voltage level of the pulse signal XCLK (25V~0V) generates a third clock signal CLK' (-4V~29V) and a fourth clock signal XCLK' (29V~-4V).

When the temperature state around the display panel 30 is a low temperature state, as shown in Table 1, the selector 204 outputs the first voltage signal V _GH1 (29V) and the second voltage signal V _GL1 (-4V) as the first voltage signal H _{O .} And the second voltage signal L _O is transmitted to the level shifter 205. Thus, the level of the first voltage signal H _O received by the drains of the transistors M30, M32 and M34 is 29V, and the level of the second voltage signal L _O received by the sources of the transistors M31, M33 and M35 is - 4V. One source of the transistor M30 is coupled to one of the drains of the transistor M31, one source of the transistor M32 is coupled to one of the drains of the transistor M33, and one source of the transistor M34 is coupled to one of the gates of the transistor M35. . One of the gates of the transistor M31 and one of the gates of the transistor M32 receives the first clock signal CLK. One of the gates of the transistor M30 and one of the gates of the transistor M33 receives the second clock signal XCLK. One of the gates of the transistor M34 is coupled to the source of the transistor M32 and the drain of the transistor M33. One of the gates of the transistor M35 is coupled to the source of the transistor M30 and the drain of the transistor M31. The capacitor C8 is coupled between the gate of the transistor M34 and the source of the transistor M34.

When the level of the first clock signal CLK is 0V and the level of the second clock signal XCLK is 25V, the states in which the transistors M30 to M35 are turned on/off are as shown in Table 2. The output terminal Out outputs a third clock signal CLK'.
Table 2

When the level of the first clock signal CLK is 25V and the level of the second clock signal XCLK is 0V, the state in which the transistors M30 to M35 are turned on/off is as shown in the following table 3.
table 3


As can be seen from Table 2, Table 3, and FIG. 7B, the level of the first clock signal CLK is 0V~25V, and is adjusted by the level converter 205, and is -4V~29V, that is, the voltage level of the third clock signal CLK'. The standard is -4V~29V.

The voltage level of the second clock signal XCLK is inverted to the voltage level of the first clock signal CLK. For example, when the voltage level of the first clock signal CLK is low level 0V, the voltage of the second clock signal XCLK The level is high level 25V, so the voltage level of the fourth clock signal XCLK' is also reversed to the voltage level of the third clock signal CLK', for example, when the voltage level of the third clock signal CLK' is low. When the voltage is quasi-4V, the voltage level of the fourth clock signal XCLK' is a high level of 29V, so the level converter 205 further includes an inverter INV3, one input end of which is coupled to the output end Out, and the third end is received. The pulse signal CLK' generates a fourth clock signal XCLK' by inverting the third clock signal CLK'. Thus, the voltage level 25V~0V of the second clock signal XCLK is adjusted by the level converter 205 to be 29V~-4V, that is, the voltage level of the fourth clock signal XCLK' is 29V~-4V.

The gate driving circuit 17 receives the adjusted control signal, that is, the third clock signal CLK', the fourth clock signal XCLK', and a start signal VST as a trigger signal, to generate a plurality of gate driving signals V _G to The display panel 30 is driven. The above-mentioned start signal VST is provided by other circuits, such as a timing control circuit (not shown) or other circuits, which are common technologies in the art, and therefore will not be described in detail herein.

In summary, it can be seen from the foregoing embodiments that the temperature sensing circuit of the present invention can be used to sense the ambient temperature of the display panel. When the temperature becomes lower, the driving circuit can adjust the driving signal outputted to the display panel. The level of the pixel to a higher level allows the pixel film at low temperatures to be used at a higher level to compensate for the effect of lower mobility on the thin film transistor at lower temperatures. Similarly, when the temperature becomes higher, the driving circuit can lower the level of the driving signal output to the display panel to achieve low power consumption.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the claims of the present invention. All should be included in the scope of the patent application of the present invention.

10‧‧‧ Temperature sensing circuit

101‧‧‧Switch circuit

102‧‧‧Charging circuit

1021‧‧‧First charging unit

103‧‧‧Judgement circuit

1031‧‧‧Comparative circuit

C1‧‧‧first capacitor

C2‧‧‧second capacitor

M1‧‧‧first transistor

M2‧‧‧second transistor

M3‧‧‧ third transistor

M4‧‧‧ fourth transistor

M5‧‧‧ fifth transistor

M9‧‧‧O crystal

Mi‧‧‧judgment signal

VDD‧‧‧ supply voltage

V _det ‧‧‧Detection signal

Claims (16)

A temperature sensing circuit comprising:
a switching circuit receives a supply voltage to generate a switching signal, the level of the switching signal being related to a temperature state;
a charging circuit coupled to the switching circuit and receiving the supply voltage, the switching signal controlling the charging circuit to generate a voltage signal according to the supply voltage, the level of the voltage signal is related to the temperature state; and a determining circuit, The charging circuit is coupled to the determining circuit, and the determining circuit generates a determining signal according to the level of the voltage signal, and the determining signal indicates the temperature state. The temperature sensing circuit of claim 1, wherein the switching circuit comprises:
a first transistor receiving the supply voltage;
a second transistor coupled between the first transistor and a ground and controlled by a reset signal; and a first capacitor coupled to the first transistor and the second transistor Between a connection point and the ground terminal, wherein the supply voltage is charged to the first capacitor via the first transistor when the first transistor is turned on and the second transistor is turned off by the reset signal And generate the switch signal. The temperature sensing circuit of claim 2, wherein one of the gates of the first transistor receives the supply voltage in common with a drain, and one of the second transistors is coupled to the first a source of one of the transistors, the gate of the second transistor receiving the reset signal, one source of the second transistor is coupled to the ground, and the first end of the first capacitor is coupled to the first The source of the transistor and the drain of the second transistor, and the second end of the first capacitor is coupled to the ground. The temperature sensing circuit of claim 2, wherein the charging circuit comprises:
a third transistor receiving the supply voltage and controlled by a sampling signal;
a fourth transistor coupled to the third transistor and the first capacitor and controlled by the switching signal;
a fifth transistor coupled between the fourth transistor and the ground and controlled by the reset signal; and a second capacitor coupled to the fourth transistor and the fifth transistor Between a connection point and the ground, wherein the supply voltage is when the third transistor is turned on by the sampling signal, the fourth transistor is turned on by the switching signal, and the fifth transistor is turned off by the reset signal The second capacitor is charged by the third transistor and the fourth transistor to generate the voltage signal, and the degree of conduction of the fourth transistor is determined by the level of the switching signal. The temperature sensing circuit of claim 4, wherein one of the third transistors receives the supply voltage, and one of the third transistors receives the sampling signal, and the fourth transistor a drain is coupled to a source of the third transistor, a gate of the fourth transistor is coupled to the first capacitor and controlled by the switch signal, and one of the fifth transistors is coupled to the drain a source of one of the fourth transistors, the gate of the fifth transistor receiving the reset signal, one source of the fifth transistor is coupled to the ground, and the first end of the second capacitor is coupled The source of the fourth transistor is coupled to the drain of the fifth transistor, and the second end of the second capacitor is coupled to the ground. The temperature sensing circuit of claim 1, wherein the charging circuit comprises at least one charging unit. The temperature sensing circuit of claim 1, wherein the determining circuit comprises:
a comparison circuit that compares the level of the voltage signal with a reference level to generate the determination signal; and a transistor coupled between the charging circuit and the comparison circuit and controlled by a detection signal, wherein When the transistor is turned on by the detection signal, the voltage signal is transmitted to the comparison circuit via the transistor. The temperature sensing circuit of claim 1, wherein the temperature state comprises a first temperature state and a second temperature state, and the first temperature state is higher than the second temperature state. A driving circuit comprising:
a switching circuit receives a supply voltage to generate a switching signal, the level of the switching signal being related to a temperature state;
a charging circuit coupled to the switching circuit and receiving the supply voltage, the switching signal controlling the charging circuit to generate a voltage signal according to the supply voltage, the level of the voltage signal being related to the temperature state;
a determining circuit coupled to the charging circuit, the determining circuit generating a determining signal according to the level of the voltage signal, the determining signal indicating the temperature state;
a selector coupled to the determining circuit and receiving a plurality of first voltage signals and a plurality of second voltage signals, wherein a level of each of the first voltage signals is greater than a level of each of the second voltage signals, the selection Selecting one of the first voltage signals and one of the second voltage signals according to the determination signal and outputting;
a quasi-converter coupled to the selector, the level converter adjusting a voltage level of the plurality of control signals according to the first voltage signal and the second voltage signal output by the selector; and a gate driving The circuit is coupled to the level converter, and the gate driving circuit generates a plurality of gate driving signals to drive a display panel according to the control signals that have been adjusted. The driving circuit of claim 9, wherein the selector comprises:
a first multiplexer coupled to the determining circuit and receiving the first voltage signals, the first multiplexer selecting one of the first voltage signals according to the determining signal; and a second multiplexer, The determining circuit is coupled to the second voltage signal, and the second multiplexer selects one of the second voltage signals according to the determining signal. The driving circuit of claim 10, wherein when the determining signal indicates that the temperature state is a first temperature state, the first multiplexer selects one of the first voltage signals according to the determining signal to have The first voltage signal of the lowest voltage level, the second multiplexer selects the second voltage signal of the one of the second voltage signals having the highest voltage level according to the determination signal. The driving circuit of claim 11, wherein when the determining signal indicates that the temperature state is a second temperature state, and the first temperature state is higher than the second temperature state, the first multiplexer is based on Determining, by the determining signal, a first voltage signal having one of the first voltage signals having a highest voltage level, and the second multiplexer selects one of the second voltage signals to have a lowest voltage level according to the determining signal The second voltage signal. The driving circuit of claim 10, wherein the first multiplexer comprises:
a selection circuit, coupled to the first voltage signals, and selecting one of the first voltage signals for output;
a charge pump circuit coupled to the selection circuit and generating a selection signal, the selection circuit selecting one of the first voltage signals to output according to the selection signal; and a control circuit coupled to the charge pump circuit, And controlling the charge pump circuit according to the determination signal. The driving circuit of claim 13, wherein the selection circuit comprises a plurality of selection transistors, wherein the selection transistors are respectively coupled to the first voltage signals, the selection signals controlling one of the selection transistors, And outputting by selecting one of the first voltage signals, the voltage level of the selection signal being equal to or higher than a voltage level of the selected first voltage signal. The driving circuit of claim 13, wherein the selecting circuit comprises:
a first selection transistor coupled to the first voltage signal of the first voltage signal, the charge pump circuit and the control circuit; and a second selection transistor coupled to the first voltage signals a first voltage signal, the charge pump circuit and the control circuit;
The control circuit turns off the first selection transistor or the second selection transistor according to the determination signal. When the control circuit turns off the first selection transistor, the selection signal turns on the second selection transistor to output the first Selecting the first voltage signal to which the transistor is coupled, and when the control circuit turns off the second selection transistor, the selection signal turns on the first selection transistor to output the first coupling transistor coupled to the first A voltage signal. For example, the driving circuit described in claim 15 of the patent scope further includes:
a first protection transistor coupled between the first selection transistor and the control circuit; and a second protection transistor coupled between the second selection transistor and the control circuit.