TW201504648A - Chip capable of implementing communication interface through legacy functional pins - Google Patents

Abstract

The invention is a chip capable of implementing communication interface through legacy functional pins. It is beneficial for the convenience of production test. The communication interface circuit is electrically connected to a power input end and a power output end. When power input end has no input signal and power output end receives an input power, the communication interface circuit cut off the original function of clock oscillator unit and power converter while clock output end of clock oscillator unit and power input end of power converter are converted to signal output end and signal input end of communication interface circuit respectively. The communication interface circuit is linked to testing machine through signal output/ input end. Accordingly, testing instruction is received for performing test under assigned test mode while testing result is sent back. Thereby testing cost may be saved.

Description

A chip that implements a communication interface using only existing function pins

The present invention relates to a wafer, and more particularly to a wafer that realizes a communication interface by using only existing function pins, and uses a function bit in the test mode to implement a test mode communication interface in a test mode. A functional circuit inside the wafer is detected.

Integrated circuits (ICs), or microcircuits, microchips, and chips are circuits in electronics (mainly including semiconductor devices, including passive components, etc.). Miniaturized and usually fabricated on the surface of semiconductor wafers. In contrast, a pin, or a pin or a pin, refers to an exposed portion (wire or pad) of an electronic component such as the above-described integrated circuit or wafer, which is usually bent down. Ding" font.

Therefore, when a plurality of pins are soldered to an aluminum wire or a gold wire on the "pads" of the integrated circuit or the chip, the integrated circuit or the wafer is transmitted through the plurality of pins to be used for transmitting power, Transfer information to other electronic components for the exchange of different functions or exchange of materials. In short, the different functions built into the integrated circuit or the chip are also connected to other electronic components through the corresponding connected pins for subsequent signal processing.

However, as of today, in the manufacturing process of all electronic components including integrated circuits or wafers, there is a real need for de-storing. This need is actually a test process. Achieving this process requires a variety of test equipment, such as the so-called electronic test equipment, also known as automatic test equipment (ATE, Automatic Test Equipment), refers to the electronic equipment used to detect the integrity of the function of electronic components related equipment . The device detects the quality of the component by generating a signal and capturing the response of the component. In the semiconductor industry's production process, testing is usually the final process of manufacturing integrated circuits to ensure the quality of integrated circuits.

Poorly, the existing test method requires the chip to additionally set the test pin to pass through the test pins connected to the test pins, and sequentially perform different function detection and analysis on the integrated circuit or the wafer. There are defects in complicated procedures and time consumption, and the chip needs to design another test pin, which will increase the test cost. Accordingly, the present invention provides a wafer that utilizes only existing functional pins to implement a communication interface that overcomes the deficiencies of the prior art.

The purpose of the invention is to provide a communication interface for connecting with the outside world by the existing power input terminal and the pulse output terminal in the test mode, so as to facilitate the release of the test command and the return of the test result, thereby reducing the test cost.
In order to achieve the above object, the present invention is a wafer that realizes a communication interface by using only existing function pins, and includes a communication interface circuit, a power input terminal and a clock output terminal, and the power input terminal is electrically connected. Connected to the power converter, the power input is added as a function to determine whether it is the test mode and the signal input to the communication interface in the test mode. The clock output of the clock oscillating unit is added to the function of the signal output of the communication interface in the test mode in addition to the existing functions. The communication interface circuit is configured to convert the normal operation mode and the test mode, and convert the power input end and the clock output end into a communication interface for the production test of the communication interface signal input and output end in the test mode. This is to facilitate the convenience of production testing, in order to improve shipment yield and reduce testing costs.

10‧‧‧ wafer
102‧‧‧clock oscillation unit
103‧‧‧First amplifier
104‧‧‧Digital buffer
105‧‧‧Three-state digital buffer
106‧‧‧Power Converter
22‧‧‧Communication interface circuit
24‧‧‧Automatic test module generation unit
26‧‧‧Memory Test Unit
28‧‧‧ physical layer test unit
Cmd_in‧‧‧Communication Agreement Signal
Cmd_out‧‧‧Communication Agreement Signal
DM‧‧‧ differential signal negative
DP‧‧‧Positive signal positive end
SCAN_in‧‧‧ scan input
SCAN_out‧‧‧ scan output
VDD5‧‧5 volt power supply
VDD3.3‧‧‧3.3 volt power supply
VIN‧‧‧ power input
VOUT‧‧‧ power output
VCC‧‧‧ internal power supply
CLK‧‧‧ internal working clock
XIN‧‧‧ clock input
XOUT‧‧‧ clock output

1 is a schematic diagram of a test circuit according to a preferred embodiment of the present invention;
2A is a timing diagram of a normal mode in accordance with a preferred embodiment of the present invention; and FIG. 2B is a timing diagram of a test mode in accordance with a preferred embodiment of the present invention.

In order to provide a better understanding and understanding of the features and the efficacies of the present invention, the preferred embodiment and the detailed description are as follows:

Please refer to FIG. 1, which is a schematic diagram of a preferred embodiment of the present invention. As shown in the figure, the wafer 10 with the test function of the present invention has a power input terminal VIN, a power output terminal VOUT, a clock input terminal XIN, a clock output terminal XOUT, and a scan input terminal SCAN_in. a scan output terminal SCAN_out, a differential signal positive terminal DP, a differential signal negative terminal DM, which is a pin corresponding to the wafer 10, and the wafer 10 includes a clock oscillation unit 102, a first amplifier 103, and a A digital buffer 104, a three-state digital buffer 105, a power converter 106, a communication interface circuit 22, an automatic test pattern generation (ATPG) unit 24, a memory test unit 26 and a The physical layer testing unit 28, wherein the connection relationships included for the wafer 10 are described as follows:

The clock oscillating unit 102 of the embodiment is connected between the clock input terminal XIN and the clock output terminal XOUT, and the clock oscillating unit 102 forms a clock according to the clock output terminal XOUT and a clock input terminal XIN connected to the external quartz crystal. In the oscillating circuit, the first amplifier 103 is connected between the clock input terminal XIN and the internal working clock CLK, and the digital buffer 104 is connected between the input power terminal VIN and the communication interface circuit 22, and the tri-state digit buffer 105 is connected. Between the pulse output terminal XOUT and the communication interface circuit 22, the power converter 106 is connected between the input power terminal VIN and the output power terminal VOUT.

The digital converter 106 of the present embodiment receives the input power of the 5 volt input power at the input power terminal VIN by the voltage converter 106, and converts it into a 3.3 volt output power supply for output to the internal power supply VCC and the output power terminal. VOUT. The automatic test module generating unit 24 cooperates with the interface unit 22 to provide a test module signal for each functional circuit to test the combinatorial logic and the sequential logic of the functional circuit one by one by scanning input. The terminal SCAN_in receives the input signal and outputs the test result by the scan output SCAN_out. The memory test unit 26 cooperates with the interface unit 22 to perform a built-in self test (BIST) on the memory and returns the result through the communication interface circuit 22. The physical layer testing unit 28 cooperates with the interface unit 22 to perform built-in self-test on all physical layer circuits by means of differential input positive/negative DP/DM and Golden Sample docking test and the result is transmitted back through the communication interface circuit 22. pass.

Please refer to FIG. 1 and FIG. 2A , which are timing diagrams of a schematic circuit diagram and a normal mode of the present invention. As shown in the figure: the external power supply VDD5 (5 volts) is input to the chip 10 from the power input terminal VIN, converted to VDD3.3 (3.3 volts) by the power converter 106, and outputted from the power output terminal VOUT and supplied to the internal power supply VCC. The interface circuit 22 learns that the power input terminal is at a high level through the digital buffer 104, and accordingly determines that the normal operation mode and all the test units 24, 26, and 28 are disabled. Therefore, the three-state digital buffer 105 has a high output. The impedance and clock oscillating unit 102 is oscillated in cooperation with an external quartz oscillating circuit, and the internal working clock CLK is obtained through the first amplifier 103. The wafer 10 enters the normal operating state and all of the input and output terminals are normally functioning.

Please refer to FIG. 1 and FIG. 2B for a timing diagram of a schematic circuit diagram and a test mode of the present invention. As shown, the external power supply VDD5 is not input to the chip 10 by the power supply input terminal VIN, but an external power supply VDD3.3 (3.3 volts) is supplied from the power supply output terminal VOUT to the internal power supply VCC, at which time the communication interface circuit 22 transmits through the digital buffer. 104 knows that the power input terminal VIN is at a low level, and accordingly determines the test mode, so the clock oscillating unit 102 is turned off and turns on the tri-state digit buffer 105, and the internal working clock CLK can pass through the test machine (not shown) The input to the clock input terminal XIN is input to the inside of the wafer 10 via the first amplifier 103. At this time, the communication interface circuit 22 can pass through the clock output terminal XOUT and the power input terminal VIN and the test machine (not shown). Linking, obtaining a test command via the communication protocol signal cmd_in/cmd_out to start any test item in any test unit and causing the corresponding input end to enter a specified test mode, and the test result can be input by the corresponding input (such as scanning) The input terminal SCAN_in/scan output terminal SCAN_out) is returned to the test machine (not shown), and can also be returned to the test machine (not shown) through the input/output terminal XOUT/VIN of the communication interface circuit 22, via this The production test of the wafer 10 can be completed under limited foot conditions, for example, performing the test corresponding to the Automatic Test Pattern Generation (ATPG) unit 24 or the memory test unit 26 or the physical layer test unit 28. The test program corresponding to the automatic test pattern generation (ATPG) unit 24 or the memory test unit 26 or the physical layer test unit 28 is built in the wafer 10 or written via an external test machine. The wafer 10 is inserted.

In summary, the present invention utilizes a chip's existing function pins to implement a communication interface to facilitate the convenience of production testing, thereby improving shipment yield and reducing test costs.

The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the variations, modifications, and modifications of the shapes, structures, features, and spirits described in the claims of the present invention. All should be included in the scope of the patent application of the present invention.

The invention is a novelty, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, and the invention patent application is filed according to law, and the prayer bureau will grant the patent as soon as possible. prayer.

10‧‧‧ wafer

102‧‧‧clock oscillation unit

103‧‧‧First amplifier

104‧‧‧Digital buffer

105‧‧‧Three-state digital buffer

106‧‧‧Power Converter

22‧‧‧Communication interface circuit

24‧‧‧Automatic Test Module Generation Unit (ATPG)

26‧‧‧Memory Test Unit (Memory BIST)

28‧‧‧ Physical Layer Test Unit (PHY BIST)

DM‧‧‧ differential signal negative

DP‧‧‧Positive signal positive end

SCAN_in‧‧‧ scan input

SCAN_out‧‧‧ scan output

VIN‧‧‧ power input

VOUT‧‧‧ power output

VCC‧‧‧ internal power supply

CLK‧‧‧ internal working clock

XIN‧‧‧ clock input

XOUT‧‧‧ clock output

Claims (5)

A wafer that utilizes an existing functional pin to implement a communication interface that facilitates production testing, the wafer comprising:
a communication interface circuit that supports a communication protocol and sets a test mode;
a power input end electrically connected to the communication interface circuit and a power converter, the power converter receives power according to the power input end; and a clock output end electrically connected to the communication interface circuit and a clock oscillation unit, The clock oscillating unit forms a clock oscillating circuit according to the clock output end and the clock input end connecting the external quartz crystal;
The communication interface circuit detects the power input terminal to determine whether the chip operates in the test mode, and the communication interface circuit is in the test mode, in addition to the existing functions of the power input terminal and the clock output terminal. The power input terminal and the clock output are converted into a signal input end and a signal output end of the communication interface, and the communication interface corresponds to the communication protocol. The wafer of claim 1, wherein the communication interface circuit determines that the wafer is in the test mode according to the power input terminal being at a low level and the wafer receiving a supply voltage. The wafer of claim 1, wherein the communication interface circuit determines that the wafer is in a normal operation mode according to the power input terminal being at a high level and the wafer receiving a supply voltage. The chip of claim 1, wherein the communication interface circuit transmits at least one communication protocol signal to the signal output terminal through the signal input terminal. The wafer of claim 1, wherein the chip performs an automatic test pattern generation (ATPG) or a memory test or a physical layer test test program through the communication interface circuit.