TW201503367A - A fabrication method of a trenched power semiconductor structure - Google Patents

Abstract

A fabrication method of a trenched power semiconductor structure is provided, which comprises the steps of: (a) providing a semiconductor base; (b) forming a gate mask on an upper surface of the semiconductor base; (c) forming a first doped region by implanting first impurities of a first conductive type into the semiconductor base; (d) forming gate trenches in the semiconductor base by using anisotropic etching technology and leave a portion of the first doped region by the sidewall of the gate trench; (e) forming a gate electrode structure in the gate trench; (f) forming a body layer in the semiconductor base; (g) forming a source doped region in the body layer by implanting second impurities of the first conductive type into the body layer.

Description

Method for manufacturing trench type power semiconductor structure

The present invention relates to a method of fabricating a power semiconductor structure, and more particularly to a method of fabricating a trench power semiconductor structure.

Power semiconductor components have low switching losses, and the advantages of the driver circuit are simple. With the rapid development of semiconductor process technology, it has become an important product of power control. The power semiconductor components can be divided into two types: a trench gate and a planar gate according to the direction of the channel. The channel of the trench gate power semiconductor structure is in the direction of the vertical wafer surface, and the channel of the planar gate power semiconductor structure is along the surface of the wafer. Compared to planar gate power semiconductor structures, trench gate power semiconductor structures can achieve larger channel widths, thereby helping to reduce channel impedance.

Figure 1 is a schematic cross-sectional view of a typical trench gate power semiconductor structure. As shown in the figure, the trench gate power semiconductor structure has an N-type heavily doped substrate 10 as its drain doped region. An N-type epitaxial layer 12 is formed on the substrate 10. A plurality of gate trenches (not shown) are formed in the N-type epitaxial layer 12, and the gate structures 16 are located in the gate trenches. A P-type body region 14 is formed in the surface region of the N-type epitaxial layer 12 to surround the gate structure 16. A source doped region 15 is formed in the body region 14 and adjacent to the gate structure 16. Attached to the gate structure 16 An interlayer dielectric layer 17 is covered. In addition, a source contact window 18 is formed between adjacent two gate trenches to expose the source doped region 15. A P-type heavily doped region 19 is formed at the bottom of the source contact window 18. A source metal layer (not shown) is filled in the source contact window 18 to be electrically connected to the source doping region 15.

In general, the power consumption of a power semiconductor component can be divided into two parts: conduction loss and switching loss. The conduction loss has a positive correlation with the on-resistance of the semiconductor element. The switching loss is related to the threshold voltage (Vth) of the transistor component and the Miller capacitance (Crss). The reduction of the threshold voltage and the Miller capacitance helps to shorten the switching time of the semiconductor component to reduce the switching loss.

The magnitude of the threshold voltage is affected by the doping concentration in the body region of the power semiconductor device, the thickness of the gate oxide layer, and the constituent materials of the gate. A lower bulk doping concentration or a thinner gate oxide layer helps to lower the threshold voltage of the power semiconductor component. However, the lower body region doping concentration has an adverse effect on the cumulative breakdown (Eas) withstand voltage of the power semiconductor components. The thinner gate oxide layer not only increases the difficulty of process control, but also causes the Miller capacitance (that is, the gate capacitance (Cgd)) to rise, which is not conducive to switching loss.

SUMMARY OF THE INVENTION A primary object of the present invention is to provide a power semiconductor device that can effectively reduce switching losses of power semiconductor components while maintaining an appropriate cumulative breakdown voltage.

An embodiment of the present invention provides a method of fabricating a trench power semiconductor structure, comprising at least the steps of: (a) providing a semiconductor substrate; and (b) forming a gate mask layer on the upper surface of the semiconductor substrate, To define the position of the plurality of gate trenches; (c) implanting a first dopant having a first conductivity type into the semiconductor via the gate mask layer a first doped region is formed in the bulk substrate, the width of the first doped region is greater than the opening width of the gate mask layer; (d) the gate trench is formed on the semiconductor substrate by anisotropic etching Inside the material, and retaining a portion of the first doped region adjacent to the sidewall of the gate trench; (e) forming a gate structure in the gate trench; (f) forming a body layer having a second conductivity type And (g) implanting a second dopant having a first conductivity type on the body layer to form a source doped region on the upper portion of the body layer; wherein the depth of the body layer is greater than The depth of a doped region, the depth of the source doped region is less than the depth of the first doped region.

In accordance with an embodiment of the invention, the rate of thermal diffusion of the first dopant within the semiconductor substrate is no greater than the rate of thermal diffusion of the second dopant within the semiconductor substrate. Also, in a preferred embodiment, the first dopant is arsenic (As).

According to an embodiment of the invention, the step of forming the body layer and forming the source doped region is later than the step of forming the gate structure.

According to an embodiment of the invention, the step of forming the body layer and forming the source doped region is earlier than the step of forming the gate cap layer.

According to an embodiment of the invention, the step of forming the body layer is earlier than the step of forming the gate mask layer, and the step of forming the source doping region is later than the step of forming the gate trench.

According to an embodiment of the invention, the manufacturing method further includes: forming a contact window between adjacent gate structures to expose the body layer and the source doping region; and forming a heavily doped region having the second conductivity type The area is at the bottom of the contact window. Also, in a preferred embodiment, the heavily doped region is adjacent to the first doped region.

According to an embodiment of the invention, the doping concentration of the first dopant in the first doping region is much greater than the doping concentration of the dopant of the second conductivity type in the body layer.

According to an embodiment of the invention, the bottom of the first doped region is spaced apart from the bottom of the body layer by a predetermined distance.

According to an embodiment of the invention, the doping concentration of the first dopant in the first doping region is smaller than the doping concentration of the dopant of the second conductivity type in the body layer.

Other objects and advantages of the present invention will become apparent from the technical features disclosed herein.

10‧‧‧Substrate

12‧‧‧ epitaxial layer

14‧‧‧ Body area

15‧‧‧ source doped area

16‧‧‧ gate structure

17‧‧‧Interlayer dielectric layer

18‧‧‧Source contact window

19‧‧‧ heavily doped area

100‧‧‧N type copper substrate

120,420,520‧‧‧N type epitaxial layer

130,430,530‧‧‧Gate pole cover

125‧‧‧ openings

140,440,540‧‧‧First doped area

142,242,342,442,542‧‧‧partial first doped area

150,450,550‧‧‧gate trench

162,462,562‧‧‧gate dielectric layer

164,464,564‧‧‧Polysilicon gate

170,370,470,570‧‧‧P type body layer

180,480,580‧‧‧ source doped area

185‧‧‧Interlayer dielectric layer

190‧‧‧Source contact window

192‧‧‧P type heavily doped area

195‧‧‧ source metal layer

Figure 1 is a schematic cross-sectional view of a typical trench gate power semiconductor structure.

2A to 2G are diagrams showing a first embodiment of a method of manufacturing a trench type power semiconductor structure of the present invention.

Figure 3 is another embodiment of a trench power semiconductor structure fabricated by a method of fabricating a trench power semiconductor structure in accordance with the present invention.

Figure 4 is a second embodiment of a method of fabricating a trench power semiconductor structure of the present invention.

5A to 5D are views showing a third embodiment of a method of manufacturing a trench type power semiconductor structure of the present invention.

6A to 6E are views showing a fourth embodiment of a method of manufacturing a trench type power semiconductor structure of the present invention.

2A to 2G are diagrams showing a first embodiment of a method of manufacturing a trench type power semiconductor structure of the present invention. An N-type MOSFET field effect transistor The (MOSFET) structure is taken as an example. However, the invention is not limited thereto. The technique of the present invention can also be applied to a P-type MOS field effect transistor structure or a controllable switching unit such as an insulated gate bipolar transistor (IGBT).

As shown in FIG. 2A, first, an N-type epitaxial layer 120 is formed on an N-type germanium substrate 100 as a semiconductor substrate of the power semiconductor structure. Subsequently, as shown in FIG. 2B, a gate mask layer 130 is formed on the upper surface of the N-type epitaxial layer 120. The gate mask layer 130 has a plurality of openings 125 (only one of which is shown), thereby defining a plurality of gate trenches in the N-type epitaxial layer 120 (the gate trench is shown in the figure) For example).

Next, an N-type first dopant is implanted into the N-type epitaxial layer 120 through the gate mask layer 130 to form a first doped region 140 corresponding to the opening 125 of the gate mask layer 130. . Because of the characteristics of the ion implantation process, the width of the first doped region 140 formed through the implantation step may be greater than the width of the opening 125 of the gate mask layer 130. In a preferred embodiment, the concentration of the N-type first dopant implanted in the ion implantation step is significantly greater than the concentration of the N-type dopant inherent in the N-type epitaxial layer 120. Secondly, in order to avoid the influence of the implanted first dopant on the subsequent source doping implantation step. The implantation depth of the first dopant is greater than the implantation depth of the source dopant.

As shown in FIG. 2C, the step of implanting the N-type first dopant through the gate mask layer 130 to form the first doping region 140 is followed by the anisotropic etching through the gate mask layer 130. A gate trench 150 is formed in the N-type epitaxial layer 120. Since the width of the first doping region 140 is significantly larger than the width of the opening 125 of the gate mask layer 130, after the anisotropic etching step, a portion of the first doping region 142 can still remain adjacent to the gate. The sidewall of the pole trench 150. Moreover, in an embodiment, to prevent the anisotropic etching step from completely removing the first doping region 140, the etching step may be performed before the etching step. A thermal diffusion step is applied to the implanted first dopant to expand the extent of the first doped region 140.

Next, as shown in FIG. 2D, the gate mask layer 130 on the surface of the N-type epitaxial layer 120 is removed, and then a gate structure is formed in the gate trench 150. The gate structure includes a gate dielectric layer 162 overlying the inner surface of the gate trench 150, and a polysilicon gate 164 filling the gate trench 150. This embodiment takes a basic trench gate structure as an example. In order to improve the performance of the power semiconductor structure, the gate structure can have various deformations, such as a gate structure having a thicker bottom oxide oxide layer or a floating polysilicon under the polysilicon gate. The gate structure. The technology provided by the present invention can be applied to a variety of different gate structures, all of which can improve their performance.

Then, as shown in FIG. 2E, a P-type body layer 170 is formed in the N-type epitaxial layer 120 by ion implantation. Next, an N-type second dopant is implanted into the P-type body layer 170 by ion implantation to form an N-type source doped region 180 over the P-type body layer 170. The depth of the P-type body layer 170 is greater than the depth of the portion of the first doping region 142, and the P-type body layer 170 is coated under the portion of the first doping region 142, and the depth of the source doping region 180 is Less than a portion of the depth of the first doped region 142. This ion implantation step simultaneously implants a P-type dopant into a portion of the first doped region 142. In this embodiment, the concentration of the P-type dopant implanted in the first doped region 142 is sufficient to change the conductivity of the portion of the first doped region 142 to the P-type.

In a preferred embodiment, the N-type first dopant used to form a portion of the first doped region 142 has a thermal diffusion rate in the N-type epitaxial layer 120 that is not greater than the source-doped region. The thermal diffusion rate of the N-type second dopant of 180 in the N-type epitaxial layer 120. In a preferred embodiment, the source implantation step may use phosphorus (P) as the second dopant, and the implantation step for forming the first doping region 140 may be selected. Arsenic (As) is used as the first dopant. The selection of the foregoing dopants is directed to the use of germanium as a semiconductor material. If a semiconductor material of the third or fifth family is used, a group of two or six elements is required as a dopant.

Next, as shown in FIG. 2F, an inter-level dielectric layer 185 is formed to cover the polysilicon gate 164 and the source doping region 180, and then a source contact window 190 is formed between adjacent gate structures by using a photolithography technique. The P-type body layer 170 and the source doped region 180 are exposed. Next, a P-type heavily doped region 192 is formed by ion implantation at the bottom of the source contact window 190. Finally, as shown in FIG. 2G, a source metal layer 195 is formed to fill the source contact window 190 to electrically connect the source doping region 180.

As the size of the unit cell of the power semiconductor structure is reduced, the separation distance of the adjacent two gate trenches 150 is also shortened. Therefore, the P-type heavily doped region implanted at the bottom of the source contact window 190 is formed. The range of 192 easily extends to the side of the gate trench 150, affecting the conduction of the channel. By forming a portion of the first doping region 142 on the side of the gate trench 150 by the fabrication method of the present invention, the P-type heavily doped region 192 can be prevented from expanding to the side of the gate trench 150. Thus, particularly in the case of small cell sizes, a portion of the first doped region 142 may be adjacent to the P-type heavily doped region 192 to maintain the conductivity type of the channel. Moreover, the presence of the portion of the first doped region 142 is also advantageous for reducing the threshold voltage to reduce switching loss. Therefore, by using the fabrication method of the present invention, even if a thick gate dielectric layer 162 is used, the original threshold voltage can be maintained. The increase in thickness of the gate dielectric layer 162 also helps to reduce the gate capacitance (Cgd) to reduce switching losses.

The dopant implanted in the P-type body layer 170 (see FIG. 2E) also enters a portion of the first doped region 142 to affect the conductivity of the portion of the first doped region 142. Further, if the doping concentration of the P-type dopant in the implanted portion of the first doping region 142 is greater than the doping concentration of the N-type dopant originally contained in the portion of the first doping region 142 A portion of the first doped region 142 exhibits a P-type conductivity. In this embodiment, the doping concentration of the N-type dopant implanted in the implantation process of the first doping region 142 in FIG. 2B is smaller than the P implanted in the implantation step of FIG. 2E. The doping concentration of the type dopant, therefore, a portion of the first doped region 142 eventually exhibits a P-type conductivity. However, the P-type partial first doping region 142 has a P-type doping concentration lower than that of the P-type body layer 170.

Figure 3 is another embodiment of a trench power semiconductor structure fabricated by a method of fabricating a trench power semiconductor structure in accordance with the present invention. Compared with the trench power semiconductor structure of FIG. 2G, this embodiment implants a higher concentration N-type first dopant in the implantation step corresponding to FIG. 2B, so even if P is implanted again After the type dopant, a portion of the first doped region 242 still exhibits an N-type conductivity. Moreover, in a preferred embodiment, a portion of the first doped region 242 ultimately has a doping concentration that is less than a doping concentration of the source doped region 180.

Next, as shown in FIG. 2G, the first doped region of the trench power semiconductor structure manufactured by the first embodiment of the present invention is covered with a P-type body layer 170, but the present invention is not limited thereto. . Figure 4 is a second embodiment of a method of fabricating a trench power semiconductor structure in accordance with the present invention. Figure 4 is the step of undertaking Figure 2D. This step forms a P-type body layer 370 in the N-type epitaxial layer 120 by ion implantation. As shown in FIG. 4, a portion of the first doped region 342 of the present embodiment extends below the bottom of the P-type body layer 370, and the doping concentration of the P-type dopant implanted in the implanting step is greater than Part of the first doping region 342 originally has a doping concentration of the N-type dopant. Thus, a portion of the first doped region 342 located within the P-type body layer 370 exhibits a lightly doped P-type conductivity. The subsequent steps of this embodiment are substantially the same as the foregoing first embodiment of the present invention, and are not described herein. Although the bottom position of a portion of the first doped region 342 can be adjusted according to actual needs.

However, as shown in FIG. 3, if part of the first doping region 242 finally presents N For the conductivity type, the bottom of the portion of the first doped region 242 needs to be located in the P-type body layer 170 and spaced apart from the bottom of the P-type body layer 170 by a predetermined distance to ensure proper operation of the power semiconductor structure.

5A to 5D are views showing a third embodiment of a method of manufacturing a trench type power semiconductor structure of the present invention. In contrast to the first embodiment of the present invention, the step of forming the P-type body layer 170 and forming the source doping region 180 is later than the step of forming the gate structure. As shown in FIGS. 5A and 5B, in this embodiment, a P-type body layer 470 and an N-type source doping region 480 are first formed in the N-type epitaxial layer 420, and then the gate mask layer 430 is formed on the N-type Lei. On the layer 420. Next, the first doped region 440 is formed into the P-type body layer 470 by ion implantation through the gate mask layer 430. Subsequently, as shown in FIGS. 5C and 5D, the fabrication steps of the subsequent gate trench 450 and the gate structure (including the gate dielectric layer 462 and the polysilicon gate 464) are performed. The subsequent manufacturing steps of the trench power semiconductor structure are substantially the same as those of the first embodiment described above, and are not described herein.

Next, in the first and third embodiments described above, the P-type body layers 170, 470 and the source doped regions 180, 480 are fabricated by two successive fabrication steps. However, the invention is not limited thereto. 6A to 6E are views showing a fourth embodiment of a method of manufacturing a trench type power semiconductor structure of the present invention. In this embodiment, as shown in FIGS. 6A and 6B, the P-type body layer 570 is first formed in the N-type epitaxial layer 520, and then the gate mask layer 530 is formed on the N-type epitaxial layer 520. surface. Next, a first doped region 540 is formed in the P-type body layer 570 through the gate mask layer 530. As for the source doping region 580, as shown in FIGS. 6C to 6E, after the manufacturing steps of forming the gate trench 550 and the gate structure (including the gate dielectric layer 562 and the polysilicon gate 564), It is formed in the P-type body layer 570 by ion implantation.

However, the above is only a preferred embodiment of the present invention, and when The scope of the present invention is defined by the scope of the invention, and the equivalent equivalents and modifications of the present invention are still within the scope of the invention. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

100‧‧‧N type copper substrate

120‧‧‧N type epitaxial layer

142‧‧‧Partial first doped area

162‧‧‧ gate dielectric layer

164‧‧‧Polysilicon gate

170‧‧‧P type body layer

180‧‧‧ source doped area

185‧‧‧Interlayer dielectric layer

192‧‧‧P type heavily doped area

195‧‧‧ source metal layer

Claims (11)

A method of fabricating a trench power semiconductor structure includes at least the steps of: providing a semiconductor substrate; forming a gate mask layer on an upper surface of the semiconductor substrate to define a plurality of gate trench locations; The gate mask layer is implanted with a first dopant having a first conductivity type in the semiconductor substrate to form a first doped region, the first doped region having a width greater than the gate Opening width of the mask layer; forming the gate trenches in the semiconductor substrate by anisotropic etching to leave a portion of the first doping region adjacent to the sidewall of the gate trench; forming a gate structure is formed in the gate trench; a body layer having a second conductivity type is formed in the semiconductor substrate; and a second dopant having the first conductivity type is implanted in the body layer, Forming a source doped region on the upper portion of the body layer; wherein the depth of the body layer is not less than a depth of the first doped region, the depth of the source doped region is less than the first doping The depth of the area. The method of fabricating a trench power semiconductor structure according to claim 1, wherein a thermal diffusion rate of the first dopant in the semiconductor substrate is not greater than the second dopant in the semiconductor substrate The rate of thermal diffusion. A method of fabricating a trench power semiconductor structure according to claim 2, wherein the first dopant is arsenic (As). The method of fabricating a trench power semiconductor structure according to claim 1, wherein the step of forming the body layer and forming the source doped region is later than the step of forming the gate structure. The method of fabricating a trench power semiconductor structure according to claim 1, wherein the step of forming the body layer and forming the source doping region is earlier than the step of forming the gate mask layer. The manufacturer of the trench power semiconductor structure as claimed in claim 1 The method of forming the body layer is earlier than the step of forming the gate mask layer, and the step of forming the source doping region is later than the step of forming the gate trench. The method for fabricating a trench power semiconductor structure according to claim 1, further comprising: forming a contact window between the adjacent gate structures to expose the body layer and the source doped region; and forming A heavily doped region having the second conductivity type is at the bottom of the contact window. The method of fabricating a trench power semiconductor structure according to claim 7, wherein the heavily doped region is adjacent to the first doped region. The method for manufacturing a trench power semiconductor structure according to claim 1, wherein a doping concentration of the first dopant in the first doping region is much larger than a second conductivity in the body layer. Doping concentration of the type of dopant. The method of fabricating a trench power semiconductor structure according to claim 1, wherein a bottom of the first doped region is spaced apart from a bottom of the body layer by a predetermined distance. The method for manufacturing a trench power semiconductor structure according to claim 1, wherein a doping concentration of the first dopant in the first doping region is smaller than a second conductivity in the body layer. Doping concentration of the type of dopant.