TW201501274A - Pixel structure - Google Patents

Abstract

A pixel structure including a semiconductor pattern, a first insulation layer, a first conductor layer, a second insulation layer, a second conductor layer, a third insulation layer and a pixel electrode is provided. The semiconductor pattern includes a first contact region, a second contact region and a channel region. The first conductor layer includes a gate and a scan line. A first upper contact hole of the first insulation layer and a first lower contact hole of the second insulation layer constitute a first contact hole. The first contact hole exposes the semiconductor pattern to define the first contact region. The second conductor layer includes a data line in contact with the first contact region. A first edge of the data line is disposed within an area of the first contact hole. The pixel electrode is electrically connected to the second contact region.

Description

Pixel structure

The present invention relates to a pixel structure, and more particularly to a pixel structure having a high aperture ratio.

In recent years, display devices have been developed toward high resolution in addition to high contrast, wide viewing angle, and high color saturation. In particular, in terms of mobile display devices, the habit of consumers using mobile display devices to browse web pages or view audiovisual multimedia is gradually formed, and the resolution of mobile display devices plays an important role in the quality of viewing.

In general, the area of the mobile display device is not large. In order to achieve high resolution for mobile display devices, designers need to have multiple pixel structures built into a limited area. However, in the pixel structure, there are many film layers having low transmittance (for example, a film layer to which a data line, a scanning line, or the like belongs), and when the number of pixel structures in the mobile display device is increased, the aperture ratio of the action display device is also sharp. decline. As a result, the mobile display device consumes more power to increase the display brightness, which is not conducive to the time available for the mobile display device. Therefore, how to properly design the pattern of each film layer in the pixel structure to increase the aperture ratio is one of the goals that the developer wants to achieve.

The present invention provides a pixel structure having a high aperture ratio.

The pixel structure of the present invention includes a semiconductor pattern, a first insulating layer, a first conductor layer, a second insulating layer, a second conductor layer, a third insulating layer, and a pixel electrode. The semiconductor pattern is disposed on the substrate. The semiconductor pattern includes a first contact region, a second contact region, and a channel region between the first contact region and the second contact region. The first insulating layer covers the semiconductor pattern and has a first lower contact opening. The first conductor layer is disposed on the substrate. The first conductor layer includes a gate that overlaps the channel region and a scan line that is connected to the gate. The second insulating layer covers the first conductor layer and has a first upper contact opening. The first upper contact opening and the first lower contact opening constitute a first contact opening. The first contact opening exposes the semiconductor pattern to define a first contact region. The second conductor layer is disposed on the second insulating layer. The second conductor layer includes data lines that intersect the scan lines. The data line contacts the first contact area exposed by the first contact opening. The first side wall of the data line is located within the area of the first contact opening. The third insulating layer covers the second conductor layer. The pixel electrode is disposed on the third insulating layer and electrically connected to the second contact region.

In an embodiment of the invention, the width of the first contact opening is not less than the width of the data line.

In an embodiment of the invention, the width of the first contact opening is greater than the width of the first contact area.

In an embodiment of the invention, the first sidewall of the data line overlaps the edge of the first contact opening.

In an embodiment of the invention, the first side wall of the data line and the first The edges of a contact opening are separated by a distance.

In an embodiment of the invention, the first contact region of the semiconductor pattern has a sidewall of the contact region. The sidewall of the contact region overlaps the first sidewall of the data line such that the sidewall of the contact region is spaced apart from the edge of the first contact opening by the distance.

In an embodiment of the invention, the second sidewall of the data line is located within the area of the first contact opening, and the first sidewall and the second sidewall are opposite to each other.

In an embodiment of the invention, the second sidewall of the data line overlaps the edge of the first contact opening.

In an embodiment of the invention, the second side wall of the data line is spaced apart from the edge of the first contact opening by a distance.

In an embodiment of the invention, the sidewall of the contact region of the first contact region of the semiconductor pattern overlaps with the first sidewall and the second sidewall of the data line. The second side wall of the data line is opposite the first side wall of the data line.

In an embodiment of the invention, the first insulating layer has a second lower contact opening. The second insulating layer has a second upper contact opening. The second upper contact opening and the second lower contact opening form a second contact opening to expose the second contact area. The second conductor layer further includes a connection pattern. The connection pattern contacts the second contact area exposed by the second contact opening. The connection pattern is electrically connected to the pixel electrode.

In an embodiment of the invention, the width of the second contact opening is not less than the width of the connection pattern.

In an embodiment of the invention, the connecting pattern sidewall of the connecting pattern overlaps the edge of the second contact opening.

In an embodiment of the invention, the connecting pattern sidewall of the connecting pattern is spaced apart from the edge of the second contact opening by a distance.

In an embodiment of the invention, the first conductor layer further includes a capacitor electrode. The capacitor electrode is superposed on the pixel electrode to constitute a storage capacitor.

In an embodiment of the invention, the data line has a fixed line width.

In an embodiment of the invention, the semiconductor pattern further includes a peripheral region adjacent to the first contact region. The peripheral area is covered by a first insulating layer. The first contact area is exposed by the first contact opening. The width of the first contact zone is less than the width of the perimeter zone.

In an embodiment of the invention, the data line includes a contact portion in contact with the first contact region and a wire portion adjacent to the contact portion, and the wire portion is on the first insulating layer and the second insulating layer.

In an embodiment of the invention, the semiconductor pattern has at least one semiconductor opening. The semiconductor opening is located within the first contact opening and a portion of the edge of the semiconductor opening overlaps the first sidewall.

Based on the above, in the pixel structure of the present invention, the data line contacts the first contact area exposed by the first contact opening, and a first side wall of the data line is located within the area of the first contact opening. By this design, the line width of the data line can be designed to be small, thereby achieving the purpose of increasing the aperture ratio of the pixel structure.

The above described features and advantages of the invention will be apparent from the following description.

100, 100A~100E‧‧‧ pixel structure

102‧‧‧Substrate

104‧‧‧First buffer layer

106‧‧‧Second buffer layer

108‧‧‧Semiconductor pattern

108a‧‧‧Part I

108b‧‧‧Part II

110‧‧‧First insulation

112‧‧‧ photoresist pattern layer

114‧‧‧First conductor layer

114'‧‧‧First pre-patterned conductor layer

114a, 114b‧‧‧ gate

114a’, 114b’‧‧‧ scheduled gate

114c‧‧‧ scan line

114c’‧‧‧ scheduled scan line

114d‧‧‧Capacitor electrode

114d'‧‧‧Predetermined capacitor electrode

118‧‧‧Second insulation

120‧‧‧Second conductor layer

120a‧‧‧Information line

120aa‧‧‧Contacts

120ab‧‧‧Wire Department

120b‧‧‧Connected pattern

122‧‧‧ third insulation

124‧‧‧pixel electrodes

A1, A2‧‧‧ the edge of the second contact opening

CH‧‧‧ passage area

D1, D1', D2, D2', S1, S1', S2, S2'‧‧‧ first doped region

D1, d2, L1, L2‧‧‧ distance

E1, E2‧‧‧ side wall of data line

E1, e2‧‧‧ the edge of the first contact opening

F1, F2‧‧‧ contact area side wall of the first contact area

G1, g2‧‧‧ connection pattern sidewall

F1, f2‧‧‧ contact area sidewalls of the second contact zone

K1‧‧‧Width of the first contact area

K2‧‧‧ width of the surrounding area

K3‧‧‧Width of the second contact zone

LDD‧‧‧Second doped area

O‧‧‧Semiconductor opening

P1‧‧‧ surrounding area

R1‧‧‧ first contact area

R2‧‧‧Second Contact Area

W1‧‧‧The width of the first contact opening

W2‧‧‧ width of the second contact opening

Wc‧‧‧Connection pattern width

Wd‧‧‧ width of data line

V1‧‧‧ first contact opening

V1U‧‧‧ first upper contact opening

V1D‧‧‧ first lower contact opening

V2‧‧‧second contact opening

V2U‧‧‧Second upper contact opening

V2D‧‧‧Second lower contact opening

V3‧‧‧ third contact opening

X‧‧‧ direction

1A to 1I are schematic cross-sectional views showing a manufacturing process of a pixel structure according to a first embodiment of the present invention.

2A to 2I are schematic top views showing a manufacturing process of a pixel structure according to a first embodiment of the present invention.

Figure 3 is a cross-sectional view taken along line C-C' of Figure 2I.

Figure 4 shows the semiconductor pattern in the vicinity of the first contact opening in Figure 2I.

Fig. 5A is a top plan view showing a pixel structure of a second embodiment of the present invention.

Fig. 5B is a cross-sectional view taken along line D-D' of Fig. 5A.

Fig. 6A is a top plan view showing a pixel structure of a third embodiment of the present invention.

Fig. 6B is a cross-sectional view taken along line E-E' of Fig. 6A.

7A is a top plan view showing a pixel structure of a fourth embodiment of the present invention.

Fig. 7B is a cross-sectional view taken along line F-F' of Fig. 7A.

Fig. 8A is a top plan view showing a pixel structure of a fifth embodiment of the present invention.

Fig. 8B is a cross-sectional view taken along line G-G' of Fig. 8A.

9A is a top plan view showing a pixel structure of a sixth embodiment of the present invention.

Fig. 9B is a cross-sectional view taken along the line H-H' of Fig. 9A.

1A to 1I are schematic cross-sectional views showing a manufacturing process of a pixel structure according to a first embodiment of the present invention. 2A to 2I are schematic top views showing a manufacturing process of a pixel structure according to a first embodiment of the present invention. In particular, FIGS. 1A to 1I are cross-sectional views taken along line AA', BB' of FIGS. 2A to 2I. Referring to FIGS. 1A and 2A, first, a first buffer layer 104 can be selectively formed on the substrate 102 before any members are fabricated. The first buffer layer 104 can cover the substrate 102 in a comprehensive manner. In the present embodiment, the material of the substrate 102 is, for example, glass, and the material of the first buffer layer 104 is, for example, tantalum nitride (SiN _x ), but the invention is not limited thereto. Next, a second buffer layer 106 is more selectively formed on the first buffer layer 104. The second buffer layer 106 can cover the first buffer layer 104 in a comprehensive manner. In the present embodiment, the material of the second buffer layer 106 is, for example, yttrium oxide (SiO _x ), but the invention is not limited thereto. Of course, the first buffer layer 104 and the second buffer layer 106 may be omitted when the substrate 102 has desirable properties, such as when it has desirable adhesion to other material layers. Alternatively, the substrate 102 itself may be a composite substrate having a multilayer structure. It is worth mentioning that in the upper view shown in FIG. 2A, only the second buffer layer 106 is indicated, and the first buffer layer 104 and the substrate 102 below it are omitted. In addition, the marking of other upper views in this paper also omits the label of the underlying film layer, so the specific film layer stacking relationship can refer to the content of the cross-sectional view.

In addition, a semiconductor pattern 108 is formed on the substrate 102. In the present embodiment, the semiconductor pattern 108 may be formed on the second buffer layer 106. The material of the semiconductor pattern 108 is, for example, polysilicon, but the invention is not limited thereto. Specifically, the outline of the semiconductor pattern 108 may be disposed in accordance with a predetermined formed member, and is not limited to the shape illustrated in FIG. 2A. In the present embodiment, the semiconductor pattern 108 may have two portions, a first portion 108a and a second portion 108b, and the two portions are connected to each other, for example.

Please refer to FIG. 1B and FIG. 2B, and then formed on the semiconductor pattern 108. The first insulating layer 110. The first insulating layer 110 may completely cover the semiconductor pattern 108. In addition, the material of the first insulating layer 110 may be tantalum oxide, tantalum nitride, an organic dielectric material or other materials that can provide ideal insulation.

Referring to FIG. 1C and FIG. 2C, a photoresist pattern layer 112 is then formed on the first insulating layer 110. The photoresist pattern layer 112 covers the first portion 108a of the semiconductor pattern 108 to expose the second portion 108b of the semiconductor pattern 108. Then, the doping process is performed with the photoresist pattern layer 112 as a mask. At this time, the second portion 108b exposed by the photoresist pattern layer 112 is doped with a dopant of a desired carrier concentration (for example, a P-type dopant or an N-type dopant). In general, the second portion 108b of the semiconductor pattern 108 has an increased conductivity, such as higher than the first portion 108a, after being doped with the dopant.

Referring to FIG. 1D and FIG. 2D, after the photoresist pattern layer 112 is removed, a first pre-patterned conductor layer 114' is formed on the first insulating layer 110, wherein the first pre-patterned conductor layer 114' uses a pre-lighting The resist pattern layer (not shown) is patterned by the mask. In this embodiment, the material of the first pre-patterned conductor layer 114 ′ is, for example, metal, but the invention is not limited thereto. The material of the first pre-patterned conductor layer 114 ′ may be metal or a plurality of conductive materials. Laminated construction. The first pre-patterned conductor layer 114' may define a plurality of members including predetermined gates 114a', 114b', predetermined scan lines 114c' connected to predetermined gates 114a', 114b', and predetermined capacitor electrodes 114d' . In the present embodiment, the predetermined scan line 114c' traverses the first portion 108a of the semiconductor pattern 108. Accordingly, the predetermined gates 114a', 114b' may be members defined by the predetermined scan line 114c' overlapping the first portion 108a. In addition, the predetermined capacitance electrode 114d' overlaps with the second portion 108b of the semiconductor pattern 108 and Separated by the first insulating layer 110.

In the present embodiment, the first pre-patterned conductor layer 114' blocks a partial area of the first portion 108a of the semiconductor pattern 108, as shown in Figure 2D. Therefore, in the present embodiment, the doping process is then performed with the first pre-patterned conductor layer 114' as a mask. At this time, in FIG. 2D, the semiconductor pattern 108 not shielded by the first pre-patterned conductor layer 114' is doped with a dopant of a desired carrier concentration (eg, an N-type dopant or a P-type dopant). The first pre-doped regions S1', S2' and the first pre-doped regions D1', D2' are formed in the vicinity of the predetermined scan line 114c', respectively. Here, the first pre-doped region S1' and the first pre-doped region D1' are located on opposite sides of the predetermined gate 114a', and the first pre-doped region S2' and the first pre-doped region D2' Located on opposite sides of the predetermined gate 114b'. Also, the first pre-doped region D1' and the first pre-doped region S2' are, for example, connected to each other.

Referring to FIG. 1E and FIG. 2E, the area of each member of the first pre-patterned conductor layer 114', such as the line width, may be further reduced to form a first conductor layer 114, wherein the first conductor layer 114 includes a gate 114a, 114b, scan line 114c, and capacitor electrode 114d. The scan line 114c of the present embodiment may have a fixed line width and the line width is reduced to a minimum within the tolerance of the process capability, thereby increasing the aperture ratio of the overall design. The first conductor layer 114 is formed by reducing the line width of the first pre-patterned conductor layer 114', which will cause a portion of the first portion 108a of the semiconductor pattern 108 that has not been doped to be further exposed. Therefore, in the present embodiment, the semiconductor pattern 108 is then subjected to a doping process with the first conductor layer 114 as a mask, and a dopant having a desired carrier concentration (for example, an N-type dopant or a P) is doped. Type dopant) to form a plurality of first dopants Miscellaneous regions S1, D1, S2 and D2 and a plurality of second doped regions LDD.

After the doping process described above, the portion of the first portion 108a that is shielded by the gates 114a and 114b of the first conductor layer 114 is defined as the undoped channel region CH, as shown in FIG. 1E. And, between the channel region CH and the first doping region D1, between the channel region CH and the first doping region D2, between the channel region CH and the first doping region S1, the channel region CH and the first doping region There is a second doped region LDD between S2, respectively. Since the second doping region LDD is subjected to a doping process once and the first doping regions S1, D1, S2, and D2 are subjected to two doping processes, the second doping regions LDD can be mitigated by the action of the hot carrier. The resulting leakage current problem further enhances the electrical characteristics of the pixel structure of the present embodiment.

Referring to FIG. 1F and FIG. 2F, a second insulating layer 118 is formed on the first conductor layer 114. Then, a patterning process is performed again to form the first contact opening V1 and the second contact opening V2 in the first insulating layer 110 and the second insulating layer 118. The first contact opening V1 exposes the first doping region S1. The second contact opening V2 exposes the first doping region D2. The first contact opening V1 and the second contact opening V2 both penetrate the first insulating layer 110 and the second insulating layer 118 to expose the first doping region S1 and the first doping region D2. Therefore, the first contact opening V1 includes the first lower contact opening V1D of the first insulating layer 110 and the first upper contact opening V1U of the second insulating layer 118, and the second contact opening V2 includes the second insulating layer 110. The lower contact opening V2D and the second upper portion of the second insulating layer 118 contact the opening V2U.

However, the present invention is not limited thereto, and the first insulating layer 110 and the second insulating layer 118 may have a multi-layer laminated structure, respectively, and the first contact opening V1 and The second contact opening V2 may be configured to communicate with each other by a plurality of contact openings penetrating the multilayer laminated structures. In addition, the sizes of the first contact opening V1 and the second contact opening V2 may be adjusted according to different needs. For example, in the first contact opening V1, the width W1 of the first contact opening V1 may be greater than the width W of the first doping region S1 on the track of the line AA' to expose the first doping region. S1 part of the side wall. Actually, the first contact opening V1 may have inclined side walls as shown in FIG. 1F, and thus the width W1 of the first contact opening V1 means the size of the first contact opening V1 at the widest point on the path of the line AA' . Further, the line A-A' is, for example, parallel to the extending direction of the scanning line 114c.

Referring to FIGS. 1G and 2G, a second conductor layer 120 is formed on the second insulating layer 118. The second conductor layer 120 includes a data line 120a intersecting the scan line 114c and a connection pattern 120b. The data line 120a is filled in the first contact opening V1 and is in electrical contact with the first doping region S1. The connection pattern 120b is electrically connected to the first doping region D2 across the capacitor electrode 114d and the first doping region D2 and fills the second contact opening V2.

In the present embodiment, the second conductor layer 120 is formed by, for example, forming a layer of a conductor material, and then patterning the conductor material layer into a desired pattern, that is, forming the data line 120a and the connection pattern 120b. In the process of forming the conductor material layer, the first contact opening V1 exposes a partial area of the first doping region S1, so the data line 120b of the second conductor layer 120 can surely contact the first doping region S1 to define The first contact area R1 is taken out. Similarly, the connection pattern 120b may contact the first doping region D2 through the second contact opening V2.

Further, in the patterning process of forming the data line 120a, the first doping region S1 is also accompanied by being patterned. Therefore, in the area of the first contact opening V1, the profile of the data line 120a and the first doping region S1 may be substantially the same. As such, in FIG. 1G, the width K1 of the first contact region R1 may be substantially equal to the width Wd of the data line 120a in the first contact opening V1. At this time, the first side wall E1 and the second side wall E2 of the data line 120a are, for example, located within the area of the first contact opening V1 and exposed by the first contact opening V1. The first contact region of the first doping region S1 has contact region sidewalls F1 and F2, and the contact region sidewall F1 and the contact region sidewall F2 are also located within the area of the first contact opening V1 and are exposed by the first contact opening V1.

It should be noted that, in this embodiment, the width W1 of the first contact opening V1, the width Wd of the data line 120a, and the width K1 of the first contact region R1 refer to the measurement width in the direction X, wherein the direction X It is a direction perpendicular to the extending direction of the data line 120a, that is, a direction parallel to the scanning line 114c, and is also an extending direction of the line A-A' in Fig. 2G. In addition, the data line 120a can be designed to have a fixed line width Wd whose width can be minimized within the tolerance of the process capability, thereby increasing the aperture ratio of the overall design.

In the conventional design, in order for the data line 120a to be in contact with the first doping region S1, it is necessary to increase the width Wd of the data line 120a made of the light-shielding conductive material at the first contact opening V1, which limits the increase of the aperture ratio. . In the present embodiment, the width W1 of the first contact opening V1 is increased. Therefore, during the formation of the second conductor layer 120, the data line 120a can be easily contacted with the first doped region S1 without corresponding Widening the data line 120a at the first contact opening V1, which helps to reduce The negative impact of the data line 120a on the aperture ratio.

Referring to FIGS. 1H and 2H, a third insulating layer 122 is formed on the second conductor layer 120. Then, a third contact opening V3 is formed in the third insulating layer 122. The third contact opening V3 exposes the connection pattern 120b. Referring to FIG. 1I and FIG. 2I, a pixel electrode 124 is formed on the third insulating layer 122, and the pixel structure 100 of the present embodiment is completed. The pixel electrode 124 is filled in the third contact opening V3 to be in contact with the connection pattern 120b. Here, the pixel electrode 124 is electrically connected to the first doping region D2 through the connection pattern 120b. Further, the pixel electrode 124, the second portion 108b of the semiconductor pattern 108, and the capacitor electrode 114d overlap each other to constitute a storage capacitor structure required for the pixel structure 100.

Specifically, in FIG. 1I, the stack of the pixel structures 100 includes the substrate 102, the first buffer layer 104, the second buffer layer 106, the semiconductor pattern 108, the first insulating layer 110, and the first conductor layer. 114. The second insulating layer 118, the second conductive layer 120, the third insulating layer 122, and the pixel electrode 124. In the present embodiment, the first buffer layer 104 and the second buffer layer 106 are disposed between the semiconductor pattern 108 and the substrate 102, but the invention is not limited thereto.

1I and 2I, the semiconductor pattern 108 includes a first portion 108a and a second portion 108b, and the first portion 108a includes a first doping region S1, D1, S2, D2, and a second doping. The zone LDD and the channel zone CH, wherein the channel zone CH is blocked by the gates 114a, 114b in Figure 2I. The first conductor layer 114 includes gates 114a, 114b overlapping the channel region CH, scan lines 114c connected to the gates 114a, 114b, and a capacitor electrode 114d overlapping the second portion 108b. Second conductor layer 120 includes a data line 120a that intersects the scan line 114c and a connection pattern 120b that spans between the capacitor electrode 114d and the first doped region D2.

The data line 120a contacts the first doping region S1 exposed by the first contact opening V1 to define a first contact region R1. The connection pattern 120b contacts the first doping region D2 exposed by the second contact opening V2 to define a second contact region R2. In addition, the pixel electrode 124 is connected to the connection pattern 120b through the third contact opening V3, and is electrically connected to the first doping region D2 through the connection pattern 120b.

In this embodiment, the gate 114a is located between the first doping region S1 and the first doping region D1, and between the gate electrode 114a and the first doping region S1 and between the gate electrode 114a and the first doping region. A second doping region LDD is disposed between D1, respectively. The gate 114b is located between the first doping region S2 and the first doping region D2, and between the gate electrode 114b and the first doping region S2 and between the gate electrode 114b and the first doping region D2. Second doped region LDD.

According to the foregoing process steps, the first doping regions S1, D1, S2, and D2 are subjected to two doping processes and may have improved conductive properties. Therefore, the first doping regions S1, D1, S2, and D2 can be regarded as the first source region, the first drain region, the second source region, and the second drain region, respectively. In this way, the first doping regions S1 and D1 as the first source region and the first drain region are respectively located on one side of one of the channel regions CH, and the gate 114a corresponds to one of the channel regions CH to constitute the first An active component. Meanwhile, the first doping regions S2 and D2 as the second source region and the second drain region are respectively located on opposite sides of the other channel region CH, and the gate electrode 114b corresponds to the other channel region CH to constitute the second active region. element. In addition, in this embodiment, the first doping region D1 The first doping regions S2 are connected to each other. That is, the first drain region of the first active device (ie, the first doped region D1) and the second source region of the second active device (ie, the first doped region S2) are connected to each other. Therefore, the first active component and the second active component substantially constitute a two-channel thin film transistor structure.

In the present embodiment, as shown in FIG. 1I, the first side wall E1 of the data line 120a is separated from the edge e1 of the first contact opening V1 by a distance d1. In addition, the contact region sidewall F1 is aligned with the first sidewall E1 of the data line 120a, and thus the contact region sidewall F1 and the edge e1 of the first contact opening V1 are substantially separated by a distance d1. The second side wall E2 of the data line 120a is separated from the edge e2 of the first contact opening V1 by a distance d2. The contact region sidewall F2 and the edge e2 of the first contact opening V1 are also substantially separated by a distance d2. Here, the distance d1 may be equal to or not equal to the distance d2.

Figure 3 is a cross-sectional view taken along line C-C' of Figure 2I. Referring to FIG. 2I and FIG. 3, the first doping region S1 of the embodiment may further divide the peripheral region P1 adjacent to the first contact region R1. The peripheral region P1 is covered by the first insulating layer 110, and the first contact region R1 is exposed through the first contact opening V1 of the first insulating layer 110. As shown in FIG. 3, the data line 120a may also be divided into a contact portion 120aa and a wire portion 120ab adjacent to the contact portion 120aa, wherein the contact portion 120aa is a portion in contact with the first contact region R1. The wire portion 120ab extends outward from the contact portion 120aa and covers the first contact opening V1 and the second insulating layer 118. In addition, the wire portion 120ab further blocks the peripheral region P1 of the first doping region S1. The above description is for explaining the relationship between the data line 120a in the structure presented by the line C-C' of Fig. 2I and the first doping region S1 as the first source, and is not intended to limit the present invention. In other corresponding to different sections In the cross-sectional structure, the data line 120a and the first doped region S1 may have other arrangement relationships.

Furthermore, FIG. 4 shows the outline of the first doping region S1 in the vicinity of the first contact opening V1 in FIG. Referring to FIG. 4, since the first doping region S1 exposed by the first contact opening V1 is patterned together with the data line 120a in FIG. 2I, the width K1 of the first contact region R1 is smaller than the width of the peripheral region P1. K2. Overall, the semiconductor pattern 108 near the first contact opening V1 (i.e., the dotted line in Fig. 4) approximates an I-shape.

Fig. 5A is a top plan view showing a pixel structure of a second embodiment of the present invention. Fig. 5B is a cross-sectional view taken along line D-D' of Fig. 5A. Referring to FIGS. 5A and 5B, the pixel structure 100A of the present embodiment is similar to the pixel structure 100 of the first embodiment, and therefore the same elements are denoted by the same reference numerals. The main difference between the pixel structure 100A and the pixel structure 100 is that the size and position of the first contact opening V1 of the present embodiment with respect to the data line 120a and the first doping region S1 are different from those of the first embodiment. The difference is explained below, and the similarities will not be repeated.

In this embodiment, the data line 120a has opposite first side walls E1 and second side walls E2, as shown in FIG. 5A. Different from the first embodiment, as shown in FIG. 5B, the first side wall E1 and the second side wall E2 of the data line 120a overlap the edges e1, e2 of the first contact opening V1, respectively. In other words, as shown in FIG. 5A, the data line 120a just fills the first contact opening V1.

Fig. 6A is a top plan view showing a pixel structure of a third embodiment of the present invention. Fig. 6B is a cross-sectional view taken along line E-E' of Fig. 6A, respectively. Please refer to FIG. 6A and 6B, the pixel structure 100B of the present embodiment is similar to the pixel structure 100 of the first embodiment, and therefore the same elements are denoted by the same reference numerals. The main difference between the pixel structure 100B and the pixel structure 100 is that the size and position of the first contact opening V1 of the present embodiment with respect to the data line 120a and the first doping region S1 are different from those of the first embodiment. The difference is explained below, and the similarities will not be repeated.

In this embodiment, the first sidewall E1 of the data line 120a is located within the first contact opening V1. Different from the first embodiment, the second side wall E2 is located outside the first contact opening V1. In other words, the data line 120a covers the edge e2 of the first contact opening V1 and is exposed or substantially aligned with the edge e1 of the first contact opening V1. In addition, the data line 120a completely covers the first doping region S1 exposed by the first contact opening V1 to define the first contact region R1. At this time, as seen from FIG. 6B, the width of the first contact region R1 is smaller than the width of the first contact opening V1 and also smaller than the width of the data line 120a.

7A is a top plan view showing a pixel structure of a fourth embodiment of the present invention. Fig. 7B is a cross-sectional view taken along line F-F' of Fig. 7A, respectively. Referring to FIGS. 7A and 7B, the pixel structure 100C of the present embodiment is similar to the pixel structure 100B of the third embodiment, and therefore the same elements are denoted by the same reference numerals. The main difference between the pixel structure 100C and the pixel structure 100B is that, as shown in FIG. 7B, the first doping region S1 of the present embodiment has at least one semiconductor opening O. The difference is explained below, and the similarities will not be repeated.

In the present embodiment, the first doping region S1 is patterned together with the data line 120a, and thus the first doping region S1 has at least one semiconductor opening O. semiconductor The opening O is located in the first contact opening V1. As shown in FIG. 7B, a portion of the edge of the semiconductor opening O overlaps the first sidewall E1 of the data line 120a that the first contact region R1 contacts. The other portion of the edge of the semiconductor opening O is overlapped with a portion of the edge of the first contact opening V1. That is, the semiconductor opening O is located between the first side wall E1 of the data line 120a and a portion of the edge of the first contact opening V1.

Fig. 8A is a top plan view showing a pixel structure of a fifth embodiment of the present invention. Fig. 8B is a cross-sectional view taken along line G-G' of Fig. 8A, respectively. Referring to FIGS. 8A and 8B, the pixel structure 100D of the present embodiment is similar to the pixel structure 100 of the first embodiment, and thus the same elements are denoted by the same reference numerals. The main difference between the pixel structure 100D and the pixel structure 100 is that the size and position of the second contact opening V2 of the present embodiment with respect to the connection pattern 120b and the first doping region D2 are different from those of the first embodiment. The difference is explained below, and the similarities will not be repeated.

In the present embodiment, the connection pattern 120b is defined as the second contact region R2 at the second contact opening V2 contacting the first doping region D2, and the second contact opening V2 exposing the second contact region R2. Specifically, at the second contact opening V2, the width W2 of the second contact opening V2 is set to be not smaller than the width Wc of the connection pattern 120b, or even larger than the width K3 of the second contact region R2. The above width is the width measured in the direction X. As shown in FIG. 8B, the connection pattern side walls g1, g2 of the connection pattern 120b and the edges A1, A2 of the second contact opening V2 are separated by, for example, a distance L1, L2. The connection pattern sidewalls g1, g2 of the connection pattern 120b are opposed to each other and coincide with the first doping region D2 at the contact region sidewalls f1, f2 of the second contact region R2. Therefore, the contact region sidewalls f1, f2 are also separated from the edges A1, A2 of the second contact opening V2, respectively. Distance L1, L2.

9A is a top plan view showing a pixel structure of a sixth embodiment of the present invention. Fig. 9B is a cross-sectional view taken along line H-H' of Fig. 9A, respectively. Referring to FIGS. 9A and 9B, the pixel structure 100E of the present embodiment is similar to the pixel structure 100D of the fifth embodiment, and therefore the same elements are denoted by the same reference numerals. The main difference between the pixel structure 100E and the pixel structure 100D is that the size and position of the second contact opening V2 of the present embodiment with respect to the connection pattern 120b and the first doping region D2 are different from those of the first embodiment. The difference is explained below, and the similarities will not be repeated. In the present embodiment, as shown in FIG. 9B, the connection pattern side walls g1, g2 of the connection pattern 120b overlap the edges A1, A2 of the second contact opening V2. In other words, as shown in FIG. 9A, the connection pattern 120b just fills the second contact opening V2.

In summary, in the pixel structure of an embodiment of the present invention, the width of the contact opening can be designed to be larger than the contact area of the semiconductor pattern to be in contact with the second conductor layer. As a result, during the formation of the second conductor layer, the second conductor layer can be easily contacted with the contact region without requiring high alignment precision. Therefore, the line width of the second conductor layer, such as the data line, can be designed to be small, thereby increasing the aperture ratio of the pixel structure.

100‧‧‧ pixel structure

108‧‧‧Semiconductor pattern

108a‧‧‧Part I

108b‧‧‧Part II

114‧‧‧First conductor layer

114a, 114b‧‧‧ gate

114c‧‧‧ scan line

114d‧‧‧Capacitor electrode

120‧‧‧Second conductor layer

120a‧‧‧Information line

120b‧‧‧Connected pattern

124‧‧‧pixel electrodes

A-A’, B-B’, C-C’‧‧‧

D1, D2, S1, S2‧‧‧ first doped area

LDD‧‧‧Second doped area

R1‧‧‧ first contact area

R2‧‧‧Second Contact Area

V1‧‧‧ first contact opening

V2‧‧‧second contact opening

V3‧‧‧ third contact opening

Claims (19)

A pixel structure includes: a semiconductor pattern disposed on a substrate, and the semiconductor pattern includes a first contact region, a second contact region, and a first contact region and the second contact region a channel region; a first insulating layer covering the semiconductor pattern and having a first lower contact opening; a first conductor layer disposed on the substrate, and the first conductor layer includes a layer overlapping the channel region a gate and a scan line connected to the gate; a second insulating layer covering the first conductor layer and having a first upper contact opening, wherein the first upper contact opening and the first lower contact opening form a first contact opening exposing the semiconductor pattern to define the first contact region; a second conductor layer disposed on the second insulating layer, and the second conductor layer includes intersecting the scan a data line of the line, the data line is in contact with the first contact area exposed by the first contact opening, and a first side wall of the data line is located within an area of the first contact opening; Edge layer covering the second conductive layer; and a pixel electrode disposed on the third insulating layer and electrically connected to the second contact region. The pixel structure of claim 1, wherein the width of the first contact opening is not less than the width of the data line. The pixel structure of claim 1, wherein the width of the first contact opening is greater than the width of the first contact region. The pixel structure of claim 1, wherein the first sidewall of the data line overlaps an edge of the first contact opening. The pixel structure of claim 1, wherein the first sidewall of the data line is spaced from the edge of the first contact opening by a distance. The pixel structure of claim 5, wherein the first contact region of the semiconductor pattern has a contact sidewall and the sidewall of the contact overlaps the first sidewall of the data line to enable the contact The side wall of the zone is spaced from the edge of the first contact opening by the distance. The pixel structure of claim 1, wherein a second sidewall of the data line is located within an area of the first contact opening, and the first sidewall and the second sidewall are opposite each other. The pixel structure of claim 7, wherein the second sidewall of the data line overlaps an edge of the first contact opening. The pixel structure of claim 7, wherein the second sidewall of the data line is spaced from the edge of the first contact opening by a distance. The pixel structure of claim 1, wherein a sidewall of the contact region of the first contact region of the semiconductor pattern overlaps with the first sidewall and a second sidewall of the data line, wherein the data line The second sidewall is opposite the first sidewall of the data line. For example, the pixel structure described in claim 1 of the patent scope, wherein the first The edge layer has a second lower contact opening, the second insulating layer has a second upper contact opening, and the second upper contact opening and the second lower contact opening form a second contact opening to expose the second contact area And the second conductor layer further includes a connection pattern, the connection pattern is in contact with the second contact region exposed by the second contact opening, and the connection pattern is electrically connected to the pixel electrode. The pixel structure of claim 11, wherein the width of the second contact opening is not less than the width of the connection pattern. The pixel structure of claim 11, wherein a connecting pattern sidewall of the connecting pattern overlaps an edge of the second contact opening. The pixel structure of claim 11, wherein a connecting pattern sidewall of the connecting pattern is spaced apart from an edge of the second contact opening by a distance. The pixel structure of claim 1, wherein the first conductor layer further comprises a capacitor electrode superposed on the pixel electrode to form a storage capacitor. The pixel structure of claim 1, wherein the data line has a fixed line width. The pixel structure of claim 1, wherein the semiconductor pattern further comprises a peripheral region adjacent to the first contact region, the peripheral region being covered by the first insulating layer, the first contact region being The first contact opening is exposed, and the width of the first contact region is less than the width of the peripheral region. The pixel structure of claim 1, wherein the data line includes a contact portion in contact with the first contact region and a wire portion adjacent to the contact portion, and the wire portion is in the first insulation And a layer on the second insulating layer. The pixel structure of claim 1, wherein the semiconductor pattern has at least one semiconductor opening, the semiconductor opening is located in the first contact opening, and a portion of an edge of the semiconductor opening overlaps the first sidewall.