TW201501258A - Composite carrier structure of flip chip chip-scale package and manufacturing method thereof - Google Patents

Abstract

The present invention provides a composite carrier structure of flip chip chip-scale package and manufacturing method thereof, which digs a through hole on the substrate lamination insulating film of flip chip region and bonds the insulating film with the carrier to form a composite carrier structure. Thereby, when the chip is implanted into the flip chip region of the composite carrier structure, the present invention can withstand different types of stress generated during packaging process, and prevent the slim-type carrier occurring with warpage due to thermal stress by combining with a substrate with low thermal expansion coefficient but maintaining the bonding function for stacked packaging elements, so as to achieve the effects of thinning, enhanced heat dissipation, and improving mechanical strength.

Description

Composite carrier structure of flip chip wafer level package and preparation method thereof

The invention relates to a composite carrier structure and a manufacturing method for a flip chip wafer level package, which is to improve mechanical strength and heat dissipation by a composite carrier structure.

According to FIG. 1A to FIG. 1D and FIG. 2A to FIG. 2D , a schematic diagram of two methods for fabricating a flip-chip wafer level package is disclosed. The Flip chip-Chip scale package (FC-CSP) is disclosed. ) is a three-element packaging technology that meets the requirements of communication products toward high power, high density, thin and light miniaturization. However, it can basically be divided into two stages: carrier board and package process. When the chip is completed through two stages, a package is formed. The package structure can also be the main structure of a package on package (POP), which can support or connect other package structures or printed circuit boards.

As shown in FIG. 1A to FIG. 1D, the flip chip wafer level packaging step method is as follows: 1. Carrier board: a) As shown in FIG. 1A, a carrier board 10 having a thickness greater than or equal to 150 um is provided, and the upper surface thereof is provided. a plurality of first and second plurality of contact points 11 and 12 are disposed. The second contact point 12 is disposed around the first contact point 11 and has a plurality of third contact points 13 on the lower surface thereof. : b) As shown in FIG. 1B, at least one die 14 is provided having opposite active and inactive surfaces 141, 142, and a plurality of bumps 143 are disposed on the active surface 141, and the bumps 143 are adhered thereto. The first contact point 11 is further reflowed by the carrier 10 carrying the wafer 14 through the flux, so that the wafer 14 can be fixed on the carrier 10, and when the reflow is completed, The deflux on the carrier 10 is removed and flowed by a capillary phenomenon, so that a primer 15 can be underfilled between the wafer 14 and the carrier 10; c) FIG. 1C As shown, a first ball 16 is attached to the second contact 12, and the first solder ball is covered by a package molding material 17. 6 and the wafer 14, according to the molding; and d) shown in FIG. 1D, a second ball 18 is adhered to the third contact point 13, and finally the laser is applied to the package molding material 17 The molten Mold Via (TMV) is placed at a predetermined position to expose the first solder ball 16 to a bare state.

As shown in FIG. 2A to FIG. 2D, the flip chip wafer level packaging step method is as follows: 1. Carrier board: a) As shown in FIG. 2A, a carrier board 10 having a thickness greater than or equal to 150 um is provided, and the upper surface thereof is provided. A plurality of first and plural second contact points 11 and 12 are disposed. The second contact point 12 is disposed around the first contact point 11 and has a plurality of third contact points 13 on the lower surface thereof. The factory pre-plants the first solder ball 16 at the second contact point 12; 2. The packaging process: b) shown in FIG. 2B, providing at least one wafer 14 having opposing active and inactive surfaces 141, 142, and The active surface 141 is provided with a plurality of bumps 143. The bumps 143 are adhered to the first contact point 11 and then reflowed by the carrier 10 carrying the wafer 14 through the flux to fix the wafer 14 to the carrier 10. When the reflow is completed, the flux on the carrier 10 can be removed; c) as shown in FIG. 2C, a package molding material 17 is provided to cover the first solder ball 16 while adhering to both sides of the wafer 14 and Between the wafer 14 and the carrier 10, the upper surface of the wafer 14 is exposed to a state of being packaged, and d) is shown in FIG. 2D. Providing a second solder balls 18 adhered to the third contact point 13, and finally to the laser 17 at a predetermined place on the molded plastic package molding material through hole, so that the top of the first solder balls 16 has a bare state.

Therefore, the above two methods for manufacturing a flip-chip wafer level package belong to the mold-molding through-hole structure adopted in the mainstream of the flip chip package product, and the carrier plate 10 itself needs to bear the support function during reflow and consider the packaged product. The warpage problem, therefore, the carrier 10 needs to use a core thickness of 150 um or more or more, so that the total thickness of the carrier 10 cannot be reduced, and the through-hole structure of the molding compound formed by the method of flip chip wafer level packaging is adopted. The total thickness of the packaged products that hinder the laminated package continues to drop, and cannot meet the demand for future thinning, so there is still room for improvement.

The main purpose of the present invention is to improve the mechanical strength by the composite structure, thereby reducing the effect of the bending of the carrier.

Another object of the present invention is to improve the substrate design to enhance the heat dissipation of the composite structure, thereby reducing the effectiveness of the carrier plate bending.

To achieve the above objective, the composite wafer carrier structure of the flip chip wafer package of the present invention comprises: a carrier board having a plurality of first and plural second contact points on the upper surface thereof, the second contact point being ring-shaped A substrate is disposed with a plurality of electrically conductive through-holes. The upper and lower ends of the electrical conductive body are exposed to the upper and lower surfaces, and the upper and lower ends of the electrical conductive body are respectively electrically connected. a surface of the lower surface of the first electrode pad and the upper surface of the plurality of second electrode pads, and the surface of the upper surface of the plurality of second electrode pads is excavated, and the surface of the upper surface of the insulating film is attached to the lower surface thereof, and a position of the lower surface of the second electrode pad relative to the second contact point, wherein the second contact point is electrically connected to the lower surface of the second electrode pad, and the position of the first contact point relative to the flip chip area, The first contact point is located in the flip chip region, and the lower surface of the insulating film is formed to bond the upper surface of the carrier.

According to the foregoing feature, the electrical via may be in the shape of a through hole; the through hole may also be a symmetric frustum having a wider upper and lower ends; the substrate having a combination of the first and second layers; The electrical via has a blind conductor-shaped upper conductor, a buried via-shaped middle conductor, and a blind via-shaped lower conductor combination. The upper conductor and the middle conductor are located at the first layer and the lower conductor is located at the second layer The electrical via has a first conductor of a blind hole shape and a second conductor combination of a semi-via shape, the first conductor being located at the first layer and the second conductor being between the first and second Floor. [00010] According to the foregoing feature, further comprising at least one wafer having opposite active and inactive surfaces, and having a plurality of bumps on the active surface, the bumps engaging the first contact point, and then applying a glue A material is filled in the gap between the flip chip region and the wafer, so that the wafer can be fixed in the flip chip region, and the inactive surface is formed in a bare state. [00011] A method for fabricating a composite wafer structure of a flip chip wafer level package includes the steps of: a) providing a carrier board having a plurality of first and plural second contacts on an upper surface thereof a second contact point collar is disposed around the first contact point; b) providing a substrate, the substrate is provided with a plurality of electrical conductive bodies, the upper and lower ends of the electrical conductive body are exposed on the substrate, a lower surface, and the upper surface of the plurality of first electrode pads and the upper surface of the plurality of second electrode pads are electrically connected to the upper and lower ends of the electrical conductive body, and the substrate is dug through a flip-chip region of the through opening, and Providing an upper surface of the insulating film to be attached to the lower surface of the substrate, and further, a position of the lower surface of the second electrode pad relative to the second contact point, and electrically connecting the second contact point to the second The lower surface of the electrode pad, and the position of the first contact point relative to the flip-chip region, is such that the first contact point is located in the flip-chip region, and the lower surface of the insulating film is formed to bond the upper surface of the carrier. According to the foregoing feature, further comprising the step c), providing at least one wafer having opposite active and inactive surfaces, and having a plurality of bumps on the active surface, the bumps engaging the first contact point Then, a glue material is filled in the gap between the flip chip region and the wafer, so that the wafer can be fixed in the flip chip region, and the non-active surface is formed in a bare state. By means of the above-mentioned technical means, the present invention uses a substrate having a heat dissipation function, the substrate is transmitted through the first and second electrode pads of the electrical conduction body, so that the substrate has the functions of conducting and overlapping bonding, and simultaneously reducing the mode. The through hole process, the substrate is provided with a flip chip region for heat dissipation, and the carrier, the insulating film and the substrate form a composite structure having mechanical strength, and further, when the wafer is implanted in the flip chip region for packaging During the reflow of the process, it is not easy to cause the thin carrier plate to cause bending problems during support, thereby further reducing the thickness, increasing the mechanical strength, enhancing the heat dissipation and reducing the bending effect.

[00015] First, referring to FIG. 3A to FIG. 3D, a composite carrier structure of a flip chip-chip scale package (FC-CSP) according to the present invention is divided into a carrier process and a package. Two stages of the process: [00016] The schematic diagram of the carrier board and the substrate shown in FIG. 3A and FIG. 3B is carried out before and after the carrier board process, which belongs to the carrier board process: a) providing a carrier board 20, the carrier board 20 is provided on the upper surface thereof. a plurality of first and second plurality of contact points 21, 22, wherein the second contact point 22 is disposed around the first contact point 21, and the lower surface thereof is provided with a plurality of third contact points 23; b) providing a substrate 40. The substrate is provided with a plurality of electrical conductive bodies 41. The upper and lower ends of the electrical conductive body 41 expose the upper and lower surfaces of the substrate. The upper and lower ends of the electrical conductive body 41 are respectively electrically connected to the first plurality. The lower surface of the electrode pad 42 and the upper surface of the plurality of second electrode pads 43 are disposed, and the substrate 40 is dug through a flip-chip region 44 extending through the opening, and an upper surface of the insulating film 30 is attached to the lower surface thereof. The lower surface of the second electrode pad 43 is opposite to the second contact point The position of 22 is such that the second contact point 22 is electrically connected to the lower surface of the second electrode pad 43 and the position of the first contact point 21 relative to the flip chip area 44, so that the first contact point 21 is Located in the flip-chip region 44, a surface under the insulating film 30 (NCF) is formed to bond the upper surface of the carrier 20. [00017] A schematic diagram of package molding and structure as shown in FIGS. 3C and 3D, which belongs to the packaging process: c) providing at least one wafer 50 having opposite active and inactive surfaces 51, 52, And the active surface 51 is provided with a plurality of bumps 53. The bumps 53 are joined to the first contact points 21, and a glue material 60 is filled in the gap between the flip chip region 44 and the wafer 50. The wafer 50 can be fixed in the flip-chip region 44 to form the inactive surface 52 in a bare state, and the solder ball B is adhered to the third contact point 23. [00018] In the present embodiment, a composite carrier structure having a strength mechanism is presented after the carrier process, the composite carrier structure is a carrier 20 having a plurality of first and plural numbers on the upper surface thereof. a second contact point 21, 22, the second contact point 22 is disposed around the first contact point 21, and a lower third surface is provided with a plurality of third contact points 23; a substrate 40 is provided with a plurality of through-holes The upper and lower surfaces of the electrically conductive body 41 are exposed to the upper and lower surfaces of the electrically conductive body 41. The upper and lower ends of the electrically conductive body 41 are electrically connected to the lower surface of the plurality of first electrode pads 42 and the plurality of second electrode pads. a surface of the upper surface of the 43, and a planar region 44 of the through opening is provided, and an upper surface of the insulating film 30 is attached to the lower surface thereof. Further, the lower surface of the second electrode pad 43 is opposite to the first surface. The position of the second contact point 22 is electrically connected to the lower surface of the second electrode pad 43 and the position of the first contact point 21 relative to the flip chip area 44, so that the first The contact point 21 is located in the flip chip region 44 to form a lower surface junction of the insulating film 30. The carrier 20 over the surface of the plate. [00019] In a feasible embodiment, the composite carrier structure and the material of the mating substrate 40 are provided as a coefficient of thermal expansion (CTE), or may be a carbon composite substrate or a ceramic substrate ( Ceramic Substrate), the thin carrier 20 below 150 um is not susceptible to thermal stress by the packaging process, and the flip-chip region 44 of the composite carrier structure is implanted into a wafer 50, which is relatively active and inactive. The surface 51 and 52 are provided with a plurality of bumps 53 on the active surface 51. The bumps 53 are joined to the first contact point 21, and a glue material 60 is filled in the flip chip region 44 and the wafer 50. The gap between the wafers 50 can be fixed in the flip-chip region 44 to form the inactive surface 52 in a bare state, and the solder ball B is adhered to the third contact point 23. [00020] A schematic diagram of thermal conduction and thermal convection of the package wafer as shown in FIG. 4, when the wafer 50 is hot pressed through the packaging process, heat is generated in the flip-chip region 44, and the substrate 40 that transmits the low thermal expansion coefficient can withstand The thermal stress caused by the heat conduction can prevent the thermal conduction from being concentrated on the carrier 20 to generate thermal expansion, and the composite structure of the substrate 40, the insulating film 30 and the carrier 20 can withstand thermal stress, and at the same time, the upper surface of the flip-chip region 44 is The open area can accelerate the heat convection. Therefore, when the wafer 50 is applied to the carrier 20, the heat conduction and heat convection can be well transmitted, and the heat generated by the carrier 20 in the packaging process can be quickly eliminated, thereby solving the heat. The stress causes thermal strain problems of the carrier plate 20 being bent up and down. [00021] In one embodiment, the substrate 40 is a Dot-Matrix Board, but not only a single layer, but also a multi-layer stack using different materials; the substrate 40 is internally drilled by a drill bit. The shape of the through holes, the blind holes, the buried holes, the semi-through holes, and the like may be generated, and the electrical conductive body 41 is filled in the shape of each of the holes by electroplating, and the electrical conductive body 41 may be a copper structure. And exhibiting a void free state, the electrical conductive body 41 can be in the shape of a through hole, and different stacked combinations can be performed by using the shapes of the blind hole, the buried hole and the half through hole, so that the electricity The conductive body 41 and the substrate 40 can cooperate with each other to exhibit different structures, but are not limited thereto. [00022] A schematic structural view of another possible embodiment shown in FIG. 5, the through hole shape of the electrical conduction body 41 may also be a symmetric frustum, and the upper and lower ends thereof are wider. [00023] FIG. 6 is a schematic structural view of another possible embodiment. The substrate 40 has a first and second layers 401 and 402. The electrical conductive body 41 has a blind hole-shaped upper conductor 411. The buried conductor-shaped intermediate conductor 412 and the blind-hole shaped lower conductor 413 are formed by a combination of the upper conductor 411 and the middle conductor 412 located in the first layer 401 and the lower conductor 413 in the second layer 402. [00024] FIG. 7 is a schematic structural view of another possible embodiment, wherein the electrical conductor 41 has a first conductor 41a of a blind hole shape and a second conductor 41b of a semi-via shape, which is formed. The conductors 41a are located on the first layer 401 and the second conductors 41b are interposed between the first and second layers 401 and 402, and the first and second layers 401 and 402 have a total thickness greater than 250 um, but are not limited thereto. [00025] By means of the above-mentioned technical means, the present invention enables a flip-chip wafer-level packaged composite carrier structure and a method for manufacturing the same, which have the following effects: 1. The carrier 20 and the insulating film 30 are used. And the formation of a composite carrier structure of the substrate 40 to enhance the mechanical strength, so that the carrier 20 can use a conventional core carrier of less than 150 um thin core build-up method or any layer build (All Layer Build Up) method The resulting coreless carrier can be packaged with a thermal stress in a thinner package. 2. The substrate 40 of the matrix board is a low thermal expansion coefficient material, so as to avoid thermal stress causing the thermal expansion of the carrier 20 to bend, so that the carrier 20 can disperse the thermal stress by the substrate 40, so that the composite The carrier structure enhances heat dissipation. 3. The improved design of the substrate 40 not only retains the bonding function of the laminated package, but also simplifies the packaging process to replace the complex molding through-hole process, and the above-mentioned, the invention realizes thinning, heat dissipation and mechanical strength enhancement. . [00026] In summary, the structure disclosed by the present invention is unprecedented, and can indeed achieve the improvement of efficacy, and has industrial availability, fully conforms to the patent requirements of the invention, and prays for a patent granted by the bureau. Inspire innovation, no sense of morality. [00027] However, the drawings and descriptions disclosed above are only preferred embodiments of the present invention, and those skilled in the art who are familiar with the art, the modifications or equivalent changes made according to the spirit of the present invention should still include the patent application in this case. Within the scope.

【00028】
20‧‧‧ Carrier Board
21‧‧‧First touch point
22‧‧‧second touch point
23‧‧‧ Third touch point
30‧‧‧Insulation film
40‧‧‧Substrate
401‧‧‧ first floor
402‧‧‧ second floor
41‧‧‧Electrical Conductors
411‧‧‧Upper conductor
412‧‧‧Medium conductor
413‧‧‧lower conductor
41a‧‧‧First conductor
41b‧‧‧second conductor
42‧‧‧First electrode pad
43‧‧‧Second electrode pad
44‧‧‧Flip area
50‧‧‧ wafer
51‧‧‧Active surface
52‧‧‧Non-active surface
53‧‧‧Bumps
60‧‧‧sealing materials
B‧‧‧ solder ball

[00014] FIG. 1A is a schematic view of a conventional carrier. Figure 1B is a schematic view of a conventional adhesive wafer. Figure 1C is a schematic view of a conventional package molding. Figure 1D is a schematic view of a conventional laser mold through hole. Figure 2A is a schematic illustration of a conventional carrier plate for a ball. Figure 2B is a schematic view of a conventional adhesive wafer. Figure 2C is a schematic view of a conventional package molding. 2D is a schematic view of a conventional laser mold through hole. 3A is a schematic view of the carrier of the present invention before being bonded to a substrate. Fig. 3B is a schematic view showing the bonding of the carrier of the present invention to a substrate. Figure 3C is a schematic illustration of the package molding of the present invention. Figure 3D is a schematic view showing the structure of a possible embodiment of the present invention. 4 is a schematic view showing heat conduction and heat convection of a package wafer of the present invention. Figure 5 is a schematic view showing the structure of still another possible embodiment of the present invention. Figure 6 is a schematic view showing the structure of still another possible embodiment of the present invention. Figure 7 is a schematic view showing the structure of another possible embodiment of the present invention.

20‧‧‧ Carrier Board

21‧‧‧First touch point

22‧‧‧second touch point

23‧‧‧ Third touch point

30‧‧‧Insulation film

40‧‧‧Substrate

41‧‧‧Electrical Conductors

42‧‧‧First electrode pad

43‧‧‧Second electrode pad

44‧‧‧Flip area

50‧‧‧ wafer

51‧‧‧Active surface

52‧‧‧Non-active surface

53‧‧‧Bumps

60‧‧‧sealing materials

B‧‧‧ solder ball

Claims (10)

A composite carrier structure for a flip chip wafer level package, comprising: a carrier board having a plurality of first and a plurality of second contact points on an upper surface thereof, the second contact point ring being disposed around the first contact point a substrate is provided with a plurality of electrically conductive through-holes, the upper and lower ends of the electrical conductive body are exposed to the upper and lower surfaces thereof, and the upper and lower ends of the electrical conductive body are electrically connected to the plurality of first electrode pads respectively a surface of the upper surface of the plurality of second electrode pads, wherein the surface of the upper surface of the insulating film is diced, and the upper surface of the insulating film is attached to the lower surface thereof. Further, the lower surface of the second electrode pad is opposite And at a position of the second contact point, the second contact point is electrically connected to the lower surface of the second electrode pad, and the first contact point is positioned relative to the flip chip region, and the first contact point is Located in the flip chip region, a lower surface of the insulating film is formed to bond the upper surface of the carrier. The composite carrier structure of a flip-chip wafer level package according to claim 1, wherein the electrical via is in the shape of a via. The composite carrier structure of a flip-chip wafer level package according to claim 2, wherein the through hole has a shape of a symmetrical frustum, and the upper and lower ends thereof are wider. The composite carrier structure of a flip-chip wafer level package according to claim 1, wherein the substrate has a combination of a first layer and a second layer. The composite carrier structure of a flip-chip wafer level package according to claim 4, wherein the electrical conduction body has a blind hole shape upper conductor, a buried hole shape middle conductor, and a blind hole shape under The conductor assembly is formed with the upper and middle conductors in the first layer and the lower conductor in the second layer. The composite carrier structure of a flip-chip wafer level package according to claim 4, wherein the electrical conduction body has a first conductor of a blind hole shape and a second conductor combination of a half via shape. The first conductor is located at the first layer and the second conductor is between the first and second layers. The composite carrier structure of a flip-chip wafer level package according to claim 1, wherein the substrate is composed of one of a dot matrix board, a low thermal expansion coefficient substrate, a carbon fiber substrate, and a ceramic substrate. The composite carrier structure of the flip-chip wafer level package of claim 7, further comprising at least one wafer having opposite active and inactive surfaces, and having a plurality of bumps on the active surface, The bump is bonded to the first contact point, and a glue material is filled in the gap between the flip chip region and the wafer, so that the wafer can be fixed in the flip chip region, and the non-active surface is formed in a bare state. A method for manufacturing a composite wafer carrier structure of a flip-chip wafer level package according to claim 1, comprising the steps of: a) providing a carrier board having a plurality of surfaces on the upper surface thereof And a plurality of second contact points, the second contact point ring is disposed around the first contact point; and b) providing a substrate, the substrate is provided with a plurality of penetrating electrical vias, and the electrical vias are The upper end exposes the upper surface and the lower surface of the substrate, and the upper surface of the plurality of first electrode pads and the upper surface of the plurality of second electrode pads are electrically connected to the upper and lower ends of the electrical conductive body, respectively, and the substrate is dug through a flip-chip region of the opening, and an upper surface of the insulating film is attached to the lower surface of the substrate, and further, a position of the lower surface of the second electrode pad relative to the second contact point causes the second contact Electrically connecting the lower surface of the second electrode pad, and the position of the first contact point relative to the flip chip region, so that the first contact point is located in the flip chip region to form a lower surface of the insulating film The upper surface of the carrier. The method of manufacturing a flip-chip wafer-level packaged carrier structure according to claim 9, wherein the method further comprises the step c) providing at least one wafer having a relative active and non-active surface, and The active surface is provided with a plurality of bumps, the bumps are joined to the first contact point, and a glue material is filled in the gap between the flip chip region and the wafer, so that the wafer can be fixed on the flip chip In the region, the inactive surface is formed to be exposed.