TW201442180A - Semiconductor package and method of manufacture - Google Patents

Abstract

The invention provides a semiconductor package and a method of manufacturing the same, the semiconductor package including a first semiconductor chip, a second semiconductor chip, an encapsulant, a first buildup layer and a second buildup layer. The first semiconductor chip has opposing first active surface and first non-active surface; the second semiconductor chip has opposing second active surface and second non-active surface and wherein the second active surface has a plurality of conductive bumps formed thereon; the second semiconductor chip is mounted onto the first non-active surface of the first semiconductor chip via the second non-active surface thereof; the encapsulant the first and second semiconductor chips and has a conductive via hole penetrating through the two surfaces, and the first and second buildup layers are respectively formed on the two surfaces, thereby reducing the planar size of the package while increasing good yield.

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package having a stacked semiconductor wafer and a method of fabricating the same.

With the evolution of semiconductor technology, semiconductor packages of different package types have been developed, and in order to pursue the thinness and thinness of semiconductor packages, a chip scale package (CSP) technology has been developed, which is characterized in that Such wafer size packages only have dimensions that are equal or slightly larger than the size of the wafer.

1A to 1F are cross-sectional views of a wafer-sized package of U.S. Patent No. 7,202,107 and a method of manufacturing the same.

As shown in FIG. 1A, first, a carrier board 10 is provided.

As shown in FIG. 1B, a heat-sensitive adhesive layer 11 is formed on the carrier 10 .

As shown in FIG. 1C, a plurality of semiconductor wafers 12 having an active surface 12a are bonded to the thermally sensitive adhesive layer 11, the active surface 12a having a plurality of electrode pads 121, and the semiconductor wafer 12 is attached with its active surface 12a. Attached to the heat-sensitive adhesive layer 11.

As shown in FIG. 1D, an encapsulant 13 is formed on the thermally sensitive adhesive layer 11, The encapsulant 13 is completely coated with the semiconductor wafer 12.

As shown in FIG. 1E, a heating step is then performed to completely separate the semiconductor wafer 12 and the encapsulant 13 from the thermally sensitive adhesive layer 11.

As shown in FIG. 1F, finally, the wiring layer 14 is formed on the active surface 12a of the semiconductor wafer 12 and the surface of the encapsulant 13 on the same side. A subsequent singulation operation (not shown) may be performed to complete a package without a package substrate.

However, if the aforementioned conventional package is to improve product multiplexability or function, it is necessary to include a plurality of semiconductor wafers in one package. In the case where a plurality of semiconductor wafers are disposed adjacent to each other, the planar size of the package is greatly increased; in addition, because of processes such as thermal processing and encapsulation of the encapsulant (for example, heating the encapsulant into a liquid and filling it), the semiconductor wafer will have Displacement occurs, and regardless of whether the dimensions of the plurality of semiconductor wafers are the same, it is difficult to make the displacement of each semiconductor wafer uniform, thereby causing problems in the alignment of the subsequent line build-up process.

Therefore, how to solve the problem that the planar size of the package is too large and the displacement of the plurality of semiconductor wafers in the same package is not the same has become an urgent problem to be solved in the industry.

In view of the above-mentioned deficiencies of the prior art, the present invention provides a semiconductor package comprising: a first semiconductor wafer having a first active surface and a first non-active surface, and the first active surface is formed with a plurality of a first electrode pad; the second semiconductor wafer is coupled to the first semiconductor wafer and has a second active surface and a second non-active surface, wherein the second active surface is formed with a plurality of second electrodes a pad, each of the second electrode pads is provided with a conductive bump, and the second semiconductor chip is attached to the first non-active surface of the first semiconductor wafer by the second non-active surface; The encapsulant encapsulates the first semiconductor wafer and the second semiconductor wafer, and has a first surface and a second surface opposite to each other, and a plurality of through holes penetrating the first surface and the second surface, the first active surface and the first surface The conductive bumps are respectively exposed on the first surface and the second surface of the encapsulant; the conductive vias are formed in the through holes; the first build-up structure is formed on the first surface to be electrically Connecting the first electrode pad and the conductive via; and forming a second build-up structure on the second surface to electrically connect the conductive bump and the conductive via.

In the foregoing semiconductor package, the second non-active surface of the second semiconductor wafer is adhered to the first non-active surface of the first semiconductor wafer by an adhesive layer.

According to the above semiconductor package, a plurality of conductive pillars are formed on each of the conductive bumps to electrically connect the second build-up structure, and the plurality of conductive elements are electrically connected. The first build-up structure.

The present invention provides a method of fabricating a semiconductor package, comprising: placing a first semiconductor wafer having a first active surface and a first non-active surface on a first carrier plate with a first active surface thereof, and the first a plurality of first electrode pads are formed on a working surface; a second semiconductor wafer having a second active surface and a second non-active surface is disposed on the first non-active surface of the first semiconductor wafer, and the second a plurality of second electrode pads are formed on the active surface, each of the second electrode pads is provided with a conductive bump, and the second semiconductor wafer is connected to the first non-active surface by the second non-active surface; Forming a package body covering the first semiconductor wafer and the second semiconductor wafer and having opposite first and second surfaces, the first surface facing the first carrier plate; forming in the encapsulant a plurality of conductive vias penetrating the first surface and the second surface; forming a second build-up structure electrically connecting the conductive bumps and the conductive vias on the second surface; removing the first carrier; and The first table Forming a first build-up structure electrically connecting the first electrode pad and the conductive via.

In the above method for manufacturing a semiconductor package, the first carrier is further provided with a peeling layer, wherein the first semiconductor wafer is placed on the first carrier by the peeling layer, and the first carrier is removed. When the plate is removed, the peeling layer is removed, and the second non-active surface is placed on the first non-active surface by an adhesive layer.

In the method of fabricating the semiconductor package of the present invention, before forming the second build-up structure, a conductive pillar is formed on each of the conductive bumps to electrically connect the second build-up structure, and is included in the method. The first build-up structure electrically connects the plurality of conductive elements.

According to the method for manufacturing a semiconductor package as described above, after the second build-up structure is formed, a second carrier is disposed on the second build-up structure, and after the first build-up structure is formed, the second carrier is removed. The second carrier board, and the first and second carrier boards are wafers or substrates.

As can be seen from the above, since the present invention stacks two semiconductor wafers in a package instead of being disposed adjacently, the planar size of the package can be reduced; in addition, the displacement of the stacked two semiconductor wafers of the present invention in the process will be Consistent, it is beneficial to the alignment process of the subsequent process, thereby improving the overall yield.

10‧‧‧Bearing board

11‧‧‧Thermal adhesive layer

12‧‧‧Semiconductor wafer

12a‧‧‧Action surface

121‧‧‧electrode pads

13‧‧‧Package colloid

14‧‧‧Line layer

20‧‧‧First carrier board

21‧‧‧ peeling layer

22‧‧‧First semiconductor wafer

22a‧‧‧First action surface

22b‧‧‧First non-active surface

221‧‧‧First electrode pad

23‧‧‧Adhesive layer

24‧‧‧Second semiconductor wafer

24a‧‧‧second action surface

24b‧‧‧Second non-active surface

241‧‧‧Second electrode pad

25‧‧‧Electrical bumps

26‧‧‧Package colloid

26a‧‧‧ first surface

26b‧‧‧ second surface

261‧‧‧Opening

262‧‧‧through hole

271‧‧‧conductive column

272‧‧‧Electrical through hole

28a‧‧‧First buildup structure

28b‧‧‧Second layered structure

29‧‧‧Second carrier board

30‧‧‧Conductive components

1A to 1F are cross-sectional views showing a wafer-sized package of US Pat. No. 7,202,107 and a method of manufacturing the same, and a cross-sectional view showing a semiconductor package of the present invention and a method of manufacturing the same according to FIGS. 2A to 2H.

The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily appreciate other aspects of the present invention from the disclosure herein. Advantages and effects.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "side", "in" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments to a relationship are considered to be within the scope of the invention, without departing from the scope of the invention.

2A to 2H are cross-sectional views showing a semiconductor package of the present invention and a method of manufacturing the same.

As shown in FIG. 2A, a release layer 21 is formed on the first carrier 20, and the first semiconductor wafer 22 having the first active surface 22a and the first non-active surface 22b is first. The active surface 22a is disposed on the peeling layer 21, wherein the first active surface 22a is formed with a plurality of first electrode pads 221, and the first carrier 20 is a wafer or a substrate.

As shown in FIG. 2B, the first non-active surface 22b of the first semiconductor wafer 22 is attached to the second active surface 24a by an adhesive layer 23 (for example, a die attach material). a second semiconductor wafer 24 of the second non-active surface 24b, and a plurality of second electrode pads 241 are formed on the second active surface 24a. Each of the second electrode pads 241 is provided with a conductive bump 25, and the second semiconductor wafer 24 is provided. And the second non-active surface 24b is attached to the adhesive layer 23.

As shown in FIG. 2C, an encapsulant 26 having an opposite first surface 26a and a second surface 26b covering the first semiconductor wafer 22 and the second semiconductor wafer 24 is formed on the first carrier 20 A surface 26a faces the first carrier plate 20.

As shown in FIG. 2D, an opening 261 exposing the conductive bump 25 and a plurality of through holes 262 extending through the first surface 26a and the second surface 26b are formed in the encapsulant 26.

As shown in FIG. 2E, a conductive pillar 271 and a conductive via 272 are formed in the opening 261 and the via 262, respectively.

As shown in FIG. 2F, a second build-up structure 28b electrically connecting the conductive bumps 25 and the conductive vias 272 is formed on the second surface 26b of the encapsulant 26, and is formed on the second build-up structure 28b. A second carrier plate 29 is provided, which is a wafer or a substrate.

The first carrier 20 and the release layer 21 are removed as shown in FIG. 2G.

As shown in FIG. 2H, a first build-up structure 28a electrically connecting the first electrode pad 221 and the conductive via 272 is formed on the first surface 26a of the encapsulant 26, and the first build-up structure 28a is formed on the first build-up structure 28a. The plurality of conductive elements 30 are electrically connected and the second carrier plate 29 is removed.

The present invention further provides a semiconductor package including a first semiconductor wafer 22 having a first active surface 22a and a first non-active surface 22b, and a plurality of first electrode pads formed on the first active surface 22a. The second semiconductor wafer 24 is electrically connected to the first semiconductor wafer 22 and has a second active surface 24a and a second non-active surface 24b. The second active surface 24a is formed with a plurality of a second electrode pad 241 is disposed on each of the second electrode pads 241, and the second semiconductor wafer 24 is attached to the first semiconductor crystal by the second non-active surface 24b. The first non-active surface 22b of the sheet 22; the encapsulant 26 covers the first semiconductor wafer 22 and the second semiconductor wafer 24, and has a first surface 26a and a second surface 26b opposite thereto, and a plurality of The first surface 22a and the conductive bump 25 are respectively exposed on the first surface 26a and the second surface 26b of the encapsulant 26, and the conductive via 272 is formed on the surface 26a and the second surface 26b. Formed in the through hole 262; a first build-up structure 28a is formed on the first surface 26a to electrically connect the first electrode pad 221 and the conductive via 272; and the second build-up structure 28b The second surface 26b is formed to electrically connect the conductive bump 25 and the conductive via 272.

In the semiconductor package of the present invention, the second non-active surface 24b of the second semiconductor wafer 24 is adhered to the first non-active surface 22b of the first semiconductor wafer 22 by the adhesive layer 23.

The semiconductor package according to the foregoing includes a plurality of conductive pillars 271 formed on each of the conductive bumps 25 to electrically connect the second build-up structure 28b, and further comprising a plurality of conductive elements 30. The first build-up structure 28a is electrically connected.

In summary, compared with the prior art, since the present invention stacks two semiconductor wafers in a package instead of being disposed adjacently, the planar size of the package can be reduced; moreover, the stacked two of the present invention The displacement of the semiconductor wafer in the process will be consistent, which is beneficial to the alignment process of the subsequent process, thereby improving the overall yield.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

22‧‧‧First semiconductor wafer

23‧‧‧Adhesive layer

24‧‧‧Second semiconductor wafer

25‧‧‧Electrical bumps

26‧‧‧Package colloid

26a‧‧‧ first surface

26b‧‧‧ second surface

271‧‧‧conductive column

272‧‧‧Electrical through hole

28a‧‧‧First buildup structure

28b‧‧‧Second layered structure

30‧‧‧Conductive components

Claims (12)

A semiconductor package includes: a first semiconductor wafer having a first active surface and a first non-active surface; and the first active surface is formed with a plurality of first electrode pads; and the second semiconductor wafer is coupled And disposed on the first semiconductor wafer, and having a second active surface and a second non-active surface, wherein the second active surface is formed with a plurality of second electrode pads, and each of the second electrode pads is electrically conductive a bump, and the second semiconductor wafer is attached to the first non-active surface of the first semiconductor wafer by the second non-active surface; the encapsulant encapsulates the first semiconductor wafer and the second semiconductor wafer, and The first surface and the second surface and the plurality of through holes extending through the first surface and the second surface, the first active surface and the conductive bump are respectively exposed on the first surface and the second surface of the encapsulant a conductive via is formed in the via hole; a first build-up structure is formed on the first surface to electrically connect the first electrode pad and the conductive via; and a second build-up structure, Formed in the first Surface, electrically connected to the conductive bumps and conductive vias. The semiconductor package of claim 1, wherein the second non-active surface of the second semiconductor wafer is adhered to the first inactive surface of the first semiconductor wafer by an adhesive layer. The semiconductor package of claim 1, further comprising a plurality of conductive pillars respectively formed on each of the conductive bumps to electrically connect the second buildup structure. The semiconductor package of claim 1, further comprising a plurality of conductive elements electrically connected to the first build-up structure. A method of manufacturing a semiconductor package includes: bonding a first semiconductor wafer having a first active surface and a first non-active surface to a first carrier on a first carrier surface thereof, and the first active surface a plurality of first electrode pads are formed; a second semiconductor wafer having a second active surface and a second non-active surface is disposed on the first non-active surface of the first semiconductor wafer, and the second active surface is formed a plurality of second electrode pads, each of the second electrode pads is provided with a conductive bump, and the second semiconductor wafer is attached to the first non-active surface by the second non-active surface; formed on the first carrier plate Encapsulating the first semiconductor wafer and the second semiconductor wafer, and having an encapsulant opposite to the first surface and the second surface, the first surface facing the first carrier; forming a plurality of through the encapsulation a conductive via having a surface and a second surface; forming a second build-up structure electrically connecting the conductive bump and the conductive via on the second surface; removing the first carrier; and the first surface Electrically formed The first electrode pad connected to the conductive vias of the first built-up structure. The method of manufacturing the semiconductor package of claim 5, wherein the first carrier is further provided with a peeling layer, wherein the first semiconductor wafer is attached to the first carrier by the peeling layer. And when the first carrier board is removed, and moved together In addition to the release layer. The method of fabricating a semiconductor package according to claim 5, wherein the second non-active surface is attached to the first non-active surface by an adhesive layer. The method of fabricating a semiconductor package according to claim 5, before forming the second build-up structure, forming a conductive pillar on each of the conductive bumps to electrically connect the second build-up structure. The method of fabricating a semiconductor package according to claim 5, further comprising electrically connecting the plurality of conductive elements to the first build-up structure. The method of manufacturing the semiconductor package of claim 5, after forming the second build-up structure, further comprising disposing a second carrier on the second build-up structure, and forming the first build-up layer After the structure, the second carrier plate is removed. The method of fabricating a semiconductor package according to claim 5, wherein the first carrier is a wafer or a substrate. The method of fabricating a semiconductor package according to claim 10, wherein the second carrier is a wafer or a substrate.