TW201440253A - Light-emitting diode structure and method for manufacturing the same - Google Patents

Abstract

A light-emitting diode structure and a method for manufacturing the same are described, which includes an insulation substrate, a plurality of light-emitting diode chips, a plurality of interconnection layers, a first conductivity type electrode pad, a second conductivity type electrode pad, an insulating reflective layer, a first conductivity type bonding pad and a second conductivity type bonding pad. Each light-emitting diode chip includes a mesa structure and a first conductivity type semiconductor layer exposed portion adjacent to each other, and a first isolation trench disposed within the mesa structure. The interconnection layers respectively connect adjacent two of the light-emitting diode chips. The first conductivity type electrode pad and the second conductivity type electrode pad electrically connect to two light-emitting diode chips respectively. The insulating reflective layer covers the interconnection layers, the mesa structures, the first conductivity type electrode pad and the second conductivity type electrode pad. The first conductivity type bonding pad and the second conductivity type bonding pad are disposed on the insulating reflective layer, and electrically connect to the first conductivity type electrode pad and the second conductivity type electrode pad respectively.

Description

Light-emitting diode structure and manufacturing method thereof

The present invention relates to a light emitting structure, and more particularly to a light emitting diode (LED) structure and a method of fabricating the same.

At present, in order to improve the luminous efficiency of the entire light-emitting diode, a plurality of light-emitting diode chips are connected in series by a wire bonding method. Since the wire bonding method has a problem of high cost and low production yield, it has been further developed to use a built-in metal to perform series connection of a plurality of light-emitting diode chips.

Please refer to FIG. 1 , which is a partial cross-sectional view showing a conventional tandem LED structure. The conventional series LED structure 100 utilizes built-in metal to connect a plurality of light emitting diode chips in series. The series light emitting diode structure 100 includes a plurality of light emitting diode chips in series, such as light emitting diode chips 106a and 106b. The light emitting diode chips 106a and 106b are disposed on the surface 104 of the insulating substrate 102. The adjacent two LED chips 106a and 106b are separated by an isolation trench 122. Each of the LED chips 106a and 106b includes an undoped semiconductor layer 108, a first electrical semiconductor layer 110, an active layer 112, and a second electrical semiconductor layer 114 which are sequentially stacked on the surface of the insulating substrate 102. Transparent conductive layer 116.

Light-emitting diode chips 106a and 106b each have a platform structure 128 And an exposed portion 130 of the first electrical semiconductor layer 110. The first electrical electrode pad 118a and the second electrical electrode pad 120a of the LED wafer 106a are respectively disposed on the exposed portion 130 of the first electrical semiconductor layer 110 and the platform structure 128. Similarly, the first electrical electrode pad 118b and the second electrical electrode pad 120b of the LED chip 106b are respectively disposed on the exposed portion 130 of the first electrical semiconductor layer 110 and the platform structure 128.

In the light emitting diode structure 100, the insulating layer 124 covers the first electrical semiconductor layer 110 and the light emitting diode of the light emitting diode chip 106a extending outside the opening of the isolation trench 122 in the isolation trench 122. The transparent conductive layer 116 of the wafer 106b electrically isolates the adjacent two LED chips 106a and 106b. In order to connect adjacent two LED chips 106a and 106b in series, the LED structure 100 has an interconnect layer 126. The interconnect layer 126 extends from the first electrical electrode pad 118a of the LED substrate 106a via the insulating layer 124 located above the exposed portion 130 of the first electrical semiconductor layer 110 and the isolation trench 122 to On the insulating layer 124 on the adjacent LED wafer 106b and the second electrode pad 120b, the LED chips 106a and 106b are electrically connected in series.

Since the tandem LED structure 100 is driven with a higher voltage, the driving circuit has higher efficiency. Secondly, compared to the plurality of independent light-emitting diode chips, the electrode pad structure of the tandem light-emitting diode structure 100 is small, and thus the light-emitting diode structure 100 has a large light-emitting area. Furthermore, since the current of the tandem LED structure 100 can be dispersed and flowed to each of the small light-emitting diode wafers, the current distribution is uniformer than that of a single large-area light-emitting diode wafer, so that the serial type is emitted. The light-emitting efficiency of the photodiode structure 100 is better.

However, since the bottom of the isolation trench 122 of the conventional tandem LED structure 100 needs to extend down to the surface 104 of the insulating substrate 102. Therefore, the aspect ratio of the isolation trench 122 is too high, so that the material of the insulating layer 124 is not easily filled, and the deposition is likely to be discontinuous, so that the insulating layer 124 is prone to generation of broken holes. Therefore, when the conductive interconnect layer 126 is subsequently deposited, the conductive material of the interconnect layer 126 may be filled into the holes of the insulating layer 124 to cause a short circuit.

In the tandem light-emitting diode structure 100, as long as one of the light-emitting diode chips 106a or 106b has a short circuit phenomenon, the entire series-connected light-emitting diode structure 100 cannot operate. Therefore, the production yield of the tandem light-emitting diode structure 100 is not good.

In addition, if the aspect ratio of the isolation trench 122 is too high, the deposition of the interconnect layer 126 is liable to be discontinuous, which may cause the interconnect layer 126 to be broken. In the tandem light-emitting diode structure 100, as long as one of the light-emitting diode chips 106a or 106b is broken, the entire series-connected light-emitting diode structure 100 is also inoperable. Therefore, the production yield of such a tandem LED structure 100 is not good.

Therefore, an aspect of the present invention is to provide a light-emitting diode structure which is formed by connecting a plurality of light-emitting diode chips in series, and has the advantages of dense arrangement and high light efficiency.

Another aspect of the present invention is to provide a light emitting diode structure and a method of fabricating the same, comprising an insulating reflective layer covering each of the light emitting diodes The inner wiring of the bulk wafer, the platform structure and the exposed portion of the first electrical semiconductor layer can be packaged by flip chip, thereby achieving high heat dissipation, no wire bonding and low thermal resistance.

Another aspect of the present invention provides a light emitting diode structure and a method of fabricating the same, wherein the interconnect layer is directly exposed from a first electrical semiconductor layer of one of the adjacent light emitting diode chips. It extends to the platform structure via the side of the platform structure of the other. Therefore, the aspect ratio of the interconnect layer can be greatly reduced, and the step coverage ability of the interconnect layer deposition can be effectively improved, thereby avoiding disconnection when the interconnect layer is deposited.

A further aspect of the present invention provides a light emitting diode structure and a manufacturing method thereof, wherein the platform structure of the light emitting diode chip can have a trapezoidal inclined side surface, thereby further improving the step coverage capability of the interconnect layer. More effective in solving the problem of disconnection of the interconnect layer.

A further aspect of the present invention provides a light emitting diode structure and a method of fabricating the same, wherein the light emitting region of the light emitting diode chip is isolated from the first electrical semiconductor layer of the adjacent light emitting diode chip. The trenches are separated, and the isolation trench is filled with only an insulating layer and no conductive material. In addition, an additional current blocking layer may be additionally disposed on the opening of the isolation trench to be electrically isolated. Therefore, even if the deposition of the insulating layer in the isolation trench is discontinuous, there is no problem of short circuit in the light-emitting region in the case where there is no conductive material in the isolation trench.

A further aspect of the present invention provides a light emitting diode structure and a method of fabricating the same, wherein the interconnect layer can directly pass through a contact hole in a dielectric layer above one of the adjacent light emitting diode chips. Extending over the electrical layer to The contact hole in the dielectric layer above the other. Therefore, the conductive material may not need to be filled in the isolation trench between the adjacent two light-emitting diode wafers, thereby solving the problem of disconnection of the interconnect layer.

A further aspect of the present invention provides a light emitting diode structure and a manufacturing method thereof, which can effectively solve the problem of short circuit and disconnection, thereby greatly improving the production yield of the series light emitting diode structure, thereby reducing the yield. production cost.

A further aspect of the present invention provides a light emitting diode structure and a manufacturing method thereof, which can effectively solve the problem of short circuit and disconnection, and therefore can detect the forward and reverse current without relying on the reverse leakage current detecting means. , the short-circuit defect in the structure of the light-emitting diode can be successfully confirmed.

According to the above object of the present invention, a light emitting diode structure is proposed. The light emitting diode structure comprises an insulating substrate, a plurality of light emitting diode chips, a plurality of interconnecting layers, a first electrical electrode pad, a second electrical electrode pad, an insulating reflective layer, and a first An electrical bond pad and a second electrical bond pad. Each of the light-emitting diode chips includes an epitaxial layer, and the epitaxial layer includes a first electrical semiconductor layer, an active layer, and a second electrical semiconductor layer stacked on one surface of the insulating substrate. Each of the light emitting diode chips includes a substrate structure adjacent to the first electrical semiconductor layer and a first isolation trench, and the first isolation trench is disposed in the platform structure. The plurality of interconnecting layers are respectively connected to adjacent ones of the light emitting diode chips. The first electrical electrode pad and the second electrical electrode pad are respectively disposed on the first one and the second one of the light emitting diode chips, and respectively exposed to the first electrical semiconductor layer of the first one and the second Second electrical semiconductor Layer electrical connection. The insulating reflective layer covers the inner wiring layer, the platform structure, the first electrical electrode pad and the second electrical electrode pad. The insulating reflective layer has at least one first through hole and at least one second through hole respectively exposing a portion of the first electrical electrode pad and the second electrical electrode pad. The first electrical bonding pad is located on a portion of the insulating reflective layer and electrically connected to the first electrical electrode pad through the at least one first through hole. The second electrical bonding pad is located on the insulating reflective layer of the other portion and is separated from the first electrical bonding pad and electrically connected to the second electrical electrode pad through the at least one second through hole.

According to an embodiment of the invention, each of the LED chips further includes an insulating layer filled in the first isolation trench to seal an opening of the first isolation trench.

According to another embodiment of the present invention, each of the light emitting diode chips further includes a current blocking layer interposed between the interconnect layer and the insulating layer on the platform structure.

According to still another embodiment of the present invention, each of the light emitting diode chips further includes a transparent conductive layer extending on the second electrical semiconductor layer of the platform structure, and the interconnect layer and the current resistance on the platform structure. Between the barriers.

According to still another embodiment of the present invention, each of the light emitting diode chips further includes a dielectric layer disposed on the epitaxial layer, and each of the light emitting diode chips is provided with a first electrical contact hole and a second Electrical contact holes extend through the dielectric layer. In addition, the first isolation trench is interposed between the second electrical contact hole of the LED chip and the first electrical contact hole of the adjacent LED chip. Furthermore, each of the interconnect layers extends from the second electrical contact hole of each of the light-emitting diode chips to the adjacent light-emitting diode crystal via the first isolation trench. The first electrical contact hole of the sheet. Moreover, the insulating reflective layer covers the dielectric layer more.

According to still another embodiment of the present invention, each of the light emitting diode chips further includes a transparent conductive layer interposed between the dielectric layer and the epitaxial layer. Next, the exposed portion of the first electrical semiconductor layer is exposed at the bottom of one of the first electrical contact holes. Moreover, the transparent conductive layer is exposed at the bottom of one of the second electrical contact holes.

According to still another embodiment of the present invention, each of the light emitting diode chips further includes at least one current blocking layer between the bottom of the second electrical contact hole and the epitaxial layer.

According to still another embodiment of the present invention, in each of the light emitting diode wafers, the epitaxial layer has a recess, and one of the bottoms of the recess exposes the exposed portion of the first electrical semiconductor layer, and the first electrical contact hole A portion of the bottom of the recess is exposed and a dielectric layer overlies one of the sidewalls of the recess.

According to still another embodiment of the present invention, each of the light emitting diode wafers further includes at least one insulating liner covering one of the sidewalls of the first electrical contact hole.

According to the above object of the present invention, there is further provided a method of fabricating a light emitting diode structure comprising the following steps. An insulating substrate is provided. An epitaxial structure is formed. The epitaxial structure includes a first electrical semiconductor layer, an active layer and a second electrical semiconductor layer stacked on one surface of the insulating substrate in sequence. A plurality of first isolation trenches and a plurality of second isolation trenches are formed in the epitaxial structure to define a plurality of epitaxial layers of the plurality of light emitting diode chips. The first isolation trenches are respectively adjacent to the second isolation trenches. Removing a portion of the second electrical semiconductor layer and a portion of the active layer to define One of the platform structures of each of the light emitting diode chips and a first electrical semiconductor layer exposed portion. Each of the light emitting diode chips includes a first isolation trench, and the first isolation trench is disposed in the platform structure. Forming a plurality of interconnect layers, a first electrical electrode pad and a second electrical electrode pad. Wherein, the interconnect layers are respectively connected to adjacent ones of the LEDs. The first electrical electrode pad and the second electrical electrode pad are respectively disposed on the first one and the second one of the light emitting diode chips, and the first electrical electrode pad and the second electrical electrode pad are respectively The first electrical semiconductor layer exposed portion of the first one and the second electrical semiconductor layer of the second one are electrically connected. An insulating reflective layer is formed to cover the inner wiring layer, the platform structure, the first electrical electrode pad and the second electrical electrode pad. The insulating reflective layer has at least one first through hole and at least one second through hole respectively exposing a portion of the first electrical electrode pad and a portion of the second electrical electrode pad. A first electrical bond pad is formed on a portion of the insulating reflective layer. The first electrical bonding pad is electrically connected to the first electrical electrode pad through the at least one first through hole. A second electrical bond pad is formed on the insulating reflective layer of the other portion. Wherein, the second electrical bonding pad is separated from the first electrical bonding pad. Moreover, the second electrical bonding pad is electrically connected to the second electrical electrode pad through the at least one second through hole.

According to an embodiment of the present invention, after the forming the first isolation trench and the second isolation trench in the epitaxial structure, the manufacturing method of the LED structure further comprises forming a plurality of dielectric layers respectively covering the epitaxial layer. . Each of the LEDs has a first electrical contact hole and a second electrical contact hole extending through the dielectric layer, and the first isolation trench is interposed between the second electrical contact hole of the LED chip. The first electricity of the adjacent LED chip Sexual contact between the holes.

According to another embodiment of the present invention, before the forming of the dielectric layer, the method for fabricating the LED structure further includes: forming a plurality of transparent conductive layers between the dielectric layer and the epitaxial layer; and forming a plurality The current blocking layers are respectively located between the epitaxial layer and the transparent conductive layer. Wherein, in each of the light emitting diode wafers, a bottom of one of the first electrical contact holes exposes the first electrical semiconductor layer, and one of the bottoms of the second electrical contact holes exposes the transparent conductive layer. The positions of the current blocking layers are correspondingly disposed under the bottom of the second electrical contact hole.

According to the above object of the present invention, a light emitting diode structure is further proposed. The light emitting diode structure comprises an insulating substrate, a plurality of light emitting diode chips, a plurality of interconnecting layers, a first electrical electrode pad, a second electrical electrode pad, an insulating layer, and a first electric a bonding pad and a second electrical bonding pad. Each of the light emitting diode chips includes an epitaxial layer. The epitaxial layer includes a first electrical semiconductor layer, an active layer, and a second electrical semiconductor layer stacked on one surface of the insulating substrate, and each of the light emitting diode chips includes a platform structure adjacent to each other. The first isolation trench is disposed in the platform structure with a first electrical semiconductor layer exposed portion and a first isolation trench. The plurality of interconnecting layers are respectively connected to adjacent ones of the light emitting diode chips. The first electrical electrode pad and the second electrical electrode pad are respectively disposed on the first and second of the LED body, and are respectively exposed to the first electrical semiconductor layer of the first one and the second The second electrical semiconductor layer is electrically connected. The insulating layer covers the inner interconnect layer, the platform structure, the first electrical electrode pad and the second electrical electrode pad. Wherein the insulating layer has at least one The first through-hole and the at least one second through-hole respectively expose a portion of the first electrical electrode pad and the second electrical electrode pad. The first electrical bonding pad is located on a portion of the insulating layer and electrically connected to the first electrical electrode pad through the at least one first through hole. The second electrical bonding pad is located on the insulating layer of the other portion and is separated from the first electrical bonding pad and electrically connected to the second electrical electrode pad through the at least one second through hole.

According to an embodiment of the invention, the insulating layer is a Bragg mirror (DBR).

According to another embodiment of the present invention, the light emitting diode structure further includes an insulating reflective layer. Each of the LED chips further includes a dielectric layer disposed on the epitaxial layer. Each of the LEDs is provided with a first electrical contact hole and a second electrical contact hole through the dielectric layer. The first isolation trench is interposed between the second electrical contact hole of the LED chip and the first electrical contact hole of the adjacent LED chip. The insulating reflective layer covers one side wall of one of the first electrical contact holes of each of the light emitting diode chips, one side wall of the second electrical contact hole, and one upper surface of the dielectric layer. Each of the interconnect layers extends from the second electrical contact hole of each of the light emitting diode chips to the first electrical contact hole of the adjacent light emitting diode chip via the first isolation trench.

According to still another embodiment of the present invention, the light emitting diode structure further includes an insulating reflective layer. Each of the LED chips further includes a dielectric layer disposed on the epitaxial layer. Each of the LEDs is provided with a first electrical contact hole and a second electrical contact hole through the dielectric layer. The first isolation trench is interposed between the second electrical contact hole of the LED chip and the first electrical contact hole of the adjacent LED chip. The epitaxial layer has a groove, the groove One of the bottom portions exposes the exposed portion of the first electrical semiconductor layer. The first electrical contact hole exposes a portion of the bottom of the recess. An insulating reflective layer covers one of the sidewalls of each of the recesses and one of the upper surfaces of each of the epitaxial layers. Each of the interconnect layers extends from the second electrical contact hole of each of the light emitting diode chips to the first electrical contact hole of the adjacent light emitting diode chip via the first isolation trench.

According to still another embodiment of the present invention, the light emitting diode structure further includes an insulating reflective layer. Each of the LED chips further includes a dielectric layer disposed on the epitaxial layer. Each of the LEDs is provided with a first electrical contact hole and a second electrical contact hole through the dielectric layer. The first isolation trench is interposed between the second electrical contact hole of the LED chip and the first electrical contact hole of the adjacent LED chip. The epitaxial layer has a recess, a bottom of the recess exposing the exposed portion of the first electrical semiconductor layer, and the first electrical contact hole exposes a portion of the bottom of the recess. The dielectric layer covers one of the sidewalls of the recess. An insulating reflective layer covers one of the upper surfaces of each of the epitaxial layers. Each of the interconnect layers extends from the second electrical contact hole of each of the light emitting diode chips to the first electrical contact hole of the adjacent light emitting diode chip via the first isolation trench.

According to still another embodiment of the present invention, the light emitting diode structure further includes an insulating reflective layer. Each of the LED chips further includes a dielectric layer disposed on the epitaxial layer. Each of the LEDs is provided with a first electrical contact hole and a second electrical contact hole through the dielectric layer. The first isolation trench is interposed between the second electrical contact hole of the LED chip and the first electrical contact hole of the adjacent LED chip. The epitaxial layer has a groove, the groove One of the bottom portions exposes the exposed portion of the first electrical semiconductor layer, and the first electrical contact hole exposes a portion of the bottom of the recess. The dielectric layer covers one of the sidewalls of the recess. An insulating reflective layer covers one of the upper surfaces of each of the dielectric layers. Each of the interconnect layers extends from the second electrical contact hole of each of the light emitting diode chips to the first electrical contact hole of the adjacent light emitting diode chip via the first isolation trench.

100‧‧‧Lighting diode structure

102‧‧‧Insert substrate

104‧‧‧ Surface

106a‧‧‧Light Diode Wafer

106b‧‧‧Light Diode Wafer

108‧‧‧Undoped semiconductor layer

110‧‧‧First electrical semiconductor layer

112‧‧‧ active layer

114‧‧‧Second electrical semiconductor layer

116‧‧‧Transparent conductive layer

118a‧‧‧First electrical electrode pad

118b‧‧‧First electrical electrode pad

120a‧‧‧second electrical electrode pad

120b‧‧‧second electrical electrode pad

122‧‧‧Isolation Ditch

124‧‧‧Insulation

126‧‧‧Internet layer

128‧‧‧ platform structure

130‧‧‧Exposed part

200‧‧‧Lighting diode structure

200a‧‧‧Lighting diode structure

200b‧‧‧Lighting diode structure

200c‧‧‧Lighting diode structure

200d‧‧‧Lighting diode structure

200e‧‧‧Lighting diode structure

200f‧‧‧Lighting diode structure

202‧‧‧Insert substrate

204‧‧‧ surface

206‧‧‧Undoped semiconductor layer

208‧‧‧First electrical semiconductor layer

210‧‧‧Active layer

212‧‧‧Second electrical semiconductor layer

214‧‧‧ epitaxial layer

214a‧‧‧ epitaxial structure

216‧‧‧Isolation Ditch

218‧‧‧Insulation

220‧‧‧Insulated reflective layer

222‧‧‧ Current Barrier

224‧‧‧Transparent conductive layer

226‧‧‧Interconnection layer

228‧‧‧Light Emitter Wafer

228a‧‧‧Light Emitter Wafer

228b‧‧‧Light Diode Wafer

228c‧‧‧Light Emitter Wafer

228d‧‧‧LED Diode Wafer

228e‧‧‧Light Emitting Diode Wafer

228f‧‧‧Light Emitting Diode Wafer

228g‧‧‧Light Diode Wafer

228h‧‧‧Light Diode Wafer

230‧‧‧ platform structure

232‧‧‧Second electrical bonding pads

234‧‧‧Exposed part

236‧‧‧Second electrical electrode pad

238‧‧‧First electrical electrode pad

240‧‧‧Isolation Ditch

242‧‧‧Insulation

244‧‧‧ Current Barrier

246‧‧‧ side

248‧‧‧ openings

250‧‧‧ openings

252‧‧‧First electrical bonding pad

254‧‧‧through holes

256‧‧‧through holes

258‧‧‧ test pad

260‧‧‧through holes

262‧‧‧ dielectric layer

264‧‧‧First electrical contact hole

266‧‧‧Second electrical contact hole

268‧‧‧Insulation lining

270‧‧‧ bottom

272‧‧‧Contact plug

274‧‧‧Contact plug

276‧‧‧ Groove

278‧‧‧ upper surface

280‧‧‧ bottom

282‧‧‧Insulation lining

284‧‧‧ bottom

286‧‧‧Insulation lining

288‧‧‧ upper surface

290‧‧‧Insulation

292‧‧‧etch stop layer

294‧‧‧hard mask layer

296‧‧‧ photoresist layer

298‧‧‧ photoresist layer

300‧‧‧ photoresist layer

‧‧‧‧ angle

Θ‧‧‧ angle

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

Figure 1 is a partial cross-sectional view showing a conventional tandem LED structure.

2 is a top plan view showing a structure of a light emitting diode according to an embodiment of the present invention.

Fig. 3 is a cross-sectional view showing the structure of the light-emitting diode obtained along the line AA' of Fig. 2;

Fig. 4 is a cross-sectional view showing the structure of the light-emitting diode obtained along the line BB' of Fig. 2;

Figure 5 is a cross-sectional view showing a structure of a light emitting diode according to another embodiment of the present invention.

Figure 6 is a cross-sectional view showing a structure of a light emitting diode according to still another embodiment of the present invention.

Figure 7 is a cross-sectional view showing a structure of a light emitting diode according to still another embodiment of the present invention.

Figure 8 is a cross-sectional view showing a structure of a light-emitting diode according to still another embodiment of the present invention.

Figure 9 is a cross-sectional view showing a structure of a light-emitting diode according to still another embodiment of the present invention.

Figure 10 is a cross-sectional view showing a structure of a light emitting diode according to still another embodiment of the present invention.

11A through 11G are cross-sectional views showing a process of a light emitting diode structure in accordance with an embodiment of the present invention.

12A to 12D are cross-sectional views showing a process of a light emitting diode structure according to another embodiment of the present invention.

13A to 13C are cross-sectional views showing a process of a light emitting diode structure according to still another embodiment of the present invention.

Please refer to FIG. 2 to FIG. 4 , wherein FIG. 2 is a top view showing a structure of a light emitting diode according to an embodiment of the present invention, and FIG. 3 is a view along line AA of FIG. 2 . A cross-sectional view of the structure of the light-emitting diode obtained by the hatching, and FIG. 4 is a cross-sectional view showing the structure of the light-emitting diode obtained along the line BB' of FIG. In the present embodiment, the LED structure 200 can be a High Voltage LED (HV LED).

The light emitting diode structure 200 is formed by connecting a plurality of light emitting diode chips 228 in series. As shown in the exemplary embodiment of FIG. 2, the LED structure 200 is comprised of 16 LED chips 228. Each of the LED chips 228 is provided with isolation trenches 216 and 240 around it for electrical Any two adjacent LED chips 228 are isolated. In addition, adjacent light-emitting diode wafers 228 are electrically connected by electrically conductive inner wiring layer 226 to connect all of the light-emitting diode wafers 228 in series.

Referring to FIG. 2 and FIG. 3 together, the LED structure 200 mainly includes an insulating substrate 202, a plurality of LED chips 228, a plurality of interconnect layers 226, and a first electrical electrode pad 238. The second electrical electrode pad 236, the insulating reflective layer 220, the first electrical bonding pad 252, and the second electrical bonding pad 232. The material of the insulating substrate 202 may be, for example, sapphire. In some examples, the insulating substrate 202 can be a patterned sapphire substrate (PSS), that is, a plurality of pattern structures (not shown) are formed on the surface 204 of the insulating substrate 202. By the arrangement of these pattern structures, the light extraction efficiency of the light-emitting diode wafer 228 can be improved.

These light emitting diode chips 228 are disposed on the surface 204 of the insulating substrate 202. Each of the light emitting diode wafers 228 includes an epitaxial layer 214. In the embodiment shown in FIG. 3, the epitaxial layer 214 includes an undoped semiconductor layer 206, a first electrical semiconductor layer 208, an active layer 210, and a second layer that are sequentially stacked on the surface 204 of the insulating substrate 202. Electrical semiconductor layer 212. In the present invention, the first electrical property and the second electrical property are different electrical properties. For example, one of the first electrical property and the second electrical property is an n-type, and the other is a p-type. In another embodiment, the epitaxial layer 214 may also not include the undoped semiconductor layer 206.

In some examples, the active layer 210 can be, for example, a multiple quantum well (MQW) structure composed of a plurality of sets of quantum wells and barrier layers stacked alternately. In one case The material of the undoped semiconductor layer 206, the first electrical semiconductor layer 208, the active layer 210 and the second electrical semiconductor layer 212 may be, for example, a gallium nitride series material.

Each of the light emitting diode wafers 228 includes a platform structure 230 and an exposed portion 234 that abut each other. The platform structure 230 includes a portion of the undoped semiconductor layer 206, a portion of the first electrical semiconductor layer 208, a portion of the active layer 210, and a portion of the second electrical semiconductor layer 212. Since the exposed portion 234 defines the platform structure 230 in the epitaxial layer 214, a portion of the second electrical semiconductor layer 212 and a portion of the active layer 210 are removed, even a portion of the first electrically conductive semiconductor layer 208, The portion formed after exposing the first electrical semiconductor layer 208. Therefore, the exposed portion 234 is a portion of the first semiconductor layer 208 that is exposed, and the exposed portion 234 includes a portion of the undoped semiconductor layer 206 and a portion of the first electrical semiconductor layer 208, but does not include the active layer 210 and the The second electrical semiconductor layer 212.

In one embodiment, as shown in FIG. 3, the cross-sectional shape of the platform structure 230 can be, for example, trapezoidal and have a sloped side 246. By having the platform structure 230 have a sloped side 246, deposition of the subsequent interconnect layer 226 can be facilitated. However, in another embodiment, the cross-sectional shape of the platform structure 230 can also be rectangular with a vertical side 246.

Each of the LED chips 228 further includes an isolation trench 216. In the light emitting diode wafer 228, the isolation trenches 216 are disposed in the platform structure 230 and are preferably adjacent to the exposed portions 234 of the adjacent light emitting diode wafers 228. In the platform structure 230, the isolation trenches 216 extend downward from the second electrically conductive semiconductor layer 212 toward the undoped semiconductor layer 206. In an embodiment, The bottom of the isolation trench 216 is located in the undoped semiconductor layer 206. In the embodiment shown in FIG. 3, the bottom of the isolation trench 216 extends directly to the surface 204 of the insulating substrate 202 to expose the surface 204 of the insulating substrate 202. In embodiments where the epitaxial structure 214 does not include the undoped semiconductor layer 206, the isolation trench 216 extends from the second electrically conductive semiconductor layer 212 toward the surface 204 of the insulating substrate 202. Thus, the bottom of the isolation trench 216 of this embodiment exposes a portion of the surface 204 of the insulating substrate 202.

In some embodiments, each of the light emitting diode wafers 228 may further include an insulating layer 218. In the LED array 228, the insulating layer 218 fills the isolation trench 216 and covers the surface 204 of the insulating substrate 202, and preferably seals the opening 248 of the isolation trench 216. As shown in FIG. 3, the insulating layer 218 can completely fill the isolation trench 216. In another embodiment, the insulating layer 218 may not fill the isolation trench 216. For example, the insulating layer 218 in the isolation trench 216 may have holes. In still other embodiments, the insulating layer 218 may only fill a portion of the depth of the isolation trench 216.

In one embodiment, as shown in FIG. 3, the isolation trench 216 has an inverted trapezoidal shape so that the insulating layer 218 is deposited in the isolation trench 216. The angle θ between the isolation trench 216 and the surface 204 of the insulating substrate 202 can be, for example, from 30° to 90°. In another embodiment, the cross-sectional shape of the isolation trench 216 may also be rectangular. Further, the material of the insulating layer 218 may be, for example, hafnium oxide or tantalum nitride (SiN _x ).

In one embodiment, each of the LED chips 228 can also optionally include a current blocking layer 222 to distribute the current distribution. As shown in FIG. 3, the current blocking layer 222 is disposed on the platform structure 230 and is located on the platform structure 230. Above the trench 216, the insulating layer 218, a portion of the second electrical semiconductor layer 212, and the side surface 246 of the platform structure 230 where the interconnect layer 226 is located are covered.

Each of the light emitting diode wafers 228 more selectively includes a transparent conductive layer 224. The material of the transparent conductive layer 224 may be, for example, indium tin oxide (ITO) or the like. The transparent conductive layer 224 is disposed on the platform structure 230 and covers the current blocking layer 222 and extends on the second electrical semiconductor layer 212 of the platform structure 230. In another embodiment, the transparent conductive layer 224 may be located only on the second electrical semiconductor layer 212 of the platform structure 230, but not over the current blocking layer 222, wherein the interconnect layer 226 extends over the transparent portion of the cover layer. Conductive layer 224 for electrical conduction.

In the LED structure 200, the interconnect layer 226 is connected to the adjacent LED chips 228 to electrically connect the LED chips 228. The interconnect layer 226 extends from the exposed portion 234 of the first electrically conductive semiconductor layer 208 of one of the two adjacent light emitting diode wafers 228 to the planar structure of the other LED array 228. A transparent conductive layer 224 on 230. As shown in FIG. 3, the interconnect layer 226 extends directly from the exposed portion 234 of one of the two adjacent light emitting diode wafers 228 to the platform structure of the other LED array 228. The current blocking layer 222 on the side 246 of the 230 is coupled to the transparent conductive layer 224 above the platform structure 230 along the side 246 of the platform structure 230. Thus, the lowest surface of interconnect layer 226 is on exposed portion 234 of first electrically conductive semiconductor layer 208 and is in contact with exposed portion 234 of first electrically conductive semiconductor layer 208. The material of the interconnect layer 226 is a conductive material, for example For metal. In an embodiment, the interconnect layer 226 may be a chromium/platinum/gold (Cr/Pt/Au) stack structure composed of a sequentially stacked chromium layer, a platinum layer and a gold layer.

As shown in FIG. 3, a portion of the interconnect layer 226 on the platform structure 230 overlies the current barrier layer 222 and the transparent conductive layer 224 over the isolation trench 216. Therefore, the current blocking layer 222 is interposed between the inner wiring layer 226 above the platform structure 230 and the insulating layer 218 in the isolation trench 216, and the transparent conductive layer 224 is interposed between the interconnecting layer 226 and the current above the platform structure 230. Between the barrier layers 222.

In an embodiment, the current blocking layer 222 may have a portion extending horizontally to the outside of the interconnect layer 226 to achieve a better current blocking effect and to prevent a large amount of current from being directly poured down from the interconnect layer 226 to The current is congested in the LED 228, which in turn forces current to flow into the platform structure 230 via the transparent conductive layer 224. Thereby, the luminous efficiency of the light-emitting diode wafer 228 can be greatly improved. Thus, in a preferred embodiment, the transparent conductive layer 224 can extend over the second electrically conductive semiconductor layer 212 on the platform structure 230.

Referring to FIGS. 2 and 3 again, the first electrical electrode pad 238 and the second electrical electrode pad 236 are respectively disposed on the two light emitting diode wafers of the LED structure 200. For example, the two-emitting diode wafers are the starting wafer and the ending wafer of the LED array, that is, the LED wafers 228a and 228b. The first electrical electrode pad 238 and the second electrical electrode pad 236 can be fabricated simultaneously with the interconnect layer 226, and the materials of the first electrical electrode pad 238 and the second electrical electrode pad 236 can also be connected to the interconnect layer. The material of 226 is the same. The first electrical electrode pad 238 and the second electrical electrode pad 236 The material is a conductive material such as a metal. In one embodiment, the first electrical electrode pad 238 and the second electrical electrode pad 236 may each be a chromium/platinum/gold stack structure composed of a chrome layer, a platinum layer and a gold layer stacked in sequence. In the light emitting diode structure 200, the first electrical electrode pad 238 may be located on the exposed portion 234 of the first electrical semiconductor layer 208 of the light emitting diode wafer 228a, and the exposed portion of the first electrical semiconductor layer 208. 234 electrical connection. On the other hand, the second electrical electrode pad 236 can be located on the transparent conductive layer 224 or the second electrical semiconductor layer 212 on the platform structure 230 of the LED substrate 228b, and electrically connected to the second electrical semiconductor layer 212. connection.

In an embodiment, the LED structure 200 may further include a test pad 258. The test pad 258 can be disposed on one or more of the desired LED chips 228 depending on the process or product requirements. As shown in the embodiment of FIG. 2, the test pad 258 extends over two adjacent two adjacent light emitting diode chips 228, that is, two light emitting diodes between the light emitting diode chips 228a and 228b. The inner wiring layer 226 is bonded to the body wafer 228 and between the two adjacent light emitting diode wafers 228.

The insulating reflective layer 220 covers the inner wiring layer 226 of the light emitting diode wafer 228, the platform structure 230, the exposed portion 234 of the first electrical semiconductor layer 212, the first electrical electrode pad 238 and the second electrical electrode pad 236. on. The insulating reflective layer 220 may be, for example, a Bragg Reflector (DBR). In this embodiment, the Bragg mirror material comprises, for example, cerium oxide/titanium dioxide (SiO ₂ /TiO ₂ ) or cerium oxide/cerium nitride. Repeated laminate of (SiO ₂ /SiN _X ), or a combination thereof. In one embodiment, the insulating reflective layer 220 is provided with at least through holes 256 and 254, wherein the two through holes 256 and 254 respectively expose a portion of the first electrical electrode pad 238 and a portion of the second electrical electrode pad 236. As a result, the subsequently formed first electrical bond pads 252 and second electrical bond pads 232 can respectively pass through the through holes 256 and 254, respectively, and the exposed first electrical electrode pads 238 and the second electrical electrodes. Pad 236 is electrically joined.

In another embodiment, the insulating reflective layer 220 is further provided with a through hole 260 according to the setting of the test pad 258. The through hole 260 can expose a portion of the test pad 258 for subsequent detection of the LED structure 200 through the exposed test pad 258 via the through hole 260.

As shown in FIG. 2, the first electrical bonding pads 252 and the second electrical bonding pads 232 are respectively disposed on the insulating reflective layer 220 to form two portions separated from each other. That is, the first electrical bond pad 252 and the second electrical bond pad 232 are separated from each other. The first electrical bonding pad 252 is further in contact with and electrically connected to the exposed first electrical electrode pad 238 via the through hole 256 of the insulating reflective layer 220. On the other hand, the second electrical bonding pad 232 is further in contact with and electrically connected to the exposed second electrical electrode pad 236 via the other through hole 254 of the insulating reflective layer 220.

Referring to FIGS. 2 and 4 together, each of the LED chips 228 further includes another isolation trench 240. The isolation trench 240 is disposed in the epitaxial layer 214 outside the platform structure 230 and is adjacent to the isolation trench 216. As shown in FIG. 2, the isolation trench 240 electrically isolates two adjacent rows of LED chips 228. Moreover, unlike the isolation trench 216, the isolation trench 240 is not covered with a conductive material such as a transparent conductive layer or an interconnect layer.

Isolation trench 240 from second electrical semiconductor layer of epitaxial layer 214 212 extends to the undoped semiconductor layer 206. Therefore, the bottom of the isolation trench 240 is located in the undoped semiconductor layer 206. In the embodiment illustrated in FIG. 4, the bottom of the isolation trench 240 extends directly to the surface 204 of the insulating substrate 202 to expose the surface 204 of the insulating substrate 202. In the embodiment in which the epitaxial layer 214 does not include the undoped semiconductor layer 206, the isolation trench 240 extends from the second electrical semiconductor layer 212 toward the surface 204 of the insulating substrate 202. At this time, the bottom of the isolation trench 240 exposes the insulating substrate 202. A portion of the surface 204.

In some embodiments, each of the LED wafers 228 may further comprise another insulating layer 242. The insulating layer 242 is filled into the isolation trench 240 and preferably encloses the opening 250 of the isolation trench 240. In an example, the insulating layer 242 can completely fill the isolation trench 240. In another example, the insulating layer 242 may also not fill the isolation trench 240. In addition, as shown in FIG. 4, the isolation trench 240 may have an inverted trapezoidal shape so that the insulating layer 242 is deposited in the isolation trench 240. In an exemplary embodiment, the angle a between the isolation trench 240 and the surface 204 of the insulating substrate 202 can be, for example, from 30° to 90°. However, in another example, the cross-sectional shape of the isolation trench 240 may also be rectangular. The material of the insulating layer 242 may be, for example, hafnium oxide or tantalum nitride.

In one embodiment, each of the LED chips 228 can also optionally include another current blocking layer 244. As shown in FIG. 4, the current blocking layer 244 is located above the isolation trench 240 and covers the insulating layer 242 in the isolation trench 240 and the second electrical semiconductor layer 212 on the periphery of the opening 250 of the isolation trench 240. The insulating reflective layer 220 also covers the current blocking layer 244 above the isolation trench 240.

Please refer to FIG. 5, which is a cross-sectional view showing a structure of a light emitting diode according to another embodiment of the present invention. The structure of the light emitting diode structure 200a of this embodiment is substantially the same as that of the light emitting diode structure 200 of the above embodiment, and the main difference between the two is that each of the light emitting diode structures 228c of the light emitting diode structure 200a is further A dielectric layer 262 is included.

In the light emitting diode structure 200a, a dielectric layer 262 is stacked on the epitaxial layer 214. Dielectric layer 262 may also be referred to as an interlayer dielectric (ILD) layer. The material of the dielectric layer 262 is an insulating material such as cerium oxide and tantalum nitride. Each of the light emitting diode wafers 228c has a first electrical contact hole 264 and a second electrical contact hole 266. The first electrical contact hole 264 and the second electrical contact hole 266 both penetrate the dielectric layer 262. The first electrical contact hole 264 extends from the upper surface 278 of the dielectric layer 262 to the first electrical semiconductor layer 208 of the epitaxial layer 214. Therefore, the bottom 270 of the first electrical contact hole 264 exposes a portion of the first electrical semiconductor layer 208.

In embodiments in which the light emitting diode wafer 228c has no transparent conductive layer, the second electrical contact hole 266 extends from the upper surface 278 of the dielectric layer 262 to the second electrical semiconductor layer 212 of the epitaxial layer 214. That is, the bottom 280 of the second electrical contact hole 266 exposes a portion of the second electrical semiconductor layer 212. In the embodiment where the LED substrate 228c has the transparent conductive layer 224, the transparent conductive layer 224 is interposed between the dielectric layer 262 and the epitaxial layer 214, and the second electrical contact hole 266 is formed from the dielectric layer 262. Upper surface 278 extends only to transparent conductive layer 224. Therefore, the bottom 280 of the second electrical contact hole 266 exposes a portion of the transparent conductive layer 224. In each of the LED chips 228c, the isolation trench 216 is interposed between the second electrical properties of the LED chip 228c. The contact hole 266 is between the first electrical contact hole 264 of the adjacent light-emitting diode wafer 228c.

Each of the light emitting diode wafers 228c further includes an insulating liner 268. The insulating liner 268 is covered on the sidewall of the first electrical contact hole 264 to electrically isolate the inner wiring layer 226 of the first electrical contact hole 264 and the sidewall of the first electrical contact hole 264. The transparent conductive layer 224, the second electrical semiconductor layer 212, the active layer 210 and the first electrical semiconductor layer 208 are formed. Thereby, the current in the first electrical contact hole 264 can be prevented from flowing through the transparent conductive layer 224 having a small resistance value to reach the second electrical contact hole 266, thereby causing a short circuit and failing to emit light. By the arrangement of the insulating liner 268, the first electrical semiconductor layer 208 and the second electrical semiconductor layer 212 of the same LED wafer 228c or the adjacent LED wafer 228c can be prevented from passing through the transparent conductive layer 224. Direct conduction.

Each of the light emitting diode wafers 228c may further include an insulating liner 282. The insulating liner 282 is overlaid on the sidewall of the second electrical contact hole 266 to improve the electrical reliability of the LED wafer 228c. However, the light emitting diode wafer 228c may only include the insulating liner 268 without the need to provide an insulating liner 282. The material of the insulating liners 268 and 282 may be, for example, hafnium oxide or tantalum nitride.

In another embodiment, the light emitting diode structure may also not include an insulating liner. Please refer to FIG. 6, which is a cross-sectional view showing a structure of a light emitting diode according to still another embodiment of the present invention. In the present embodiment, the structure of the LED structure 200b is substantially the same as that of the LED structure 200a of the above embodiment, and the difference between the two is that the illumination is two. The first electrical contact hole 264 and the second electrical contact hole 266 of the LED body 228d of the polar body structure 200b are not provided with an insulating liner.

In the light emitting diode structure 200b, the epitaxial layer 214 of each of the light emitting diode wafers 228d is provided with a recess 276. The recess 276 extends from the second electrical semiconductor layer 212 of the epitaxial layer 214 toward the first electrical semiconductor layer 208. The bottom 284 of the recess 276 is located in the first electrically conductive semiconductor layer 208, i.e., the bottom 284 of the recess 276 exposes the first electrically conductive semiconductor layer 208. The first electrical contact hole 264 is in contact with the recess 276. Moreover, one of the dielectric layers 262 partially overlies the sidewalls of the recess 276, and the bottom 270 of the first electrical contact hole 264 exposes a portion of the bottom 284 of the recess 276.

By designing the dielectric layer 262 to extend over the sidewall of the recess 276 of the epitaxial layer 214, the LED structure 200b can be disposed on the sidewall of the first electrical contact hole 264 without additionally providing an insulating liner. The effect of electrically interconnecting the interconnect layer 226 and the epitaxial layer 214 and the transparent conductive layer 224 exposed by the sidewalls of the recess 276.

Referring to FIG. 5 again, in the LED structure 200a, the interconnect layer 226 is respectively filled in the second electrical contact hole 266 of the LED array 228c, and is connected via the isolation trench 216. The upper surface 278 of the electrical layer 262 extends and fills the first electrical contact hole 264 of the adjacent light emitting diode wafer 228c. Portions of the interconnect layer 226 that fill the first electrical contact hole 264 and the second electrical contact hole 266 may also be referred to as contact plugs 272 and 274, respectively. The insulating reflective layer 220 covers the dielectric layer 262 and the interconnect layer 226.

As shown in FIG. 5, in each of the light-emitting diode wafers 228c, The current blocking layer 222 is disposed on a portion of the epitaxial layer 214 and below the bottom 280 of the second electrical contact hole 266. Therefore, the current blocking layer 222 is interposed between the bottom 280 of the second electrical contact hole 266 and the epitaxial layer 214. Moreover, the transparent conductive layer 224 covers the current blocking layer 222.

By the arrangement of the current blocking layer 222, a large amount of current can be prevented from being directly poured down into the LED array 228c via the contact plug 274 of the interconnect layer 226, thereby causing current congestion, thereby forcing the current to pass through the transparent The conductive layer 224 flows into the epitaxial layer 214. In one embodiment, the current blocking layer 222 is preferably larger than the area of the bottom of the contact plug 274, that is, the current blocking layer 222 preferably covers the entire bottom of the contact plug 274 to obtain a better current. Barrier effect.

In another embodiment, the insulating layer 218 may only fill a portion of the depth of the isolation trench 216 without the upper surface of the insulating layer 218 being as high as the epitaxial layer 214. In this embodiment, the current blocking layer 222 can extend from below the bottom 280 of the second electrical contact hole 266 to the opening 248 of the adjacent insulating trench 216, and the current blocking layer 222 covers the insulating trench 216. Opening 248. By the arrangement of the current blocking layer 222, the insulating effect can be further increased to prevent the transparent conductive layer 224 from covering the epitaxial layer 214 to cause a short circuit.

Please refer to FIG. 7, which is a cross-sectional view showing a structure of a light emitting diode according to still another embodiment of the present invention. In the present embodiment, the structure of the LED structure 200c is substantially the same as that of the LED structure 200a of the above embodiment, and the difference is that the insulating reflective layer 220 of the LED structure 200c replaces the LED. Insulating liners 268 and 282 of the polar body structure 200a. Moreover, the insulating reflective layer 220 covers the light emitting diode The sidewall of the first electrical contact hole 264 of the bulk wafer 228e, the sidewall of the second electrical contact hole 266, and the upper surface 278 of the dielectric layer 262. In addition, the light emitting diode structure 200c further includes an insulating layer 290. The insulating layer 290 covers the inner wiring layer 226 and the insulating reflective layer 220.

Referring to FIG. 2 together, in the LED structure 200c, the insulating layer 290 can be provided with at least two through holes, such as the insulating reflective layer 220 of the LED structure 200, wherein the two through holes respectively expose portions. The first electrical electrode pad 238 and a portion of the second electrical electrode pad 236. As a result, the first electrical bonding pads 252 and the second electrical bonding pads 232 are respectively formed through the two through holes, respectively, and the exposed first electrical electrode pads 238 and the second electrical electrode pads respectively. 236 electrical engagement.

In another embodiment, the insulating layer 290 is further provided with another through hole according to the setting of the test pad 258. The through hole may expose a portion of the test pad 258 for subsequent detection of the light emitting diode structure 200c through the exposed test pad 258 via the through hole.

Please refer to FIG. 8 , which is a cross-sectional view showing a structure of a light emitting diode according to still another embodiment of the present invention. In the present embodiment, the structure of the LED structure 200d is substantially the same as that of the LED structure 200b of the above embodiment, and the difference between the two is that each LED of the LED structure 200d is different. An insulating reflective layer 220 of 228f overlies the sidewalls of the recess 276 of the epitaxial layer 214 and the upper surface 288 of the transparent conductive layer 224. In addition, the light emitting diode structure 200d further includes an insulating layer 290. The insulating layer 290 covers the inner wiring layer 226 and the upper surface 278 of the dielectric layer 262.

In the LED structure 200d of this embodiment, since the insulating reflective layer 220 is disposed closer to the active layer 210, the light emitted by the active layer 210 does not pass through the dielectric layer 262. Therefore, the loss of light absorbed by the dielectric layer 262 can be reduced, and the luminous efficiency of the light-emitting diode structure 200d can be further improved.

Referring to FIG. 2 together, in the LED structure 200d, the insulating layer 290 can be provided with at least two through holes, such as the insulating reflective layer 220 of the LED structure 200, wherein the two through holes respectively expose portions. The first electrical electrode pad 238 and a portion of the second electrical electrode pad 236. Therefore, the first electrical bonding pads 252 and the second electrical bonding pads 232 can be electrically connected to the exposed first and second electrical electrode pads 238 and 236, respectively. Sexual engagement.

In another embodiment, the insulating layer 290 is further provided with another through hole according to the setting of the test pad 258. The through hole may expose a portion of the test pad 258 for subsequent detection of the light emitting diode structure 200d through the exposed test pad 258 via the through hole.

Please refer to FIG. 9, which is a cross-sectional view showing a structure of a light emitting diode according to still another embodiment of the present invention. In the present embodiment, the structure of the LED structure 200e is substantially the same as the structure of the LED structure 200b of the above embodiment, and the difference between the two is that each of the LEDs 200e of the LED structure 200e A 228 g of insulating reflective layer 220 overlies the upper surface 288 of the transparent conductive layer 224. In addition, the light emitting diode structure 200e further includes an insulating layer 290. The insulating layer 290 covers the inner wiring layer 226 and the upper surface 278 of the dielectric layer 262.

Referring to FIG. 2 together, in the LED structure 200e, the insulating layer 290 can be provided with at least two through holes, such as the insulating reflective layer 220 of the LED structure 200, wherein the two through holes respectively expose portions. The first electrical electrode pad 238 and a portion of the second electrical electrode pad 236. As a result, the first electrical bonding pads 252 and the second electrical bonding pads 232 are respectively formed through the two through holes, respectively, and the exposed first electrical electrode pads 238 and the second electrical electrode pads respectively. 236 electrical engagement.

In another embodiment, the insulating layer 290 is further provided with another through hole according to the setting of the test pad 258. The through hole may expose a portion of the test pad 258 to facilitate subsequent detection of the light emitting diode structure 200e through the exposed test pad 258 via the through hole.

Please refer to FIG. 10, which is a cross-sectional view showing a structure of a light emitting diode according to still another embodiment of the present invention. In the present embodiment, the structure of the LED structure 200f is substantially the same as that of the LED structure 200b of the above embodiment, and the difference between the two is that each LED of the LED structure 200f is printed. An insulating reflective layer 220 of 228h overlies the upper surface 278 of the dielectric layer 262. In addition, the light emitting diode structure 200f further includes an insulating layer 290. The insulating layer 290 covers the inner wiring layer 226 and the insulating reflective layer 220.

Referring to FIG. 2 together, in the LED structure 200f, the insulating layer 290 can be provided with at least two through holes, such as the insulating reflective layer 220 of the LED structure 200, wherein the two through holes respectively expose portions. The first electrical electrode pad 238 and a portion of the second electrical electrode pad 236. As a result, the first electrical bonding pad 252 and the second electrical bonding pad 232 are formed subsequently. The first electrical electrode pad 238 and the second electrical electrode pad 236 are electrically connected to each other through the two through holes.

In another embodiment, the insulating layer 290 is further provided with another through hole according to the setting of the test pad 258. The through hole may expose a portion of the test pad 258 for subsequent detection of the light emitting diode structure 200f through the exposed test pad 258 via the through hole.

Please refer to FIG. 11A to FIG. 11G, which are schematic cross-sectional views showing a process of a light emitting diode structure according to an embodiment of the present invention. In this embodiment, when the light emitting diode structure 200 is manufactured, the insulating substrate 202 is first provided. The undoped semiconductor layer 206, the first electrical semiconductor layer 208, the active layer 210 and the first layer are formed on the surface 204 of the insulating substrate 202 by an epitaxial growth mode, such as an organic metal chemical vapor deposition (MOCVD) method. The second electrical semiconductor layer 212. As shown in FIG. 11A, the undoped semiconductor layer 206, the first electrical semiconductor layer 208, the active layer 210, and the second electrical semiconductor layer 212 are sequentially stacked to form an epitaxial structure 214a. In another embodiment, the epitaxial structure 214a may also not include the undoped semiconductor layer 206.

Next, an etch stop layer 292 is formed overlying the second electrical semiconductor layer 212 by, for example, a deposition method. The material of the etch stop layer 292 may be, for example, tantalum nitride (SiN _x ). As shown in FIG. 11B, a hard mask layer 294 is formed over the etch stop layer 292 by, for example, deposition. The material of the hard mask layer 294 can be, for example, nickel or cerium oxide. The etch stop layer 292 can serve as an etch end point when the hard mask layer 294 pattern is defined.

Next, a photoresist layer 296 is formed on the hard mask layer 294 by, for example, a coating method. Reusing, for example, a lithography process, the photoresist layer 296 A pattern definition is performed to remove portions of the photoresist layer 296 to expose portions of the hard mask layer 294, thereby defining the predetermined locations and shapes of the isolation trenches 216 and 240 in the photoresist layer 296. Subsequently, the exposed portion of the hard mask layer 294 is removed by, for example, etching, with the patterned photoresist layer 296 as an etch mask, and the etch stop layer 292 as the etch end, thereby placing the photoresist layer 296 therein. The pattern is transferred to the hard mask layer 294. In this way, the predetermined position and shape of the isolation trenches 216 and 240 originally defined in the photoresist layer 296 can be transferred to the hard mask layer 294 as shown in FIG. 11C.

Next, the epitaxial structure 214a is etched by, for example, an inductively coupled plasma etching (ICP) method, and the patterned photoresist layer 296 and the hard mask layer 294 are used as an etching mask to remove a portion of the second electricity. The semiconductor layer 212, a portion of the active layer 210, a portion of the first electrical semiconductor layer 208 and a portion of the undoped semiconductor layer 206, thereby transferring the pattern in the hard mask layer 294 into the epitaxial structure 214a, A plurality of isolation trenches 216 and 240 are formed in the epitaxial structure 214a. As shown in FIGS. 2 and 11D, the isolation trenches 216 are respectively adjacent to the isolation trenches 240, and the isolation trenches 216 and 240 define the epitaxial structures 214a as the epitaxial layers 214 of the plurality of light emitting diode wafers 228. Each of the LED chips 228 includes an isolation trench 216, and an isolation trench 240 is spaced between adjacent two rows of LED chips 228.

In one embodiment, as shown in FIGS. 4 and 11D, the bottom of the isolation trench 216 and the bottom of the isolation trench 240 expose a portion of the surface 204 of the insulating substrate 202. In another embodiment, the bottom of the isolation trench 216 and the bottom of the isolation trench 240 may be located in the undoped semiconductor layer 206. in. In embodiments where the epitaxial layer 214 does not include the undoped semiconductor layer 206, the isolation trenches 216 and 240 extend from the second electrically conductive semiconductor layer 212 toward the surface 204 of the insulating substrate 202, and the isolation trenches 216 and 240 are exposed. A portion of the surface 204 of the insulating substrate 202.

In one embodiment, as shown in FIG. 11D, after the isolation trenches 216 and 240 are formed, the residual photoresist layer 296 and the hard mask layer 294 may be removed to expose the etch stop layer 292. In another embodiment, the etch stop layer 292 may not need to be formed before the hard mask layer 294, but after the photoresist layer 296 and the hard mask layer 294 are removed, an etch stop layer 292 is formed to cover the second On the semiconductor layer 212.

Next, an insulating material can be selectively formed over the etch stop layer 292 and the isolation trenches 216 and 240, for example, by plasma assisted chemical deposition (PECVD), depending on product requirements. The insulating material can be, for example, hafnium oxide or tantalum nitride. Next, in an embodiment, the insulating material on the etch stop layer 292 can be removed by, for example, etchback, and the etch stop layer 292 is used as an etch stop, thereby filling the isolation trenches 216 and 240 with insulating layers, respectively. 218 and 242, as shown in Figures 11E and 4. In some embodiments, excess insulating material on the etch stop layer 292 can be removed using, for example, a chemical mechanical polishing (CMP) process. At this time, the etch stop layer 292 serves as the polishing end point.

The insulating layers 218 and 242 preferably enclose the opening 248 of the isolation trench 216 and the opening 250 of the isolation trench 240, respectively. In one embodiment, as shown in FIG. 11E, the insulating material can completely fill the isolation trenches 216 and 240. In another embodiment, the insulating material may not fill the isolation trench 216 and 240, and holes are formed in the isolation trenches 216 and 240.

Next, the etch stop layer 292 is removed to expose the second electrical semiconductor layer 212. In one embodiment, the platform definition of the LED array 228 can be performed directly. However, in another embodiment, a current blocking material may be selectively formed on the insulating layers 218 and 242 and the second electrical semiconductor layer 212, for example, by a deposition method. A portion of the current blocking material on the second electrical semiconductor layer 212 is removed by, for example, lithography and etching to form current blocking layers 222 and 244, as shown in FIGS. 11F and 4. The current blocking layer 222 overlies the insulating layer 218 and extends over the second electrically conductive semiconductor layer 212 outside the opening 248 of the isolation trench 216. Similarly, current barrier layer 244 overlies insulating layer 242 and extends over second electrically conductive semiconductor layer 212 outside of opening 250 of isolation trench 240.

As shown in FIG. 11F, in the embodiment in which the current blocking layers 222 and 244 are provided, the transparent conductive layer 224 may be formed over the current blocking layers 222 and 244, and then by, for example, evaporation or sputtering. On the second electrical semiconductor layer 212. The material of the transparent conductive layer 224 may be, for example, indium tin oxide. Next, the definition of the platform for each of the LED chips 228 is performed using, for example, a lithography and etching process, such as an inductively coupled plasma etch process. In the platform definition process, a portion of the transparent conductive layer 224, a portion of the second electrical semiconductor layer 212, a portion of the active layer 210, and even a portion of the first electrical semiconductor layer 208 are removed to expose portions of the transparent conductive layer 224. The first electrically conductive semiconductor layer 208 forms a land structure 230 and an exposed portion 234 of each of the light emitting diode wafers 228. In addition, as shown in FIG. 4, the platform definition process further removes the transparent conductive layer 224 on the isolation trench 240. After the platform is defined, each The isolation trench 216 of the LED chip 228 is located in the platform structure 230, and the transparent conductive layer 224 is located on the platform structure 230.

In another embodiment, the current barrier layers 222 and 244 may be formed after the definition of the platform of each of the LED chips 228 is completed, and then the transparent conductive layer 224 is formed. At this time, as shown in FIG. 11G, the current blocking layer 222 is located on the platform structure 230 and above the isolation trench 216, and covers the insulating layer 218, a portion of the second electrical semiconductor layer 212, and subsequently formed. Side 246 of platform structure 230 where interconnect layer 226 is located. Moreover, the transparent conductive layer 224 is located on the platform structure 230 and overlies the current blocking layer 222 and extends over the second electrical semiconductor layer 212 of the platform structure 230. On the other hand, the current blocking layer 244 is located above the isolation trench 240 and covers the insulating layer 242 in the isolation trench 240 and the second electrical semiconductor layer 212 on the periphery of the opening 250 of the isolation trench 240.

Next, a conductive layer is formed overlying the exposed portions 234 of the landing structure 230 and the first electrically conductive semiconductor layer 208 by, for example, deposition. A portion of the metal layer is removed by, for example, lithography and etching to form a plurality of interconnect layers 226, a first electrical electrode pad 238, and a second electrical electrode pad 236. In another embodiment, as shown in FIG. 2, a test pad 258 can be fabricated simultaneously while the interconnect layer 226 is being formed. The interconnect layer 226 is connected to the adjacent LED chips 228 to electrically connect the LED chips 228. The first electrical electrode pad 238 and the second electrical electrode pad 236 are respectively disposed on the two LED chips of the LED structure 200, such as the LED array 228b of the LED array, respectively. 228a. The first electrical electrode pad 238 can be located at the first electrical property of the LED chip 228b. The exposed portion 234 of the semiconductor layer 208 is electrically coupled to the exposed portion 234 of the first electrically conductive semiconductor layer 208. On the other hand, the second electrical electrode pad 236 can be located on the transparent conductive layer 224 or the second electrical semiconductor layer 212 on the platform structure 230 of the LED body 228a, and electrically connected to the second electrical semiconductor layer 212. connection.

Next, the insulating reflective layer 220 is formed to cover the inner wiring layer 226, the land structure 230, the exposed portion 234 of the first electrical semiconductor layer 208, the first electrical electrode pad 238, and the second electrical electrode by, for example, deposition. Pad 236. Referring again to FIG. 2, the insulating reflective layer 220 can be defined by, for example, a patterning technique to form at least through holes 256, 254, and 260 in the insulating reflective layer 220. The three through holes 256, 254, and 260 respectively expose a portion of the first electrical electrode pad 238, a portion of the second electrical electrode pad 236, and a portion of the test pad 258. The detection of the light-emitting diode structure 200 can be performed through the test pad 258 exposed through the through hole 260 by the provision of the through hole 260.

Next, as shown in FIG. 2 and FIG. 11G, the first electrical bonding pads 252 and the second electrical bonding pads 232 are respectively formed on the two separated portions of the insulating reflective layer 220, and the tandem illumination is completed. Polar body structure 200. The first electrical bond pad 252 and the second electrical bond pad 232 are separated from each other. In addition, the first electrical bonding pads 252 and the second electrical bonding pads 232 can respectively contact the exposed first electrical electrode pads 238 and the second electrical electrode pads 236 via the through holes 256 and 254, respectively. Sexual engagement.

Please refer to FIG. 12A to FIG. 12D , which are cross-sectional views showing a process of a light emitting diode structure according to another embodiment of the present invention. In the present embodiment, the structure shown in FIG. 11F can be completed according to the process steps of the above embodiment. Next, a layer of dielectric material is formed overlying the transparent conductive layer 224 over the epitaxial layer 214. The dielectric material is an insulating material such as hafnium oxide and tantalum nitride. In one embodiment, the layer of dielectric material can be formed using, for example, plasma-assisted chemical deposition, wherein the thickness of the layer of dielectric material can range from about 2000 Å to about 3,000 Å. In another embodiment, the layer of dielectric material can be formed using, for example, spin coating, wherein the thickness of the layer of dielectric material can range from about 2 [mu]m to about 3 [mu]m.

Then, the dielectric material layer can be planarized by, for example, chemical mechanical polishing according to actual process requirements, to obtain a layer of dielectric material having a substantially flat surface. Then, as shown in FIG. 12A, a portion of the dielectric material layer is removed by, for example, lithography and etching, such as inductively coupled plasma etching, to form a portion and a plurality of first electrical contact holes 264. A second electrical contact hole 266 and a plurality of dielectric layers 262 are formed. Each of the LED wafers 228c includes a dielectric layer 262, and a portion of the first electrical contact holes 264 and the second electrical contact holes 266 extend through the dielectric layer 262.

Next, a photoresist layer 298 is formed on the dielectric layer 262 and filled in the first electrical contact hole 264 and the second electrical contact hole 266. The photoresist layer 298 is patterned using, for example, a lithography process. When the photoresist layer 298 is defined, the photoresist layer 298 in the first electrical contact hole 264 is removed, and the transparent conductive layer 224 in the first electrical contact hole 264 is exposed. Then, the exposed portion of the transparent conductive layer 224 and the second electrical half below it are removed by, for example, etching, and using the patterned photoresist layer 298 as an etch mask. The conductor layer 212, the active layer 210 and a portion of the first electrical semiconductor layer 208 complete the first electrical contact hole 264. As such, the definition of the exposed structure 234 of the platform structure 230 and the first electrically conductive semiconductor layer 208 of each of the LED wafers 228c is completed. As shown in FIG. 12B, the isolation trench 216 of each LED wafer 228c is interposed between its second electrical contact hole 266 and the first electrical contact hole 264 of the adjacent LED wafer 228c.

As shown in FIG. 12B, in each of the light-emitting diode wafers 228c, the bottom 270 of the first electrical contact hole 264 exposes a portion of the first electrical semiconductor layer 208 and is located in the first electrical semiconductor layer 208. . The bottom 280 of the second electrical contact hole 266 exposes a portion of the transparent conductive layer 224. In addition, the current blocking layer 222 is between the second electrical semiconductor layer 212 of the epitaxial layer 214 and the bottom 280 of the second electrical contact hole 266. The transparent conductive layer 224 covers the current blocking layer 222 and is between the second electrical semiconductor layer 212 of the epitaxial layer 214 and the dielectric layer 262. In another embodiment, the LED wafer 228c has no transparent conductive layer, and the bottom 280 of the second electrical contact hole 266 exposes a portion of the second electrical semiconductor layer 212.

Next, the residual photoresist layer 298 is removed to expose the dielectric layer 262, the first electrical contact hole 264 and the second electrical contact hole 266. The insulating material layer is formed on the sidewalls and the bottom portion 270 of the first electrical contact hole 264 and the sidewalls and the bottom portion 280 of the second electrical contact hole 266 by using, for example, plasma-assisted chemical deposition. The material of the insulating material layer may be, for example, hafnium oxide or tantalum nitride. Then, the upper surface 278 of the dielectric layer 262, the bottom 270 of the first electrical contact hole 264, and the bottom 280 of the second electrical contact hole 266 may be removed by an anisotropic etching method such as dry etching. The insulating material layer is formed on the sidewalls of the first electrical contact hole 264 and the sidewalls of the second electrical contact hole 266 to form insulating liners 268 and 282, respectively, as shown in FIG. 12C.

Then, a conductive layer is formed on the upper surface 278 of the dielectric layer 262 by using, for example, a deposition method, and is filled in the first electrical contact hole 264 and the second electrical contact hole 266. Referring to FIG. 12D and FIG. 2 simultaneously, a portion of the metal layer is removed by, for example, lithography and etching to form a plurality of interconnect layers 226, a first electrical electrode pad 238, and a second electrical electrode. Pad 236. Portions of each of the interconnect layers 226 that are filled in the first electrical contact holes 264 and the second electrical contact holes 266 may also be referred to as contact plugs 272 and 274, respectively.

Next, an insulating reflective layer 220 is formed over the inner wiring layer 226 and the upper surface 278 of the dielectric layer 262 by, for example, deposition. Referring again to FIG. 2, the insulating reflective layer 220 can be defined by, for example, a patterning technique to form at least through holes 256, 254, and 260 in the insulating reflective layer 220. The three through holes 256, 254, and 260 respectively expose a portion of the first electrical electrode pad 238, a portion of the second electrical electrode pad 236, and a portion of the test pad 258.

Next, as shown in FIG. 2 and FIG. 12D, the first electrical bonding pads 252 and the second electrical bonding pads 232 separated from each other are formed on the insulating reflective layer 220, and the tandem light emitting diode structure 200a is completed. . The first electrical bond pad 252 and the second electrical bond pad 232 are separated from each other. In addition, the first electrical bonding pads 252 and the second electrical bonding pads 232 can respectively pass through the through holes 256 and 254, and respectively expose the first electrical electrode pads 238 and the second The electrical electrode pads 236 are in contact and electrically coupled.

Please refer to FIG. 13A to FIG. 13C, which are cross-sectional views showing a process of a light emitting diode structure according to still another embodiment of the present invention. In the present embodiment, the structure shown in FIG. 11F can be completed according to the process steps of the above embodiment. The photoresist layer 300 is formed on the transparent conductive layer 224 by, for example, a coating method. The photoresist layer 300 is patterned using, for example, a lithography process. When the photoresist layer 300 is defined, a portion of the photoresist layer 300 is removed, and a portion of the transparent conductive layer 224 is exposed to define a predetermined position and shape of the recess 276 in the photoresist layer 300. Then, as shown in FIG. 13A, the exposed portion of the transparent conductive layer 224 and a portion of the second electrical semiconductor below it are removed by, for example, etching, and using the patterned photoresist layer 300 as an etching mask. The layer 212, a portion of the active layer 210 and a portion of the first electrical semiconductor layer 208 form a recess 276 in the epitaxial layer 214. The bottom 284 of the recess 276 exposes a portion of the first electrically conductive semiconductor layer 208. As such, the definition of the epitaxial layer 214, the land structure 230, and the exposed portion 234 of the first electrically conductive semiconductor layer 208 of each of the light emitting diode wafers 228d is completed.

Next, the residual photoresist layer 300 is removed to expose the transparent conductive layer 224 and the recess 276. The layer of dielectric material is overlaid on the transparent conductive layer 224 and filled into the recess 276 by, for example, plasma-assisted chemical deposition or spin coating. The dielectric material is an insulating material such as hafnium oxide and tantalum nitride. After the dielectric material layer is formed, the dielectric material layer may be planarized by, for example, chemical mechanical polishing according to actual process requirements, to obtain a substantially uniform surface dielectric material layer.

Then, as shown in FIG. 13B, a portion of the dielectric material layer is removed by, for example, lithography and etching, for example, inductively coupled plasma etching, to form a plurality of first electrical contact holes 264 and a plurality of Two electrical contact holes 266 and a plurality of dielectric layers 262 are formed. Each of the LED chips 228c includes a dielectric layer 262, and the first electrical contact holes 264 and the second electrical contact holes 266 extend through the dielectric layer 262.

As shown in FIG. 13B, in each of the light-emitting diode wafers 228d, one of the dielectric layers 262 partially covers the sidewalls of the recess 276, and the bottom 270 of the first electrical contact hole 264 exposes the recess 276. Part of bottom 284. The bottom 280 of the second electrical contact hole 266 exposes a portion of the transparent conductive layer 224. In the present embodiment, since the dielectric layer 262 extends over the sidewall of the recess 276, the LED structure 200b (please refer to FIG. 13C first) does not need to additionally provide an insulating liner to the first electrical contact hole 264. The inner wiring layer 226 is electrically insulated from the epitaxial layer 214 and the transparent conductive layer 224 exposed by the sidewalls of the recess 276.

Then, a conductive layer is formed on the upper surface 278 of the dielectric layer 262 by using, for example, a deposition method, and is filled in the first electrical contact hole 264 and the second electrical contact hole 266. Reusing, for example, lithography and etching, removing portions of the metal layer to form a plurality of interconnect layers 226, a first electrical electrode pad and a second electrical electrode pad (as shown in FIG. 2) The electrode pad 238 and the second electrode pad 236) complete the tandem LED structure 200b as shown in FIG. 13C.

As shown in FIG. 13C, the interconnect layer 226 is first electrically contacted from one of the two adjacent light emitting diode wafers 228d. The exposed portion of the first electrical semiconductor layer 208 in the hole 264 extends through the upper surface 278 of the dielectric layer 262 over the isolation trench 216 of the adjacent light-emitting diode wafer 228d and fills the adjacent light-emitting diode The second electrical contact hole 266 of the bulk wafer 228d is in contact with the exposed portion of the transparent conductive layer 224 of the adjacent light emitting diode wafer 228d. Therefore, the interconnect layer 226 can be electrically connected to the adjacent two LED chips 228d.

Next, an insulating reflective layer 220 is formed over the inner wiring layer 226 and the upper surface 278 of the dielectric layer 262 by, for example, deposition. Referring again to FIG. 2, the insulating reflective layer 220 can be defined by, for example, a patterning technique to form at least through holes 256, 254, and 260 in the insulating reflective layer 220. The three through holes 256, 254, and 260 respectively expose a portion of the first electrical electrode pad 238, a portion of the second electrical electrode pad 236, and a portion of the test pad 258.

Next, as shown in FIG. 2 and FIG. 13C, the first electrical bonding pads 252 and the second electrical bonding pads 232 separated from each other are formed on the insulating reflective layer 220, respectively, and the series LED structure is completed. 200b. The first electrical bond pad 252 and the second electrical bond pad 232 are separated from each other. In addition, the first electrical bonding pads 252 and the second electrical bonding pads 232 can respectively contact the exposed first electrical electrode pads 238 and the second electrical electrode pads 236 via the through holes 256 and 254, respectively. Sexual engagement.

It can be seen from the above embodiments that one of the advantages of the present invention is that since the light emitting diode structure of the present invention is formed by connecting a plurality of light emitting diode chips in series, it has the advantages of dense arrangement and high luminous efficiency.

It can be seen from the above embodiments that another advantage of the present invention is that The light-emitting diode structure of the present invention comprises an insulating reflective layer covering the inner wiring of each of the light-emitting diode chips, the platform structure and the exposed portion of the first electrical semiconductor layer, and thus can be packaged by flip chip method. Achieve high heat dissipation, free wire and low thermal resistance.

It can be seen from the above embodiments that another advantage of the present invention is that since the interconnect layer is exposed from the exposed portion of the first electrical semiconductor layer of one of the adjacent light-emitting diode chips, directly via the platform structure of the other. The side surface extends to the structure of the platform, so that the aspect ratio of the interconnect layer can be greatly reduced, and the step coverage capability of the interconnect layer deposition can be effectively improved, thereby avoiding disconnection during the deposition of the interconnect layer.

It can be seen from the above embodiments that another advantage of the present invention is that since the platform structure of the LED substrate can have a trapezoidal inclined side surface, the step coverage capability of the interconnect layer can be further improved, and the interconnect layer can be more effectively solved. The problem of disconnection.

According to the above embodiments, another advantage of the present invention is that the light-emitting region of the LED chip and the first electrical semiconductor layer of the adjacent LED chip are separated by an isolation trench, and the isolation trench Only the insulating layer is filled without conductive material. In addition, an additional current blocking layer may be additionally disposed on the opening of the isolation trench to be electrically isolated. Therefore, even if the deposition of the insulating layer in the isolation trench is discontinuous, there is no problem of short circuit in the light-emitting region in the case where there is no conductive material in the isolation trench.

It can be seen from the above embodiments that another advantage of the present invention is that the interconnect layer can extend directly from the contact hole in the dielectric layer above one of the adjacent light-emitting diode wafers via the dielectric layer to the other. Dielectric above Contact hole in the layer. Therefore, the conductive material may not need to be filled in the isolation trench between the adjacent two light-emitting diode wafers, thereby solving the problem of disconnection of the interconnect layer.

It can be seen from the above embodiments that another advantage of the present invention is that the problem of short circuit and disconnection can be effectively solved, so that the production yield of the series LED structure can be greatly improved, and the manufacturing cost can be reduced.

It can be seen from the above embodiments that another advantage of the present invention is that the problem of short circuit and disconnection can be effectively solved, so that it is possible to smoothly confirm the light emission by detecting the forward current without relying on the detection method of the reverse leakage current. Short circuit defects in the polar body structure.

While the present invention has been described above by way of example, it is not intended to be construed as a limitation of the scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

200‧‧‧Lighting diode structure

202‧‧‧Insert substrate

204‧‧‧ surface

206‧‧‧Undoped semiconductor layer

208‧‧‧First electrical semiconductor layer

210‧‧‧Active layer

212‧‧‧Second electrical semiconductor layer

214‧‧‧ epitaxial layer

216‧‧‧Isolation Ditch

218‧‧‧Insulation

220‧‧‧Insulated reflective layer

222‧‧‧ Current Barrier

224‧‧‧Transparent conductive layer

226‧‧‧Interconnection layer

228‧‧‧Light Emitter Wafer

230‧‧‧ platform structure

232‧‧‧Second electrical bonding pads

234‧‧‧Exposed part

246‧‧‧ side

248‧‧‧ openings

Θ‧‧‧ angle

Claims (18)

A light emitting diode structure comprising: an insulating substrate; a plurality of light emitting diode chips, wherein each of the light emitting diode chips comprises an epitaxial layer, and the epitaxial layer comprises sequentially stacked on the insulating substrate a first electrical semiconductor layer, an active layer and a second electrical semiconductor layer on a surface, and each of the light emitting diode chips comprises a substrate structure adjacent to a first conductive semiconductor layer And a first isolation trench, the first isolation trench is disposed in the platform structure; a plurality of interconnect layers are respectively connected to adjacent ones of the light emitting diode chips; a first electrical electrode pad and a second electrical electrode pad is respectively disposed on the first one and the second one of the light emitting diode chips, and the exposed portion of the first electrical semiconductor layer and the second portion respectively of the first one The second electrical semiconductor layer is electrically connected; an insulating reflective layer covering the interconnect layers, the platform structures, the first electrical electrode pads and the second electrical electrode pads, wherein the The insulating reflective layer has at least one first through hole The at least one second through hole exposes a portion of the first electrical electrode pad and the second electrical electrode pad respectively; a first electrical bonding pad is located on the portion of the insulating reflective layer, and passes through the at least one The first electrical electrode pad is electrically connected to the first electrical electrode pad; and a second electrical bonding pad is disposed on the insulating reflective layer of the other portion and separated from the first electrical bonding pad, and passes through the at least a second through hole is electrically connected to the second electrical electrode pad. The light emitting diode structure of claim 1, wherein each of the light emitting diode chips further comprises an insulating layer filled in the first isolation trench to seal the first isolation trench An opening. The light emitting diode structure of claim 1, wherein each of the light emitting diode chips further comprises a current blocking layer interposed between the interconnect layer and the insulating layer on the platform structure. The light emitting diode structure of claim 3, wherein each of the light emitting diode chips further comprises a transparent conductive layer extending over the second electrical semiconductor layer of the platform structure, and the platform structure is Between the inner wiring layer and the current blocking layer. The light emitting diode structure of claim 1, wherein each of the light emitting diode chips further comprises a dielectric layer disposed on the epitaxial layer, and each of the light emitting diode chips is provided with a first An electrical contact hole and a second electrical contact hole extend through the dielectric layer, the first isolation trench being interposed between the second electrical contact hole of the LED chip and the adjacent LED chip Between the first electrical contact holes, each of the interconnect layers extends from the second electrical contact hole of each of the light emitting diode chips to the adjacent via the first isolation trench The first electrical contact hole of the light emitting diode chip and the insulating reflective layer further cover the dielectric layer. The light emitting diode structure according to claim 5, wherein Each of the light emitting diode chips further includes a transparent conductive layer interposed between the dielectric layer and the epitaxial layer; a bottom portion of the first electrical contact hole exposes the exposed portion of the first electrical semiconductor layer And the bottom of one of the second electrical contact holes exposes the transparent conductive layer. The light emitting diode structure of claim 6, wherein each of the light emitting diode chips further comprises at least one current blocking layer between the bottom of the second electrical contact hole and the epitaxial layer . The light emitting diode structure of claim 5, wherein in each of the light emitting diode wafers, the epitaxial layer has a recess, and one of the recesses exposes the first electrical semiconductor layer And exposing a portion, the first electrical contact hole exposing a portion of the bottom of the recess, and the dielectric layer overlying a sidewall of the recess. The light-emitting diode structure of claim 5, wherein each of the light-emitting diode wafers further comprises at least one insulating liner covering one of the sidewalls of the first electrical contact hole. A method for fabricating a light-emitting diode structure, comprising: providing an insulating substrate; forming an epitaxial structure, wherein the epitaxial structure comprises a first electrical semiconductor layer, one of which is sequentially stacked on one surface of the insulating substrate, An active layer and a second electrical semiconductor layer; forming a plurality of first isolation trenches and a plurality of second isolation trenches In the epitaxial structure, a plurality of epitaxial layers of the plurality of light emitting diode chips are defined, wherein the first isolation trenches are adjacent to the second isolation trenches respectively; and the second electrical semiconductor layer is removed And a portion of the active layer to define a planar structure of each of the light emitting diode chips and a first electrical semiconductor layer exposed portion, wherein each of the light emitting diode chips includes the first isolation One of the trenches, and the one of the first isolation trenches is disposed in the platform structure; forming a plurality of interconnect layers, a first electrical electrode pad and a second electrical electrode pad, wherein the inner The wiring layer is respectively connected to the adjacent ones of the LED chips, and the first electrical electrode pad and the second electrical electrode pad are respectively disposed on the first one of the light emitting diode chips and the first In the second, the first electrical electrode pad and the second electrical electrode pad are respectively exposed to the first electrical semiconductor layer of the first one and the second electrical semiconductor layer of the second Electrically connecting; forming an insulating reflective layer covering the interconnect layers, On the platform structure, the first electrical electrode pad and the second electrical electrode pad, wherein the insulating reflective layer has at least one first through hole and at least one second through hole respectively exposing a portion of the first electrical electrode a pad and a portion of the second electrical electrode pad; forming a first electrical bond pad on the portion of the insulating reflective layer, wherein the first electrical bond pad passes through the at least one first through hole and the first The electrical electrode pads are electrically connected; and a second electrical bonding pad is formed on the insulating reflective layer of the other portion, wherein the second electrical bonding pad is separated from the first electrical bonding pad, and the second electrical The bonding pad is electrically connected to the second electrical electrode pad through the at least one second through hole. The method for fabricating the LED structure of claim 10, after forming the first isolation trench and the second isolation trench in the epitaxial structure, further comprising forming a plurality of dielectric layers respectively covering The light-emitting diodes have a first electrical contact hole and a second electrical contact hole extending through the dielectric layer, and the first isolation trench is interposed between the light-emitting diodes The second electrical contact hole of the polar body wafer is between the first electrical contact hole of the adjacent light emitting diode chip. The method for fabricating the LED structure of claim 11, before forming the dielectric layers, further comprising: forming a plurality of transparent conductive layers between the dielectric layers and the epitaxial layers And forming a plurality of current blocking layers respectively between the epitaxial layers and the transparent conductive layers, wherein in each of the light emitting diode wafers, one of the first electrical contact holes is exposed at the bottom The first electrically conductive layer, and the bottom of the second electrical contact hole is exposed to the bottom of the transparent conductive layer, and the positions of the current blocking layers are correspondingly disposed on the second electrical contact holes. Some bottom down. A light emitting diode structure comprising: an insulating substrate; a plurality of light emitting diode chips, wherein each of the light emitting diode chips comprises an epitaxial layer, and the epitaxial layer comprises sequentially stacked on the insulating substrate a first electrical semiconductor layer, an active layer and a second electrical semiconductor layer on a surface, and each of the light emitting diode chips comprises a substrate structure adjacent to a first conductive semiconductor layer And a first isolation trench, the first An isolation trench is disposed in the platform structure; a plurality of interconnect layers are respectively connected to adjacent ones of the LED chips; a first electrical electrode pad and a second electrical electrode pad are respectively disposed on The first one of the light emitting diode chips and the second one are electrically connected to the first electrical semiconductor layer exposed portion of the first one and the second electrical semiconductor layer of the second one An insulating layer covering the inner wiring layers, the platform structures, the first electrical electrode pads and the second electrical electrode pads, wherein the insulating layer has at least one first through hole and at least a second through hole respectively exposes a portion of the first electrical electrode pad and the second electrical electrode pad; a first electrical bonding pad is located on a portion of the insulating layer and passes through the at least one first pass The second electrical pad is electrically connected to the first electrical electrode pad; and a second electrical bonding pad is disposed on the insulating layer of the other portion and separated from the first electrical bonding pad, and passes through the at least one second The through hole is electrically connected to the second electrical electrode pad. The light emitting diode structure of claim 13, wherein the insulating layer is a Bragg mirror (DBR). The light-emitting diode structure of claim 13 further comprising an insulating reflective layer, wherein each of the light-emitting diode chips further comprises a dielectric layer disposed on the epitaxial layer, and each of the light-emitting layers The diode chip is provided with a first electrical contact hole and a second electrical contact hole extending through the dielectric layer, and the first isolation trench is adjacent to the second electrical contact hole of the LED substrate. Light-emitting diode Between the first electrical contact holes of the wafer, the insulating reflective layer covers one side wall of the first electrical contact hole of each of the light emitting diode chips, and one side wall of the second electrical contact hole, And an upper surface of the dielectric layer, and each of the interconnect layers extending from the second electrical contact hole of each of the light emitting diode chips to the phase via the first isolation trench Adjacent to the first electrical contact hole of the LED chip. The light-emitting diode structure of claim 13 further comprising an insulating reflective layer, wherein each of the light-emitting diode chips further comprises a dielectric layer disposed on the epitaxial layer, and each of the light-emitting layers The diode chip is provided with a first electrical contact hole and a second electrical contact hole extending through the dielectric layer, and the first isolation trench is adjacent to the second electrical contact hole of the LED substrate. Between the first electrical contact holes of the LED chip, the epitaxial layer has a recess, and one of the bottom portions exposes the exposed portion of the first electrical semiconductor layer, the first electrical property The contact hole exposes a portion of the bottom of the recess, the insulating reflective layer covering a sidewall of each of the recesses, and an upper surface of each of the epitaxial layers, and each of the interconnects The wire layer extends from the second electrical contact hole of each of the light emitting diode chips through the first isolation trench to the first electrical contact hole of the adjacent light emitting diode chip. The light emitting diode structure of claim 13, further comprising an insulating reflective layer, wherein each of the light emitting diode chips further comprises a dielectric layer disposed on the epitaxial layer a first electrical contact hole and a second electrical contact hole are formed in the dielectric layer, and the first isolation trench is interposed between the light emitting diode chip. Between the second electrical contact hole and the first electrical contact hole of the adjacent LED chip, the epitaxial layer has a recess, and one of the recess exposes the first electrical semiconductor a portion of the exposed portion of the layer exposing a portion of the bottom portion of the recess, and the dielectric layer overlying a sidewall of the recess, the insulating reflective layer covering each of the epitaxial layers And on the upper surface, and each of the interconnect layers extends from the second electrical contact hole of each of the light emitting diode chips to the adjacent one of the light through the first isolation trench The first electrical contact hole of the polar body wafer. The light-emitting diode structure of claim 13 further comprising an insulating reflective layer, wherein each of the light-emitting diode chips further comprises a dielectric layer disposed on the epitaxial layer, and each of the light-emitting layers The diode chip is provided with a first electrical contact hole and a second electrical contact hole extending through the dielectric layer, and the first isolation trench is adjacent to the second electrical contact hole of the LED substrate. Between the first electrical contact holes of the LED chip, the epitaxial layer has a recess, and one of the bottom portions exposes the exposed portion of the first electrical semiconductor layer, the first electrical property The contact hole exposes a portion of the bottom of the recess, and the dielectric layer covers a sidewall of the recess, the insulating reflective layer covering an upper surface of each of the dielectric layers, and each The interconnect layers are formed by each of the plurality of light emitting diode chips The two electrical contact holes extend through the first isolation trench to the first electrical contact hole of the adjacent LED chip.