TW201438320A - Method for making vertical nitride-based light emitting diode - Google Patents

Method for making vertical nitride-based light emitting diode Download PDF

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TW201438320A
TW201438320A TW102111206A TW102111206A TW201438320A TW 201438320 A TW201438320 A TW 201438320A TW 102111206 A TW102111206 A TW 102111206A TW 102111206 A TW102111206 A TW 102111206A TW 201438320 A TW201438320 A TW 201438320A
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buffer layer
semiconductor
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emitting diode
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TW102111206A
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TWI517475B (en
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Yu-Zung Chiou
Chun-Kai Wang
Kuan-Wei Lin
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Univ Southern Taiwan Sci & Tec
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Abstract

The present invention relates to a method for making a vertical nitride-based light emitting diode. It essentially focuses on a buffer layer of AlN, GaN or InN being deposited on a substrate by a spattering technology, and then a semiconductor layer can be directly grown on the buffer layer without advance growth of any undoped conductor layers thereon. As a result, this invention has substantial efficacy in reducing time for epitaxial growth, simplifying the process of manufacture, promoting stability and reliability of components.

Description

垂直式氮化物發光二極體的製造方法Method for manufacturing vertical nitride light emitting diode

  本發明係有關於一種垂直式氮化物發光二極體的製造方法,尤其是指一種可以減少磊晶成長的時間,還可以減少製作的複雜性及提升元件穩定性之垂直式氮化物發光二極體的製造方法者。The invention relates to a method for manufacturing a vertical nitride light-emitting diode, in particular to a vertical nitride light-emitting diode which can reduce the time of epitaxial growth, reduce the complexity of fabrication and improve the stability of components. The method of manufacturing the body.

  按,Ⅲ-Ⅴ族發光二極體是由Ⅲ族化學元素和V族化學元素結合而成,其中,Ⅲ族化學元素為:鋁(Al)、鎵(Ga)、銦(In),V族化學元素為:為氮(N)、磷(P)、砷(As);當在Ⅲ-Ⅴ族的發光二極體兩電極間施加電壓,便能令電子與電洞注入於主動層中並相互復合,而復合時剩下的能量即以光的形式激發釋出,而達成發光效果。According to the group III-V light-emitting diodes, the group III chemical elements and the group V chemical elements are combined, wherein the group III chemical elements are: aluminum (Al), gallium (Ga), indium (In), V group The chemical elements are: nitrogen (N), phosphorus (P), arsenic (As); when a voltage is applied between the two electrodes of the III-V group, electrons and holes can be injected into the active layer. Recombining with each other, and the remaining energy in the recombination is excited and released in the form of light to achieve a luminous effect.

  請參看第一圖所示,即係揭示傳統的Ⅲ-Ⅴ族發光二極體中的氮化鎵發光二極體垂直元件的製造流程。係先於一暫時基板(11)上,利用有機金屬化學氣相沉積法(metal organic chemical -vapor deposition,MOCVD)依序長出緩衝層(12)、未參雜半導體層(13)、n型半導體層(14)、主動層〔多層量子井〕(15)、p型半導體層(16),接著再於p型半導體層(16)表面製作反射鏡層(17),反射鏡層(17)上再製作貼合層(18A),如此形成第一半導體塊材(A)。另外,於一永久基板(19)上製作另一貼合層(18B),以形成第二半導體塊材(B)。接續,將第一半導體塊材(A)之貼合層(18A)與第二半導體塊材(B)之貼合層(18B)彼此對應貼合,將兩個半導體塊材貼合在一起。然後利用基板剝離方法〔如雷射剝離或研磨蝕刻剝離法〕,並以緩衝層(12)作為該暫時基板(11)分離半導體的犧牲層,最後利用乾式蝕刻法將未參雜半導體層(13)移除,並於n型半導體層(14)表面製作n型電極(10),且以永久基板(19)作為p型電極。Please refer to the first figure to reveal the manufacturing process of the gallium nitride light-emitting diode vertical component in the conventional III-V light-emitting diode. The buffer layer (12), the undoped semiconductor layer (13), and the n-type are sequentially grown on a temporary substrate (11) by metal organic chemical-vapor deposition (MOCVD). a semiconductor layer (14), an active layer [multilayer quantum well] (15), a p-type semiconductor layer (16), and then a mirror layer (17), a mirror layer (17) on the surface of the p-type semiconductor layer (16) A bonding layer (18A) is formed thereon to form the first semiconductor bulk (A). In addition, another bonding layer (18B) is formed on a permanent substrate (19) to form a second semiconductor bulk (B). Subsequently, the bonding layer (18A) of the first semiconductor bulk material (A) and the bonding layer (18B) of the second semiconductor bulk material (B) are bonded to each other, and the two semiconductor bulk materials are bonded together. Then, a substrate stripping method (such as laser stripping or polishing etching) is used, and a buffer layer (12) is used as the sacrificial layer for separating the semiconductor from the temporary substrate (11), and finally the undoped semiconductor layer is used by dry etching (13). The n-type electrode (10) is removed on the surface of the n-type semiconductor layer (14), and the permanent substrate (19) is used as a p-type electrode.

  由於在成長垂直式之Ⅲ-Ⅴ族發光二極體時,於成長完緩衝層之後,均會再成長幾個μm厚度的未摻雜半導體層,以改善緩衝層的結晶性及平坦度不佳的問題。Since the vertical type III-V light-emitting diode is grown, after the buffer layer is grown, an undoped semiconductor layer having a thickness of several μm is further grown to improve the crystallinity and flatness of the buffer layer. The problem.

  然而,正因為傳統之成長技術必須在完成成長該緩衝層之後,再成長未摻雜半導體層,才能接著成長n型半導體層,以致增加Ⅲ-Ⅴ族發光二極體的製造流程,而繁雜的製造流程也可能進一步導致元件穩定性不佳之問題。However, it is precisely because the conventional growth technology has to grow the undoped semiconductor layer after the growth of the buffer layer, and then the n-type semiconductor layer can be grown, so that the manufacturing process of the III-V group LED is increased, and the complicated process is complicated. The manufacturing process may also further cause problems with poor component stability.

  本發明之主要目的,係提供一種垂直式氮化物發光二極體的製造方法,主要係藉由能在以氮化鋁、氮化銦或氮化鎵等材料系列其中之一的薄膜所形成之緩衝層上直接成長半導體層,而不需先成長未摻雜半導體層後再成長半導體層,以藉此減少磊晶成長的時間,並能因此進一步減少氮化物發光二極體製作的複雜性,同時提升垂直式氮化物發光二極體的元件穩定性。The main object of the present invention is to provide a method for manufacturing a vertical nitride light-emitting diode, which is mainly formed by a film which can be one of a series of materials such as aluminum nitride, indium nitride or gallium nitride. The semiconductor layer is directly grown on the buffer layer without first growing the undoped semiconductor layer and then growing the semiconductor layer, thereby reducing the time for epitaxial growth, and thereby further reducing the complexity of the fabrication of the nitride light-emitting diode. At the same time, the element stability of the vertical nitride light-emitting diode is improved.

  上述本發明垂直式氮化物發光二極體的製造方法的主要目的與功效,是由以下之具體技術手段所達成:The main purpose and effect of the above-described method for manufacturing a vertical nitride light-emitting diode of the present invention are achieved by the following specific technical means:

  一種垂直式氮化物發光二極體的製造方法,包括以下之步驟:A method for manufacturing a vertical nitride light emitting diode includes the following steps:

步驟一:先於暫時基板上,依序成長出非晶性緩衝層與多晶或單晶性緩衝層;Step 1: preliminarily growing an amorphous buffer layer and a polycrystalline or single crystal buffer layer on the temporary substrate;

步驟二:然後再用有機金屬化學氣相沉積法(metal organic chemical -vapor deposition,MOCVD)依序成長第一半導體層、主動層(多層量子井)、第二半導體層;Step 2: sequentially growing a first semiconductor layer, an active layer (multilayer quantum well), and a second semiconductor layer by metal organic chemical vapor deposition (MOCVD);

步驟三:接著於第二半導體層表面製作反射鏡層;Step 3: forming a mirror layer on the surface of the second semiconductor layer;

步驟四:再於反射鏡層表面製作貼合層,以形成第一半導體塊材;Step 4: further forming a bonding layer on the surface of the mirror layer to form a first semiconductor block;

步驟五:於一永久基板上製作貼合層,以形成第二半導體塊材;Step 5: forming a bonding layer on a permanent substrate to form a second semiconductor block;

步驟六:將第一半導體塊材之貼合層與第二半導體塊材之貼合層進行貼合製程,使第一、第二半導體塊材貼合在一起;Step 6: performing a bonding process on the bonding layer of the first semiconductor bulk material and the bonding layer of the second semiconductor bulk material, so that the first and second semiconductor blocks are bonded together;

步驟七:利用基板剝離方法,且以非晶性緩衝層為犧牲層,將暫時基板分離;Step 7: separating the temporary substrate by using a substrate stripping method and using the amorphous buffer layer as a sacrificial layer;

步驟八:最後於第一半導體層表面製作第一電極,該永久基板為第二電極。Step 8: Finally, a first electrode is formed on the surface of the first semiconductor layer, and the permanent substrate is a second electrode.

  如上所述垂直式氮化物發光二極體的製造方法,其中,基板剝離方法係為雷射剝離或研磨蝕刻剝離法。The method for producing a vertical nitride light-emitting diode as described above, wherein the substrate peeling method is a laser peeling or a polishing etching peeling method.

  如上所述之垂直式氮化物發光二極體的製造方法,其中,該永久基板之材質係選自藍寶石基板、半導體基板或金屬基板其中之一。The method for manufacturing a vertical nitride light-emitting diode according to the above aspect, wherein the material of the permanent substrate is one selected from the group consisting of a sapphire substrate, a semiconductor substrate, and a metal substrate.

  如上所述之垂直式氮化物發光二極體的製造方法,其中,該半導體基板為矽半導體基板、碳化矽半導體基板、砷化鎵半導體基板或氧化鋅半導體基板其中之一。The method for producing a vertical nitride light-emitting diode according to the above aspect, wherein the semiconductor substrate is one of a germanium semiconductor substrate, a tantalum carbide semiconductor substrate, a gallium arsenide semiconductor substrate, or a zinc oxide semiconductor substrate.

  如上所述之垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與該多晶或單晶性緩衝層成長於該暫時基板上之技術是採用濺鍍技術、單元子層沉積系統(ALD)或分子束磊晶系統(MBE)其中之一。The method for manufacturing a vertical nitride light-emitting diode as described above, wherein the technique of growing the amorphous buffer layer and the polycrystalline or single crystal buffer layer on the temporary substrate is a sputtering technique or a unit sublayer One of a deposition system (ALD) or a molecular beam epitaxy system (MBE).

  如上所述之垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與該多晶或單晶性緩衝層之厚度為幾個nm至幾千個nm。The method for producing a vertical nitride light-emitting diode as described above, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer have a thickness of several nm to several thousands nm.

  如上所述之氮化物發光二極體,其中,該非晶性緩衝層與該多晶或單晶性緩衝層成長溫度範圍為300℃~1000℃。The nitride light-emitting diode according to the above aspect, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer have a growth temperature in the range of 300 ° C to 1000 ° C.

  如上所述之垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與該多晶或單晶性緩衝層成長溫度為固定溫度或漸變溫度其中之一。The method for producing a vertical nitride light-emitting diode according to the above aspect, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer have a growth temperature of one of a fixed temperature or a gradual temperature.

  如上所述之垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與該多晶或單晶性緩衝層呈相互交替堆疊。The method for producing a vertical nitride light-emitting diode as described above, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer are alternately stacked one on another.

  如上所述之垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與該多晶或單晶性緩衝層係由氮化鋁、氮化銦或氮化鎵等材料系列其中之一的薄膜所形成。The method for manufacturing a vertical nitride light-emitting diode as described above, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer are made of a material series such as aluminum nitride, indium nitride or gallium nitride. One of the films is formed.

<本發明><present invention>

(2)...暫時基板(2). . . Temporary substrate

(3A)...非晶性緩衝層(3A). . . Amorphous buffer layer

(3B)...多晶或單晶性緩衝層(3B). . . Polycrystalline or single crystal buffer layer

(4)...第一半導體層(4). . . First semiconductor layer

(40)...第一電極(40). . . First electrode

(5)...主動層(多層量子井)(5). . . Active layer (multilayer quantum well)

(6)...第二半導體層(6). . . Second semiconductor layer

(7)...反射鏡層(7). . . Mirror layer

(8A)...貼合層(8A). . . Fit layer

(C)...第一半導體塊材(C). . . First semiconductor block

(9)...永久基板(9). . . Permanent substrate

(8B)...貼合層(8B). . . Fit layer

(D)...第二半導體塊材(D). . . Second semiconductor block

<現有><existing>

(11)...暫時基板(11). . . Temporary substrate

(12)...緩衝層(12). . . The buffer layer

(13)...未參雜半導體層(13). . . Undoped semiconductor layer

(14)...n型半導體層(14). . . N-type semiconductor layer

(15)...主動層〔多層量子井〕(15). . . Active layer

(16)...p型半導體層(16). . . P-type semiconductor layer

(17)...反射鏡層(17). . . Mirror layer

(18A)...貼合層(18A). . . Fit layer

(A)...第一半導體塊材(A). . . First semiconductor block

(19)...永久基板(19). . . Permanent substrate

(18B)...貼合層(18B). . . Fit layer

(B)...第二半導體塊材(B). . . Second semiconductor block

(10)...n型電極(10). . . N-type electrode

第一圖:現有垂直型氮化物發光二極體的製造步驟流程圖First: Flow chart of manufacturing steps of existing vertical nitride light-emitting diodes

第二圖:本發明垂直型氮化物發光二極體的製造步驟流程圖Second: Flow chart of manufacturing steps of the vertical nitride light-emitting diode of the present invention

  為令本發明所運用之技術內容、發明目的及其達成之功效有更完整且清楚的揭露,茲於下詳細說明之,並請一併參閱所揭之圖式及圖號:For a more complete and clear disclosure of the technical content, the purpose of the invention and the effects thereof achieved by the present invention, it is explained in detail below, and please refer to the drawings and drawings:

  請參看第二圖所示,其係揭示本發明之垂直式氮化物發光二極體的製造方法的步驟流程圖。本發明之垂直式氮化物發光二極體的製造方法,包括以下之步驟:Referring to the second figure, it is a flow chart showing the steps of the method for fabricating the vertical nitride light-emitting diode of the present invention. The method for manufacturing a vertical nitride light-emitting diode of the present invention comprises the following steps:

  步驟一:先於暫時基板(2)上,採用濺鍍技術、單元子層沉積系統(ALD)或分子束磊晶系統(MBE)其中之一,以成長溫度範圍為300℃~1000℃,依序成長出厚度為幾個nm至幾千個nm的非晶性緩衝層(3A)與多晶或單晶性緩衝層(3B);此外,較佳為該非晶性緩衝層(3A)與該多晶或單晶性緩衝層(3B)成長溫度為固定溫度或漸變溫度其中之一;又,該非晶性緩衝層(3A)與該多晶或單晶性緩衝層(3B)係進一步呈相互交替堆疊設置;且該非晶性緩衝層(3A)與該多晶或單晶性緩衝層(3B)係由氮化鋁、氮化銦或氮化鎵等材料系列其中之一的薄膜所形成;Step 1: Prior to the temporary substrate (2), one of sputtering, OLED or molecular beam epitaxy (MBE) is used, and the growth temperature ranges from 300 ° C to 1000 ° C. Forming an amorphous buffer layer (3A) having a thickness of several nm to several thousand nm and a polycrystalline or single crystal buffer layer (3B); more preferably, the amorphous buffer layer (3A) and the The growth temperature of the polycrystalline or single crystal buffer layer (3B) is one of a fixed temperature or a gradual temperature; further, the amorphous buffer layer (3A) and the polycrystalline or single crystal buffer layer (3B) further interact with each other. Alternating stacking; and the amorphous buffer layer (3A) and the polycrystalline or single crystal buffer layer (3B) are formed of a film of one of a series of materials such as aluminum nitride, indium nitride or gallium nitride;

  步驟二:然後再用有機金屬化學氣相沉積法(metal organic chemical -vapor deposition,MOCVD)依序成長第一半導體層(4)、主動層(多層量子井)(5)、第二半導體層(6);Step 2: Then, the first semiconductor layer (4), the active layer (multilayer quantum well) (5), and the second semiconductor layer are sequentially grown by metal organic chemical vapor deposition (MOCVD). 6);

  步驟三:接著於第二半導體層(6)表面製作反射鏡層(7);Step three: then forming a mirror layer (7) on the surface of the second semiconductor layer (6);

  步驟四:再於反射鏡層(7)表面製作貼合層(8A),以形成第一半導體塊材(C);Step 4: further forming a bonding layer (8A) on the surface of the mirror layer (7) to form a first semiconductor bulk (C);

  步驟五:於一永久基板(9)上製作貼合層(8B),以形成第二半導體塊材(D);該永久基板(9)之材質係選自藍寶石基板、半導體基板或金屬基板其中之一,且該半導體基板為矽半導體基板、碳化矽半導體基板、砷化鎵半導體基板或氧化鋅半導體基板其中之一;Step 5: forming a bonding layer (8B) on a permanent substrate (9) to form a second semiconductor block (D); the material of the permanent substrate (9) is selected from a sapphire substrate, a semiconductor substrate or a metal substrate. One of the semiconductor substrate is one of a germanium semiconductor substrate, a tantalum carbide semiconductor substrate, a gallium arsenide semiconductor substrate or a zinc oxide semiconductor substrate;

  步驟六:將第一半導體塊材(C)之貼合層(8A)與第二半導體塊材(D)之貼合層(8B)進行貼合製程,使第一半導體塊材(C)、第二半導體塊材(D)貼合在一起;Step 6: bonding the bonding layer (8A) of the first semiconductor bulk material (C) and the bonding layer (8B) of the second semiconductor bulk material (D) to form a first semiconductor bulk material (C), The second semiconductor bulk (D) is bonded together;

  步驟七:利用基板剝離方法,例如:雷射剝離或研磨蝕刻剝離法,且以非晶性緩衝層(3A)為犧牲層,將暫時基板(2)分離;Step 7: using a substrate stripping method, for example, a laser stripping or abrading etching stripping method, and separating the temporary substrate (2) with the amorphous buffer layer (3A) as a sacrificial layer;

  步驟八:最後於第一半導體層(4)表面製作第一電極(40),並以該永久基板(9)為第二電極。Step 8: Finally, a first electrode (40) is formed on the surface of the first semiconductor layer (4), and the permanent substrate (9) is used as a second electrode.

  以上所舉者僅係本發明之部份實施例,並非用以限制本發明,致依本發明之創意精神及特徵,稍加變化修飾而成者,亦應包括在本專利範圍之內。The above is only a part of the embodiments of the present invention, and is not intended to limit the present invention. It is intended to be included in the scope of the present invention.

  綜上所述,本發明實施例確能達到所預期之使用功效,又其所揭露之具體技術手段,不僅未曾見諸於同類產品中,亦未曾公開於申請前,誠已完全符合專利法之規定與要求,爰依法提出發明專利之申請,懇請惠予審查,並賜准專利,則實感德便。In summary, the embodiments of the present invention can achieve the expected use efficiency, and the specific technical means disclosed therein have not been seen in similar products, nor have they been disclosed before the application, and have completely complied with the patent law. The regulations and requirements, the application for invention patents in accordance with the law, and the application for review, and the grant of patents, are truly sensible.

(2)...暫時基板(2). . . Temporary substrate

(3A)...非晶性緩衝層(3A). . . Amorphous buffer layer

(3B)...多晶或單晶性緩衝層(3B). . . Polycrystalline or single crystal buffer layer

(4)...第一半導體層(4). . . First semiconductor layer

(40)...第一電極(40). . . First electrode

(5)...主動層(多層量子井)(5). . . Active layer (multilayer quantum well)

(6)...第二半導體層(6). . . Second semiconductor layer

(7)...反射鏡層(7). . . Mirror layer

(8A)...貼合層(8A). . . Fit layer

(C)...第一半導體塊材(C). . . First semiconductor block

(9)...永久基板(9). . . Permanent substrate

(8B)...貼合層(8B). . . Fit layer

(D)...第二半導體塊材(D). . . Second semiconductor block

Claims (10)

一種垂直式氮化物發光二極體的製造方法,包括以下之步驟:
步驟一:先於暫時基板上,依序成長出非晶性緩衝層與多晶或單晶性緩衝層;
步驟二:利用有機金屬化學氣相沉積法依序成長第一半導體層、主動層、第二半導體層;
步驟三:於第二半導體層表面製作反射鏡層;
步驟四:於反射鏡層表面製作貼合層,以形成第一半導體塊材;
步驟五:於一永久基板上製作貼合層,以形成第二半導體塊材;
步驟六:將第一半導體塊材之貼合層與第二半導體塊材之貼合層進行貼合製程,使第一、第二半導體塊材貼合在一起;
步驟七:利用基板剝離方法,且以非晶性緩衝層為犧牲層,將暫時基板分離;
步驟八:於第一半導體層表面製作第一電極,該永久基板為第二電極。
A method for manufacturing a vertical nitride light emitting diode includes the following steps:
Step 1: preliminarily growing an amorphous buffer layer and a polycrystalline or single crystal buffer layer on the temporary substrate;
Step 2: sequentially growing the first semiconductor layer, the active layer, and the second semiconductor layer by using an organometallic chemical vapor deposition method;
Step 3: forming a mirror layer on the surface of the second semiconductor layer;
Step 4: forming a bonding layer on the surface of the mirror layer to form a first semiconductor block;
Step 5: forming a bonding layer on a permanent substrate to form a second semiconductor block;
Step 6: performing a bonding process on the bonding layer of the first semiconductor bulk material and the bonding layer of the second semiconductor bulk material, so that the first and second semiconductor blocks are bonded together;
Step 7: separating the temporary substrate by using a substrate stripping method and using the amorphous buffer layer as a sacrificial layer;
Step 8: forming a first electrode on the surface of the first semiconductor layer, the permanent substrate being a second electrode.
如申請專利範圍第1項所述垂直式氮化物發光二極體的製造方法,其中,該永久基板之材質係選自藍寶石基板、半導體基板或金屬基板其中之一。The method for manufacturing a vertical nitride light-emitting diode according to claim 1, wherein the material of the permanent substrate is one selected from the group consisting of a sapphire substrate, a semiconductor substrate, and a metal substrate. 如申請專利範圍第2項所述垂直式氮化物發光二極體的製造方法,其中,該半導體基板為矽半導體基板、碳化矽半導體基板、砷化鎵半導體基板或氧化鋅半導體基板其中之一。The method for producing a vertical nitride light-emitting diode according to claim 2, wherein the semiconductor substrate is one of a germanium semiconductor substrate, a tantalum carbide semiconductor substrate, a gallium arsenide semiconductor substrate, or a zinc oxide semiconductor substrate. 如申請專利範圍第1項所垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與多晶或單晶性緩衝層沉積於該暫時基板上之技術是採用濺鍍技術、單元子層沉積系統或分子束磊晶系統其中之一。The method for manufacturing a vertical nitride light-emitting diode according to claim 1, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer are deposited on the temporary substrate by using a sputtering technique. One of a unit sublayer deposition system or a molecular beam epitaxy system. 如申請專利範圍第1或4項所述垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與多晶或單晶性緩衝層之厚度為幾個nm至幾千個nm。The method for producing a vertical nitride light-emitting diode according to claim 1 or 4, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer have a thickness of several nm to several thousand nm. . 如申請專利範圍第5項所述垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與多晶或單晶性緩衝層成長溫度範圍為300℃~1000℃。The method for producing a vertical nitride light-emitting diode according to claim 5, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer have a growth temperature in the range of 300 ° C to 1000 ° C. 如申請專利範圍第6項所述垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與多晶或單晶性緩衝層成長溫度為固定溫度或漸變溫度其中之一。The method for producing a vertical nitride light-emitting diode according to claim 6, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer have a growth temperature of one of a fixed temperature or a gradual temperature. 如申請專利範圍第1項所述垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與多晶或單晶性緩衝層呈相互交替堆疊成長。The method for producing a vertical nitride light-emitting diode according to the first aspect of the invention, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer are alternately stacked and grown. 如申請專利範圍第1項所述垂直式氮化物發光二極體的製造方法,其中,該基板剝離方法為雷射剝離或研磨蝕刻剝離法其中之一。The method for producing a vertical nitride light-emitting diode according to the first aspect of the invention, wherein the substrate peeling method is one of a laser peeling and a polishing etching stripping method. 如申請專利範圍第1項所述垂直式氮化物發光二極體的製造方法,其中,該非晶性緩衝層與多晶或單晶性緩衝層係由氮化鋁、氮化銦或氮化鎵等材料系列其中之一的薄膜所形成。The method for manufacturing a vertical nitride light-emitting diode according to claim 1, wherein the amorphous buffer layer and the polycrystalline or single crystal buffer layer are made of aluminum nitride, indium nitride or gallium nitride. It is formed by a film of one of the material series.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11489050B2 (en) 2020-01-16 2022-11-01 Shinichiro Takatani Vertical nitride semiconductor transistor device
TWI825886B (en) * 2022-05-05 2023-12-11 環球晶圓股份有限公司 Epitaxial structure and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11489050B2 (en) 2020-01-16 2022-11-01 Shinichiro Takatani Vertical nitride semiconductor transistor device
TWI789636B (en) * 2020-01-16 2023-01-11 高谷信一郎 Vertical nitride semiconductor transistor device
TWI825886B (en) * 2022-05-05 2023-12-11 環球晶圓股份有限公司 Epitaxial structure and manufacturing method thereof

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