TW201438231A - Semiconductor structure and process thereof - Google Patents

Abstract

A semiconductor structure includes a metal gate, a second dielectric layer and a contact plug. The metal gate is located on a substrate and in a first dielectric layer, wherein the metal gate includes a work function metal layer having a U-shaped cross-sectional profile and a low resistivity material located on the work function metal layer. The second dielectric layer is located on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in a third dielectric layer, thereby a capacitor being formed. Moreover, the present invention also provides a semiconductor process formed said semiconductor structure.

Description

Semiconductor structure and its process

The present invention relates to a semiconductor structure and a process thereof, and more particularly to a semiconductor structure incorporating a capacitor and a transistor and a process therefor.

The capacitor in a semiconductor component is usually composed of two electrodes and a dielectric between the two electrodes. This structure is commonly used on many semiconductor components, such as dynamic random access memory (DRAM). The process of such a capacitor is generally as follows. First, a conductor layer is formed on the substrate, a pattern is defined and etched to form the lower electrode of the capacitor. Next, a dielectric layer is formed over the lower electrode. Finally, a capacitor is formed by covering the dielectric layer with another conductor layer.

The material of the electrode includes at least polycrystalline germanium, polycrystalline germanium metal, and metal. Therefore, there are currently three types of capacitor fabrication methods offered by semiconductor fabs: Metal-insulator-Metal (MIM) capacitors, poly-insulator-Poly (PIP) Capacitors, as well as Metal Oxide Semiconductor (MOS) capacitors, are compatible with CMOS processes to simplify process integration. The MIM capacitor is formed by using two metal layers to form an electrode plate. The PIP capacitor is formed by using two layers of polysilicon layers to form an electrode plate. The MOS capacitor connects the drain and source of the MOS together, and forms two electrode plates with the gate to form a capacitor.

When the positiveness of the integrated circuit is increased, and the size of each semiconductor component in the circuit is reduced, how to integrate the components of the transistor, such as a capacitor and a transistor, to achieve the required capacitance value and operation power, and to simplify Process and cost reduction have become important issues in the industry.

The invention provides a semiconductor structure and a process thereof, which are prepared by combining an electrode of a capacitor with a gate of a transistor and a contact plug to combine a transistor and a capacitor on the same semiconductor structure, thereby simplifying the process and thereby reducing the cost.

The present invention provides a semiconductor structure including a metal gate, a second dielectric layer, and a contact plug. The metal gate is located on a substrate and a first dielectric layer, wherein the metal gate has a U-shaped work function metal layer and a low resistivity material is located on the U-shaped work function metal layer. The second dielectric layer is on the metal gate and the first dielectric layer. The contact plug is located on the second dielectric layer and in the third dielectric layer, thereby forming a capacitor structure.

The present invention provides a semiconductor process comprising the steps described below. First, a first dielectric layer is formed on a substrate. Next, a metal gate is formed in the first dielectric layer, the metal gate has a U-shaped work function metal layer and a low resistivity material is located on the U-shaped work function metal layer. Successively, a second dielectric layer is formed on the metal gate and the first dielectric layer. Thereafter, a third dielectric layer is formed on the second dielectric layer. Then, a contact plug is formed in the third dielectric layer and is located in the vertical direction of the metal gate, thereby forming a capacitor structure.

Based on the above, the present invention provides a semiconductor structure and a process thereof, which will The process of the capacitor structure is integrated with the MOS transistor process, so that the capacitor structure can be formed in the same process as the MOS transistor structure, so that the process steps can be simplified and the cost can be reduced. Specifically, the electrode under the capacitor structure may be formed together with the metal gate of the MOS transistor; after that, the second dielectric layer is covered on the MOS transistor and the electrode under the capacitor structure to serve as an insulating layer of the capacitor structure and The MOS transistor is insulated upward; finally, the upper electrode of the capacitor structure is formed together with a contact plug for electrically connecting the MOS transistor to the outside.

10‧‧‧Insulation structure

20‧‧‧MOS transistor

22, 42‧‧ ‧ gate dielectric layer

24, 44‧‧ ‧ gate electrode layer

26, 46‧‧‧ cover

28, 48‧‧ ‧ clearance

29‧‧‧Source/Bungee

40‧‧‧ Sacrificial electrode

50‧‧‧Contact hole etch stop layer

110‧‧‧Base

120, 120'‧‧‧ first dielectric layer

130a‧‧‧First metal gate

130b‧‧‧Metal gate

132a, 132b‧‧‧U-shaped high dielectric constant dielectric layer

132a', 132b'‧‧‧"-shaped" high-k dielectric layer

Work function metal layer of 134a, 134b‧‧‧ U-shaped profile

136a, 136b‧‧‧ low resistivity materials

140‧‧‧Second dielectric layer

150, 150'‧‧‧ third dielectric layer

160‧‧‧Contact plug

170‧‧‧fourth insulation

180‧‧‧ fifth insulation

A‧‧‧First District

B‧‧‧Second District

C1‧‧‧first contact plug

C2, C3‧‧‧ second contact plug

C4‧‧‧Interconnection structure

G1, G2‧‧‧ Sacrificial Gate

P‧‧‧Capacitor structure

R1, R2‧‧‧ grooves

T1, T2‧‧‧ top surface

V‧‧‧Contact hole

V1, V2‧‧‧ second contact hole

1-9 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention.

Figure 10 is a cross-sectional view showing a semiconductor process in accordance with an embodiment of the present invention.

1-9 are schematic cross-sectional views showing a semiconductor process according to an embodiment of the present invention. As shown in FIG. 1, a substrate 110 is provided in which the substrate 110 has a first region A and a second region B. In this embodiment, the first region A is a transistor region in which a MOS transistor is formed, and the second region B is a capacitor region B in which a capacitor structure is formed. In this embodiment, only one MOS transistor is respectively shown in the first region A, and a capacitor structure is in the second region B, to clearly and simplifies the disclosure, but the number of the MOS transistor and the capacitor structure is not only Limited to one, it can also be plural, depending on the actual needs. The substrate 110 is, for example, a substrate, a germanium-containing substrate, a tri-five-layer overlying substrate (eg, GaN-on-silicon), a graphene-on-silicon or a silicon-on-insulator (silicon- On-insulator, SOI) A semiconductor substrate such as a substrate.

Next, an insulating structure 10 is formed in the substrate 110 of the second region B. Absolutely The edge structure 10 can be, for example, a shallow trench isolation (STI) structure or other oxide structure, and can be formed, for example, by a shallow trench isolation process or other oxidation process, but the invention is not limited thereto. In this way, the insulating structure 10 can insulate the capacitor structure formed thereon from the substrate 110, or electrically insulate the MOS transistor and the capacitor structure formed next to the capacitor structure from each other. In the present embodiment, the insulating structure 10 is specifically formed as a block-shaped insulating structure in the base 110 of most of the second region B to prevent the subsequently formed capacitor structure from being electrically connected to the substrate 110 to leak electricity, but the present invention does not This is limited. In other embodiments, the insulating structure 10 in the substrate 110 of the second region B may also be composed of a plurality of smaller insulating structures, as desired.

Then, a MOS transistor 20 is formed on the substrate 110 of the first region A, and a sacrificial electrode 40 is formed on the substrate 110 of the second region B. In the present embodiment, the sacrificial gate G1 of the MOS transistor 20 and the sacrificial electrode 40 are formed in the same process step to simplify the process. In detail, a dielectric layer (not shown), an electrode layer (not shown), and a cap layer (not shown) are sequentially formed on the substrate 110; then, the cap layer and the electrode are patterned. a layer and a dielectric layer to form a stacked gate dielectric layer 22 and 42, a gate electrode layer 24 and 44, and a cap layer 26 and 46, thereby forming a sacrificial gate G1 and a sacrificial gate G2, The sacrificial gate G1 includes a gate dielectric layer 22, a gate electrode layer 24, and a cap layer 26 from bottom to top. Correspondingly, the sacrificial gate G2 includes a gate dielectric layer 42 and a gate from bottom to top. The electrode layer 44 and the cap layer 46. In the present embodiment, the sacrificial gate G2 is located directly above the insulating structure 10 so that it does not leak to the substrate 110 when it is subsequently used as an electrode of the capacitor. Next, a layer of spacer material (not shown) is overlaid on the sacrificial gates G1, G2 and the substrate 110, and the spacer material layer is patterned to form a spacer 28 on the substrate 110 on the side of the sacrificial gate G1. At the same time, a spacer 48 is formed on the substrate 110 on the side of the sacrificial gate G2, thereby forming the sacrificial electrode 40 on the substrate 110. Continued, a source/drain 29 is formed on the spacer 28 The side substrate 110 is formed to form the MOS transistor 20.

Furthermore, after performing the above steps or after the above steps, other MOS transistor process steps can be performed to further form the MOS transistor 20 of better quality. For example, a lightly doped source/drain (not shown) is selectively formed in the substrate 110 on the side of the sacrificial gate G1; and an epitaxial structure (not shown) is selectively formed on the substrate on the side of the sacrificial gate G1. 110 is medium, and before forming a lightly doped source/drain or epitaxial structure, spacers (not shown) are additionally formed on the side of the sacrificial gate G1 to respectively adjust the lightly doped source/drain or epitaxial The distance between the structure and the sacrificial gate G1. The process steps of the MOS transistor are well known in the art and will not be described again.

Next, the spacers 28 and 48 are selectively removed, as shown in FIG. Then, a contact hole etch stop layer 50 and a first dielectric layer 120' are sequentially covered on the sacrificial gate G1, the sacrificial gate G2, and the substrate 110. The contact hole etch stop layer 50 can be, for example, a nitride layer or a doped nitride layer or the like. The first dielectric layer 120' may be, for example, an oxide layer, which may be formed by a chemical vapor deposition (CVD) process, but the invention is not limited thereto. Then, a planarization process (not shown) may be performed to form a planarized first dielectric layer 120, and the contact hole etch stop layer 50 on the sacrificial gates G1 and G2 is removed; An etching process removes the sacrificial gate G1 and the sacrificial gate G2, thereby forming two recesses R1 and R2, as shown in FIG. In other embodiments, portions of the sacrificial gate G1 and the sacrificial gate G2, such as the cap layers 26 and 46, may be removed prior to the planarization process.

As shown in FIG. 4, a high-k dielectric layer (not shown), a work function metal layer (not shown), and a low-resistivity material (not shown) are sequentially covered in the recess R1 and R2 and the first dielectric layer 120; then, planarizing the low resistivity material, the work function a plurality of metal layers and a high-k dielectric layer exposing the first dielectric layer 120 to form a stacked U-shaped high-k dielectric layer 132a and 132b, and a U-shaped work function metal layer 134a and 134b, and a low resistivity material 136a and 136b, respectively in the recesses R1 and R2, thereby forming a first metal gate 130a of the MOS transistor 20 in the first dielectric layer 120 of the first region A And a metal gate 130b is in the first dielectric layer 120 of the second region B. In detail, the first metal gate 130a includes a U-shaped high-k dielectric layer 132a, a U-shaped work function metal layer 134a, and a low-resistivity material 136a; the metal gate 130b includes a A high-k dielectric layer 132b having a U-shaped cross section, a work function metal layer 134b having a U-shaped cross section, and a low resistivity material 136b. Thus, in the present invention, the metal gate 130b and the first metal gate 130a can be formed in the same process, and the metal gate 130b and the first metal gate 130a are located on the same horizontal plane. In the present embodiment, the insulating structure 10 is located directly under the metal gate 130b to prevent current from flowing into the substrate 110 downwardly from the metal gate 130b. In the present invention, since the first metal gate 130a is formed simultaneously by the same metal gate process, and the metal gate 130b as an electrode under the capacitor structure is made of the same material as the first metal gate 130a. In addition to meeting the electrical requirements required for the MOS transistor 20, it is preferred to further consider the conductivity requirements of the formed capacitor structure and the need to store charge. In addition, the metal gate 130b and the first metal gate 130a may further include a selective barrier layer (not shown) in the high-k dielectric layer 132a and 132b of the U-shaped cross section, and a work function metal of the U-shaped cross section. Between the layers 134a and 134b and the low-resistivity materials 136a and 136b, a buffer layer (not shown) is disposed between the high-k dielectric layers 132a and 132b of the U-shaped cross-section and the substrate 110.

The high-k dielectric layers 132a and 132b of the U-shaped cross-section may be selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), and hafnium silicon oxynitride (hafnium silicon oxynitride). HfSiON), Aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), barium titanate (strontium) Titanate oxide, SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate Lead zirconate titanate, PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1-xTiO3, BST) group; U-shaped profile of the work function metal layer 134a and 134b is a crystal A metal requiring a work function requirement and an electrical conductivity requirement of the electrode, which may be a single layer structure or a composite layer structure, such as titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (tantalum nitride, TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminide (TiAl) or aluminum titanium nitride (TiAlN); low resistivity material 136a and 136 b may be composed of aluminum, tungsten, titanium aluminum alloy (TiAl) or cobalt tungsten phosphide (CoWP).

In addition, this embodiment is exemplified by a gate-Last for High-K Last process after the high-k dielectric layer is disposed, as shown in FIG. 4, which has a U-shaped cross section. The high-k dielectric layers 132a and 132b respectively surround the work function metal layers 134a and 134b of the U-shaped cross section. In other embodiments, the present invention can also be applied to a Gate-Last for High-K First process, which can be as shown in FIG. A schematic cross-sectional view of a semiconductor process in accordance with an embodiment of the invention. The gate dielectric layers 22 and 42 of this embodiment are a high-k dielectric layer and are not removed; in other words, when the recesses R1 and R2 are formed (as shown in FIG. 3), only the exposure is exposed. Gate dielectric layers 22 and 42 are exited. Then, directly put the work function A plurality of metal layers are stacked on the gate dielectric layers 22 and 42. Thus, high-k dielectric layers 132a' and 132b' having a "in-line" cross-section are formed between the work function metal layers 134a and 134b and the substrate 110 (and the insulating structure 10) of the U-shaped cross-section. However, it is still formed by the same metal gate process to form the metal gate 130b and the first metal gate 130a.

As shown in FIG. 5, a second dielectric layer 140 is formed on the metal gate 130b, the first metal gate 130a, and the first dielectric layer 120. The second dielectric layer 140 can be, for example, a nitride layer, an oxynitride layer, a carbon-containing tantalum nitride layer, or an oxide layer. In the present embodiment, the second dielectric layer 140 serves as an insulating layer of a capacitor structure, and is preferably selected such as the above-mentioned insulating material layer or the like in consideration of the dielectric constant and the like, preferably in consideration of the electrical properties of the capacitor structure. Furthermore, the second dielectric layer 140 in turn can insulate the MOS transistor from the metal interconnect structure subsequently formed thereon.

Next, the second dielectric layer 140 and the first dielectric layer 120 are patterned to form a plurality of first contact holes (not shown) in the second dielectric layer 140 and the first dielectric layer 120; The conductive material is filled into the first contact hole to form a plurality of first contact plugs C1 in the second dielectric layer 140 and the first dielectric layer 120, and physically contacts the source/drain 29 of the MOS transistor 20. . The first contact plug C1 may be composed of, for example, a material such as tungsten, aluminum or copper. Furthermore, before filling the conductive material to form the first contact plug C1, a self-aligned metal salicide process may be selectively performed to form a source of the metal telluride N in the first contact hole/ The drain 29 and the first contact plug C1 are between each other, thereby reducing the contact resistance of the source/drain 29 and the first contact plug C1. Of course, in other embodiments, a metal germanide may be formed on the source/drain 29 immediately after the source/drain 29 is formed, followed by a full coverage of the dielectric layer before the first contact hole is formed.

As shown in Figures 6-7, a third dielectric layer 150' is formed over the second dielectric layer 140. The third dielectric layer 150' may be, for example, an oxide layer, which may be formed by a chemical vapor deposition (CVD) process, but the invention is not limited thereto. In detail, a third dielectric layer (not shown) may be completely covered and then patterned to form a third dielectric layer 150 ′ having two second contact holes V1 and a contact hole V. At least a portion of the first contact plug C1 and a portion of the second dielectric layer 140 are exposed, as shown in FIG. The second dielectric layer 140 can be a single layer or multiple layers. In a preferred embodiment, the second dielectric layer 140 is a plurality of layers and includes at least two layers of material having different etch rates for an etch process. For example, when the second dielectric layer 140 is a double layer, which is a nitride layer and an oxide layer stacked from bottom to top, an etching process is performed to form a second contact hole V1 and a contact hole V in the third layer. In the case of the dielectric layer 150', the oxide layer can be used as an etch stop layer, ensuring that the etching process can be stopped in the nitride layer without over-etching. As a result, the top surface T1 of the second dielectric layer 140 contacting a portion of the contact plug formed later on the contact hole V is lower than the top surface of the second dielectric layer 140 at the other portion of the contact plug. T2.

Then, the third dielectric layer 150 ′ is patterned to form a third dielectric layer 150 , which further has two second contact holes V2 extending to the second dielectric layer 140 to expose at least a portion of the first metal gate. 130a and metal gate 130b, as shown in FIG.

Then, a conductive material (not shown) is simultaneously filled in the contact hole V, the second contact holes V1 and V2 and the conductive material is planarized to form a contact plug 160 in the third dielectric layer 150, which is located at The metal gate 130b is vertically oriented; and the second contact plugs C2 are physically in contact with the first contact plugs C1, respectively, and the second contact plugs C3 are physically in contact with the first metal gates 130a and the metal gates, respectively. 130b, as in the first Figure 8 shows. In the present embodiment, the second contact plugs C2 and C3 and the contact plug 160 serving as the upper electrode of the capacitor are simultaneously formed by the same contact plug process. In this way, the fabrication of a capacitor structure P is completed. The capacitor structure P is formed by the contact plug 160 as an upper electrode, the second dielectric layer 140 as an insulating layer, and the metal gate 130b as a lower electrode. The second contact plug C3 can electrically connect one end of the capacitor structure P to the outside by physically connecting the metal gate 130b, and the second contact plugs C2 and C3 can physically connect the first contact plug C1 and The first metal gate 130a electrically connects the MOS transistor 20 to the outside. The contact plug 160 and the second contact plugs C2 and C3 may be composed of, for example, aluminum or a material such as copper or tungsten. In the present embodiment, the contact plug 160 is an upper electrode of a capacitor structure, and is preferably further considered in addition to the electrical requirements required for the material to be connected to other structures in addition to the MOS transistor 20. The conductive requirements of the formed capacitor structure are selected from conductive materials.

As shown in FIG. 9, a fourth insulating layer 170 and a fifth insulating layer 180 are sequentially formed on the third dielectric layer 150, the contact plug 160, and the second contact plugs C2 and C3, and form an inner portion. The wiring structure C4 is in the fourth insulating layer 170 and the fifth insulating layer 180. In detail, a fourth insulating layer (not shown) and a fifth insulating layer (not shown) are disposed on the third dielectric layer 150, the contact plug 160, and the second contact plug C2. And C3, and then the first insulating layer and the fourth insulating layer are patterned by a dual damascene process such as trench first, via first, and self-aligned. And forming a recess (not shown) and a via hole (not shown) in the fourth insulating layer 170 and the fifth insulating layer 180. Thereafter, a conductive material (not shown) is filled in the recess and the conductive material is planarized to form the interconnect structure C4 in the fourth insulating layer 170 and the fifth insulating layer 180. The interconnect structure C4 physically connects the contact plug 160 and electrically connects one end of the capacitor structure P to the outside. Furthermore, The interconnect structure C4 is physically connected to the second contact plug C2 to electrically connect the MOS transistor 20 to the outside. In this embodiment, the interconnect structure C4 has a plurality of dual damascene structures, but the invention is not limited thereto. The interconnect structure C4 may be composed of, for example, a material such as aluminum or copper.

In summary, the present invention provides a semiconductor structure and a process thereof, which integrates a process of a capacitor structure with a MOS transistor process, so that a capacitor structure can be formed in the same process as a MOS transistor structure, thereby simplifying the process. Steps to achieve the goal of reducing costs. Specifically, the electrode under the capacitor structure can be formed together with the metal gate of the MOS transistor, so that the structure of the lower electrode is the same as that of the metal gate, and the work function metal layer having a U-shaped profile and the low resistivity material are located at the U The work function is formed on the metal layer, and the electrode under the capacitor structure formed by the present invention is located at the same level as the metal gate of the MOS transistor; after that, the second dielectric layer is covered under the MOS transistor and the capacitor structure On the electrode, on one hand, the MOS transistor can be insulated from the metal formed thereon, and on the other hand, it can be used as an insulating layer of the capacitor structure; finally, the upper electrode of the capacitor structure can be used to externally electrify the MOS transistor. The connected second contact plug is formed together.

10‧‧‧Insulation structure

20‧‧‧MOS transistor

110‧‧‧Base

120‧‧‧First dielectric layer

130a‧‧‧First metal gate

130b‧‧‧Metal gate

140‧‧‧Second dielectric layer

150‧‧‧ third dielectric layer

160‧‧‧Contact plug

170‧‧‧fourth insulation

180‧‧‧ fifth insulation

A‧‧‧First District

B‧‧‧Second District

C1‧‧‧first contact plug

C2, C3‧‧‧ second contact plug

C4‧‧‧Interconnection structure

P‧‧‧Capacitor structure

Claims (20)

A semiconductor structure comprising: a metal gate on a substrate and a first dielectric layer, wherein the metal gate has a U-shaped work function metal layer and a low resistivity material is located in the U-shaped profile a work function metal layer; a second dielectric layer on the metal gate and the first dielectric layer; and a contact plug on the second dielectric layer and a third dielectric layer A capacitor structure is formed. The semiconductor structure of claim 1, further comprising: an insulating structure located in the substrate and directly under the metal gate. The semiconductor structure of claim 1, wherein the metal gate further comprises a U-shaped high-conductivity dielectric layer under the work function metal layer of the U-shaped profile. The semiconductor structure of claim 1, wherein the metal gate further comprises a high-k dielectric layer of a "in-line" profile, located between the work function metal layer of the U-shaped profile and the substrate . The semiconductor structure of claim 1, wherein the work function metal layer of the U-shaped cross section comprises a titanium nitride layer, an aluminum titanium layer or a titanium carbide layer. The semiconductor structure of claim 1, wherein the low resistivity material comprises tungsten or aluminum. The semiconductor structure of claim 1, wherein the second dielectric layer comprises a nitride layer, an oxynitride layer, a carbon-containing tantalum nitride layer or an oxide layer. The semiconductor structure of claim 1, wherein the second dielectric layer is a single layer or a plurality of layers. The semiconductor structure of claim 1, wherein the second dielectric layer comprises a stacked two material layer having different etch rates for an etching process. The semiconductor structure of claim 1, wherein a top surface of the second dielectric layer contacting a portion of the contact plug is lower than another portion of the second dielectric layer adjacent to the contact plug Part of the top surface. The semiconductor structure of claim 1, further comprising: a MOS transistor comprising a first metal gate, and the first metal gate is at the same level as the metal gate. The semiconductor structure of claim 11, further comprising: a plurality of first contact plugs, located in the second dielectric layer and the first dielectric layer, and physically contacting one of the MOS transistors Source / bungee. The semiconductor structure of claim 11, further comprising: a plurality of second contact plugs located in the third dielectric layer and physically contacting the metal gate and the MOS transistor. A semiconductor process includes: forming a first dielectric layer on a substrate; Forming a metal gate in the first dielectric layer, the metal gate has a U-shaped work function metal layer and a low resistivity material on the work function metal layer of the U-shaped profile; forming a second a dielectric layer on the metal gate and the first dielectric layer; forming a third dielectric layer on the second dielectric layer; and forming a contact plug in the third dielectric layer The metal gate is vertically oriented, thereby forming a capacitor structure. The semiconductor process of claim 14, wherein before forming the first dielectric layer, further comprising: forming an insulating structure in the substrate and directly under the metal gate. The semiconductor process of claim 14, wherein the metal gate further comprises a U-shaped high dielectric constant dielectric layer or a "in-line" high dielectric constant dielectric layer. The work function metal layer of the U-shaped profile and between the substrates. The semiconductor process of claim 14, wherein the second dielectric layer is a single layer or a stacked plurality of layers having different etch rates for the same etching process. The semiconductor process of claim 14, wherein a top surface of the second dielectric layer contacting a portion of the contact plug is lower than another portion of the second dielectric layer adjacent to the contact plug Part of the top surface. The semiconductor process of claim 14, wherein before forming the second dielectric layer, further comprising: forming a MOS transistor in the first dielectric layer, wherein the MOS transistor package A first metal gate is formed, which is formed in the same process as the metal gate and is located on the same horizontal plane. The semiconductor process of claim 19, after forming the third dielectric layer, further comprising: forming a plurality of second contact plugs in the third dielectric layer, respectively physically contacting the MOS a crystal and the metal gate, and the second contact plugs are formed in the same process as the contact plug.