TW201436209A - Semiconductor device and method of forming the same - Google Patents

Abstract

A method of forming a semiconductor device includes the following steps. At first, a semiconductor substrate is provided, and a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, wherein a top surface of the metal gate structure is aligned with a top surface of the first dielectric layer. Then, a patterned mask is formed on the metal gate structure, and the patterned mask does not overlap the first dielectric layer. Subsequently, a second dielectric layer covering the patterned mask is overall formed on the semiconductor substrate. Furthermore, a part of the first dielectric layer and a part of the second dielectric layer are removed for forming at least a contact hole.

Description

Semiconductor device and method of fabricating the same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device in which a patterned mask is disposed on a metal gate structure and a method of fabricating the same.

In the conventional semiconductor industry, polycrystalline lanthanide is widely used in semiconductor components such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. However, as the size of the MOS transistor continues to shrink, the conventional polysilicon gate causes a decrease in component efficiency due to boron penetration effects, and an unavoidable depletion effect, etc., resulting in an equivalent gate. The thickness of the dielectric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the deterioration of the component driving capability. Therefore, the semiconductor industry has attempted to replace the traditional polysilicon gate with a new gate material, such as a work function metal, as a metal electrode matching a high-k gate dielectric layer. .

Conventionally, after forming a transistor having a metal gate, an external gate is formed thereon to electrically connect the metal gate and the source/drain region of the transistor, respectively, as input/output terminals of the external electronic signal. The external circuit usually includes a plurality of contact plugs. The conventional method for forming the contact plug includes: forming an interlayer dielectric layer covering the transistor and the source/drain regions on both sides of the transistor, and then patterning the interlayer dielectric layer. To form a contact hole exposing the source/drain region, after which a metal such as tungsten is deposited in the contact hole to form a contact plug connecting the source/drain regions.

As the critical size of the transistor shrinks, the spacing between the transistors will be reduced. In the process of forming the contact plug connecting the source/drain regions, the position of the contact hole will be more likely to occur. The subsequently formed contact plug will be more likely to directly contact the metal gate and the source/drain regions simultaneously to form a short circuit, resulting in an unexpected electrical performance of the transistor. Therefore, how to improve the manufacturing process of a semiconductor device having a contact plug and a metal gate structure is an object to be improved by those skilled in the art.

One of the objects of the present invention is to provide a semiconductor device in which a patterned mask is disposed on a metal gate structure and a method of fabricating the same, to prevent contact plugs of unaligned source/drain regions from directly contacting the metal gate Pole structure.

A preferred embodiment of the present invention provides a method of fabricating a semiconductor device comprising the following steps. First, a semiconductor substrate is provided, wherein a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, and a top surface of the metal gate structure is aligned with a top surface of the first dielectric layer. Next, a patterned mask is formed on the metal gate structure, and the patterned mask does not overlap the first dielectric layer. Subsequently, a second dielectric layer is formed on the semiconductor substrate, and the second dielectric layer covers the patterned mask. Next, a portion of the second dielectric layer is removed from the first dielectric layer to form at least one contact. hole.

Another preferred embodiment of the present invention provides a semiconductor device including a semiconductor substrate, a metal gate structure, a contact etch stop layer, an interlayer dielectric layer, a patterned mask, and at least one contact plug . The metal gate structure, the contact hole etch stop layer and the interlayer dielectric layer are disposed on the semiconductor substrate, and the patterned mask is disposed on the metal gate structure, wherein the patterned mask covers only the metal gate structure, higher than the contact hole The stop layer is etched and the contact etch stop layer is not overlapped. In addition, the contact plug is disposed in the interlayer dielectric layer and partially overlaps the patterned mask and the metal gate structure, wherein the contact plug has at least one stepped side.

In the invention, when forming the contact plug electrically connected to the source/drain region, the gate conductive layer of the metal gate structure is completely covered by the patterned mask to ensure that the gate conductive layer is not exposed to the contact plug. The effect, such as the gate conductive layer, will not contact the cleaning solution, etchant or chemical solvent used in the multiple lithography processes required to form the contact holes to maintain the material properties of the gate conductive layer. In addition, the process of forming the patterned mask does not include an etch back portion of the gate conductive layer, which can avoid deterioration of existing defects such as voids in the gate conductive layer.

10,100‧‧‧Semiconductor substrate

12,104‧‧‧Optoelectronics

14,14', 112, 112A‧‧‧ gate dielectric layer

16,16’‧‧‧Metal gate

18,116‧‧‧ 边边子

20,118‧‧‧Contact hole etch stop layer

22‧‧‧Dielectric layer

24, 24’ ‧ ‧ hollow

102‧‧‧Shallow trench isolation

106‧‧‧First dielectric layer

108‧‧‧Metal gate structure

110,110A‧‧‧Source/Bungee Area

114‧‧‧ gate conductive layer

120‧‧‧Material layer

122‧‧‧mask layer

124‧‧‧patterned mask

126‧‧‧Second dielectric layer

128,130‧‧‧Contact hole

132‧‧‧Metal Telluride

134‧‧‧Resistance/adhesive layer

136‧‧‧ Conductive layer

138,140‧‧‧Contact plug

142‧‧‧Interlayer dielectric layer

144‧‧‧ third dielectric layer

146‧‧‧Second contact plug

148‧‧‧3rd contact plug

200‧‧‧Semiconductor device

B1‧‧‧ bottom

S‧‧‧stepped sides

T1, T2, T3, T4, T5, T6‧‧‧ top surface

W1, W2‧‧‧ width

1 to 2 are schematic views showing a method of forming a semiconductor device according to an embodiment of the present invention.

3 to 10 are schematic views showing a method of forming a semiconductor device in accordance with a preferred embodiment of the present invention.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

In order to prevent the subsequently formed contact plug from directly contacting the metal gate, a mask layer may be formed to cover the metal gate before forming the contact plug. Please refer to FIG. 1 to FIG. 2 . FIG. 1 to FIG. 2 are schematic diagrams showing a method of forming a semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, a transistor 12, a contact etch stop layer 20 and a dielectric layer 22 are disposed on a semiconductor substrate 10, and the transistor 12 includes a gate dielectric layer 14 and a metal gate. 16 is disposed on the semiconductor substrate 10 between the two sidewalls 18. The method of forming the metal gate 16 includes an alternative metal gate (RMG) process in which the metal material layer is removed due to the reduction in critical dimension. It may not be possible to completely fill the trench (not shown) between the two side walls 18 to form a defect such as a void 24 in the metal gate 16. Next, as shown in FIG. 2, a portion of the metal gate 16 is etched back to form a recess (not shown) between the sidewalls 18, and then a dielectric material layer is filled in the opening (Fig. Not shown), and a chemical mechanical polishing (CMP) process is performed to remove the dielectric material layer outside the opening and form a mask layer 26 to the remaining metal gate 16' and the remaining gate Above the electrical layer 14'. Wherein, in the process of removing part of the metal gate 16, the defect will be deteriorated, that is, the cavity 24' may be extended downward in synchronization with the etching process, and the space occupied by the cavity 24' will be increased. Or even the transistor 12 loses its normal function.

Therefore, in order to avoid deterioration of void defects, it is preferable not to include a step of removing the metal gate to form an opening during the formation of the mask layer. Please refer to Figures 3 to 10. 3 to 10 are schematic views showing a method of forming a semiconductor device in accordance with a preferred embodiment of the present invention. The preferred embodiment avoids the deterioration of void defects. As shown in FIG. 3, a semiconductor substrate 100 is first provided, and the semiconductor substrate 100 includes a plurality of shallow trench isolation (STI) 102. The semiconductor substrate 100 can be, for example, a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator. , SOI) a substrate composed of a substrate or other semiconductor substrate material, but is not limited to the above. The shallow trench isolation 102 may comprise an insulating material such as tantalum oxide, or may be replaced by another insulating structure such as field oxide (FOX), and the method of forming shallow trench isolation is known to those skilled in the art. Usually known to the knowledge, no more details are mentioned here.

Next, at least one transistor 104 and a first dielectric layer 106 are formed on the semiconductor substrate 100. The transistor 104 includes a metal gate structure 108 and two source/drain regions 110. The gate structure 108 includes a gate dielectric layer 112 and a gate conductive layer 114 disposed on the sidewalls 116. The two source/drain regions 110 are disposed in the semiconductor substrate 100 on both sides of the metal gate structure 108, respectively. The invention can be applied to various metal gate processes including a gate first process, a gate last process, a high-k first process, and a gate process after a gate process. Dielectric layer (high-k last) process, etc. This embodiment is an example of the transistor 104 formed by the gate dielectric process after the gate process. Therefore, the gate dielectric layer 112 includes a high-k dielectric layer having a U-shaped cross section. A dielectric material having an electric constant greater than 4 is, for example, selected from hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), hafnium silicon oxynitride (HfSiON). , aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), oxidation Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), yttrium Oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT), barium strontium titanate, Ba _x Sr _a group consisting of _1-x TiO ₃ , BST), or a combination thereof. The method of forming the gate dielectric layer 112 includes an atomic layer deposition (ALD) process or a metal-organic chemical vapor deposition (MOCVD), but is not limited thereto. In addition, a dielectric layer (not shown) such as a tantalum oxide layer may be selectively disposed between the semiconductor substrate 100 and the gate dielectric layer 112; and the gate conductive layer 114 may include one or more layers of metal material. For example, it includes a work function metal layer, a barrier layer, and a low resistance metal layer. The work function metal layer is used to adjust the work function of the formed metal gate structure 108 to be suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer may be selected from a metal material having a work function of 3.9 eV to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), or tungsten aluminide ( WAl), tantalum aluminide (TaAl) or hafnium aluminide (HfAl), etc., but not limited to this; if the transistor is a P-type transistor, the work function metal layer may be selected from a metal having a work function of 4.8 eV to 5.2 eV Materials such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC), etc., but not limited thereto.

For example, the process of forming the metal gate structure 108 and the source/drain region 110 may first form a dummy gate structure (not shown) on the semiconductor substrate 100, and then sequentially form the sidewall spacer 116, the source/ The drain region 110, the contact etch stop layer (CESL) 118, and the first dielectric layer 106. The contact hole etch stop layer 118 may be selectively disposed between the metal gate structure 108 and the first dielectric layer 106, and the material thereof may include, for example, a tantalum nitride-nitrogen doped silicon carbide (NDC) layer. And other dielectric materials. The first dielectric layer 106 may be formed of a dielectric material formed by a spin-on-coating (SOC) process, a chemical vapor deposition (CVD) process, or other suitable process, and the dielectric material includes a low dielectric layer. Dielectric constant (k) material (dielectric constant value less than 3.9), ultra low dielectric constant (ultra low-k, hereinafter referred to as ULK) material (dielectric constant value less than 2.6), or porous ultra low dielectric Electrical constant (porous ULK) material, but is not limited thereto. Then, a planarization process, such as a chemical mechanical polish (CMP) process or an etch process, is performed to sequentially remove a portion of the first dielectric layer 106 and a portion of the contact hole etch stop layer 118. a portion of the sidewall 116, to expose the dummy gate structure, and then remove a portion of the dummy gate structure to form a trench (not shown), and finally fill the trench with at least one high-k dielectric material a layer (not shown) and at least one metal material layer (not shown), and performing another chemical mechanical polishing process to remove the dielectric material layer and the metal material layer outside the trench to form the gate of the metal gate structure 108 The dielectric layer 112 and the gate conductive layer 114 are such that one top surface T1 of the metal gate structure 108 is aligned with the top surface T3 of the first dielectric layer 106. In more detail, at this time, the metal gate structure 108 The top surface T1, the top surface T2 of the contact hole etch stop layer 118, and the top surface T3 of the first dielectric layer 106 will be coplanar.

In another embodiment, as shown in FIG. 4, in the embodiment different from FIG. 3, the gate dielectric layer 112 is formed by a "high-k last process" process ( Gate The dielectric layer is formed after the dummy gate is removed. In the embodiment of FIG. 4, the gate dielectric layer 112A is formed by a "high-k first process" process (ie, gate). The dielectric layer is formed before the dummy gate, so the gate dielectric layer 112A has a "-type" profile. Furthermore, the contact hole etch stop layer 118 may additionally have a stress.

On the other hand, the source/drain regions 110 of the foregoing two embodiments may also form a source/drain doping region by ion implantation or doping epitaxy, and the shape of the source/drain region 110. It can also be adjusted according to the stress required for the channel below the metal gate structure 108. In addition, each element in the transistor may have different implementations according to different designs. For example, the source/drain region may include an epitaxial layer formed by selective epitaxial growth (SEG). a layer, wherein the epitaxial layer can be directly formed on the semiconductor substrate 100, such as the source/drain region 110A shown in FIG. 4, or a groove is formed on both sides of the metal gate structure 108, and then the epitaxial layer is filled. The source/drain regions 110 are layered in the recesses as shown in FIG. 3 to provide a channel region under stress to the metal gate structure. In the present embodiment, when the transistor 104 is an N-type MOS transistor (NMOS), the epitaxial layer of the source/drain region 110 may be composed of bismuth phosphide (SiP) or tantalum carbide (SiC). Providing tensile stress to the channel region, and when the transistor 104 is a P-type MOS transistor (PMOS), the epitaxial layer of the source/drain region 110 may be composed of germanium telluride (SiGe) to provide compressive stress to Channel area, but not limited to this. In addition, a dry and wet etching process can be mixed to form various shapes such as a barrel shape (a straight shape), a hexagonal shape, a polygonal groove, and a protrusion formed in a groove of such a shape in a subsequent process. The seed layer may have a cross-sectional shape of a hexagonal or octagon and has a substantially flat bottom surface to increase the stress provided to the channel region. The above embodiments are merely examples, and the transistor of the present invention may have various implementations, which are not described herein. The following embodiments will be described in terms of an embodiment of the transistor 104 in FIG.

Next, a patterned mask is formed on the metal gate structure to pattern the mask On the gate conductive layer and the two sidewalls, and the patterned mask covers only the metal gate structure, that is, does not overlap the first dielectric layer, that is, the patterned mask only contacts the metal gate structure The top surface of the contact etch stop layer and the top surface of the first dielectric layer are exposed. The method of forming a patterned mask can include the following steps. First, as shown in FIG. 5 and FIG. 6, a mask material layer 120 is integrally formed on the semiconductor substrate 100. The mask material layer 120 will simultaneously cover the metal gate structure 108, the contact hole etch stop layer 118, and the first Dielectric layer 106. Subsequently, a mask layer 122 is formed, for example, a patterned photoresist layer on the mask material layer 120, and the photoresist layer is patterned as a mask, and one or more etching processes are performed to remove a portion of the mask material layer 120. To complete the patterned mask 124, and finally, the mask layer 122 is removed. The material of the patterned mask 124 may comprise a dielectric material such as silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), silicon carbonitride, A single layer structure or a multilayer structure composed of SiCN), silicon oxynitride (SiON) or a combination thereof.

It should be noted that, in this embodiment, the material of the patterned mask 124, that is, the material of the mask material layer 120 is preferably different from the material of the contact hole etch stop layer 118 and the material of the first dielectric layer 106. The masking material layer 120 is provided with an etch selectivity ratio to the contact hole etch stop layer 118 and the first dielectric layer 106, that is, when the mask layer 120 is removed using the same etchant, the contact hole etch stop layer 118 And the removed rate of the first dielectric layer 106 will be substantially less than the removed speed of the masking material layer 120, thus, after completing the patterned mask 124, the contact hole etch stop layer 118 and the first dielectric layer 106 can still maintain most of its original structure, at this time, the top surface T1 of the metal gate structure 108 or one of the bottom surfaces B1 of the patterned mask 124 in contact therewith will be substantially higher than or in contact with the hole etch stop layer 118. The top surface T2 and the top surface T3 of the first dielectric layer 106, and one of the top surfaces T4 of the patterned mask 124 is substantially higher than the top surface T2 of the contact hole etch stop layer 118 and the top of the first dielectric layer 106 Face T3. In other embodiments, if the material of the mask material layer and the material of the contact hole etch stop layer or the first dielectric When the materials of the layers are the same, the operating conditions of the etching process can be adjusted by a time mode, for example, the processing time of the etching process is adjusted to determine the thickness of the removed mask material layer, so that the unoverlapping metal gates are The layer of the mask material of the pole structure can be completely removed, and the etching process is stopped to expose the top surface of the contact hole etch stop layer and the top surface of the first dielectric layer. In addition, in the process of forming the patterned mask 124, the mask material layer 120 completely covers the gate conductive layer 114 and the boundary between the gate conductive layer 114 and each sidewall 116, preventing the partial mask material layer 120 from being removed. The etchant or chemical solvent used contacts the gate conductive layer 114 and is not formed between the sidewalls 116 to maintain the original structure of the gate conductive layer 114 and to avoid deteriorating defects in the gate conductive layer, for example: avoiding increase The size of the hollow hole of the large gate conductive layer. In addition, the layout pattern, size or shape of the patterned mask 124 can be adjusted according to process requirements, that is, the patterned mask 124 can completely cover the sidewall spacer 116 or partially cover the sidewall spacer 116.

Next, as shown in FIG. 7, a second dielectric layer 126 composed of a dielectric material is formed on the semiconductor substrate 100 in a comprehensive manner, and the second dielectric layer 126 will cover the patterned mask 124 and the contact hole is etched. Layer 118 and first dielectric layer 106. Then, a planarization process can be performed on the second dielectric layer 126 such that the second dielectric layer 126 has a substantially flat top surface. The material of the second dielectric layer 126 may be the same as or different from the material of the first dielectric layer 106, and the material of the second dielectric layer 126 is preferably different from the material of the patterned mask 124 and the contact hole is etched. The material of layer 118 has an etch selectivity ratio between second dielectric layer 126 and patterned mask 124 and contact etch stop layer 118. Subsequently, as shown in FIG. 8 , a portion of the second dielectric layer 126 and the first dielectric layer 106 are removed to form at least one contact hole 128 / 130 in the second dielectric layer 126 and the first dielectric layer 106, The contact holes 128/130 are respectively connected to the source/drain regions 110 of at least one side of the metal gate structure 108, that is, the contact holes 128/130 will expose a portion of the semiconductor substrate 100. Each contact hole 128/130 is not limited to a single single port, and may each include a plurality of independent openings or an extended strip extending in a direction parallel to the parallel metal gate structure 108. , that is, the direction of the vertical paper, extending in the source/drain region 110 Preferably, and preferably extending the entire source/drain region 110 to increase the contact area of the subsequently formed contact plug with the source/drain region 110 and reduce the resistance. That is to say, the size, shape, number and layout pattern of the contact holes 128/130 can be adjusted according to the process requirements. In addition, the contact holes 128/130 exposing the two source/drain regions 110 can be formed simultaneously by a patterning process or by double patterning (DPT).

The method of forming the contact hole 128/130 includes the following steps, but is not limited thereto. First, a mask layer (not shown) is formed over the second dielectric layer 126. Preferably, the mask layer of the multi-layer structure may include an advanced patterning film (APF). For example, an amorphous carbon layer, a dielectric anti-reflective coating film (DARC) (not shown), a bottom anti-reflective coating film (BARC) (not shown) And a patterned photoresist layer (not shown) is sequentially disposed on the second dielectric layer 126, wherein the patterned photoresist layer comprises a pattern of subsequently formed contact plugs, and the advanced patterned material layer (APF) has Good aspect ratio (HAR), low line edge roughness (LER) and PR-like ashability, so it is often used in processes with line widths less than 60 nm. in. Then, using the patterned photoresist layer as a mask, one or more etching processes, such as an anisotropic dry etch process, are performed to remove the second dielectric layer that is not covered by the patterned photoresist layer. The electrical layer 126 and the first dielectric layer 106 are exposed to the contact hole etch stop layer 118 on the source/drain region 110. Finally, the exposed contact hole etch stop layer 118 is removed to complete the contact hole 128/130.

In the present embodiment, since the material of the patterned mask 124 is, for example, tantalum nitride (SiN) and the contact hole etch stop layer 118, for example, a material of nitrogen-doped tantalum carbide (NDC) is different from the second dielectric layer 126. The material is, for example, yttrium oxide (SiO) and a material of the first dielectric layer 106 such as yttrium oxide (SiO). Therefore, the etchant used in forming the contact hole 128/130 removes the second dielectric layer 126 and the first The rate of a dielectric layer 106 will be substantially greater than the removal of the patterned mask 124 The rate at which the hole 118 is etched to stop the layer 118. In addition, when the size of the contact hole is different, for example, the cross-sectional width W1 of the contact hole 128 is larger than the cross-sectional width W2 of the contact hole 130, or the position of the contact hole is shifted, the formed contact hole may partially overlap the metal gate structure. 108. For example, the contact hole 128 simultaneously exposes the source/drain region 110 and the patterned mask 124. At this time, one of the top surfaces T5 of the patterned mask 124 exposed by the contact hole 128 will be slightly lower than the second dielectric layer. 126 is still covered by one of the top surfaces T4 of the patterned mask 124 such that the patterned mask 124 has a non-flat top surface (ie, top surface T4 and top surface T5), but still completely covers the metal gate structure 108 That is, the material properties and thickness of the patterned mask 124 are sufficient to maintain the integrity of the metal gate structure 108 during the formation of the contact holes 128. The placement of the patterned mask 124 will help increase the contact hole process. Process window.

After the contact holes 128/130 are formed, a cleaning process, such as cleaning the surface of the contact holes 128/130 with argon (Ar), may be selectively performed. Subsequently, a self-aligned metal salicide process can be performed to form a metal silicide layer 132 on the source/drain regions 110 exposed by the contact holes 128/130, for example, a silicide layer. Nickel (NiSi) layer. In other embodiments, this step of forming a metal telluride may be omitted if the metal telluride layer has been formed on the source/drain regions prior to forming the contact holes.

Subsequently, a plurality of contact plugs are formed in the contact holes 128/130. For the method of forming the contact plug, refer to FIG. 9. As shown in FIG. 9, for example, a barrier/adhesion layer 134, a seed layer (not shown), and a conductive layer are sequentially formed on the semiconductor substrate 100. The layer 136 covers the second dielectric layer 126 and fills the contact holes 128/130, wherein the barrier/adhesion layer 134 is conformally filled into the contact holes 128/130, and the conductive layer 136 is completely filled in contact. Hole 128/130. The barrier/adhesion layer 134 can be used to prevent metal atoms of the conductive layer 136 from diffusing into the surrounding second dielectric layer 126 / first dielectric layer 106 and to increase the conductive layer 136 and the second dielectric layer 126 / first dielectric Adhesion between layers 106. The material of the barrier/adhesive layer 134 is, for example, 钽 (Ta), titanium (Ti), titanium nitride (TiN), titanium telluride (TaN) or any combination thereof such as titanium/titanium oxide, but not limited thereto. The material of the seed layer is preferably the same as the material of the conductive layer 136, and the material of the conductive layer 136 comprises various low-resistance metal materials such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W). Materials such as niobium (Nb), molybdenum (Mo), copper (Cu), preferably tungsten or copper, preferably tungsten, are suitably formed with the metal telluride layer 132 or the source/drain regions 110 below. Ohmic contact. Then, a planarization process such as a chemical mechanical polishing (CMP) process, an etching process, or a combination of the two is performed to remove the barrier/adhesion layer 134, the seed layer and the conductive layer 136 in a region other than the contact hole. The surface of one of the remaining conductive layers 136 is coplanar with the surface of one of the second dielectric layers 126, thereby completing a plurality of contact plugs 138/140, i.e., source/drain plugs.

Referring to FIG. 9 , the semiconductor device 200 of the present invention includes a metal gate structure 108 , a contact etch stop layer 118 , and an interlayer dielectric layer 142 formed by the first dielectric layer 106 and the second dielectric layer 126 . Disposed on the semiconductor substrate 100, the patterned mask 124 is disposed on the metal gate structure 108, and the contact plugs 138/140 are disposed in the interlayer dielectric layer 142 on at least one side of the metal gate structure 108. The patterned mask 124 covers only the metal gate structure 108 without overlapping the first dielectric layer 106, the second dielectric layer 126, and the source/drain regions 110. The patterned mask 124 has a non-flat top surface. More specifically, one of the top surfaces T4 of the patterned mask 124 covered by the interlayer dielectric layer 142 is higher than the patterned mask not covered by the interlayer dielectric layer 142. One of the top faces T5 of the cover 124. In addition, the patterned mask 124 is again higher than the contact hole etch stop layer 118 and does not overlap the contact hole etch stop layer 118. In the present embodiment, the contact hole etch stop layer 118 between the contact plug 140 and the patterned mask 124 maintains an original top surface T2, which is higher than the top surface of the contact hole etch stop layer 118 where the contact plug 138 overlaps. T6, in addition, the top surface T6 of the contact hole etch stop layer 118 of the contact plug 138 will be slightly lower than the top surface T5 of the patterned mask 124 of the contact plug 138, that is, one of the metal gate structures 108 The face T1 (i.e., the top surface of the gate conductive layer 114) will be interposed between the top surface T5 of the patterned mask 124 and Contact hole between one of the top surfaces T6 of the etch stop layer 118. In addition, the contact plug 138 has at least one stepped side S, that is, a partially patterned mask 124 and a partial contact hole etch stop layer 118, that is, the contact hole 128 as shown in the previous FIG. The patterned mask 124 and the contact hole etch stop layer 118 are exposed and not aligned with each other.

As shown in FIG. 10, after the contact plugs 138/140 are formed, a third dielectric layer 144 may be further formed on the interlayer dielectric layer 142, and a plurality of second contact plugs 146 are formed. The electrical layer 144 is electrically connected to the contact plugs 138 / 140, respectively, and the at least one third contact plug 148 is formed on the third dielectric layer 144, the partial interlayer dielectric layer 142 (the second dielectric layer 126), and The patterned mask 124 is electrically connected to the metal gate structure 108. Finally, a metal interconnect process can be performed to form a metal interconnection system (not shown) on the third dielectric layer 144, which includes a plurality of metal interlayer dielectric layers (inter-metal) A dielectric layer (IMD layer) and a plurality of metal layers (so-called metal 1, metal 2, etc.). The metal interconnecting system electrically connects the gate conductive layer 114 of the transistor 104 through the third contact plug 148, and electrically connects the transistor 104 through the second contact plug 146 and the contact plug 138/140. The source/drain region 110 provides input/output of the external signal of the transistor 104.

In summary, when forming a contact plug electrically connected to the source/drain region, the gate conductive layer of the metal gate structure is completely covered by the patterned mask to ensure that the gate conductive layer is not protected. The influence of the process of the contact plug, for example, the gate conductive layer will not contact the cleaning solution, etching solution or chemical solvent used in the multiple lithography process required to form the contact hole to maintain the material properties of the gate conductive layer. . In addition, the process of forming the patterned mask does not include an etch back portion of the gate conductive layer, which can avoid deterioration of existing defects such as voids in the gate conductive layer.

100‧‧‧Semiconductor substrate

102‧‧‧Shallow trench isolation

106‧‧‧First dielectric layer

108‧‧‧Metal gate structure

110‧‧‧Source/Bungee Area

112‧‧‧ gate dielectric layer

114‧‧‧ gate conductive layer

120‧‧‧Material layer

116‧‧‧ Sidewall

118‧‧‧Contact hole etch stop layer

124‧‧‧patterned mask

126‧‧‧Second dielectric layer

132‧‧‧Metal Telluride

134‧‧‧Resistance/adhesive layer

136‧‧‧ Conductive layer

138,140‧‧‧Contact plug

142‧‧‧Interlayer dielectric layer

200‧‧‧Semiconductor device

S‧‧‧stepped sides

T1, T2, T4, T5, T6‧‧‧ top

Claims (20)

A method of forming a semiconductor device, comprising: providing a semiconductor substrate, wherein a metal gate structure and a first dielectric layer are disposed on the semiconductor substrate, and a top surface of the metal gate structure and the first dielectric Forming a top surface of the layer; forming a patterned mask on the metal gate structure, and the patterned mask does not overlap the first dielectric layer; forming a second dielectric layer on the semiconductor substrate in a comprehensive manner And the second dielectric layer covers the patterned mask and the first dielectric layer; and the portion of the second dielectric layer and the first dielectric layer are removed to form at least one contact hole. A method of forming a semiconductor device according to claim 1, wherein a bottom surface of the patterned mask contacts the top surface of the metal gate structure. The method of forming a semiconductor device according to claim 1, wherein the method of forming the patterned mask comprises: forming a mask material layer on the semiconductor substrate in a comprehensive manner; forming a patterned photoresist layer on the mask material On the layer, and using the patterned photoresist layer as a mask, a portion of the mask material layer is removed. A method of forming a semiconductor device according to claim 1, wherein the material of the patterned mask comprises a dielectric material. The method of forming a semiconductor device according to claim 1, further comprising a contact hole etch stop layer disposed between the metal gate structure and the first dielectric layer. A method of forming a semiconductor device according to claim 5, wherein the top of the metal gate structure The top surface of the contact etch stop layer and the top surface of the first dielectric layer are coplanar. The method of forming a semiconductor device according to claim 5, wherein the patterned mask covers the top surface of the metal gate structure, and exposes a top surface of the contact hole etch stop layer and the first dielectric layer The top surface. The method of forming a semiconductor device according to claim 7, wherein a top surface of the patterned mask is substantially higher than the top surface of the contact hole etch stop layer and the top surface of the first dielectric layer. The method of forming a semiconductor device according to claim 5, wherein the material of the contact hole etch stop layer is different from the material of the patterned mask. The method of forming a semiconductor device according to claim 1, wherein the metal gate structure comprises a gate dielectric layer and a gate conductive layer sequentially disposed on the semiconductor substrate between the two sidewalls, and the patterning A mask is located on the gate conductive layer and the two sidewalls. The method of forming a semiconductor device according to claim 1, further comprising forming at least one source/drain region on at least one side of the metal gate structure. The method of forming a semiconductor device according to claim 11, further comprising forming a metal halide layer in the source/drain region exposed by the contact hole. A method of forming a semiconductor device according to claim 1, wherein the contact hole exposes a portion of the semiconductor substrate. A semiconductor device comprising: a metal gate structure, a contact hole etch stop layer, and an interlayer dielectric layer disposed on a semiconductor a patterned mask disposed on the metal gate structure, wherein the patterned mask covers only the metal gate structure, and the patterned mask is higher than the contact hole etch stop layer and does not overlap Contacting the etch stop layer; and at least one contact plug is disposed in the interlayer dielectric layer and partially overlapping the patterned mask and the metal gate structure, wherein the contact plug has at least one stepped side. The semiconductor device of claim 14, wherein the stepped side of the contact plug includes a portion of the patterned mask and a portion of the contact hole etch stop layer. The semiconductor device of claim 14, wherein the metal gate structure comprises a gate dielectric layer and a gate conductive layer disposed on the semiconductor substrate between the two sidewalls, and the patterned mask is located The gate conductive layer and the two sidewalls. The semiconductor device of claim 14, wherein the patterned mask has a non-flat top surface. The semiconductor device of claim 17, wherein a top surface of the patterned mask covered by the interlayer dielectric layer is higher than a top surface of the patterned mask not covered by the interlayer dielectric layer. The semiconductor device of claim 14, wherein a top surface of the metal gate structure is between a top surface of the patterned mask and a top surface of the contact etch stop layer. The semiconductor device of claim 14, wherein the material of the contact hole etch stop layer is different from the material of the patterned mask.