TW201438177A - Memory device structure and method of manufacturing the same, and semiconductor device structure - Google Patents

Abstract

A memory device structure at least includes a plurality of memory devices and a plurality of bit lines. Each of the bit lines connects with each of the memory devices respectively, and the bit lines consist of two story parallel bit lines. Therefore, it can reduce bit line resistance by increasing the width thereof.

Description

Memory structure, manufacturing method thereof and semiconductor component

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, and more particularly to a memory structure capable of reducing a bit line resistance, a method of fabricating the same, and a semiconductor device.

In recent years, the process of memory components has been developed in the generations of the nanometer, from the hundreds of nanometer processes in the early years to the processes below 40 nanometers. Although each process technology can increase production compared to previous generation technologies, problems such as process yield stability and component efficiency are increasingly difficult.

Taking the 40 nm process as an example, because of the design rule of the process, the bit line can be made almost exclusively by the copper process. Moreover, as the size of the device shrinks, the sheet resistance of the bit line inevitably increases, affecting the efficiency of the element.

The present invention provides a memory structure capable of preventing an increase in bit line resistance while the component size is reduced.

The invention further provides a method for manufacturing a memory structure, which can expand the line width of the bit line to more than 2 times under the design specification of the process.

The present invention further provides a semiconductor structure that can be used for components below 40 nm generation.

The method of fabricating the memory structure of the present invention includes forming a plurality of memory elements, and then forming a plurality of bit lines respectively connected to the respective memory elements, wherein the bit lines are composed of double-layer bit lines that are parallel to each other.

The semiconductor structure of the present invention includes a plurality of semiconductor elements and a plurality of interconnects. The interconnect wires are respectively connected to the respective semiconductor elements, and the interconnect wires are composed of two-layer wires which are parallel to each other.

Based on the above, the structure of the present invention divides the bit lines parallel to each other into a two-layer structure, so that when the element size is reduced, the line width of the bit line can still exceed twice the design specification of the process, so the bit can be lowered. The material of the wire is replaced by aluminum instead of the copper process of the 40nm generation.

The above described features and advantages of the invention will be apparent from the following description.

100, 300‧‧‧ base

102, 302‧‧‧Isolation structure

104, 304‧‧‧Doped area

106, 306a, 306b‧‧‧ first layer bit line contact window

108‧‧‧First contact window

110‧‧‧layer window

112, 114, 132‧‧‧ dielectric layer

116‧‧‧Barrier layer

118, 308‧‧ ‧ etch stop layer

120‧‧‧Oxide layer

122, 310‧‧‧ first bit line

124, 312‧‧ ‧ spacer

126‧‧‧ditch

128, 202, 314‧‧ ‧ lining

130, 200, 316‧‧‧ second layer bit line contact window

134, 318‧‧‧ second bit line

136‧‧ ‧ cover layer

138‧‧‧ double-layer line

1A-1 to 1F-3 are schematic views showing a manufacturing process of a memory structure in accordance with a first embodiment of the present invention.

2A-1 to 2C are schematic views showing a manufacturing process of a memory structure in accordance with a second embodiment of the present invention.

3A through 3E are top views of a manufacturing process of a memory structure in accordance with a third embodiment of the present invention.

1A-1 to 1F-3 are schematic diagrams showing a manufacturing process of a memory structure according to a first embodiment of the present invention, and the present embodiment is exemplified by NAND Flash, but the present invention is not limited thereto.

1A-1 and 1A-2, FIG. 1A-1 is a top view, and FIG. 1A-2 is a cross-sectional view taken along line II-II of FIG. 1A-1. In FIG. 1A-1 and FIG. 1A-2, the substrate 100 has an isolation structure 102 and a doped region 104 as an active region of the memory structure. Since the NAND flash is taken as an example in this embodiment, each doped region is used. 104 represents a single memory component, ie, a portion of a memory string; if it is another type of memory component, the doped region 104 can be part of a memory cell. The aforementioned memory cell or memory string belongs to the existing memory element, and therefore will not be described in detail in this embodiment. A plurality of first layer bit line contact windows 106 are formed on the substrate 100. The first layer bit line contact windows 106 may include direct connection with the doped regions 104. The first contact window 108 that touches and the via window 110 that is in direct contact with the first contact window 108 are sometimes designed to match the structure and type of the memory element itself, and thus the first layer of the bit line in the present invention The contact window 106 may also have only the first contact window 108 without the via window 110. Moreover, the first layer of bit line contact windows 106 are disposed in a spaced apart configuration, that is, a doped region 104 is spaced between the two first bit line contact windows 106 on the same cross section. In addition, the first contact window 108 and the via 110 are formed in the dielectric layers 112 and 114, and between the first contact window 108 and the dielectric layer 112 of the metal material, and the via 110 and the dielectric Between the layers 114, a barrier layer 116 (such as Ti/TiN) is provided.

1B-1 and FIG. 1B-2, FIG. 1B-1 is a top view, and FIG. 1B-2 is a cross-sectional view taken along line II-II of FIG. 1B-1. A tantalum nitride layer is formed over the dielectric layer 114 as an etch stop layer 118, which is then patterned to expose the first layer of bit line contact windows 106. The etching stopper layer 118 may be other suitable materials in addition to tantalum nitride, and the present invention is not limited thereto.

1C-1 and FIG. 1C-2, FIG. 1C-1 is a top view, and FIG. 1C-2 is a cross-sectional view taken along line II-II of FIG. 1C-1. Forming a stack of Ti/Al and oxide layer 120 on the first layer of bit line contact windows 106 exposed in the previous step, and patterning the stack to obtain via the first layer of bit line contact windows 106 and The doped region 104 is electrically connected to the first bit line 122, and a barrier layer (not shown) such as Ti/TiN may be disposed between the first bit line 122 and the oxide layer 120. The configuration of the first bit line 122 is a spacing configuration, that is, a doped region 104 is spaced between the two first bit lines 122 on the same cross section. At this time, the first layer is not covered by the first bit line 122. The line contact window 106 is exposed after patterning the layer.

1D-1, FIG. 1D-2 and FIG. 1D-3, FIG. 1D-1 is a top view, FIG. 1D-2 is a cross-sectional view taken along line II-II of FIG. 1D-1, and FIG. A cross-sectional view taken along line III-III of Fig. 1D-1. After the spacers 124 are formed on the sidewalls of the first bit line 122 and the oxide layer 120, the spacers in the trenches 126 are removed by spacer etching (eg, isotropic etching), leaving a gap in the sidewalls of the trenches 126. The wall 124, and TiN as the lining layer 128 is formed in the trench 126 between the spacers 124, and the metal tungsten (W) is further filled as the second layer bit line contact window 130, but the present invention is not limited thereto. A copper contact window can also be used as the second level bit line contact window 130. Subsequently, the second layer bit line contact window 130 may be defined on the first layer bit line contact window 106 exposed in FIG. 1C-1 by a patterning process to make the first layer bit line contact window 106 and the second layer. The bit line contact windows 130 are electrically connected.

1E-1 and FIG. 1E-2, FIG. 1E-1 is a cross-sectional view of the same line segment as FIG. 1D-2, and FIG. 1E-2 is a cross-sectional view of the same line segment as FIG. 1D-3. Before the second layer of the bit line is formed, a dielectric layer 132 may be deposited on the etch stop layer 118, and the dielectric layer is smoothed by chemical mechanical polishing so that the second layer of the bit line contact window 130 exposes the metal tungsten. a surface, and a second bit line 134 formed of Ti/Al, such as a second bit line 134 and a second layer bit line contact window, is formed on the dielectric layer 132 and the second layer bit line contact window 130. The 130 is electrically contacted and electrically connected to the doped region 104 by the first and second bit line contact windows 106 and 130. Thereafter, a mask layer 136 is formed on the second bit line 134, and an intermediate layer (not shown) such as Ti/TiN may be disposed between the second bit line 134 and the mask layer 136. Since this embodiment is an aluminum layer As the second bit line 134, a process such as photolithography etching is employed, but the present invention is not limited thereto; in other words, if a copper interconnect is used as the second bit line 134, a copper process is required.

1F-1, FIG. 1F-2 and FIG. 1F-3, FIG. 1F-1 is a top view, FIG. 1F-2 is a cross-sectional view taken along line II-II of FIG. 1F-1, and FIG. 1F-3 is A cross-sectional view taken along line III-III of Fig. 1F-1. After the mask layer 136 is used as an etch mask to remove the second bit line 134 exposed in FIG. 1E-1, the mask layer 136 is removed to obtain a gap between the two first bit lines 122. The second bit line 134 above. Moreover, since the first bit line 122 and the second bit line 134 are double-layer bit lines 138 that are parallel to each other, the line widths of the bit lines 122 and 134 can be greater than the lower limit of the design rule of the process. (ie, the line width of the first or second layer bit line contact window 106 or 130) is more than twice, and even partial overlap of the bit lines 122 and 134 on the layout is also possible.

In addition, the process of the first embodiment may have other alternatives.

2A-1 to 2C are schematic views showing a manufacturing process of a memory structure in accordance with a second embodiment of the present invention, wherein a part of the process follows the steps in the first embodiment, and thus the same component symbols as in the first embodiment are used. To represent the same or similar components.

2A-1 and 2A-2, FIG. 2A-1 is a top view, and FIG. 2A-2 is a cross-sectional view taken along line II-II of FIG. 2A-1. This step is similar to that of FIG. 1D-1 of the first embodiment, but after forming the spacers 124 and performing the spacer etching, the metal tungsten is filled and chemical mechanical polishing (CMP) is performed, which is then at the spacers 124. Forming a second The layer line contacts the window 200 and the liner 202, but the second layer of the bit line contact window 200 is not patterned at this time. Therefore, the second layer bit line contact window 200 in FIGS. 2A-1 and 2A-2 fills the space between the spacers 124.

Next, please refer to FIG. 2B, which is a cross-sectional view of the same line segment as that of FIG. 2A-2. Forming a second bit line 134, such as Ti/Al, on the second bit line contact window 200, and the second bit line 134 is in electrical contact with the second bit line contact window 200, and The first and second bit line contact windows 106 and 200 are electrically connected to the doped region 104. Thereafter, a mask layer 136 is formed on the second bit line 134, and an intermediate layer (not shown) such as Ti/TiN may be disposed between the second bit line 134 and the mask layer 136. Of course, if the copper interconnect is used as the second bit line 134, then a copper process is required.

Next, please refer to FIG. 2C, which is a cross-sectional view of the same line segment as that of FIG. 1F-3. After the etch process is performed using the mask layer 136 as an etch mask, the mask layer 136 is removed to obtain an upper second bit line 134 between the two first bit lines 122. At this time, the second layer bit line contact window 200 under the second bit line 134 is formed by the same patterning process as the second bit line 134, so the second embodiment is at least one less than the first embodiment. Patterning process.

3A to 3E are top views of a manufacturing process of a memory structure in accordance with a third embodiment of the present invention, and the present embodiment is exemplified by NAND Flash, but the present invention is not limited thereto.

Referring to FIG. 3A, there is an isolation structure 302 and a doping region 304 as an active region of the memory structure in the substrate 300. Since the NAND flash is taken as an example in the embodiment, each doping region 304 represents a single memory device. Memory serial A portion of a (memory string), such as a drain of a select gate; if it is a memory element of another type, the doped region 304 may be part of a memory cell. The aforementioned memory cell or memory string belongs to the existing memory element, and therefore will not be described in detail in this embodiment.

Then, a plurality of first layer bit line contact windows 306a and 306b are formed on the substrate 300. Moreover, the first layer of bit line contact windows 306a is disposed in a spaced apart configuration, that is, a doped region 304 is spaced between the two first layer bit line contact windows 306a on the same cross section. As for the configuration of the first-level bit line contact window 306b, three doped regions 304 are spaced between the two first-level bit line contact windows 306b on the same cross-section to form a subsequently formed second-level bit. Line contact window contact. In addition, the first contact window 108 and the via window 110 of FIG. 1A-2 of the first embodiment can be referred to in the detailed description of the first layer of the bit line contact windows 306a and 306b.

Next, referring to FIG. 3B, a tantalum nitride layer is formed on the substrate 300 as an etch stop layer 308, which is then patterned to expose the first layer bit line contact windows 306a and 306b. The etch stop layer 308 may be other suitable materials in addition to tantalum nitride, and the present invention is not limited thereto.

Then, referring to FIG. 3C, a first bit line 310 covering the first layer bit line contact window 306a is formed on the substrate 300, wherein the first bit line 310 may be composed of Ti/Al, and the first bit line 310 An oxide layer may be formed thereon, and a barrier layer such as Ti/TiN may be disposed between the first bit line 310 and the oxide layer (refer to FIG. 1C-2 of the first embodiment). Since the present embodiment uses the aluminum layer as the first bit line 310, a process such as photolithography etching is employed, but the present invention is not limited thereto; in other words, if it is in copper As the first bit line 310, the connection requires a copper process.

Next, referring to FIG. 3D, after the spacers 312 are formed on the sidewalls of the first bit line 310, the spacers are etched to remove the underlying spacers. At this time, TiN as the liner 314 is deposited between the spacers 312. The metal tungsten (W) is further filled as the second layer bit line contact window 316, but the present invention is not limited thereto, and a copper contact window may be used as the second layer bit line contact window 316. Subsequently, the metal tungsten and the liner TiN are removed by chemical mechanical polishing, as shown in FIG. 3D, and the second layer of the bit line contact window 316 at different positions is separated by the dielectric layer after chemical mechanical polishing. Without touching each other.

Then, referring to FIG. 3E, a second bit line 318, such as Ti/Al, is formed between the two first bit lines 310, and the second bit line 318 and the second bit line contact window are formed. The 316 is electrically contacted and electrically coupled to the doped region 304 by the first and second bit line contact windows 306b and 316. Since the present embodiment uses the aluminum layer as the second bit line 318, a process such as lithography etching is employed, but the present invention is not limited thereto; in other words, if the copper interconnect is used as the second bit line 318, the copper process is required.

Because the first bit line 310 and the second bit line 318 are two-layer bit lines parallel to each other, the line widths of the bit lines 310 and 318 can be greater than the lower limit of the design specification of the process (ie, the first layer or the first The line width of the two-layer bit line contact window 306a-b or 316 is more than twice, and even a partial overlap of the bit lines 122 and 134 in the layout is also possible.

Although the memory structures are mainly used in the above first to third embodiments, the application of the present invention is not limited thereto; that is, the concept of the double-layer bit line of the present invention can also be applied to other non-memory structures. Semiconductor-like structures, such as the development of the nano-generation process, the interconnects connecting the semiconductor components must be reduced in line width, but once the line width is reduced, the resistance of the interconnects will increase. If the interconnected wires are made of double-layer wires, the wire width of the wires can be reduced by more than twice the design specification of the process while the component size is reduced, so as to reduce the sheet resistance of the interconnect wires and even replace the aluminum wires. Copper process below 40nm generation.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

106‧‧‧1st level line contact window

122‧‧‧first bit line

130‧‧‧Second layer bit line contact window

134‧‧‧second bit line

Claims (19)

A method of fabricating a memory structure, comprising: forming a plurality of memory elements; and forming a plurality of bit lines respectively connected to the memory elements, wherein the bit lines are formed by mutually parallel double-layer bit lines . The method of fabricating a memory structure according to claim 1, wherein the memory elements comprise a memory cell or a memory string. The method of fabricating a memory structure according to claim 1, wherein the bit lines comprise an aluminum layer or a copper interconnect. The method of fabricating a memory structure according to claim 1, wherein the line width of the bit lines is greater than a lower limit of a design specification of the process. The method of fabricating a memory structure according to claim 1, wherein the method of forming a plurality of bit lines comprises: forming a plurality of first bit lines on the memory elements; and A plurality of second bit lines are formed above the first bit line. The method for fabricating a memory structure according to claim 5, wherein before forming the first bit lines, further comprising: forming a plurality of first layer bit line contact windows for respectively One element is electrically contacted. The method for fabricating a memory structure according to claim 5, wherein before forming the second bit lines, further comprising: forming a plurality of second layers above the first layer bit line contact windows Bit line contact window for each of the second bits The electrical line is electrically contacted. The method for fabricating a memory structure according to claim 7, wherein the method of forming the second layer bit line contact windows and forming the second bit lines is a single patterning process. The method of fabricating a memory structure according to claim 7, wherein the second layer of bit line contact windows comprises a tungsten contact window or a copper contact window. A semiconductor structure comprising: a plurality of semiconductor elements; and a plurality of interconnect lines respectively connected to the memory elements, wherein the interconnect lines are formed by two-layer wires that are parallel to each other. The semiconductor structure of claim 10, wherein the semiconductor elements comprise memory elements. The semiconductor structure of claim 10, wherein the interconnects comprise an aluminum layer or a copper interconnect. The semiconductor structure of claim 10, wherein the line width of the interconnect lines is greater than a lower limit of a design specification of the process. The semiconductor structure of claim 10, wherein the wires of the different layers of the interconnects partially overlap in layout. The semiconductor structure of claim 10, wherein the double-layer wire comprises: a plurality of first wires; and a plurality of second wires located between the two of the first wires. The semiconductor structure of claim 15, further comprising: a plurality of first layer contact windows electrically contacting each of the first wires; and a plurality of second layer contact windows located on the first layer Above the contact window, each of the second layer contact windows is in electrical contact with each of the second wires. The semiconductor structure of claim 16, wherein the second layer contact windows are staggered. The semiconductor structure of claim 16, wherein the second layer contact windows and the second wires are formed by a single patterning process. The semiconductor structure of claim 16, wherein the second layer contact windows comprise tungsten contact windows or copper contact windows.