CN104112713B - Memory construction and its manufacture method and semiconductor element - Google Patents
Memory construction and its manufacture method and semiconductor element Download PDFInfo
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- CN104112713B CN104112713B CN201310140310.9A CN201310140310A CN104112713B CN 104112713 B CN104112713 B CN 104112713B CN 201310140310 A CN201310140310 A CN 201310140310A CN 104112713 B CN104112713 B CN 104112713B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
The invention discloses a kind of memory construction and its manufacture method and semiconductor element, the memory construction at least includes multiple memory components and multiple bit lines.Bit line connects each memory component respectively, and these bit lines are made up of bi-level digit lines parallel to each other.Accordingly, it is capable to reach by increasing bit line line width to reduce its resistance.
Description
Technical field
The memory of bit line resistance can be reduced the invention relates to a kind of semiconductor element, and in particular to a kind of
Structure and its manufacture method and semiconductor element.
Background technology
Nanometer develops the technique of memory component from generation to generation before in recent years, is received from hundreds of nanometers of techniques in one's early years to nearest 40
Technique below rice.Although each technology can increase yield, stability and the member of process yields by generation technique earlier above
The problems such as efficiency of part, is but increasingly difficult.
By taking 40 nanometer technologies as an example, because design specification (design rule) limitation of technique, can only almost use copper
Technique makes bit line.Moreover, as component size reduces, the sheet resistance of bit line inevitably can also increase, and influence element
Efficiency.
The content of the invention
It is an object of the invention to provide a kind of memory construction, bit line piece electricity can be prevented while component size reduces
Resistance increase.
, can be under the design specification of technique another object of the present invention is to provide a kind of manufacture method of memory construction
The line width of bit line is extended to more than 2 times.
A further object of the present invention is to provide a kind of semiconductor structure, and aluminium technique can be used for the member of below 40nm generations
Part.
The manufacture method of the memory construction of the present invention includes forming multiple memory components, then forms multiple bit lines point
Each memory component is not connected, wherein the bit line is made up of bi-level digit lines parallel to each other.
In one embodiment of this invention, above-mentioned memory component includes memory cell or memory tandem.
In one embodiment of this invention, above-mentioned bit line includes aluminium lamination or copper intraconnections.
In one embodiment of this invention, the line width of above-mentioned bit line is more than the lower limit of the design specification of technique.
In one embodiment of this invention, the method for the above-mentioned bit line of formation, which is included on multiple memory components, forms a plurality of
First bit line and a plurality of second bit line of formation, top of every second bit line between two adjacent first bit lines.
In one embodiment of this invention, also connect before a plurality of first bit line is formed including forming multiple first layer bit lines
Window is touched, in electrical contact with each first bit line respectively.
In one embodiment of this invention, also it is included in first layer bit line contacting window before a plurality of second bit line is formed
Top form multiple second layer bit line contacting windows, in electrical contact with each second bit line respectively.
In one embodiment of this invention, it is single patterned to form second layer bit line contacting window and the method for the second bit line
Technique.
In one embodiment of this invention, above-mentioned second layer bit line contacting window includes tungsten contact hole or copper contact hole.
The semiconductor structure of the present invention includes multiple semiconductor elements and a plurality of intraconnections.Intraconnections connects each respectively
Semiconductor element, and these intraconnections are made up of dual-layer metal line parallel to each other.
In another embodiment of the invention, above-mentioned semiconductor element includes memory component.
In another embodiment of the invention, above-mentioned intraconnections includes aluminium lamination or copper intraconnections.
In another embodiment of the invention, the line width of above-mentioned intraconnections is more than the lower limit of the design specification of technique.
In another embodiment of the invention, the wire of different layers has part overlapping in layout in above-mentioned intraconnections.
In another embodiment of the invention, above-mentioned dual-layer metal line includes a plurality of first wire and a plurality of second wire,
Every one second wire is located at the top between two the first adjacent wires.
In another embodiment of the invention, above-mentioned semiconductor structure also includes multiple first layer contact holes and multiple the
Two layers of contact hole, first layer contact hole is in electrical contact with each first wire respectively, and second layer contact hole is located at first layer contact hole
Top, wherein each second layer contact hole is in electrical contact with each second wire respectively.
In another embodiment of the invention, above-mentioned multiple second layer contact holes are interconnected.
In another embodiment of the invention, above-mentioned second layer contact hole and the second wire are with single patterned technique shape
Into.
In another embodiment of the invention, above-mentioned second layer contact hole includes tungsten contact hole or copper contact hole.
Based on above-mentioned, of the invention structure because bit line parallel to each other is divided into double-decker, work as component size
While diminution, the line width of bit line remains to more than twice of the design specification beyond technique, so bit line sheet resistance can be reduced, even
Replace the process for copper of below 40nm generations with aluminium.
For the features described above and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Brief description of the drawings
Figure 1A -1 to Fig. 1 F-3 is a kind of manufacturing process signal of memory construction according to the first embodiment of the present invention
Figure.
Fig. 2A -1 to Fig. 2 C is a kind of manufacturing process schematic diagram of memory construction according to the second embodiment of the present invention.
Fig. 3 A to Fig. 3 E are a kind of manufacturing process top views of memory construction according to the third embodiment of the present invention.
Wherein, description of reference numerals is as follows：
100、300：Substrate
102、302：Isolation structure
104、304：Doped region
106、306a、306b：First layer bit line contacting window
108：First contact hole
110：Interlayer hole
112、114、132：Dielectric layer
116：Barrier layer
118、308：Etch stop layer
120：Oxide layer
122、310：First bit line
124、312：Clearance wall
126：Raceway groove
128、202、314：Lining
130、200、316：Second layer bit line contacting window
134、318：Second bit line
136：Mask layer
138：Bi-level digit lines
Embodiment
Figure 1A -1 to Fig. 1 F-3 is a kind of manufacturing process signal of memory construction according to the first embodiment of the present invention
Figure, and the present embodiment is that by taking NAND Flash as an example, but the invention is not limited in this.
Refer to Figure 1A -1 and Figure 1A -2, Figure 1A -1 be top view, Figure 1A -2 be Figure 1A -1 II-II line segments section
Figure.In Figure 1A -1 and Figure 1A -2, there is the doped region of isolation structure 102 and the active region as memory construction in substrate 100
104, because the present embodiment is by taking NAND Flash as an example, so each doped region 104 represents single memory component, that is, to deposit
A part for reservoir tandem (memory string)；If the memory component of other classes, then doped region 104 can be storage
A part for unit.Foregoing memory cell or memory tandem belong to existing memory component, therefore in the present embodiment not
Describe in detail.And multiple first layer bit line contacting windows 106 are formed with the substrate 100, these first layer bit line contacting windows 106 can
The first contact hole 108 directly contacted with doped region 104 and the interlayer hole directly contacted with the first contact hole 108 can be included
110, such design is sometimes to coordinate the first layer position in the structure and type, therefore the present invention of memory component in itself
Linear contact lay window 106 can also only have the first contact hole 108, and without interlayer hole 110.And the configuration of first layer bit line contacting window 106
It is to adopt interval configuration, that is, across a doped region between the bit line contacting window of first layer two-by-two 106 on same profile being
104.In addition, the first contact hole 108 and interlayer hole 110 are all formed in dielectric layer 112 and 114, and in metal material
Between first contact hole 108 and dielectric layer 112 and between interlayer hole 110 and dielectric layer 114, barrier layer 116 is equipped with (such as
Ti/TiN)。
Then, refer to Figure 1B -1 and Figure 1B -2, Figure 1B -1 be top view, Figure 1B -2 be Figure 1B -1 II-II line segments
Profile.Silicon nitride layer is formed on dielectric layer 114 as etch stop layer 118, then is patterned, to expose first
Layer bit line contacting window 106.Beyond the silicon nitride of etch stop layer 118, other suitable materials can be also used, the present invention is not limited
In this.
Then, refer to Fig. 1 C-1 and Fig. 1 C-2, Fig. 1 C-1 be top view, Fig. 1 C-2 be Fig. 1 C-1 II-II line segments
Profile.The lamination being made up of Ti/Al and oxide layer 120 is formed on the first layer bit line contacting window 106 that previous step is exposed,
The lamination is patterned again and obtains the first bit line for being electrical connected via first layer bit line contacting window 106 and doped region 104
122, and can be provided with the barrier layer (not illustrating) such as Ti/TiN between the first bit line 122 and oxide layer 120.First bit line 122
Configuration be to adopt interval configuration, that is, across a doped region 104 between the first bit line 122 two-by-two on same profile being.
Now, the first layer bit line contacting window 106 not covered by the first bit line 122, can expose after the lamination is patterned.
Then, refer to Fig. 1 D-1, Fig. 1 D-2 and Fig. 1 D-3, Fig. 1 D-1 be top view, Fig. 1 D-2 be Fig. 1 D-1 II-II
Profile, Fig. 1 D-3 of line segment are the profiles of Fig. 1 D-1 III-III line segments.In the first bit line 122 and the side of oxide layer 120
Wall forms after clearance wall (spacer) 124, then is removed the clearance wall in raceway groove 126 with spacer etch (such as isotropic etching)
Remove, leave the clearance wall 124 of the side wall of raceway groove 126, and formed in the raceway groove 126 between clearance wall 124 and be used as lining (liner)
128 TiN, is further filled with tungsten (W) as second layer bit line contacting window 130, but the invention is not limited in this, also can be used
Copper contact hole is used as second layer bit line contacting window 130.Then, can be with one of Patternized technique by second layer bit line contacting window 130
It is defined on the first layer bit line contacting window 106 that Fig. 1 C-1 expose, makes first layer bit line contacting window 106 and second layer bit line contact
Window 130 is electrical connected.
Then, refer to Fig. 1 E-1 and Fig. 1 E-2, Fig. 1 E-1 be the profile of line segment identical with Fig. 1 D-2, Fig. 1 E-2 be with
The profile of the identical line segments of Fig. 1 D-3., can be prior to depositing one layer of dielectric on etch stop layer 118 before second layer bit line is made
Layer 132, and polished dielectric layer with the mode of cmp so that second layer bit line contacting window 130 exposes the table of tungsten
Face, forms the second bit line 134 being for example made up of Ti/Al, second on dielectric layer 132 and second layer bit line contacting window 130
Bit line 134 and second layer bit line contacting window 130 are in electrical contact, and by first and second layer of bit line contacting window 106 and 130 with
Doped region 104 is electrical connected.Afterwards, mask layer 136 is formed on the second bit line 134, and in the second bit line 134 and mask layer
The intermediate layer (not illustrating) such as Ti/TiN can be provided between 136.Because the present embodiment is to be used as the second bit line 134, institute using aluminium lamination
To use the techniques such as Lithography Etching, but the invention is not limited in this；In other words, if being used as second using copper intraconnections
Line 134, then need to use process for copper.
Then, refer to Fig. 1 F-1, Fig. 1 F-2 and Fig. 1 F-3, Fig. 1 F-1 be top view, Fig. 1 F-2 be Fig. 1 F-1 II-II
Profile, Fig. 1 F-3 of line segment are the profiles of Fig. 1 F-1 III-III line segments.Etching mask is being used as by the use of mask layer 136
After removing the second bit line 134 exposed in Fig. 1 E-1, then mask layer 136 removed, you can obtain in the first bit line 122 two-by-two
Between the second bit line of top 134.Moreover, because the first bit line 122 and the second bit line 134 are bi-level digit lines parallel to each other
138, so the line width of bit line 122 and 134 can all be more than lower limit (the i.e. first layer of the design specification (design rule) of technique
Or the line width of second layer bit line contacting window 106 or 130), up to more than twice, even bit line 122 and 134 is in layout (Layout)
On have part it is overlapping also feasible.
In addition, the technique of first embodiment can also have other alternative solutions.
Fig. 2A -1 to Fig. 2 C is a kind of manufacturing process schematic diagram of memory construction according to the second embodiment of the present invention,
Some processes therein continue to use the step in first embodiment, therefore are represented using with first embodiment identical component symbol
Same or analogous component.
Refer to Fig. 2A -1 and Fig. 2A -2, Fig. 2A -1 be top view, Fig. 2A -2 be Fig. 2A -1 II-II line segments section
Figure.The step is similar with Fig. 1 D-1 of first embodiment, but after forming clearance wall 124 and finishing spacer etch,
Tungsten is filled up, and does cmp (CMP), second layer bit line contacting window 200 can be now formed between clearance wall 124
With lining 202, but now not to second layer bit line contacting window 200 carry out Patternized technique.Therefore, in Fig. 2A -1 and Fig. 2A -2
Second layer bit line contacting window 200 can be filled in the space between clearance wall 124.
Then, Fig. 2 B are refer to, it is the profile of line segment identical with Fig. 2A -2.In on second layer bit line contacting window 200
The second bit line 134 being for example made up of Ti/Al is formed, the second bit line 134 and second layer bit line contacting window 200 are in electrical contact, and
By first and second layer of bit line contacting window 106 with 200 and be electrical connected with doped region 104.Afterwards, on the second bit line 134
Mask layer 136 is formed, and can be provided with the intermediate layer (not illustrating) such as Ti/TiN between the second bit line 134 and mask layer 136.When
So, if using copper intraconnections as the second bit line 134, now needing to use process for copper.
Then, Fig. 2 C are refer to, it is the profile of line segment identical with Fig. 1 F-3.Etching is being used as by the use of mask layer 136
Mask is etched after technique, then mask layer 136 is removed, you can obtain the top second between the first bit line 122 two-by-two
Bit line 134.Now, the second layer bit line contacting window 200 below the second bit line 134 is and the second same pattern of bit line 134
Chemical industry skill is formed, so second embodiment one of Patternized technique at least fewer than first embodiment.
Fig. 3 A to Fig. 3 E are a kind of manufacturing process top views of memory construction according to the third embodiment of the present invention, and
And the present embodiment is that by taking NAND Flash as an example, but the invention is not limited in this.
Fig. 3 A are refer to, the doped region for having isolation structure 302 and the active region as memory construction in substrate 300
304, because the present embodiment is by taking NAND Flash as an example, so each doped region 304 represents single memory component, that is, to deposit
The drain electrode of a part for reservoir tandem (memory string), such as selection grid (select gate)；If other classes
Memory component, then doped region 304 can be a part for memory cell.Foregoing memory cell or memory tandem belong to existing
Memory component, therefore be not explained in detail in the present embodiment.
Then, multiple first layer bit line contacting window 306a and 306b are formed with substrate 300.And first layer bit line connects
The configuration for touching window 306a is to adopt interval configuration, that is, is interval between the bit line contacting window of the first layer two-by-two 306a on same profile
A doped region 304.Configuration as first layer bit line contacting window 306b is then first layer bit line two-by-two on same profile
Across three doped regions 304 between contact hole 306b, to be contacted with the second layer bit line contacting window being subsequently formed.In addition, the
One layer of bit line contacting window 306a and 306b detailed generation type can refer to Figure 1A -2 of first embodiment the first contact hole 108
And interlayer hole 110, therefore repeated no more in the present embodiment.
Then, Fig. 3 B are refer to, silicon nitride layer is formed on substrate 300 and is schemed as etch stop layer 308, then to it
Case, to expose first layer bit line contacting window 306a and 306b.Beyond the silicon nitride of etch stop layer 308, other can be also used
Suitable material, the present invention is not limited thereto.
Then, Fig. 3 C are refer to, covering first layer bit line contacting window 306a the first bit line 310 is formed on substrate 300,
Wherein the first bit line 310 can be made up of Ti/Al, and oxide layer can be formed with the first bit line 310, and in the He of the first bit line 310
The barrier layer (Fig. 1 C-2 that can refer to first embodiment) such as Ti/TiN can be provided between oxide layer.Because the present embodiment is with aluminium
Layer uses the techniques such as Lithography Etching as the first bit line 310, but the invention is not limited in this；In other words, if with
Copper intraconnections then needs to use process for copper as the first bit line 310.
Then, Fig. 3 D are refer to, after the side wall formation clearance wall 312 of the first bit line 310, and spacer etch are finished
Bottom clearance wall is removed, the TiN of lining 314 is now first deposited as between clearance wall 312, tungsten (W) conduct is further filled with
Second layer bit line contacting window 316, but the invention is not limited in this, also copper contact hole can be used to be used as second layer bit line contacting window
316.Then with cmp mode by tungsten and lining TiN abrade now can as shown in Figure 3 D, the of diverse location
Two layers of bit line contacting window 316 can be because after cmp, and is separated by dielectric layer, without contacting with each other.
Then, Fig. 3 E are refer to, the top between the first bit line 310 two-by-two forms second be for example made up of Ti/Al
Bit line 318, the second bit line 318 and second layer bit line contacting window 316 are in electrical contact, and pass through first and second layer of bit line contacting window
306b with 316 and be electrical connected with doped region 304.Because the present embodiment is using aluminium lamination as the second bit line 318, so using light
The techniques such as etching quarter, but the invention is not limited in this；In other words, if using copper intraconnections as the second bit line 318, then
Process for copper need to be used.
Because the first bit line 310 and the second bit line 318 are bi-level digit lines parallel to each other, the line of bit line 310 and 318
The lower limit (i.e. first layer or second layer bit line contacting window 306a-b or 316 line width) of the wide design specification that can be all more than technique,
Up to more than twice, even bit line 122 has part overlapping also feasible with 134 in layout.
Though the above first is into 3rd embodiment based on memory construction, the application of the present invention is not limited to this；
That is, the concept of bi-level digit lines of the invention can be used for other based semiconductor structures of non-memory structure, for example develop into
Nanometer later technique from generation to generation, connects the intraconnections of semiconductor element due to closer to each other so must reduce line width therewith, but
Once line width is reduced, the resistance of intraconnections can also increase therewith, so such as constituted intraconnections parallel to each other with dual-layer metal line,
The line width of wire while component size reduces, can be made beyond more than twice of the design specification of technique, to reduce intraconnections
Sheet resistance, or even with aluminium replace the 40nm generations below process for copper.
Although the present invention is disclosed as above with embodiment, so it is not limited to the present invention, any art
Middle technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore the protection of the present invention
Scope is worked as to be defined depending on the scope of the appended claims person of defining.
Claims (14)
1. a kind of manufacture method of memory construction, it is characterised in that the manufacture method includes：
Form multiple memory components；
The multiple first layer bit line contacting windows for being arranged in number row are formed, wherein each first layer bit line contacting window connects each respectively
Memory component, and the plurality of first layer bit line contacting window of adjacent row is interconnected；
The first bit line is formed on the first layer bit line contacting window every a row, wherein first bit line is with being arranged in same row
The first layer bit line contacting window contact；
Multiple second layer bit line contacts are formed in the top not with the plurality of first layer bit line contacting window of first bit line contact
Window；And
A plurality of second bit line is formed on the plurality of second layer bit line contacting window, wherein every second bit line is with being arranged in same row
Second layer bit line contacting window contact, and first bit line and a plurality of second bit line are parallel to each other.
2. the manufacture method of memory construction as claimed in claim 1, it is characterised in that the plurality of memory component includes depositing
Storage unit or memory tandem.
3. the manufacture method of memory construction as claimed in claim 1, it is characterised in that first bit line with this plurality of second
Bit line includes aluminium lamination or copper intraconnections.
4. the manufacture method of memory construction as claimed in claim 1, it is characterised in that first bit line with this plurality of second
The line width of bit line is more than the lower limit of the design specification of technique.
5. the manufacture method of memory construction as claimed in claim 1, it is characterised in that：The plurality of second layer bit line is formed to connect
The method that window is touched with forming a plurality of second bit line is single patterned technique.
6. the manufacture method of memory construction as claimed in claim 1, it is characterised in that the plurality of second layer bit line contacting window
Including tungsten contact hole or copper contact hole.
7. a kind of semiconductor structure, it is characterised in that the semiconductor structure includes：
Multiple semiconductor elements；
Multiple first layer contact holes of number row are arranged in, wherein each first layer contact hole connects each semiconductor element respectively,
And the plurality of first layer contact hole of adjacent row is interconnected；
Dielectric layer, position is between the plurality of first layer contact hole；
A plurality of first wire, is contacted with the first layer contact hole every a row respectively；
Multiple second layer contact holes, position in top not with the plurality of first layer contact hole of a plurality of first conductive contact, and
It is connected with the plurality of first layer contact hole, wherein the upper surface of the plurality of second layer contact hole is higher than the upper surface of the dielectric layer；
And
A plurality of second wire, wherein every second wire is contacted with being arranged in the second layer contact hole of same row, and this is a plurality of
Second wire and a plurality of first wire are parallel to each other.
8. semiconductor structure as claimed in claim 7, it is characterised in that the plurality of semiconductor element includes memory component.
9. semiconductor structure as claimed in claim 7, it is characterised in that a plurality of first wire and a plurality of second wire bag
Include aluminium lamination or copper intraconnections.
10. semiconductor structure as claimed in claim 7, it is characterised in that a plurality of first wire and a plurality of second wire
Line width is more than the lower limit of the design specification of technique.
11. semiconductor structure as claimed in claim 7, it is characterised in that in a plurality of first wire and a plurality of second wire
The wire of different layers has part overlapping in layout.
12. semiconductor structure as claimed in claim 7, it is characterised in that the plurality of second layer contact hole is interconnected.
13. semiconductor structure as claimed in claim 7, it is characterised in that the plurality of second layer contact hole a plurality of second is led with this
Line is with the formation of single patterned technique.
14. semiconductor structure as claimed in claim 7, it is characterised in that the plurality of second layer contact hole include tungsten contact hole or
Copper contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310140310.9A CN104112713B (en) | 2013-04-22 | 2013-04-22 | Memory construction and its manufacture method and semiconductor element |
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| CN201310140310.9A CN104112713B (en) | 2013-04-22 | 2013-04-22 | Memory construction and its manufacture method and semiconductor element |
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| CN104112713B true CN104112713B (en) | 2017-10-20 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1162845A (en) * | 1996-01-12 | 1997-10-22 | 株式会社日立制作所 | Semiconductor integrated circuit device and method for manufacturing the same |
| US6624460B1 (en) * | 2002-08-15 | 2003-09-23 | Macronix International Co., Ltd. | Memory device with low resistance buried bit lines |
| KR100497912B1 (en) * | 2001-06-29 | 2005-06-29 | 가부시끼가이샤 도시바 | Semiconductor device and manufacturing method thereof |
| CN102768848A (en) * | 2011-05-02 | 2012-11-07 | 海力士半导体有限公司 | Semiconductor device, semiconductor module and method of manufacturing the same |
| US8350310B2 (en) * | 2009-02-20 | 2013-01-08 | Fujitsu Semiconductor Limited | Semiconductor device including memory cell having capacitor |
-
2013
- 2013-04-22 CN CN201310140310.9A patent/CN104112713B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1162845A (en) * | 1996-01-12 | 1997-10-22 | 株式会社日立制作所 | Semiconductor integrated circuit device and method for manufacturing the same |
| KR100497912B1 (en) * | 2001-06-29 | 2005-06-29 | 가부시끼가이샤 도시바 | Semiconductor device and manufacturing method thereof |
| US6624460B1 (en) * | 2002-08-15 | 2003-09-23 | Macronix International Co., Ltd. | Memory device with low resistance buried bit lines |
| US8350310B2 (en) * | 2009-02-20 | 2013-01-08 | Fujitsu Semiconductor Limited | Semiconductor device including memory cell having capacitor |
| CN102768848A (en) * | 2011-05-02 | 2012-11-07 | 海力士半导体有限公司 | Semiconductor device, semiconductor module and method of manufacturing the same |
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| CN104112713A (en) | 2014-10-22 |
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