TW201435605A - Re-driver power management - Google Patents

Abstract

The present disclosure provides techniques for increasing the power efficiency of re-drivers by providing a technique for a re-driver to recognize a variety of power states. A message generator may be located in a host device and may encode a signal indicating a change in a power state. The message may be transmitted to a message decoder located in a re-driver. The message decoder may decode the message and the re-driver may enter a power state in response to the decoded message.

Description

Re-driver power management

The disclosure of the present invention relates to an input/output (I/O) signal communication protocol. In more detail, this disclosure relates to a signal communication protocol for power management of a re-driver.

As the data rate of high speed I/Os continues to increase, the length of the associated cable that is supported tends to decrease due to signal degradation. In order to increase the length of the supported cable, the re-driver is often used to reduce signal degradation. In particular, the re-driver can amplify the signal and, in the case of differential transmission diffracting, re-arrange the signal and re-synchronize the signal.

The present disclosure provides techniques for increasing the power efficiency of the re-driver. In particular, some embodiments described herein provide techniques for re-routing drivers to distinguish power supply levels, including various low power supply levels.

As the data rate of high speed I/Os continues to increase, the associated cable length supported thus begins to decrease. This is because the channel of the current interconnection will They manifest themselves as low-pass filters, which results in signal degradation in the voltage domain not only due to channel losses, but also jitter in the time domain due to inter-symbol interference (ISI). The longer the channel passes through the channel, the more attenuated and distorted the signal. In order to overcome the more attenuated signal quality as the same data rate increase is achieved in the same channel, the re-driver can be used to reform the signal. This can be accomplished by using a mechanism that equalizes the channel through the transmitter pre-equalization and receiver equalization to offset the channel attenuation and minimize the channel distortion.

Although these re-drivers can improve the channel, they encounter significant obstacles in device power management when high-speed I/O enters a lower power state, mainly due to the limited awareness of the I/O activity. resulting in. In the case of a re-driver for a PCIe or USB3 application, the re-driver can only recognize some connection status, such as connection, active or electrical idle (EI). If the link enters a different low power state, the transfer drive cannot be resolved (eg, L0s, L1, and L2/L3 in the case of PCIe applications, or U1, U2, and U3 in the case of USB3 applications). If the re-driver structure uses a single low power state that reflects the connections in the EI, the re-driver can consume power that is idle in the tens of milliwatts scale. By enabling the re-driver to recognize a wide range of power states, the re-driver can be made more energy efficient, thus enabling the re-driver to be used in high energy efficiency systems.

Figure 1 is a block diagram of a high speed interconnect link topology. The host 102 can be connected to the device 104 via the re-driver 106. The host 102 can be as in a mobile phone, a laptop, a desktop computer or a tablet computer. A computing device such as this. The device 104 can be a high speed input/output (IO) device as if it were a high speed, dual simplex connection. For example, the device 104 can be a USB device, such as a USB1 device, a USB2 device, or a USB3 device. As used herein, the term USB is used to refer to any USB protocol, including USB1, USB2, USB3, or any other USB protocol, including USB protocols that can be developed in the future. In another example, the device 104 can include a bonded link, such as a Thunderbolt interface. In a still further example, the device 104 can be a PCIe device. In one example, the host 102, the redriver 106, and the device 104 can be connected through a system bus and/or interface. The re-driver 106 can be adapted to receive a message, such as a PWM message, indicating that the re-driver 106 is entering a particular power state. The re-driver 106 can enter the power state in accordance with the indication included in the message. In connection with Figures 5 and 7, the re-driver 106 will be described further below.

2 is a block diagram of a computing system consistent with an embodiment. The computing system 200 can be, for example, a mobile phone, a laptop, a desktop or a tablet, and the like. The computing system 200 can include an indication that the processor 202 is adapted to perform storage, and similarly, the memory device 204 stores instructions for execution by the processor 202. The processor 202 can be a single core processor, a multi-core processor, a computing cluster, or any number of other configurations. The memory device 204 can include random access memory (eg, SRAM, DRAM, zero capacitor RAM, SONOS, eDRAM, EDO RAM, DDR RAM, RRAM, PRAM, etc.), read only memory Body (eg, Mask ROM, PROM, EPROM, EEPROM, etc.), flash memory, or any other suitable memory system.

The processor 202 can be connected to an input / output (I / O) device interface 208 via system bus 206 (e.g., PCI, ISA, PCI-Express , HyperTransport ®, NuBus , etc.), adapted to connect the computing system 200 To one or more I/O devices 210. The I/O devices 210 can include, for example, a keyboard and a pointing device, wherein the pointing device can include a touch pad or a touch screen, and the like. The I/O device 210 can be a built-in component of the computing system 200 or can be externally coupled to the computing system 200.

The processor 202 can also be coupled to the display interface 212 via the system bus 206, which is adapted to connect the computing system 200 to the display device 214. The display device 214 can include a display screen that is a built-in component of the computing system 200. The display device 214 can include a computer screen, a television, a projector, and the like that are externally coupled to the computing system 200.

A network interface card (NIC) 216 can be adapted to connect the computing system 200 to a network (not depicted) via the system bus 206. The network (not depicted) can be a wide area network (WAN), a local area network (LAN), or the Internet, and the like.

The USB interface 218 can be adapted to be coupled to the computing system 200 via the system bus 206. The USB interface 218 can transmit and receive data from the USB device 220 through the re-driver 222. The re-driver 222 can accelerate the amplitude of the signal to overcome signal degradation. When using differential The re-driver 222 can also re-arrange the signal in order to synchronize the signal and reduce interference. The re-driver can be adapted to receive a power status message indicating that the re-driver is entering a different power state. For example, the re-driver can include a receiver for receiving the power status message, such as from a message generator in the host or device. The power status message can include a period between the states, such as between an idle state and a pulsed state. For example, the power status message can be a PWM modulation message, as further described in FIGS. 3 and 4.

It will be understood that the block diagram of FIG. 2 is not intended to indicate that the computing system 200 includes all of the elements of FIG. 2, but that the computing system 200 can include fewer or additional elements not depicted in FIG. (eg extra USB port, extra USB interface, extra internet interface, etc.).

FIG. 3 is an illustration of a PWM signal according to a pulse state and an electrical idle (EI) state consistent with the embodiment. In particular, FIG. 3 illustrates a binary pulse width modulation (PWM) signal 300. The format of the PWM signal according to the low frequency period signal (LFPS) is formed by two distinct transmit signal states, a pulse state, and an electrical idle (EI) state. The pulse state is the state when the signal is transmitted or detected. The EI state is in a state in which it is connected in an electrically idle state, and only the common mode voltage is maintained. The logical "0" 302 can be represented in the period (T) by the pulse state of the leading 1/3 period T, and the EI state of the remaining 2/3 period T follows. The logical "1" 304 can be represented in the period (T) by the pulse state of the 2/3 period T of the preamble, and the EI state of the remaining 1/3 period T follows.

Figure 4 is an example of a fixed-width PWM message consistent with the embodiment. Bright. The fixed width PWM message 400 can be constructed to allow the host or device to notify the redirector of changes in the connected power states. The fixed width PWM message 400 can be an 8-bit connection power status message. The first two cycles can be constructed as a continuous pulse state 2T. The continuous pulse state 2T can be followed by one cycle of the electrical idle EI state, the combination of the continuous pulse state 2T and one of the EI states representing the start sequence 402 of the fixed width PWM message 400. The start sequence 402 can behave as a wake-up signal to the receiver. In particular, the start sequence can inform the receiver that the message is being transmitted. A Link Power Management (LPM) message 404, such as a 4-bit LPM message, can be appended to the start sequence. The message can include a control loop between idle and Linked Power Management (LPM), which represents the PWM message 400. This loop between idle and LPM can be represented by a sequence of logics 1 and 0. The sequence of logic 1 and 0 can be associated with the LPM message 404 and can provide an indication of its power state. For example, the LPM message 404 shown in FIG. 4 is represented as a data sequence of "1001". The LPM message 404 can be followed by one of the pulse states 406. The period 406 of the pulse state can be signaled to the receiver when the end of the message has arrived. After receiving the "end" 406, depending on the message 400, the re-driver can enter a different power state.

Figure 5 is a table showing the state of the connections consistent with the embodiment and their respective triggers. The triggering action causes a change in the power state. By using a fixed-width PWM message, the re-driver can clearly know the state of the link and take the appropriate re-driver state map accordingly. In effect In the link state, the re-driver may not receive the PWM message and the re-driver state can be active (RD0). While the re-driver is receiving and generating data packets from both the host and the device, RD0 is active. In addition, the corresponding host or device status, such as the PCIe/USB3 link status, can be individually L0 or U0. If the re-driver detects a lack of signal activity, the re-driver can enter the inactive state (RD0s). RD0s are in a state where electrical idle (EI) is detected and no packets are forwarded. The re-driver can be ready to resume operation as soon as it detects an interruption in the EI state in the standby mode. The corresponding host or device status, such as PCIe/USB3 link status, can be L0s or U1 individually. If the re-driver detects an electrical idle state and receives a specific signal (LPM1), such as a PWM signal, the re-driver can enter a low power state 2, a deep low power state (RD1). RD1 can be in the state where EI is detected, and the re-driver can disable more circuits to save more power with extended exit latency. The PWM message can be received in the re-driver and can be transmitted by either the host or the device or both the host and the device. The corresponding PCIe/USB3 link status can be L1 or U2, respectively. If the re-driver detects an electrical idle state and receives another specific signal (LPM2), the re-driver can enter a low power state 3, a deeper low power state (RD2). Where longer exit latency is allowed, the RD2 is a more active low power state than the RD1, and the re-driver can be allowed to disable additional circuitry to save more power. The PWM message can be received in the re-driver and can be transmitted by either the host or the device or both the host and the device. The corresponding PCIe/USB3 link status can be L2, L3 or U3, respectively.

Figure 6 is a block diagram of a PWM message generator consistent with the embodiment. The message generator 600 can be placed in a host, such as the host. In another example, the message generator 600 can be placed in a device, such as a device. In still further examples, the first message generator 600 can be placed in a host, such as the host, and the second message generator 600 can be placed in the device, such as a device. The host can enter different power states. Immediately before entering a different power state, the host can indicate the change in power state to PWM state machine 602 via Link Power Management (LPM) 604. Instructing the power state to the PWM state machine 602 enables (En) the message generator 600 to initiate transmission of the PWM message. A ring oscillator (Rosc) 606 can send a signal. This signal can oscillate between high and low. A ring oscillator (Rosc) 606 can be coupled to the low frequency period signal (LFPS) transmitter 608 and can transmit the oscillating signal to the transmitter 608. The timing of the ring oscillator 606 can be controlled by the PWM state machine 602, which can be coupled to both the Rosc 606 and the LFPS transmitter 608. By controlling the timing of the ring oscillator 606, the PWM state machine 602 can generate a particular PWM message to transmit the power state change signal indicated by the host (not shown).

The PWM message can be formatted as illustrated in Figure 4. In particular, the PWM message can be led by a "start" message indicating that the receiver message begins. Furthermore, the PWM message can be followed by an "end" message indicating that the PWM message is complete. The PWM message can be a sequence of logic 1s and 0s, represented by the configured oscillation signal.

When the PWM message is configured in the LFPS transmitter 608, the The LFPS transmitter 608 can transmit the PWM message to the message detector via the existing data channels 610 TxP and TxN. These data channels can carry differential signals. Additionally, the LFPS transmitter 608 can be coupled to the data channels in parallel with a USB transmitter (not shown). The USB transmitter can be a USB overspeed transmitter. When the USB system actively transmits a message, the LFPS transmitter 608 may not actively transmit a message. This implementation of PWM message generator 600 can be included in the existing LFPS circuitry in accordance with local clock generator (Rosc) 606 and LFPS transmitter 608.

The block diagram of Figure 6 is not intended to indicate that the message generator 600 includes all of the elements shown in Figure 6. Further, depending on the details of the particular implementation, the message generator 600 can include any number of additional elements not shown in FIG.

Figure 7 is a block diagram of a PWM message detector consistent with the embodiment. The message detector 700 can include a receiver 702, such as a low frequency periodic signal (LFPS) receiver 702. The LFPS receiver 702 can be connected in parallel to the existing data channels 704 RxP and RXN in parallel and can receive PWM messages transmitted by a message generator located in the host or device. When the message is received in the receiver 702, the message can be transmitted to the LFPS Envelope Detector 706. This message can be an oscillating signal to represent binary information. The envelope detector 706 can extract the binary information from the oscillating signal, that is, the sequence of 1s and 0s. This binary information can be transmitted to the PWM message decoder 708. The PWM message decoder 708 can decode the binary information to determine the power management state that the redriver is instructed to enter. The Rosc can operate the state machine and assist in the detection, decoding, and regeneration.

When the PWM message decoder 708 has decoded the message, the PWM message decoder 708 transmits the message to the transit driver link power management (LPM) 712. The link power management 712 places the transfer driver in a power state in accordance with the decoded message. The power state can be one of an active, ready to use, deep low power state, and a deeper low power state. The PWM message detector 700 can be included in the existing LFPS circuit in accordance with the Rosc and LFPS transceivers.

The block diagram of FIG. 7 is not intended to indicate that the message detector 700 includes all of the elements shown in FIG. Further, depending on the details of the particular implementation, the message detector 700 can include any number of additional components not shown in FIG.

Figure 8 is a flow diagram illustrating a method of detecting a state of a connected power source consistent with an embodiment. In block 802, the power status message can be encoded. In one example, the power status message can be a fixed width pulse width modulation (PWM) message. This message can be encoded in the state machine of the message generator. The message generator can be placed in a host or device. In one example, the host can be a computing device, such as a laptop or desktop computer. In another example, the device can be a USB device, such as a USB2 device, a USB3 device, or a USB 3.5 device. In another example, the device can be a PCIe device. This state machine can be a pulse width modulation (PWM) state machine. The state machine can be coupled to a clock, such as a ring oscillator (Rosc) clock, which can transmit a signal that oscillates between high and low, enabling the state machine to encode the power state message. The state machine can also be electrically coupled to the transmitter.

At block 804, the power status message can be transmitted to the re-driver. In one example, the transmitter can be a low frequency periodic signal (LFPS) transmitter that can transmit the encoded power status message to the transponder via a data path that can carry the differential signal, thereby reducing interference.

At block 806, the encoded power status message can be received in the re-driver. The encoded power status message can be received in a message detector integrated with the re-driver. In particular, the encoded power status message can be received in the receiver via a data path carrying the differential signal. The receiver can be a low frequency period signal (LFPS) receiver. The encoded signal can pass through an envelope detector to a message decoder, which can be a PWM message decoder that can be electrically coupled to a clock generator, such as a ring oscillator.

At block 808, the power status message can be decoded. In particular, the power status message can be decoded by the message decoder. The Rosc can be enabled by detection of the message. The Rosc can supply the oversampled clock to the PWM message decoder to decode the message after the envelope detector.

At block 810, the re-driver can enter a power state based on at least a portion of the power status message. The power status message can be one of an active, inactive, deep low power state or a deeper low power state. The re-driver can enter the power state based on a combination of the decoded power state message and the detection of an electrical idle (EI) link state. By using a fixed-width PWM message, the re-driver can clearly know the link status and take the appropriate re-driver power state map.

100‧‧‧High speed interconnect link topology

102‧‧‧Host

104‧‧‧ device

106‧‧‧Replacement drive

200‧‧‧ Computing System

202‧‧‧ processor

204‧‧‧ memory device

206‧‧‧System Bus

208‧‧‧Input/Output (I/O) device interface

210‧‧‧I/O devices

212‧‧‧Display interface

214‧‧‧ display device

216‧‧‧Network Interface Card

218‧‧‧USB interface

220‧‧‧USB device

222‧‧‧Replacement drive

300‧‧‧Digital Pulse Width Modulation (PWM) Signal

302‧‧‧Logic: "0"

304‧‧‧Logic: "1"

400‧‧‧Fixed Width PWM Message

402‧‧‧Start sequence

404‧‧‧Link Power Management (LPM) Message

406‧‧‧One cycle of pulse state

600‧‧‧Message Generator

602‧‧‧PWM state machine

604‧‧‧Link power management

606‧‧‧ Ring Oscillator

608‧‧‧Low Frequency Periodic Signal (LFPS) Transmitter

610‧‧‧ data channel

700‧‧‧Message Detector

702‧‧‧ Receiver

704‧‧‧data channel

706‧‧‧Encapsulation detector

708‧‧‧PWM Message Decoder

710‧‧‧ Ring Oscillator

712‧‧‧Link power management

800‧‧‧ method

802‧‧‧ block

804‧‧‧ Block

806‧‧‧ Block

808‧‧‧ Block

810‧‧‧ Block

BRIEF DESCRIPTION OF THE DRAWINGS Some exemplary embodiments will be described with reference to the drawings in which: FIG. 1 is a block diagram of a high speed interconnect link topology; FIG. 2 is a block diagram of a computing system; FIG. 3 is a PWM according to a pulse state and an idle idle EI state. Figure 4 is an example of a fixed-width PWM message; Figure 5 is a table showing the connection status and their respective triggers; Figure 6 is a block diagram of the PWM message generator; Figure 7 is a block of the PWM message detector. Figure 8 is a flow chart illustrating a method of detecting a state of a connected power source.

Example 1

One method is disclosed herein. The method includes receiving a power status message in the re-driver. The power status message can correspond to a power state of the port coupled to the transfer driver. The method also includes decoding the power status message and entering the re-driver into the re-driver power state in accordance with the power status message. The power status message includes a loop between the idle state and the pulse state.

If the power state of the device is the USB U2 state, the power state of the re-driver can be the RD1 power state. If the power state of the device In the USB U3 state, the transfer drive power state can be the RD2 power state. The re-driver can enter one of at least four different power states. The method can include entering a power state in accordance with a combination of the power state message and the detection of an electrical idle (EI) link state. The power status message can be a Pulse Width Modulation (PWM) message that can be received from a data channel carrying a differential signal.

Example 2

One method is disclosed herein, the method comprising detecting a link state of a port, decoding a power state message corresponding to the power state of the port, and transmitting the power state message to the re-driver. The power status message includes a loop between the idle state and the pulse state.

The message generator can be placed in one of the host or device. The power status message can be a Pulse Width Modulation (PWM) message. The power status message can be transmitted by the low frequency periodic signal transmitter. The power status message can be transmitted via a data channel carrying a differential signal.

Example 3

An electronic device disclosed herein includes a transmitter and a state machine for controlling the transmitter to encode a pulse width modulated (PWM) power state message and transmitting the encoded power state message to the redirect driver.

The transmitter can be a low frequency period signal (LFPS) transmitter. The power status message can be transmitted on the data channel carrying the differential signal. This power status message can be transmitted from a high speed, dual simplex device. The power state The message can be transmitted from a USB device, a USB2 device, a USB3 device, a PCIe device, or a Thunderbolt device.

Example 4

A re-driver is disclosed herein. The re-driver includes a receiver to receive a pulse width modulation (PWM) power state message from a port coupled to the re-driver. The re-driver also includes a message decoder to decode the PWM power status message and the controller to enter the re-driver into the re-driver power state in accordance with the power status message.

The receiver is a low frequency period signal (LFPS) receiver. The re-driver can enter a power state in response to detection of an electrical idle (EI) link state and a combination of the power state messages. The power status message can be received from a data channel carrying a differential signal.

Example 5

A system is disclosed herein. The system includes a message generator. The message generator includes a state machine to encode a power status message and a transmitter to transmit the encoded power status message. The system also includes a message detector. The message detector includes a receiver to receive the transmitted encoded power status message and a message decoder to decode the encoded power status message. The message detector is integrated with the re-driver and the re-driver enters a power state based on the power status message.

The power status message can be a Pulse Width Modulation (PWM) message. If the power state of the port is USB U2 state, the transfer drive state can be RD1 Power status. If the power state of the device is USB U3 state, the transfer driver can be in the RD2 power state. The crucible can be disposed of in a device that includes a high speed, double simplex connection. The device can be disposed on one of a USB device, a USB2 device, a USB3 device, a PCIe device, or a Thunderbolt device. The re-driver can enter one of at least four different power states. The re-driver can enter the power state according to the power status message and the electrical idle (EI) link state. The power status message can be transmitted on the data channel carrying the differential signal.

The terms "coupled" and "connected", along with their derivatives, can be used in the foregoing description of the invention and the scope of the claims. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupling" can mean that two or more elements are directly physics. Or electrical contact. However, "coupled" can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

Certain embodiments can be implemented in one or a combination of hardware, firmware or software. Some embodiments can also be like instructions stored on a machine readable medium that can be read and executed by a computing platform to perform the operations described herein. A machine-readable medium can include any mechanism for storing or transmitting information in a machine readable form, such as a computer. For example, a machine-readable medium can include a read only memory (ROM), a random access memory (RAM), a disk storage medium, an optical storage medium, a flash memory device, or an electric, optical, acoustic, or propagating device. Other forms of signals, such as carrier waves, infrared signals, and numbers Bit signal or interface for transmitting and/or receiving signals, etc.

The embodiment is an embodiment or an example in which "the embodiment", "an embodiment", "some embodiments", "various embodiments" or "other embodiments" are used to indicate an embodiment. Particular features, structures, or characteristics are included in at least some embodiments, but are not necessarily all embodiments of the invention. The various embodiments of the "embodiment", "an embodiment" or "an embodiment" are not necessarily all referring to the same embodiment. Elements or forms from the embodiments can be combined with elements or forms of another embodiment.

Not all of the components, features, structures, features, etc. described and illustrated herein are required to be included in a particular embodiment or some embodiments. If the components, features, structures or features described in this specification are "may be", "maybe", "can" or "may" be included, for example, specific components, features, structures, and features are not required to be included. If the specification or the scope of the patent application mentions "a" element, it does not mean that there is only one element. If the specification or the scope of the patent application mentions "extra" elements, it does not exclude that there will be more than one additional element.

It is to be noted that while certain embodiments have been described with reference to particular implementations, other implementations are possible in accordance with certain embodiments. In addition, the arrangement of the circuit elements or other arrangements and/or sequences described herein are not necessarily to be construed in a particular form or description. Many other arrangements are possible in accordance with certain embodiments.

For each system in the drawings, the components may have the same reference numerals or different reference numerals in some cases to suggest the representative components. Can be different and / or similar. However, the components can be flexible enough to have different implementations and operate with some or all of the systems described or occurring herein. The various components shown in the figures can be the same or different. Which one is called the first element and which one is called the second element is arbitrary.

In the foregoing description, various aspects of the disclosed invention have been described herein. For the purposes of explanation, specific numbers, systems, and configurations are presented to provide a thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the disclosure of the present invention may be realized without the specific details. In other instances, known features, components or modules are deleted, simplified, combined or separated to make the invention clear.

The present invention has been described by way of example with reference to the accompanying drawings. The various modifications of the described embodiments, as well as other embodiments of the invention, are apparent to those of ordinary skill in the art.

While the illustrated techniques can be tolerated by various modifications and alternative forms, the exemplary examples discussed above have been shown in an exemplary manner. It is to be understood that the technology is not intended to be limited to the particular embodiments disclosed herein. Rather, the illustrated techniques include all alternatives, modifications, and equivalents and scope of the scope of the appended claims.

Claims (25)

A method comprising: receiving a power status message in a transit drive, the power status message corresponding to a power state coupled to the switch driver; decoding the power status message; and causing the switch according to the power status message The driver enters a re-driver power state, wherein the power state message includes a loop between the electrical idle state and the pulse state. The method of claim 1, wherein the power state of the re-driver is a power state of the RD1 if the power state of the device is a USB U2 state. The method of claim 1, wherein the re-driver power state is a RD2 power state if the power state of the device is a USB U3 state. The method of claim 1, wherein the re-driver enters one of at least four different power states. The method of claim 1, wherein the method of entering the power state is based on a combination of the detection of the power state message and the electrical idle (EI) link state. The method of claim 1, wherein the power status message includes a pulse width modulation (PWM) message. The method of claim 1, wherein the power status message is received by a data channel carrying a differential signal. The method of claim 1, wherein the power status message is transmitted from one of a USB device, a PCIe device, or a Thunderbolt device. A method comprising: detecting a link state of a port; encoding a power state message corresponding to the power state of the port; and transmitting the power state message to the re-driver; wherein the power state message includes an idle state and a pulse state The loop between. The method of claim 9, wherein the message generator is located in one of a host and a device. The method of claim 9, wherein the power status message comprises a pulse width modulation (PWM) message. The method of claim 9, wherein the power status message is transmitted by a low frequency periodic signal transmitter. The method of claim 9, wherein the power status message is received via a data channel carrying a differential signal. The method of claim 9, wherein the power status message is transmitted from one of a USB device, a PCIe device, or a Thunderbolt device. An electronic device comprising: a transmitter; a state machine that controls the transmitter to encode a Pulse Width Modulation (PWM) power status message and transmits the encoded power status message to the re-driver. The device of claim 15, wherein the transmitter is a low frequency periodic signal (LFPS) transmitter. The device of claim 15, wherein the power status message is transmitted on a data channel carrying the differential signal. The device of claim 15 wherein the power status message is transmitted from a device comprising a high speed, dual simplex link. The device of claim 15, wherein the power status message is transmitted from one of a USB device, a PCIe device, or a Thunderbolt device. A re-driver includes: a receiver for receiving a pulse width modulation (PWM) power state message from a port coupled to the re-driver; and a message decoder for decoding the pulse width modulation power state message; And a controller for causing the re-driver to enter a re-driver power state according to the power status message. The system of claim 20, wherein the receiver is a low frequency period signal (LFPS) receiver. The system of claim 20, wherein the re-driver enters a power state in response to detection of an electrical idle (EI) link state and a combination of the power state messages. The system of claim 20, wherein the power status message is received from a data channel carrying the differential signal. The system of claim 20, wherein the power source The status message is transmitted from one of a USB device, a PCIe device, or a Thunderbolt device. A system comprising: a message generator comprising: a state machine for encoding a power status message and a transmitter for transmitting the encoded power status message; and a message detector comprising: a receiver for receiving the transmitted The encoded power status message and message decoder is for decoding the encoded power status message, wherein the message decoder is integrated with the transfer driver and wherein the transfer driver enters a power state according to the power status message.