JP2014033073A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow a consumption current in a power-saving mode to be reduced and prevent an indefinite signal from propagating from an output circuit with power being turned off to an input circuit with power being turned on, thereby suppressing a through current and stabilizing a circuit operation.SOLUTION: A semiconductor device comprises: a circuit block 11A for generating a first control signal and a second control signal, respectively, so as to correspond to predetermined states; a power supply switch SW inserted in a power feeding path, whose on/off operations are controlled in response to the first control signal; a circuit block 12A including a circuit in which the second control signal is inputted, a third control signal is outputted, and power feeding is stopped when the power supply switch is turned off; and a circuit block 13A including a circuit to which the third control signal is inputted. When turning off the power supply switch while setting the first control signal as a non-active state, the second control signal is settled in a predetermined value, and after a value of the third control signal supplied from the circuit block 12A to the circuit block 13A is settled in a predetermined value, the first control signal is shifted from an active state to the non-active state.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an interface device.

  FIG. 1 is a diagram for explaining an interface of USB (Universal Serial Bus) 3.0. USB is a serial bus standard that connects host devices to various peripheral devices. In USB3.0, the maximum data transfer rate is 5 Gbps (Gigabits per second), and the technology of PCI (Peripheral Component Interconnect) Express2.0 is applied to the physical layer (PHY). In addition, the power management function has been enhanced in USB3.0. In USB3.0, the power supply capacity is 900 mA in the U0 state, but the current consumption per average time is 2.5 mA or less in the suspended state (for example, the U3 state). Referring to FIG. 1, a link layer (LINK) 11 includes a transmission circuit (TX BLOCK) that packetizes transmission data and transmits it, a reception circuit (RX BLOCK) that decomposes a reception packet (depacketizes) and acquires data, and It includes a link training status state machine LTSSM (LINK Training & Status State Machine) for managing the link state and a port logic (PORT LOGIC) including a control status register (Control Status Register). In FIG. 1, link power management LPM (LINK Power Management) included in the port logic (PORT LOGIC) is not shown.

  The PIPE layer 12 receives a 2-bit signal POWER DOWN [1: 0] (representing the U0 to U3 states) from the LTSSM in the LINK layer 11, and from the transmission circuit (TX BLOCK) in the LINK layer 11. A transmitting circuit (TX BLOCK) that converts the signal of the signal of the PHY layer 13 and a receiving circuit that converts the signal from the receiving circuit (RX BLOCK) of the PHY layer 13 and outputs the signal to the receiving circuit (RX BLOCK) of the LINK layer 11 ( RX BLOCK).

  The physical layer (PHY) 13 receives the signal from the transmission circuit (TX BLOCK) of the PIPE layer 12 and serially receives the signal from the input terminal DIN and the transmission circuit (TX BLOCK) that serially outputs to the output terminal DOUT. A reception circuit (RX BLOCK) that outputs to the reception circuit (RX BLOCK) of the layer 12, an LFPS (Low Frequency Periodic Signaling) detection circuit, and a logic circuit that controls these circuits are provided. A low frequency burst signal called LFPS (Low Frequency Periodic Signaling) is used as a sideband signal for returning from the power down (sleep) state. After the link is established, it operates at 5 Gbps. When the link is not established, communication is performed in a mode in which the link speed is lowered. The control signal (RXelecIdle) from the LFPS detection circuit is in an active state, indicates detection by an electric idle reception circuit, and is deactivated by detection of LFPS or the like.

  The USB3.0 link power supply interface (LINK PM (LINK Power Management)) has four states from U0 to U3. The 2-bit signal POWER DOWN [1: 0] = “00”, “01”, “10”, “11” from the LTSSM of the LINK layer 11 represents the U0, U1, U2, and U3 states, respectively. U0 to U3 are notified to the control state circuit (Control State) of the PIPE layer 12 by the 2-bit control signal POWER DOWN [1: 0] from the LTSSM.

  In U0 (LINK Active), all circuits are in operation, and packets are transmitted and received with the link partner. U1 to U3 are low power modes.

  U1 (LINK Idle with Fast Exit) is powered down a little (usually, the clock supply to the receiving circuit is stopped, packet transmission / reception is stopped, the return is fast). The return from U1 to U0 is usually when a packet needs to be transmitted. Successful LFPS handshake, transition to recovery state, return to U0 state after training. In the U1 state, when the timer (U2 inactivity timer: starts when entering the U1 state) times out, the state transits to U2. Furthermore, when the LFPS handshake fails (for example, LFPS timeout), the state transits to the SS.Inactive state.

  U2 (LINK Idle, Slower Exit) takes a little time to recover when turning down power deeper than U1, for example, turning off PLL (Phase Locked Loop) and exiting U2. The U2 state returns to the U0 state after successful LFPS handshake, recovery state, and training. If the LFPS handshake fails in the U2 state (for example, LFPS timeout), the state transits to the SS.Inactive state.

  Turn off the power at U3 (LINK Suspended). However, LFPS is handled by the LFPS detection circuit (return is slow). The entry for U3 is initiated by the host. From the U3 state, the LFPS handshake, the recovery (Recovery) state, and training return to the U0 state. If the LFPS handshake fails (LFPS timeout) in the U2 state, the U3 state remains.

  In the function stop state (SS.Disable), the LFPS detection function is unnecessary and the current consumption is 2.5 mA or less.

  In the U3 state, the LFPS detection circuit of the physical layer (PHY) 13 needs to be turned on, but the current consumption is 2.5 mA or less. For this reason, in the U3 state, the specification cannot be satisfied unless the leakage current is reduced. The output signal defined by the PIPE standard does not include a signal indicating the SS Disabled state. The PIPE function can be stopped, but the power is the same as in the U3 state.

  As a configuration for avoiding the occurrence of a through current in an input circuit due to an indefinite wiring potential caused by power-off of the output circuit in a circuit that transmits and receives signals (output circuit, input circuit), for example, Patent Document 1 Discloses a configuration in which the output level of the gate circuit is forcibly fixed at a low level by fixing the input level of the gate circuit on the power-on side to a low level, thereby preventing the occurrence of a through current. Patent Document 2 discloses a method for changing a circuit up to the nearest retention flip-flop to power-on as a configuration for preventing an indefinite signal from propagating from a power-off region to a power-on region. Has been.

JP 2004-48370 A JP 2010-218441 A

  The analysis of related technology is given below.

  In the U3 state, in the physical layer (PHY) 13, there is a state in which the LFPS detection circuit needs to be activated (operating state) in order to transmit and receive the LFPS signal. In this case, a power switch is required as a countermeasure against leakage current to satisfy the USB3.0 standard of current consumption of 2.5 mA or less. FIG. 3 shows a configuration example (prototype) including a power switch. 3 includes a power switch (SW) between the power source (VDD), the PIPE layer 12 and the PHY layer 13 in the configuration of FIG. In addition, it is good also as a structure provided with the power switch separately between the power supply and the PIPE layer 12, and between the power supply and the PHY layer 13, respectively. In FIG. 3, in order to activate the LFPS detection circuit of the physical layer (PHY) 13, the power supply to the PIPE layer 12 and the physical layer (PHY) 13 must be turned on.

  By turning off the power switch (SW) with the power enable signal deactivated, the power supply to the PIPE layer 12 and the PHY layer 13 is stopped, and the power can be reduced in the SS Disabled state.

  In the prototype example of FIG. 3, when the LFPS detection circuit of the PHY layer 13 is turned on in the U3 state, the power switch (SW) of the PIPE layer 12 and the PHY 13 must be turned on. It is difficult to satisfy the following. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a first circuit block that generates a first control signal and a second control signal corresponding to a predetermined state, respectively, and a power supply path of a first power source, A first power switch that is turned on / off in response to a first control signal, the second control signal is input, a third control signal is output, and the first power switch is turned off A second circuit block having an output circuit for stopping power supply and a third circuit block having an input circuit for inputting the third control signal. Before the first circuit block transitions the first control signal from the active state to the inactive state when the first control signal is deactivated to turn off the first power switch, The second control signal is fixed to a predetermined value, and the value of the third control signal supplied from the second circuit block to the third circuit block becomes a predetermined value. After that, the first control signal is changed from the active state to the inactive state.

  According to the embodiment, the current consumption in the power saving mode can be reduced, the indefinite signal is prevented from being propagated from the power-off output circuit to the power-on input circuit, the through current is suppressed, and the circuit operation is suppressed. Contributes to stabilization.

It is a figure explaining related technology. It is a figure explaining the state of related technology. It is a figure explaining a prototype. It is a figure explaining embodiment. (A), (B) is a diagram (Comparative Example 1) showing the connection between PIPE and PHY and timing waveforms. (A), (B) is a figure (comparative example 2) which shows a connection and timing waveform of PIPE and PHY. It is a figure (comparative example 3) explaining the connection of PIPE and PHY. FIG. 8 is a diagram (Comparative Example 3) illustrating the timing waveform of FIG. 7. FIG. 3 is a diagram illustrating connection between PIPE and PHY according to the first embodiment. It is a figure which shows the timing waveform of FIG. It is a figure explaining the connection of PIPE and PHY of Embodiment 2. FIG. It is a figure which shows the timing waveform of FIG. It is a figure explaining the connection of PIPE and PHY of Embodiment 3. It is a figure which shows the timing waveform of FIG. It is a figure explaining the connection of PIPE and PHY of Embodiment 4. It is a figure which shows the timing waveform of FIG.

  Embodiments will be described. According to the embodiment, the first control signal (power enable signal) and the second control signal (LPEN) corresponding to a predetermined state (for example, USB 3.0 U3 state) are generated. A circuit block (11A) and a first power switch (SW) inserted in a power supply path of a first power supply (VDD or VSS) and controlled to be turned on / off in response to the first control signal; A second circuit block (12A) having an output circuit for inputting the second control signal, outputting a third control signal, and stopping power supply when the first power switch (SW) is off; And a third circuit block (13A) having an input circuit for inputting the third control signal. The first circuit block sets the first control signal (power enable signal) from the active state to turn off the first power switch by deactivating the first control signal (power enable signal). Before the transition to the inactive state, the second control signal is fixed to a predetermined value, and the value of the third control signal supplied from the second circuit block to the third circuit block is a predetermined value. Then, the first control signal (power enable signal) is changed from the active state to the inactive state.

  According to the embodiment, the third circuit block (13A) includes at least one first circuit (logic circuit / TX / RX circuit) whose power supply is controlled by the first power switch (SW). And at least one second circuit (LFPS detection circuit) in which power feeding is controlled based on the value of the third control signal.

  According to the embodiment, even when the first control signal (power enable signal) is changed from the active state to the inactive state and the power supply to the first circuit is stopped, the third control signal (LPEN ) Takes an active state, power is supplied to the second circuit (LFPS detection circuit).

  According to the embodiment, the first power source is a high potential power source (VDD), and the first power switch (SW) is provided between the second circuit block (12A) and the first power source, The third control signal output from the output circuit of the second circuit block (12A) is low before the transition timing from the active state to the inactive state of the first control signal (power enable signal). The second power supply potential (Low potential) on the potential side is set.

  According to another embodiment, the first power source is a low potential power source (VSS), and the first power switch (SW) is connected between the second circuit block (12A) and the first power source. And the third control signal output from the output circuit of the second circuit block before the transition timing from the active state to the inactive state of the first control signal power enable signal is on the high potential side. The second power supply potential (High potential) is set.

  According to yet another embodiment, the first power switch (SW) is inserted between the second circuit block and the first power supply, and the third circuit block (PHY in FIG. 13) is A circuit group that receives the third control signal and transfers it to the second circuit, at least one circuit (INV1, INV2 in FIG. 13) in which power feeding is controlled via the first power switch. And a circuit group (INV1 to INV4 in FIG. 13) including at least one circuit (INV3 and INV4 in FIG. 13) fed from the first power source. According to the embodiment, the first power supply is a high-potential power supply (VDD), and the second circuit block (see FIG. 5) before the transition timing of the first control signal from the active state to the inactive state. 13 PIPE) is set to the second power supply potential on the low potential side (FIG. 14).

  According to the embodiment, in the third circuit block (PHY in FIG. 15), the circuit group (INV1 to INV4 in FIG. 15) that inputs the third control signal and transfers it to the second circuit. Then, at least one circuit (INV2 in FIG. 15) whose power supply is controlled via the first power switch is switched to the connection to the first power supply, and the first control signal is deactivated from the activated state. Prior to the transition timing to the state, the third control signal output from the output circuit of the second circuit block is set to the first power supply potential (see FIG. 16).

  According to the second embodiment, the second circuit in which on / off is controlled between the third circuit block and the first power source in common with the first power switch (SW) by the first control signal. A power switch (SW2) is provided. According to the embodiment, the current consumption in the power saving mode can be reduced, the indefinite signal is prevented from propagating from the power-off output circuit to the power-on input circuit, the through current is suppressed, and the circuit operation is stabilized. Contribute to

  FIG. 4 is a diagram illustrating a configuration of an embodiment. The present embodiment is an application example to the interface of the USB3.0 specification described with reference to FIGS. Referring to FIG. 4, in the physical layer (PHY) 13A, power control of the LFPS detection circuit is separated from power control of the transmission circuit (TX BLOCK) and the reception circuit (RX BLOCK).

  The power supply to each circuit of the PIPE layer 12A, the logic circuit of the physical layer (PHY) 13A, the transmission circuit (TX BLOCK), and the reception circuit (RX BLOCK) is a power supply whose on / off is controlled by a power enable signal. It is controlled in common via a switch (SW).

  The LFPS detection circuit of the physical layer (PHY) 13A is directly connected to the LFPS detection circuit without going through the power switch, and is supplied from the LTSSM of the link layer (LINK) 11A to the physical layer (PHY) 13A via the PIPE layer 12A. Is controlled by a control signal LPEN.

  Even when the power switch (SW) is turned off by the power enable signal and power supply to circuits other than the LFPS detection circuit of the physical layer (PHY) 13A is stopped, the control of the LFPS detection circuit is performed by the value of the control signal LPEN. . When the control signal LPEN is active, the LFPS detection circuit is turned on, and when the control signal LPEN is inactive, the LFPS detection circuit is turned off.

  Therefore, in the U3 state, the power switch (SW) is turned off, the LFPS detection circuit is turned on, the power supply to other circuits in the physical layer (PHY) 13A is stopped, and the control signal LPEN is set to the active state low. The power supply to the PIPE layer 12A is turned off, and the power supply to the P physical layer (PHY) 13A logic circuit, transmission circuit (TX BLOCK), and reception circuit (RX BLOCK) is turned off to reduce current consumption. However, it can support the 2.5mA specification.

  In the U3 state, the signal RXELECIDLE from the ON state LFPS detection circuit is directly connected to the PIPE layer 12A. In FIG. 4, the control signal LPEN is supplied from the LTSSM of the link layer (LINK) 11A to the physical layer (PHY) 13A via the PIPE layer 12A, but the link layer (LINK) 11A. Alternatively, LPEN may be generated and output by a control state circuit (Control State) that receives POWER DOWN [1: 0] from the LTSSM and supplied to the physical layer (PHY) 13A.

  FIG. 5A is a diagram (comparative example) for explaining connection (prototype) of control signals between the LFPS detection circuits of the PIPE layer 12A and the physical layer (PHY) 13A in FIG. A power switch (PchMOS transistor) is inserted between the power supply terminal of the output buffer of the PIPE layer 12A and the power supply. A power enable signal is input to the gate of the PchMOS transistor. The control signal input (LPEN in FIG. 4) is input from the LINK layer 11A to the output buffer of the PIPE layer 12A, and the control signal output from the output buffer of the PIPE layer 12A is input to the input buffer of the PHY layer 13. . The output of the input buffer of the PHY layer 13 is supplied to an LFPS detection circuit (not shown in FIG. 5A).

  FIG. 5B is a diagram (comparative example) illustrating an example of timing waveforms of the power supply enable signal, the control signal input, and the control signal output in the configuration of FIG. When the power enable signal changes from the active state (Low) to the inactive state (High), the power switch (PchMOS transistor) is turned off and the power supply to the PIPE 12A is turned off. Following the transition of the power enable signal from Low to High, the control signal input (LPEN signal) supplied from the LINK layer 11A to the PIPE layer 12A changes from High to Low. The control signal output from the output buffer of the PIPE layer 12A to the input buffer (power on) of the physical layer (PHY) 13A turns off the output buffer of the PIPE layer 12A when the power switch SW is turned off. Does not immediately change to Low, but gradually changes from High potential → intermediate potential → Low side to become an indefinite state or intermediate potential that is not determined as High or Low. In the input buffer for the LFPS circuit of the physical layer (PHY) 13A that receives the control signal output from the PIPE layer 12A as an input signal, when the logic of the input signal is not fixed and is at an intermediate potential, the power supply (VDD) is connected to the GND ( A through current may flow to the VSS) side.

  FIG. 6A is a diagram (comparative example) illustrating a configuration (prototype) when the power switch SW is inserted on the low potential side of the power path. FIG. 6B is a diagram (comparative example) illustrating an example of timing waveforms of the power supply enable signal, the control signal input, and the control signal output in the configuration of FIG. When the power enable signal changes from the active state (High) to the inactive state (Low), the power switch SW composed of the NchMOS transistor is turned off, and the signal input supplied from the LINK layer 11A to the PIPE layer 12A is changed from Low to High. The control signal output that is output from the output buffer of the PIPE layer 12A to the input buffer (power on) of the physical layer (PHY) 13A is in an indefinite state or an intermediate potential because the power of the output buffer of the PIPE layer 12A is off. . The output of the input buffer of the PHY layer 13 is supplied to an LFPS detection circuit (not shown in FIG. 5A). When the power switch on the GND side of the output buffer of the PIPE layer 12A is OFF, as shown in FIG. 6B, the control signal output gradually changes from low side potential → intermediate potential → high potential. There is a case where a through current flows in the input buffer of the PHY layer 13A without being determined (intermediate potential).

  Therefore, as another comparative example, the output level of the gate circuit (AND) is fixed by fixing the input level of the gate circuit (AND) on the power-on side to Low as shown in FIG. Can be forcibly fixed to Low to prevent the occurrence of a through current. FIG. 8 is a timing chart showing an operation example of the circuit of FIG. In synchronization with the transition of the power supply enable signal to deactivation (High), the interface control signal is set to Low, and the output (after isolation) of the AND circuit is set to Low.

  However, in the case of the configuration of FIG. 7, an additional circuit for fixing the logic, the addition of a control signal and the routing of the control signal wiring are required, and the circuit is added in the region where the power is on. An increase in area due to an increase or an increase in circuit is conceivable. Further, if the power cut-off area is increased finely to save power, the interface section increases each time the leakage current and the circuit increase. On the other hand, as disclosed in Patent Document 2, if all the power sources of the paths that are indefinite are turned on, the leakage current greatly increases.

  In the embodiment, when the power supply enable signal is deactivated from the active state in the circuit that turns off the power switch, the control signal input to be input to the output buffer of the PIPE layer is determined before the power switch of the PIPE layer is turned off. (In this case, set to Low, which represents the active state of the control signal input), and the value determined by the control signal output from the output buffer of the PIPE layer that is still powered on (in this case, the active state of the control signal output) And turn off the power switch of the PIPE layer. After the power is turned off, the output of the output buffer is turned off and enters a high impedance state, but the output of the control signal is maintained at the low level that is set when the power switch is turned on (to the intermediate potential). Will not float). Even when the PIPE layer is powered off, a low-level control signal output is input to the input buffer in the power-on state. The output of the input buffer is supplied to the LFPS detection circuit.

<Embodiment 1>
FIG. 9 is a diagram illustrating the configuration of the first embodiment. FIG. 10 is a timing chart for explaining the operation of the embodiment of FIG. Referring to FIG. 9, the state detection circuit 111 in the LINK layer 11A detects a state transition by LTSSM. For example, when the transitioned state (current state) is U3, such as when transitioning from the U0 state to the U3 state, the state detection circuit 111 sends an output signal (for example, High) to instruct power-off to the delay circuit (DELAY) 114. The first control signal generation circuit 112 is notified through this. The power switch SW between the PIPE layer output circuit and the high-potential power supply VDD is composed of a PchMOS transistor that inputs the power enable signal from the first control signal generation circuit 112 to the gate. The first control signal generation circuit 112 receives the signal delayed by the delay circuit (DELAY) 114, and when this signal is a value indicating power off, the power enable signal is deactivated (for example, High), and PchMOS When the power switch SW made of a transistor is turned off and the signal from the delay circuit (DELAY) 114 instructs to turn on the power, the power enable signal is activated (Low), and the power switch SW made of a PchMOS transistor is turned on. The state detection circuit 111 outputs an instruction to activate the control signal input to the second control signal generation circuit 113 when the transitioned state (current state) is U0, U1, U2, U3. The second control signal generation circuit 113 activates the control signal input input to the output buffer of the PIPE layer. Therefore, the control signal output from the output buffer of the PIPE layer 12A is activated and input to the input buffer of the physical layer (PHY) 13A. The output of the input buffer is supplied to an LFPS detection circuit (not shown). Power is supplied to the LFPS detection circuit, and it is activated (operating). When the transitioned state (current state) is in the SS.Disablej state, the state detection circuit 111 outputs an instruction to deactivate the control signal input to the second control signal generation circuit 113. Based on the instruction, the second control signal generation circuit 113 deactivates the control signal input input to the output buffer of the PIPE layer. The control signal output from the PIPE layer output buffer is deactivated and input to the input buffer of the LFPS detection circuit. For this reason, the power supply of the LFPS detection circuit is stopped and inactivated.

  Referring to the timing waveform diagram of FIG. 10, when the U3 state is detected (for example, when transitioning from U0 to U3 state), the power enable signal is in an active state (for example, delayed by a delay time by the delay circuit (DELAY) 114). Low) to inactive state (for example, High). Prior to the transition timing of the power enable signal from the active state (for example, Low) to the inactive state (for example, High), the control signal input input to the output buffer of the PIPE layer transitions to the active state (for example, Low). For this reason, prior to the transition timing of the power enable signal from the active state (for example, Low) to the inactive state (for example, High), the control signal output from the output buffer of the PIPE layer transitions to the active state (Low). When the power enable signal is in an inactive state (for example, High) (when the PIPE layer is in a power off state), the control signal output is in an active state (Low). That is, as shown in FIG. 5B, the control signal output does not gradually change from the high potential to the low potential side after the power switch of the PIPE layer is turned off. For this reason, it can be avoided that the control signal output takes an indefinite or intermediate value and a through current flows to the input buffer that inputs the control signal to the LFPS detection circuit of the physical layer (PHY). According to the embodiment, the current consumption in the power saving mode can be reduced, the indefinite signal is prevented from propagating from the power-off output circuit to the power-on input circuit, the through current is suppressed, and the circuit operation is stabilized. Contribute to

<Embodiment 2>
FIG. 11 is a diagram illustrating a configuration of the second embodiment. The second embodiment is a modification of the first embodiment. FIG. 12 is a timing chart for explaining the operation of the second embodiment shown in FIG. Referring to FIG. 11, the state detection circuit 111 in the LINK layer 11A detects a state transition by LTSSM. When the transition state (current state) is U3, for example, at the time of transition from the U0 to the U3 state, the state detection circuit 111 sends an output signal (for example, High) for instructing power off to the delay circuit (DELAY) 114. Via the first control signal generation circuit 112. The power switch SW between the output circuit of the PIPE layer and the low potential power supply VSS (GND) is composed of an NchMOS transistor that inputs the power enable signal from the first control signal generation circuit 112 to the gate. The first control signal generation circuit 112 receives the output signal of the delay circuit (DELAY) 114, and when the value indicates power supply off, the first control signal generation circuit 112 deactivates the power supply enable signal (for example, Low) and supplies a power switch composed of an NchMOS transistor. When the SW is turned off and the signal from the delay circuit (DELAY) 114 instructs to turn on the power, the power enable signal is activated (Low) and the power switch SW composed of an NchMOS transistor is turned on. When the transitioned state (current state) is U0, U1, U2, or U3, the state detection circuit 111 outputs an instruction to activate the control signal input to the second control signal generation circuit 113. The second control signal generation circuit 113 activates a control signal input that is input to the output buffer of the PIPE layer. The control signal output from the output buffer of the PIPE layer is activated and input to the input buffer of the physical layer (PHY). The output of the input buffer is supplied to an LFPS detection circuit (not shown). The LFPS detection circuit (not shown) is supplied with power and is activated (operated). When the transitioned state (current state) is in the SS.Disablej state, the state detection circuit 111 outputs an instruction to deactivate the control signal input to the second control signal generation circuit 113. Based on the instruction, the second control signal generation circuit 113 deactivates the control signal input input to the output buffer of the PIPE layer. The control signal output from the PIPE layer output buffer is deactivated and input to the input buffer of the LFPS detection circuit, and the power supply of the LFPS detection circuit is stopped and deactivated.

  Referring to the timing waveform diagram of FIG. 12, the power supply enable signal from the first control signal generation circuit 112 is active (High) at the timing delayed by the delay circuit (DELAY) 114 by the delay circuit (DELAY) 114 when the U3 state is detected. To an inactive state (Low). Prior to the transition timing of the power enable signal from the active state (High) to the inactive state (Low), the control signal input to the output buffer of the PIPE layer transitions to the active state (High). For this reason, prior to the transition timing of the power enable signal from the active state (High) to the inactive state (Low), the control signal output from the output buffer of the PIPE layer transitions to the active state (High. When inactive (low)) (when the PIPE layer is powered off), the control signal output is active (high). That is, as shown in FIG. 6B, after the power switch on the GND side of the PIPE layer is turned off, the control signal output does not gradually change from the low potential to the high potential side. For this reason, it can be avoided that the control signal output is indefinite or takes an intermediate value, and a through current flows in the input buffer of the LFPS detection circuit of the physical layer (PHY). Also in this embodiment, there exists an effect similar to the said embodiment.

<Embodiment 3>
FIG. 13 is a diagram illustrating a configuration of the third embodiment. The power supply for the first and second inverters INV1 and INV2 of the inverter train (INV1 to INV4) that receives the control signal output from the PIPE layer output buffer is supplied via the PIPE layer power switch SW (PchMOS transistor). Supplied. The inverters INV3 and INV4 in the third and subsequent stages of the inverter train (INV1 to INV4) are connected to the power supply via the power switch SW2 (PchMOS transistor) in the physical layer (PHY). The power switch SW of the PIPE layer and the power switch SW2 of the physical layer (PHY) are turned on / off by a common power enable signal. The transition timing of the power enable signal from the active state (Low) to the inactive state (High) is delayed from the transition timing of the control signal input and control signal output, as in the first embodiment.

  FIG. 14 is a diagram illustrating an example of the timing waveform of FIG. The power supply of the inverters INV1 and INV2 in the physical layer (PHY) stops due to the transition of the power enable signal to high in the U3 state, but the control signal output is low before the transition timing of the power enable signal to high When the inverters INV1 and INV2 are turned off in response to the transition of the power supply enable signal to High, the boundary signal that is the output signal of the inverter INV2 is The LPEN control signal input to the LFPS detection circuit is determined to be Low because it is set to Low (see the waveform (4) in FIG. 14).

  When the LPEN control signal input to the LFPS detection circuit is set to High, as shown in FIG. 15, for example, the inverter INV2 among the inverters INV1 and 2 operating with the PIPE power supply in the physical layer (PHY) is connected to the PHY power supply. Change to At this time, before the power supply enable signal is inactivated (High), the control signal input is set to High and the control signal output is set to High.

  The high potential of the control signal output, which is the output signal of the PIPE layer output buffer, is the same voltage as the power supply voltage, and when the power enable signal is deactivated, the power switch SW is turned off, so it gradually goes to the low potential side. However, when the power switch SW is off, the power supply of the inverter INV1 in the next stage of the output buffer of the PIPE layer is also at the same level, so no through current flows through the inverter INV1. In addition, the boundary signal that is the output signal of the inverter INV1 does not become an intermediate potential and remains low because the control signal output is already low before the power enable signal transitions to high. To do. At this time, the LPEN control signal becomes High. By combining the circuits of FIGS. 6 and 7, the control signal output can correspond to both low and high when the power switch of the PIPE layer is turned off.

  In a circuit in which the power supply area of the PIPE layer and the always power-on area of the physical layer (PHY) are arranged in an array, the power supply is switched only by switching the power supply. The logic of signals to the inverters INV3 and INV4) can be changed. According to the present embodiment, the current consumption in the power saving mode can be further reduced, the indeterminate signal is prevented from propagating from the power-off output circuit to the power-on input circuit, the through current is suppressed, and the circuit operation Contribute to the stabilization of

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say. It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) can be combined or selected within the scope of the claims of the present invention. . That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

11, 11A LINK layer 12, 12A PIPE layer 13, 13A Physical layer (PHY)
111 State Detection Circuit 112 First Control Signal Generation Circuit 113 Second Control Signal Generation Circuit 114 Delay Circuit

Claims (10)

A first circuit block that respectively generates a first control signal and a second control signal in correspondence with a predetermined state;
A first power switch that is inserted into a power supply path of a first power source and is controlled to be turned on and off in response to the first control signal;
A second circuit block including an output circuit that inputs the second control signal, outputs a third control signal, and stops power feeding when the first power switch is off;
A third circuit block including an input circuit for inputting the third control signal;
With
Before the first circuit block transitions the first control signal from the active state to the inactive state when the first control signal is deactivated to turn off the first power switch, The second control signal is fixed to a predetermined value, and the value of the third control signal supplied from the second circuit block to the third circuit block becomes a predetermined value. And then transitioning the first control signal from an active state to an inactive state. The third circuit block includes at least one first circuit whose power supply is controlled by the first power switch;
A second circuit in which power feeding is controlled separately from the first circuit, wherein at least one second circuit in which power feeding is controlled based on a value of the third control signal;
The semiconductor device according to claim 1, comprising:   Even when the first control signal transitions from the active state to the inactive state and the power supply to the first circuit is stopped in the third circuit block, the third control signal remains in the active state. The semiconductor device according to claim 2, wherein power is supplied to the second circuit. The first power source is a high potential power source, and the first power switch is provided between the second circuit block and the first power source;
Before the transition timing of the first control signal from the active state to the inactive state, the third control signal output from the output circuit of the second circuit block is the second power supply potential on the low potential side. The semiconductor device according to claim 3, wherein The first power source is a low-potential power source, and the first power switch is provided between the second circuit block and the first power source;
Prior to the transition timing of the first control signal from the active state to the inactive state, the third control signal output from the output circuit of the second circuit block is the second power supply potential on the high potential side. The semiconductor device according to claim 3, wherein The first power switch is inserted between the second circuit block and the first power source;
The third circuit block is a circuit group that receives the third control signal and transfers the third control signal to the second circuit, and at least one of which power supply is controlled via the first power switch The semiconductor device according to claim 2, comprising a circuit group including a circuit and at least one circuit fed from the first power source.   The first power source is a high potential power source, and the third control signal output from the output circuit of the second circuit block before the transition timing of the first control signal from the active state to the inactive state. The semiconductor device according to claim 6, wherein the control signal is set to a second power supply potential on a low potential side.   In the third circuit block, at least one circuit that inputs the third control signal and transfers the third control signal to the second circuit, the power feeding being controlled via the first power switch. To the connection to the first power supply, and before the transition timing from the active state to the inactive state of the first control signal, the third output from the output circuit of the second circuit block The semiconductor device according to claim 7, wherein a control signal is set to the first power supply potential.   9. A second power switch that is turned on / off in common with the first power switch by the first control signal is provided between the third circuit block and the first power supply. The semiconductor device described.   10. The semiconductor device according to claim 1, wherein the first, second, and third circuit blocks are USB (Universal Serial Bus) LINK, PIPE, and PHY, respectively.

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